Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of expanding a range of data voltages. According to an embodiment of the present disclosure, a display device includes: a substrate; a first electrode on the substrate; a second electrode on the first electrode; and a first intermediate layer between the first electrode and the second electrode in the first emission region, in which the first intermediate layer includes a plurality of sub-intermediate layers in the first emission region, and the sub-intermediate layers of the first intermediate layer have different thicknesses.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0086477 filed in the Korean Intellectual Property Office on July 4, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device capable of extending a data voltage range. Background Art

[0003] An organic light emitting display device includes a display element that exhibits variable brightness based on an electric current, such as an organic light emitting diode (OLED) for example. Summary of the invention

[0004] Aspects and features of embodiments of the present disclosure provide a display device capable of extending a range of a data voltage.

[0005] Aspects and features of the embodiments of the present disclosure are not limited to the above-mentioned aspects and features, and additional aspects and features of the present disclosure not mentioned here will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0006] However, the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects and features of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0007] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a first electrode on the substrate; a second electrode on the first electrode; and a first intermediate layer between the first electrode and the second electrode in a first emission region, wherein the first intermediate layer includes a plurality of sub-intermediate layers in the first emission region, and the sub-intermediate layers of the first intermediate layer have different thicknesses.

[0008] In one or more embodiments, the sub-intermediate layers of the first intermediate layer include different numbers of light emitting layers.

[0009] In one or more embodiments, the thickness of the sub-intermediate layer of the first intermediate layer is a distance from a bottom surface of the first intermediate layer to a top surface of an uppermost light emitting layer of the sub-intermediate layer of the first intermediate layer.

[0010] In one or more embodiments, the bottom surface of the first intermediate layer is an interface between the first electrode and the first intermediate layer.

[0011] In one or more embodiments, the uppermost light emitting layer of the sub-intermediate layers of the first intermediate layer is a light emitting layer farthest from the first electrode among the sub-intermediate layers of the first intermediate layer.

[0012] In one or more embodiments, a top surface of the uppermost light emitting layer of the sub-intermediate layer of the first intermediate layer is an interface between the uppermost light emitting layer of the sub-intermediate layer of the first intermediate layer and the uppermost electron transport layer of the sub-intermediate layer of the first intermediate layer.

[0013] In one or more embodiments, the sub-intermediate layers of the first intermediate layer include different numbers of light emitting units.

[0014] In one or more embodiments, each of the sub-intermediate layers of the first intermediate layer further includes a charge generation layer between adjacent light emitting units.

[0015] In one or more embodiments, the first intermediate layer further includes a functional layer in each of the light emitting units.

[0016] In one or more embodiments, the display device also includes: a third electrode between the substrate and the second electrode; and a second intermediate layer between the second electrode and the third electrode in the second emission region, wherein the second intermediate layer includes a plurality of sub-intermediate layers located in the second emission region, and the sub-intermediate layers of the second intermediate layer have different thicknesses.

[0017] In one or more embodiments, the sub-intermediate layers of the second intermediate layer respectively have the same thickness as their corresponding sub-intermediate layers of the first intermediate layer.

[0018] In one or more embodiments, the sub-intermediate layers of the second intermediate layer respectively include the same number of light-emitting layers as their corresponding sub-intermediate layers of the first intermediate layer.

[0019] In one or more embodiments, the sub-intermediate layers of the second intermediate layer respectively have different thicknesses than their corresponding sub-intermediate layers of the first intermediate layer.

[0020] In one or more embodiments, the sub-intermediate layers of the second intermediate layer respectively include different numbers of light-emitting layers than their corresponding sub-intermediate layers of the first intermediate layer.

[0021] In one or more embodiments, the second electrode includes a plurality of sub-electrodes on a sub-intermediate layer of the first intermediate layer.

[0022] In one or more embodiments, the sub-electrodes are separated from each other.

[0023] In one or more embodiments, the first emission region includes a plurality of sub-emission regions respectively corresponding to sub-middle layers of the first middle layer.

[0024] In one or more embodiments, the display device further includes: a color filter on the second electrode in the first emission region.

[0025] In one or more embodiments, the sub-intermediate layers of the first intermediate layer include light emitting layers configured to emit light of the same color.

[0026] In one or more embodiments, the sub-intermediate layers of the first intermediate layer include light emitting layers configured to emit light of different colors.

[0027] In one or more embodiments, the sub-intermediate layers of the first intermediate layer are arranged along one direction.

[0028] In one or more embodiments, the sub intermediate layer of the first intermediate layer includes a first sub intermediate layer and a second sub intermediate layer, the second sub intermediate layer has a thickness greater than that of the first sub intermediate layer and the first sub intermediate layer surrounds the second sub intermediate layer.

[0029] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a first electrode on the substrate; a second electrode on the first electrode; and an intermediate layer between the first electrode and the second electrode in an emission region, wherein the intermediate layer includes a plurality of sub-intermediate layers in the emission region, and at least two of the sub-intermediate layers include different numbers of light-emitting layers.

[0030] In one or more embodiments, at least two of the sub-intermediate layers have different thicknesses.

[0031] According to the above and other embodiments of the present disclosure, the middle layer of each pixel includes a plurality of sub-middle layers, and the sub-middle layers include different numbers of light-emitting layers. Therefore, even at a lower voltage, a wider range of gray levels can be presented in each pixel. As a result, the range of data voltages used to generate pixel voltages can be expanded.

[0032] It should be noted that the effects, aspects, and features of the present disclosure are not limited to the above effects, aspects, and features, and other effects, aspects, and features of the present disclosure will be apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0034] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure;

[0035] Figure 2 yes Figure 1 A block diagram of a display device;

[0036] Figure 3 yes Figure 1 An equivalent circuit diagram of a pixel of a display device;

[0037] Figure 4 yes Figure 1 A plan view of a plurality of pixels of a display device;

[0038] Figure 5 It is along Figure 4 A cross-sectional view taken along line II';

[0039] Figure 6 yes Figure 5 A detailed cross-sectional view of a first light emitting element of a display device;

[0040] Figure 7 yes Figure 5 A detailed cross-sectional view of a first light emitting element of a display device;

[0041] Figure 8 yes Figure 5 A detailed cross-sectional view of a first light emitting element of a display device;

[0042] Fig. 9 yes Figure 5 A detailed cross-sectional view of a first light emitting element of a display device;

[0043] Fig.10 yes Figure 5 A detailed cross-sectional view of a second light emitting element of a display device;

[0044] Fig.11 yes Figure 5 A detailed cross-sectional view of a third light emitting element of a display device;

[0045] Fig.12 is a display device according to one or more embodiments of the present disclosure along Figure 4 A cross-sectional view taken along line II';

[0046] Fig.13 is a display device according to one or more embodiments of the present disclosure along Figure 4 A cross-sectional view taken along line II';

[0047] Fig.14 yes Fig.13 A cross-sectional view of a first light emitting element of a display device;

[0048] Fig.15 yes Fig.13 A detailed cross-sectional view of a second light emitting element of a display device;

[0049] Fig.16 yes Fig.13 A detailed cross-sectional view of a third light emitting element of a display device;

[0050] Fig.17is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure;

[0051] Fig.18 is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure;

[0052] Fig.19 is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure;

[0053] Fig. 20 is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure;

[0054] Fig.21 is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure;

[0055] Fig. 22 is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure;

[0056] Fig.23 is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure;

[0057] Fig.24 It is along Fig.23 A cross-sectional view taken along line II-II';

[0058] Fig.25 is a cross-sectional view of a first light emitting element of a display device according to one or more embodiments of the present disclosure;

[0059] Fig.26 is a graph comparing luminance at a specific pixel voltage between a display device according to an embodiment of the present disclosure and a display device according to a comparative example;

[0060] Fig. 27 is a graph showing the variation of luminance with respect to driving voltage for different series configurations; and

[0061] Fig.28 is a graph comparing driving current error rates of a display device according to an embodiment of the present disclosure and a display device according to a comparative example. DETAILED DESCRIPTION

[0062] When referring to the detailed embodiments provided with the accompanying drawings, the aspects, features and methods of implementing the detailed embodiments in the present disclosure will become apparent. However, the present disclosure is not limited to the embodiments disclosed herein, but may be implemented in various other forms. The embodiments are merely intended to ensure the completeness of the present disclosure to those skilled in the art and to fully convey the scope of the present disclosure defined by the claims.

[0063] The term "on..." referring to a component or layer placed on another component or layer includes the case where another layer or component exists directly above or between. Throughout the specification, the same reference numerals represent the same components. The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings for illustrating the embodiments are examples and are not limited to the aspects described in the present disclosure.

[0064] Although terms such as "first", "second", etc. are used to describe various components, these terms are used to distinguish one component from another component, and the components referred to by these terms are not limited by the corresponding terms. Therefore, within the technical concept of the present disclosure, the first component mentioned below may also be the second component.

[0065] The features of various embodiments of the present disclosure may be combined in part or in whole, or integrated in a technically diverse manner. The embodiments of the present disclosure may be implemented independently or all together in an associated relationship.

[0066] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0067] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure.

[0068] The first direction DR1, the second direction DR2 and the third direction DR3 are Figure 1 See Figure 1 , the first direction DR1 and the second direction DR2 may be orthogonal to each other, the first direction DR1 and the third direction DR3 may be orthogonal to each other, and the second direction DR2 and the third direction DR3 may be orthogonal to each other. The first direction DR1 may be a horizontal direction, the second direction DR2 may be a vertical direction, and the third direction DR3 may be a direction from top to bottom or a thickness direction. In the following description, unless otherwise specifically stated, the term "direction" may refer to both sides extending in the corresponding direction. In addition, if it is necessary to distinguish between the two sides extending in each direction, one of the two sides will be referred to as "one side" or "first side", and the other side will be referred to as "the other side" or "second side". With reference Figure 1 , the direction indicated by each arrow is referred to as "one side" or "first side" in the corresponding direction, and the opposite direction is referred to as "the other side" or "second side" in the corresponding direction. However, it should be understood that the directions mentioned here refer to relative directions, and the present disclosure is not limited thereto.

[0069] For convenience, when referring to the surface of the display device 1 or the surface of each component of the display device 1, a surface facing the direction of the displayed image (i.e., one side on the third direction DR3) will be referred to as the top surface hereinafter, and the opposite surface will be referred to as the bottom surface hereinafter. However, the present disclosure is not limited to this. Optionally, the one surface and the other surface may also be referred to as the front surface and the rear surface, respectively, or as the first surface and the second surface, respectively. In addition, when describing the relative position of each component of the display device 1, one side on the third direction DR3 may be referred to as the upper side, and the other side on the third direction DR3 may be referred to as the lower side.

[0070] The display device 1 may refer to any electronic device that provides a display screen. For example, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a mobile communication terminal, an electronic notepad, an e-book reader, a portable multimedia player (PMP), a navigator, a game console, a digital camera, a television, a laptop computer, a netbook, a monitor, an advertising board, and / or an Internet of Things (IoT) device may be included in the display device 1. Figure 1 The embodiment shows an example in which the display device 1 is applied to a medium-sized portable device such as a tablet PC.

[0071] There is no limitation on the planar shape of the display device 1. The planar shape of the display device 1 may be modified in various ways according to the applicable field of the display device 1, such as modified to a rectangular shape, a square shape, a diamond shape, another polygonal shape, a circular shape, an elliptical shape, etc. The illustrated planar shape of the display device 1 is a rectangular shape with rounded corners in which two long sides are positioned parallel to the second direction DR2. For convenience, one side of the two opposite long sides of the rectangular shape located in the first direction DR1 (i.e., Figure 1 The left side of the first direction DR1 (i.e., the left side of the first direction DR2) will be referred to as the first long side LS1 hereinafter, and the other side of the first direction DR1 (i.e., the left side of the first direction DR2) will be referred to as the first long side LS1 hereinafter. Figure 1 The long side of the right side in the rectangular shape will be referred to as the second long side LS2 hereinafter. Similarly, one of the two opposite short sides of the rectangular shape located in the second direction DR2 (ie, Figure 1 The bottom side of the first short side SS1 will be referred to as the first short side SS1 below, and is located on the other side in the second direction DR2 (ie, Figure 1 The short side of the display device 1 (the top side in the figure) will be referred to as the second short side SS2 hereinafter. The terms "first long side LS1", "second long side LS2", "first short side SS1" and "second short side SS2" may also be used interchangeably to refer to their corresponding sides not only in the display device 1 but also in each component of the display device 1 having a shape and positional relationship similar to the display device 1.

[0072] The display device 1 may include a display area DA and a non-display area NDA along an edge or periphery of the display area DA. The display area DA is an area where an image is displayed, and the non-display area NDA is an area where no image is displayed. The terms "display area DA" and "non-display area NDA" may also be used interchangeably to refer to their corresponding areas not only in the display device 1 but also in each component of the display device 1 having a shape and positional relationship similar to the display device 1.

[0073] A plurality of pixels PX may be disposed in the display area DA. The structure of the pixel PX will be described later.

[0074] The non-display area NDA may be disposed around the display area DA. When the display area DA has a rectangular shape, the non-display area NDA may be positioned around four sides of the display area DA (e.g., positioned to surround the four sides of the display area DA), but the present disclosure is not limited thereto. Alternatively, the non-display area NDA may be located outside only some of the sides of the display area DA. Alternatively, the non-display area NDA may be located within the display area DA, or may be surrounded by the display area DA.

[0075] Figure 2 yes Figure 1 A block diagram of a display device.

[0076] Reference Figure 1 and Figure 2 The display device 1 includes a display panel PNL. The display device 1 may further include a driving unit connected to the display panel PNL.

[0077] In the present disclosure, the term "connection" refers not only to a component being physically connected to another component by direct contact, but also to connection through another component. In addition, the term "connection" may be understood as different parts interconnected by being unified into a single component. In addition, the connection between one component and another component may be interpreted as including not only direct physical contact, but also electrical connection through other components.

[0078] The display panel PNL provides a display screen. The direction in which the display panel PNL provides the display screen is the third direction DR3. The display panel PNL may have a planar shape similar to the display device 1. The display area DA of the display device 1 may also be referred to as the display area DA of the display panel PNL. The display area DA of the display panel PNL may include a plurality of pixels PX arranged in a matrix. In other words, the plurality of pixels PX may be arranged along rows and columns of the matrix.

[0079] Examples of the display panel PNL include an organic light-emitting display panel, a micro light-emitting diode (LED) display panel, a nano-LED display panel, a quantum dot light-emitting display panel, a liquid crystal display (LCD) panel, a plasma display panel (PDP), a field emission display (FED) panel, an electrophoretic display panel, an electrowetting display panel, etc. The display panel PNL will be described below as, for example, an organic light-emitting display panel, but the present disclosure is not limited thereto. That is, the display panel PNL may also be applicable to other display panels within the scope of the present disclosure.

[0080] The driving unit drives the operation of the display panel PNL. At least some components of the driving unit drive the pixels PX in the display area DA of the display panel PNL. In one or more embodiments, the driving unit may be provided in the form of a chip, a film, and / or a circuit board.

[0081] The driving unit may include a display scan driver 250, a data driver 210, a timing controller 220, and a power supply (or power supply unit) 230. The driving unit may be located in the non-display area NDA of the display panel PNL, but some of its components may be disposed in the display area DA.

[0082] In the display area DA, not only pixels PX but also multiple lines connected to the driving unit may be arranged, which may include multiple display writing lines GWL, multiple display initialization lines GIL, multiple display control lines GCL, multiple emission lines EL, and multiple data lines DTL.

[0083] The data lines DTL may extend in the second direction DR2. The display write lines GWL, the display initialization lines GIL, the display control lines GCL, and the emission lines EL may extend in the first direction DR1.

[0084] Each of the pixels PX may be connected to one of the display write lines GWL, one of the display initialization lines GIL, one of the display control lines GCL, and one of the emission lines EL. The pixels PX may receive data voltages from their corresponding data lines DTL according to display write signals, display initialization signals, display control signals, and emission signals from their corresponding display write lines GWL, display initialization lines GIL, display control lines GCL, and emission lines EL. Subsequently, the pixels PX may emit light by applying a drive current to their light emitting elements according to the received data voltages.

[0085] The display scan driver 250 may be connected to the display write line GWL, the display initialization line GIL, the display control line GCL, and the emission line EL. The display scan driver 250 may include a display signal output module that outputs a display write signal to be applied to the display write line GWL, a display initialization signal to be applied to the display initialization line GIL, and a display control signal to be applied to the display control line GCL, and an emission signal output module that outputs an emission signal to be applied to the emission line EL.

[0086] The display scan driver 250 may receive a write control signal WCS, an initialization control signal ICS, a scan control signal CCS, and an emission control signal ECS from the timing controller 220. The display signal output module of the display scan driver 250 may generate a display write signal according to the write control signal WCS, and may output the generated display write signal to the display write line GWL. In addition, the display signal output module of the display scan driver 250 may generate a display initialization signal according to the initialization control signal ICS, and may output the generated display initialization signal to the display initialization line GIL. In addition, the display signal output module of the display scan driver 250 may generate a display control signal according to the scan control signal CCS, and may output the generated display control signal to the display control line GCL. In addition, the emission signal output module of the display scan driver 250 may generate an emission signal according to the emission control signal ECS, and may output the generated emission signal to the emission line EL.

[0087] The data driver 210 converts the digital video data DATA into a data voltage and outputs the data voltage to the data line DTL. The data driver 210 may output the data voltage in synchronization with the display write signal. The pixel PX may be selected by the display write signal from the display scan driver 250, and the data voltage may be supplied to the selected pixel PX.

[0088] The timing controller 220 receives digital video data DATA and a timing signal from an external graphic device. For example, the external graphic device may be a graphic card or a set-top box of a computer, but the present disclosure is not limited thereto.

[0089] The timing controller 220 may generate a write control signal WCS, an initialization control signal ICS, a scan control signal CCS, and an emission control signal ECS for controlling the operation timing of the display scan driver 250 according to the timing signal. In addition, the timing controller 220 may generate a data control signal DCS for controlling the operation timing of the data driver 210 according to the timing signal.

[0090] The timing controller 220 may output a write control signal WCS, an initialization control signal ICS, a scan control signal CCS, and an emission control signal ECS to the display scan driver 250. The timing controller 220 may output digital video data DATA and a data control signal DCS to the data driver 210.

[0091] The power supply 230 may generate a plurality of driving voltages and may output the driving voltages to the display area DA. The power supply 230 may output a first driving voltage VDD, a second driving voltage VSS, and an initialization voltage VINT to the display panel PNL. The first driving voltage VDD may be a high potential driving voltage, the second driving voltage VSS may be a low potential driving voltage, and the initialization voltage VINT may be a voltage for initializing a gate electrode of a driving transistor of a pixel PX.

[0092] Figure 3 yes Figure 1 An equivalent circuit diagram of a pixel of a display device.

[0093] Reference Figure 3 , the pixel PX can be connected to the kth display initialization line GILk, the kth display write line GWLk and the kth display control line GCLk (where k is a positive integer). The pixel PX can also be connected to a first driving voltage line VDL supplied with a first driving voltage, a second driving voltage line VSL supplied with a second driving voltage, and an initialization voltage line VIL supplied with an initialization voltage.

[0094] The pixel PX may include a pixel circuit PXC and a light emitting element ED. The light emitting element ED may be connected to the pixel circuit PXC.

[0095] The pixel circuit PXC may include a driving transistor DT, a switching element, and a capacitor CST. The switching element may include first to sixth transistors ST1 to ST6.

[0096] The driving transistor DT may include a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current (hereinafter, a driving current Ids) flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode. The driving current Ids flowing through the channel of the driving transistor DT is proportional to the square of the difference between the threshold voltage (Vth) of the driving transistor DT and the voltage (Vgs), which is the voltage applied between the first electrode and the gate electrode of the driving transistor DT, as indicated by equation (1):

[0097] Ids=k ’ ×(Vgs-Vth) 2 ……(1)

[0098] where k’ represents a proportionality coefficient determined by the structure and physical characteristics of the driving transistor DT, Vgs represents a voltage between the first electrode and the gate electrode of the driving transistor DT, and Vth refers to a threshold voltage of the driving transistor DT.

[0099] The light emitting element ED emits light according to the driving current Ids. The larger the driving current Ids is, the larger the amount of light emitted by the light emitting element ED is.

[0100] The light emitting element ED may be an OLED including an organic light emitting layer disposed between an anode and a cathode. Alternatively, the light emitting element ED may be an inorganic light emitting element including an inorganic semiconductor disposed between an anode and a cathode. Alternatively, the light emitting element ED may be a quantum dot light emitting element including a quantum dot light emitting layer disposed between an anode and a cathode. Alternatively, the light emitting element ED may be a micro light emitting element including a micro LED disposed between an anode and a cathode. The light emitting element ED will hereinafter be described as an OLED having an organic light emitting layer disposed between an anode and a cathode.

[0101] The anode of the light emitting element ED may also be referred to as a pixel electrode, and the cathode of the light emitting element ED may also be referred to as a common electrode CE (see Figure 5 ).

[0102] An anode of the light emitting element ED may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and a cathode of the light emitting element ED may be connected to the second driving voltage line VSL. A parasitic capacitor Cel may be formed between the anode and cathode of the light emitting element ED.

[0103] The first transistor ST1 is turned on by the initialization scan signal from the kth display initialization line GILk, and connects the gate electrode of the driving transistor DT to the initialization voltage line VIL. As a result, the initialization voltage from the initialization voltage line VIL can be applied to the gate electrode of the driving transistor DT. The gate electrode of the first transistor ST1 can be connected to the kth initialization line GILk, the first electrode of the first transistor ST1 can be connected to the gate electrode of the driving transistor DT, and the second electrode of the first transistor ST1 can be connected to the initialization voltage line VIL.

[0104] The second transistor ST2 is turned on by the display write signal from the kth display write line GWLk, and connects the first electrode of the driving transistor DT to the jth data line Dj. As a result, the data voltage from the jth data line can be applied to the first electrode of the driving transistor DT. The gate electrode of the second transistor ST2 can be connected to the kth display write line GWLk, the first electrode of the second transistor ST2 can be connected to the first electrode of the driving transistor DT, and the second electrode of the second transistor ST2 can be connected to the jth data line Dj.

[0105] The third transistor ST3 is turned on by a display write signal from the kth display write line GWLk, and connects the gate electrode and the second electrode of the drive transistor DT. When the gate electrode and the second electrode of the drive transistor DT are connected, the drive transistor DT operates as a diode (for example, the drive transistor DT is diode-connected). The gate electrode of the third transistor ST3 may be connected to the kth display write line GWLk, the first electrode of the third transistor ST3 may be connected to the second electrode of the drive transistor DT, and the second electrode of the third transistor ST3 may be connected to the gate electrode of the drive transistor DT.

[0106] The fourth transistor ST4 is turned on by the display control signal from the kth display control line GCLk, and connects the anode of the light emitting element ED to the initialization voltage line VIL. The initialization voltage from the initialization voltage line VIL can be applied to the anode of the light emitting element ED. The gate electrode of the fourth transistor ST4 can be connected to the kth display control line GCLk, the first electrode of the fourth transistor ST4 can be connected to the anode of the light emitting element ED, and the second electrode of the fourth transistor ST4 can be connected to the initialization voltage line VIL.

[0107] The fifth transistor ST5 is turned on by the emission signal from the k-th emission line ELk, and connects the first electrode of the driving transistor DT to the first driving voltage line VDL. The gate electrode of the fifth transistor ST5 may be connected to the k-th emission line ELk, the first electrode of the fifth transistor ST5 may be connected to the first driving voltage line VDL, and the second electrode of the fifth transistor ST5 may be connected to the first electrode of the driving transistor DT.

[0108] The sixth transistor ST6 is disposed between the second electrode of the driving transistor DT and the anode of the light emitting element ED. The sixth transistor ST6 is turned on by the emission control signal from the k-th emission line ELk, and connects the second electrode of the driving transistor DT to the anode of the light emitting element ED. The gate electrode of the sixth transistor ST6 may be connected to the k-th emission line ELk, the first electrode of the sixth transistor ST6 may be connected to the second electrode of the driving transistor DT, and the second electrode of the sixth transistor ST6 may be connected to the anode of the light emitting element ED.

[0109] When both the fifth transistor ST5 and the sixth transistor ST6 are turned on, the driving current Ids of the driving transistor DT may flow into the light emitting element ED according to the data voltage applied to the gate electrode of the driving transistor DT.

[0110] The capacitor CST is formed between the gate electrode of the driving transistor DT and the first driving voltage line VDL. A first electrode of the capacitor CST may be connected to the gate electrode of the driving transistor DT, and a second electrode of the capacitor CST may be connected to the first driving voltage line VDL.

[0111] When the first electrodes of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 are source electrodes, the second electrodes of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 are drain electrodes. On the contrary, when the first electrodes of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 are drain electrodes, the second electrodes of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 are source electrodes. The first and second electrodes of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 can be respectively referred to as source electrodes and drain electrodes according to the direction in which a plurality of carriers move in the semiconductor layer, and vice versa. The first and second electrodes of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 can also be referred to as source / drain electrodes. If the first and second electrodes of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 need to be distinguished, they can also be respectively referred to as first source / drain electrodes and second source / drain electrodes.

[0112] Active layers of the driving transistor DT and the first to sixth transistors ST1 to ST6 may be formed of one of polysilicon, amorphous silicon, and an oxide semiconductor. Figure 3 The driving transistor DT and the first to sixth transistors ST1 to ST6 are shown as p-type metal oxide semiconductor field effect transistors (MOSFETs), but the present disclosure is not limited thereto. Alternatively, the driving transistor DT and the first to sixth transistors ST1 to ST6 may be formed as n-type MOSFETs.

[0113] The pixel circuit PXC may have a "7T1C" structure consisting of seven transistors and one capacitor, and the number of transistors and capacitors forming the pixel circuit PXC may vary. For example, the pixel circuit PXC may have a "5T2C" structure consisting of five transistors and two capacitors.

[0114] Figure 4 yes Figure 1 A plan view of a plurality of pixels of a display device. Figure 5 It is along Figure 4 A cross-sectional view taken along line II'.

[0115] Reference Figure 5 , the display device 1 may include a substrate SUB, a transistor layer TRL, a light emitting element layer EMTL and an encapsulation layer ENC.

[0116] The substrate SUB may be a base substrate or a member. The substrate SUB may be a flexible substrate that is bendable, foldable and / or rollable. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but the present disclosure is not limited thereto. In another example, the substrate SUB may include a glass material or a metal material. In another example, the substrate SUB may be a semiconductor pattern formed on a silicon (Si) substrate. In another example, the substrate SUB may be a Si semiconductor substrate formed by a complementary metal oxide semiconductor (CMOS) process. The substrate SUB may include a single crystal Si wafer, a polycrystalline Si wafer and / or an amorphous Si wafer, or may be a germanium (Ge) substrate or a silicon germanium (SiGe) substrate.

[0117] The transistor layer TRL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a transistor TR, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0118] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic films alternately stacked.

[0119] The lower metal layer BML may be disposed on the first buffer layer BF1. For example, the lower metal layer BML may be formed as a single layer or multiple layers including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and / or alloys thereof.

[0120] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic film capable of preventing penetration of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic films alternately stacked.

[0121] The transistor TR may be disposed on the second buffer layer BF2 and may form a pixel circuit of the pixel PX. For example, the transistor TR may be a pixel circuit ( Figure 4 The "PXC") driver transistor ( Figure 4 The transistor TR may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0122] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the lower metal layer BML and the gate electrode GE in the thickness direction (e.g., the third direction DR3), and may be insulated from the gate electrode GE by the gate insulating layer GI (i.e., the gate insulating film). The source electrode SE and the drain electrode DE may be formed by converting some portions of the semiconductor layer ACT into a conductive material.

[0123] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT with the gate insulating layer GI interposed therebetween.

[0124] The gate insulating layer GI may be disposed on the semiconductor layer ACT and the second buffer layer BF2. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 and may insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer GI may include a contact hole penetrated by the first connection electrode CNE1.

[0125] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole penetrated by the first connection electrode CNE1. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0126] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in the thickness direction (eg, the third direction DR3). The capacitor electrode CPE and the gate electrode GE may form a capacitor. For example, the gate electrode GE may overlap the capacitor ( Figure 3 The capacitor electrode CPE may correspond to the first electrode of the capacitor ( Figure 3 The second electrode of “CST” corresponds to the second electrode of “CST”.

[0127] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole penetrated by the first connection electrode CNE1. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0128] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the transistor TR to the second connection electrode CNE2. The first connection electrode CNE1 may contact the drain electrode DE of the transistor TR by being inserted into a contact hole of each of the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI.

[0129] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the transistor TR. The first passivation layer PAS1 may include a contact hole penetrated by the second connection electrode CNE2.

[0130] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the first light emitting element ED1, the second light emitting element ED2, the third light emitting element ED3, and the first electrode of the fourth light emitting element (or the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the fourth pixel electrode PE4). The second connection electrode CNE2 may contact the first connection electrode CNE1 by being inserted into the contact hole of the first passivation layer PAS1.

[0131] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes penetrated by the pixel electrodes PE1, PE2, PE3, and PE4.

[0132] The light emitting element layer EMTL may be disposed on the transistor layer TRL. The light emitting element layer EMTL may include a first light emitting element ED1, a second light emitting element ED2, a third light emitting element ED3, and a bank PDL. The first light emitting element ED1, the second light emitting element ED2, the third light emitting element ED3, and the fourth light emitting element may include respective first pixel electrodes PE1, second pixel electrodes PE2, third pixel electrodes PE3, and fourth pixel electrodes PE4, respective first intermediate layers ML1, second intermediate layers ML2, third intermediate layers ML3, and fourth intermediate layers ML4, and a common electrode CE.

[0133] The display device 1 may include a plurality of emission areas EA1, EA2, EA3, and EA4 disposed in the display area DA. The emission areas EA1, EA2, EA3, and EA4 may include a first emission area EA1, a second emission area EA2, a third emission area EA3, and a fourth emission area EA4 that emit light of different colors. The fourth emission area EA4 may emit light of the same color as the second emission area EA2. The first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4 may emit red light, blue light, green light, and blue light, respectively, and the color of the light emitted by each of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4 may vary according to the type of the light emitting element disposed in the light emitting element layer EMTL. For example, the first emission area EA1 may emit red light, the second emission area EA2 and the fourth emission area EA4 may emit blue light, and the third emission area EA3 may emit green light. However, the present disclosure is not limited to this example.

[0134] The first emission area EA1, the second emission area EA2, the third emission area EA3 and the fourth emission area EA4 may be defined by a plurality of openings formed in the embankment PDL of the light emitting element layer EMTL. The first emission area EA1, the second emission area EA2, the third emission area EA3 and the fourth emission area EA4 may have the same area or size. For example, the first emission area EA1, the second emission area EA2, the third emission area EA3 and the fourth emission area EA4 may all have the same area, but the present disclosure is not limited thereto. Alternatively, the first emission area EA1, the second emission area EA2, the third emission area EA3 and the fourth emission area EA4 may have different areas or sizes. The intensity of light emitted by each of the first emission area EA1, the second emission area EA2, the third emission area EA3 and the fourth emission area EA4 may vary according to the area of ​​the corresponding emission area, and the color of the picture displayed by the display device 1 may be controlled by adjusting the area of ​​each of the first emission area EA1, the second emission area EA2, the third emission area EA3 and the fourth emission area EA4. Figure 4The first emission area EA1, the second emission area EA2, the third emission area EA3 and the fourth emission area EA4 are shown as having the same area, but the present disclosure is not limited to this. The area of ​​each of the first emission area EA1, the second emission area EA2, the third emission area EA3 and the fourth emission area EA4 can be freely adjusted according to the picture color required by the display device 1. The areas of the first emission area EA1, the second emission area EA2, the third emission area EA3 and the fourth emission area EA4 may be related to factors such as the optical efficiency and life of the light-emitting element, and may also be subject to a trade-off relationship with external reflection, and taking these factors into consideration, the areas of the first emission area EA1, the second emission area EA2, the third emission area EA3 and the fourth emission area EA4 may be adjusted.

[0135] In the display device 1, a first emission area EA1, a second emission area EA2, a third emission area EA3, and a fourth emission area EA4 positioned adjacent to each other may form a single unit pixel together. A single unit pixel may represent a white grayscale by including a plurality of emission areas emitting light of different colors, but the present disclosure is not limited thereto. The combination of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4 forming a single unit pixel may vary according to the layout of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4 and the color of the light emitted by each of the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4.

[0136] The display device 1 may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3, respectively, which are arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3, and a fourth light emitting element arranged in the fourth emission area EA4. For example, the light emitting element layer EMTL of the display device 1 may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3, respectively, which are arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3, and a fourth light emitting element arranged in the fourth emission area EA4. The first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may include respective first pixel electrodes PE1, second pixel electrodes PE2, and third pixel electrodes PE3, respective first intermediate layers ML1, second intermediate layers ML2, and third intermediate layers ML3, and a common electrode CE (or a second electrode), and the fourth light emitting element may include a fourth pixel electrode PE4, a fourth intermediate layer ML4, and a common electrode CE.

[0137] The first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4 forming a single unit pixel can provide various colors of light by the first light-emitting element ED1, the second light-emitting element ED2, the third light-emitting element ED3, and the fourth light-emitting element emitting different colors of light. For example, the unit pixel may include a first pixel, a second pixel, a third pixel, and a fourth pixel arranged adjacent to each other, and the first pixel, the second pixel, and the third pixel may include a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3 that emit red light, blue light, and green light, respectively, and the fourth pixel may include a fourth light-emitting element that emits blue light. In the present embodiment, the unit pixel can provide various colors of light by mixing the red light provided by the first light-emitting element ED1 of the first pixel, the blue light provided by the second light-emitting element ED2 of the second pixel and the fourth light-emitting element of the fourth pixel, and the green light provided by the third light-emitting element ED3 of the third pixel.

[0138] The first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3 and the fourth pixel electrode PE4 may be disposed on the second passivation layer PAS2. For example, the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3 and the fourth pixel electrode PE4 may be positioned to correspond to the first emission area EA1, the second emission area EA2, the third emission area EA3 and the fourth emission area EA4, respectively.

[0139] The first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the fourth pixel electrode PE4 may be electrically connected to the drain electrode DE of the transistor TR through the first connection electrode CNE1 and the second connection electrode CNE2. For example, the first pixel electrode PE1 may be connected to the drain electrode DE of the transistor TR of the first pixel through the first connection electrode CNE1 and the second connection electrode CNE2, the second pixel electrode PE2 may be connected to the drain electrode DE of the transistor TR of the second pixel through the first connection electrode CNE1 and the second connection electrode CNE2, the third pixel electrode PE3 may be connected to the drain electrode DE of the transistor TR of the third pixel through the first connection electrode CNE1 and the second connection electrode CNE2, and the fourth pixel electrode PE4 may be connected to the drain electrode of the transistor of the fourth pixel through the first connection electrode CNE1 and the second connection electrode CNE2.

[0140] Each of the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the fourth pixel electrode PE4 may have a layer in which a material having a high work function (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3)) and a reflective material layer containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) and / or a mixture thereof. The high work function material layer can be disposed above the reflective material layer, close to the first middle layer ML1, the second middle layer ML2 and the third middle layer ML3. For example, the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3 and the fourth pixel electrode PE4 can have a material layer such as ITO / Mg, ITO / MgF 2 , ITO / Ag or ITO / Ag / ITO multilayer structure, but the present disclosure is not limited thereto.

[0141] A bank PDL (or a pixel defining film) may be disposed on the first pixel electrode PE1 , the second pixel electrode PE2 , the third pixel electrode PE3 , and the fourth pixel electrode PE4 .

[0142] The embankment PDL may define a first emission area EA1, a second emission area EA2, a third emission area EA3, and a fourth emission area EA4 of the first pixel, the second pixel, the third pixel, and the fourth pixel. To this end, the embankment PDL may be disposed on the second passivation layer PAS2 to expose portions of the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the fourth pixel electrode PE4. For example, the embankment PDL may cover an edge of each of the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the fourth pixel electrode PE4. The embankment PDL may be formed as an organic film including an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0143] The first middle layer ML1, the second middle layer ML2, the third middle layer ML3 and the fourth middle layer ML4 may be disposed on the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3 and the fourth pixel electrode PE4, respectively. In a plan view, the first middle layer ML1 may have, for example, a rectangular shape. The first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1 may have a rectangular shape that is longer in the second direction DR2 than in the first direction DR1. In a plan view, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1 may face each other and may contact each other. In addition, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1 may be positioned to face each other in the first direction DR1. The second middle layer ML2, the third middle layer ML3 and the fourth middle layer ML4 may have the same shape as the first middle layer ML1.

[0144] The common electrode CE may be disposed on the first intermediate layer ML1, the second intermediate layer ML2, the third intermediate layer ML3, and the fourth intermediate layer ML4. For example, the common electrode CE may be located on the first intermediate layer ML1, the second intermediate layer ML2, the third intermediate layer ML3, and the fourth intermediate layer ML4 to overlap with the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the fourth pixel electrode PE4, the first emission area EA1, the second emission area EA2, the third emission area EA3, and the fourth emission area EA4, and the embankment PDL. The common electrode CE may be a common layer commonly used for the first light-emitting element ED1, the second light-emitting element ED2, the third light-emitting element ED3, and the fourth light-emitting element. In other words, the first light-emitting element ED1, the second light-emitting element ED2, the third light-emitting element ED3, and the fourth light-emitting element may share the common electrode CE. In the top emission structure, the common electrode CE may be formed of a transparent conductive oxide (TCO) (such as ITO or IZO) or a semi-transmissive metal material (such as Mg, Ag, or an alloy thereof) capable of transmitting light therethrough. In the case where the common electrode CE is a semi-transmissive metal material, the light emission efficiency of the display device 1 may be improved due to the microcavity.

[0145] The cover layer CPL may be disposed on the common electrode CE. The cover layer CPL may include an inorganic insulating material. For example, the cover layer CPL may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0146] The encapsulation layer ENC may be disposed on the cover layer CPL. The encapsulation layer ENC may cover the top surface and the side surface of the light emitting element layer EMTL, and may protect the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EMTL. Specifically, the encapsulation layer ENC may include at least one inorganic film for preventing oxygen or moisture from penetrating into the light emitting element layer EMTL. The encapsulation layer ENC may include at least one organic film for protecting the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer ENC may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0147] The first encapsulation inorganic film TFE1 may be disposed on the cover layer CPL, the encapsulation organic film TFE2 may be disposed on the first encapsulation inorganic film TFE1, and the second encapsulation inorganic film TFE3 may be disposed on the encapsulation organic film TFE2. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 may be formed as a multilayer film in which one or more inorganic films selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked. The encapsulation organic film TFE2 may be formed as an organic film containing acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0148] The first light emitting element ED1 may include a first pixel electrode PE1, a common electrode CE, and a first middle layer ML1. The first middle layer ML1 may be disposed between the first pixel electrode PE1 and the common electrode CE. The first middle layer ML1 may be disposed on the first pixel electrode PE1 to overlap the first pixel electrode PE1.

[0149] The second light emitting element ED2 may include a second pixel electrode PE2, a common electrode CE, and a second middle layer ML2. The second middle layer ML2 may be disposed between the second pixel electrode PE2 and the common electrode CE. The second middle layer ML2 may be disposed on the second pixel electrode PE2 to overlap the second pixel electrode PE2.

[0150] The third light emitting element ED3 may include a third pixel electrode PE3, a common electrode CE, and a third intermediate layer ML3. The third intermediate layer ML3 may be disposed between the third pixel electrode PE3 and the common electrode CE. The third intermediate layer ML3 may be disposed on the third pixel electrode PE3 to overlap the third pixel electrode PE3.

[0151] The fourth light emitting element may include a fourth pixel electrode PE4, a common electrode CE, and a fourth intermediate layer ML4. The fourth intermediate layer ML4 may be disposed between the fourth pixel electrode PE4 and the common electrode CE. The fourth intermediate layer ML4 may be disposed on the fourth pixel electrode PE4 to overlap the fourth pixel electrode PE4.

[0152] exist Figures 4 to 5In the example, each of the first intermediate layer ML1, the second intermediate layer ML2, the third intermediate layer ML3 and the fourth intermediate layer ML4 may have different thicknesses in its corresponding emission area. Each of the first intermediate layer ML1, the second intermediate layer ML2, the third intermediate layer ML3 and the fourth intermediate layer ML4 may have different thicknesses in the emission area superimposed with the corresponding pixel electrode. For example, the first intermediate layer ML1 superimposed (or in contact with) the first pixel electrode PE1 and disposed in the first emission area EA1 may have different thicknesses in the first emission area EA1, that is, the first thickness T1 and the second thickness T2 (wherein T2>T1). For example, the second intermediate layer ML2 superimposed (or in contact with) the second pixel electrode PE2 and disposed in the second emission area EA2 may have different thicknesses in the second emission area EA2, that is, the first thickness T1 and the second thickness T2 (wherein T2>T1). For example, the third intermediate layer ML3 overlapping (or contacting) the third pixel electrode PE3 and disposed in the third emission area EA3 may have different thicknesses in the third emission area EA3, that is, a first thickness T1 and a second thickness T2 (wherein T2>T1). For example, the fourth intermediate layer ML4 overlapping (or contacting) the fourth pixel electrode PE4 and disposed in the fourth emission area EA4 may have different thicknesses in the fourth emission area EA4. Here, the term "thickness" refers to a dimension measured in the third direction DR3.

[0153] Each of the first middle layer ML1, the second middle layer ML2, the third middle layer ML3, and the fourth middle layer ML4 may include a plurality of sub-middle layers. Figure 5 The first middle layer ML1 may include a first sub-middle layer SML1 and a second sub-middle layer SML2 respectively disposed in the first sub-emission region SEA1 and the second sub-emission region SEA2 of the first emission region EA1. The second thickness T2 of the second sub-middle layer SML2 of the first middle layer ML1 may be greater than the first thickness T1 of the first sub-middle layer SML1 of the first middle layer ML1 (ie, T2>T1).

[0154] For example, refer to Figure 5 The second middle layer ML2 may include a first sub-middle layer SML1 and a second sub-middle layer SML2 respectively disposed in the first sub-emission region SEA1 and the second sub-emission region SEA2 of the second emission region EA2. A second thickness T2 of the second sub-middle layer SML2 of the second middle layer ML2 may be greater than a first thickness T1 of the first sub-middle layer SML1 of the second middle layer ML2 (ie, T2>T1).

[0155] For example, refer to Figure 5The third middle layer ML3 may include a first sub-middle layer SML1 and a second sub-middle layer SML2 respectively disposed in the first sub-emission area SEA1 and the second sub-emission area SEA2 of the third emission area EA3. The second thickness T2 of the second sub-middle layer SML2 of the third middle layer ML3 may be greater than the first thickness T1 of the first sub-middle layer SML1 of the third middle layer ML3 (ie, T2>T1).

[0156] For example, refer to Figure 4 The fourth middle layer ML4 may include a first sub-middle layer SML1 and a second sub-middle layer SML2 respectively disposed in the first sub-emission region SEA1 and the second sub-emission region SEA2 of the fourth emission region EA4. The second sub-middle layer SML2 of the fourth middle layer ML4 may be thicker than the first sub-middle layer SML1 of the fourth middle layer ML4.

[0157] The thickness of the first sub intermediate layer SML1 and the second sub intermediate layer SML2 of each of the first, second, third, and fourth intermediate layers ML1, ML2, ML3, and ML4 may refer to a size measured in the third direction DR3.

[0158] Each of the first intermediate layer ML1, the second intermediate layer ML2, the third intermediate layer ML3, and the fourth intermediate layer ML4 may include a light emitting layer (eg, Figure 6 The first red light-emitting layer REML1 in the embodiment of the present invention and the first functional layer and the second functional layer located above and below the light-emitting layer. The first functional layer may include, for example, a hole transport layer and / or a hole injection layer. The second functional layer disposed on the light-emitting layer may be optional. That is, each of the first intermediate layer ML1, the second intermediate layer ML2, the third intermediate layer ML3 and the fourth intermediate layer ML4 may not include the second functional layer. The second functional layer may include an electron transport layer and / or an electron injection layer.

[0159] Each of the first intermediate layer ML1, the second intermediate layer ML2, the third intermediate layer ML3, and the fourth intermediate layer ML4 may include two or more light-emitting units sequentially stacked between the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, or the fourth pixel electrode PE4 and the common electrode CE, and a charge generation layer disposed between the two or more light-emitting units. In this case, the first light-emitting element ED1, the second light-emitting element ED2, the third light-emitting element ED3, and the fourth light-emitting element may be series light-emitting elements. Since each of the first light-emitting element ED1, the second light-emitting element ED2, the third light-emitting element ED3, and the fourth light-emitting element has a structure in which a plurality of light-emitting units are stacked, the color purity and light emission efficiency of the display device 1 may be improved.

[0160] Each of the two or more light-emitting units included in each of the first intermediate layer ML1, the second intermediate layer ML2, the third intermediate layer ML3, and the fourth intermediate layer ML4 may include a light-emitting layer and a first functional layer and a second functional layer located below and above the light-emitting layer. The charge generation layer included in each of the first intermediate layer ML1, the second intermediate layer ML2, the third intermediate layer ML3, and the fourth intermediate layer ML4 may include a negative charge generation layer and a positive charge generation layer. Due to the presence of the negative charge generation layer and the positive charge generation layer, the light emission efficiency of the OLED as a tandem light-emitting element equipped with a plurality of light-emitting layers can be further improved.

[0161] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host of the negative charge generation layer may include an organic material, and the dopant of the negative charge generation layer may include a metal material. The positive charge generation layer may be a p-type charge generation layer (CGL). The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host of the positive charge generation layer may include an organic material, and the dopant of the positive charge generation layer may include a metal material.

[0162] Figure 6 yes Figure 5 Detailed cross-sectional view of a first light-emitting element of a display device.

[0163] Reference Figure 6 , the first light emitting element ED1 may include a first pixel electrode PE1 , a common electrode CE and a first middle layer ML1 .

[0164] The first middle layer ML1 may be disposed between the first pixel electrode PE1 and the common electrode CE. The first middle layer ML1 may include a first sub-middle layer SML1 and a second sub-middle layer SML2.

[0165] The first sub intermediate layer SML1 may be disposed in the first sub emission region SEA1 of the first emission region EA1, and the second sub intermediate layer SML2 may be disposed in the second sub emission region SEA2 of the first emission region EA1.

[0166] The first sub intermediate layer SML1 may include a first light emitting unit EU1 on the first pixel electrode PE1. The first light emitting unit EU1 may include a first red light emitting layer REML1. In other words, the first sub intermediate layer SML1 may include a first red light emitting layer REML1 disposed in the first sub emission area SEA1 between the first pixel electrode PE1 and the common electrode CE.

[0167] The second sub-intermediate layer SML2 may include a first light emitting unit EU2_1 on the first pixel electrode PE1, a charge generation layer CGL on the first light emitting unit EU2_1, and a second light emitting unit EU2_2 on the charge generation layer CGL. The first light emitting unit EU2_1 of the second sub-intermediate layer SML2 may include a first red light emitting layer REML1, and the second light emitting unit EU2_2 of the second sub-intermediate layer SML2 may include a second red light emitting layer REML2. In other words, the second sub-intermediate layer SML2 may include a first red light emitting layer REML1, a charge generation layer CGL, and a second red light emitting layer REML2 sequentially stacked in the second sub-emission area SEA2 between the first pixel electrode PE1 and the common electrode CE along the third direction DR3.

[0168] The first red light emitting layer REML1 may be a common layer commonly positioned for the first sub intermediate layer SML1 and the second sub intermediate layer SML2. In other words, the first sub intermediate layer SML1 and the second sub intermediate layer SML2 may share the first red light emitting layer REML1.

[0169] The first sub-middle layer SML1 and the second sub-middle layer SML2 may include different numbers of light emitting layers. For example, the number of red light emitting layers included in the second sub-middle layer SML2 may be greater than the number of red light emitting layers included in the first sub-middle layer SML1. Figure 6 As shown in FIG. 1 , the first sub-intermediate layer SML1 may include one red light emitting layer (ie, the first red light emitting layer REML1 ), and the second sub-intermediate layer SML2 may include two red light emitting layers (ie, the first red light emitting layer REML1 and the second red light emitting layer REML2 ).

[0170] The first sub-middle layer SML1 and the second sub-middle layer SML2 may have different thicknesses. For example, the second thickness T2 of the second sub-middle layer SML2 may be greater than the first thickness T1 of the first sub-middle layer SML1. In other words, because the second sub-middle layer SML2 further includes a charge generation layer CGL and a second red light emitting layer REML2 compared to the first sub-middle layer SML1, the second thickness T2 of the second sub-middle layer SML2 may be greater than the first thickness T1 of the first sub-middle layer SML1 (i.e., T2>T1).

[0171] Both the first red light emitting layer REML1 and the second red light emitting layer REML2 may emit red light.

[0172] The first red light emitting layer REML1 may include an organic material layer. The organic material layer of the first red light emitting layer REML1 may include a host material including carbazole biphenyl (CBP) or 1,3-bis(carbazole-9-yl) (mCP), and may be a phosphorescent material including a dopant, the dopant including at least one selected from bis(1-phenylisoquinoline) iridium acetylacetonate (PIQIr(acac)), bis(1-phenylquinoline) iridium acetylacetonate (PQIr(acac)), tris(1-phenylquinoline) iridium (PQIr) and platinum octaethylporphyrin (PtOEP). Optionally, the organic material layer of the first red light emitting layer REML1 may include PBD:Eu(DBM) 3 (Phen) and / or perylene fluorescent materials, but the present disclosure is not limited thereto.

[0173] The second red light emitting layer REML2 may include an organic material layer. The organic material layer of the second red light emitting layer REML2 may be the same as the organic material layer of the first red light emitting layer REML1.

[0174] Since the number of red light-emitting layers included in the first sub-middle layer SML1 is different from the number of red light-emitting layers included in the second sub-middle layer SML2, the first sub-middle layer SML1 and the second sub-middle layer SML2 can emit red light with different gray levels (or brightness) according to the electric field between the first pixel electrode PE1 and the common electrode CE. For example, the sub-middle layer having a relatively small number of light-emitting layers can first emit light in response to the voltage (e.g., pixel voltage) applied to the first pixel electrode PE1. For example, when the pixel voltage is applied to the first pixel electrode PE1, the first sub-middle layer SML1 can emit red light with a second gray level, and the second sub-middle layer SML2 can emit red light with a first gray level lower than the second gray level or darker red light. That is, for each given pixel voltage, the sub-middle layer having a relatively large number of light-emitting layers can emit red light with a lower gray level. Therefore, even at a lower voltage, a wider range of gray levels can be presented in each pixel. As a result, the range of data voltages used to generate pixel voltages can be extended.

[0175] Figure 7 yes Figure 5 Detailed cross-sectional view of a first light-emitting element of a display device.

[0176] Reference Figure 7 , the first light emitting element ED1 may include a first pixel electrode PE1 , a common electrode CE and a first middle layer ML1 .

[0177] The first middle layer ML1 may be disposed between the first pixel electrode PE1 and the common electrode CE. The first middle layer ML1 may include a first sub-middle layer SML1 and a second sub-middle layer SML2.

[0178] The first sub intermediate layer SML1 may be disposed in the first sub emission region SEA1 of the first emission region EA1, and the second sub intermediate layer SML2 may be disposed in the second sub emission region SEA2 of the first emission region EA1.

[0179] The first sub-intermediate layer SML1 may include a first light emitting unit EU1 on the first pixel electrode PE1. The first light emitting unit EU1 may include a hole injection layer HIL, a hole transport layer HTL, a first red light emitting layer REML1, an electron transport layer ETL, and an electron injection layer EIL sequentially stacked in the third direction DR3. In other words, the first sub-intermediate layer SML1 may include a hole injection layer HIL, a hole transport layer HTL, a first red light emitting layer REML1, an electron transport layer ETL, and an electron injection layer EIL sequentially stacked in the first sub-emission region SEA1 of the first emission region EA1 along the third direction DR3.

[0180] The second sub-middle layer SML2 may include a first light emitting unit EU2_1 disposed on the first pixel electrode PE1 in the second sub-emission area SEA2 of the first emission area EA1, a charge generation layer CGL located on the first light emitting unit EU2_1, and a second light emitting unit EU2_2 located on the charge generation layer CGL. The first light emitting unit EU2_1 of the second sub-middle layer SML2 may include a hole injection layer HIL, a hole transport layer HTL, a first red light emitting layer REML1, and an electron transport layer ETL sequentially stacked in the third direction DR3. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL sequentially stacked on the electron transport layer ETL along the third direction DR3. The second light emitting unit EU2_2 may include a hole transport layer HTL', a second red light emitting layer REML2, an electron transport layer ETL', and an electron injection layer EIL sequentially stacked on the positive charge generation layer pCGL along the third direction DR3. In other words, the second sub-intermediate layer SML2 may include a hole injection layer HIL, a hole transport layer HTL, a first red light emitting layer REML1, an electron transport layer ETL, a negative charge generation layer nCGL, a positive charge generation layer pCGL, a hole transport layer HTL', a second red light emitting layer REML2, an electron transport layer ETL' and an electron injection layer EIL sequentially stacked in the second sub-emission area SEA2 of the first emission area EA1 between the first pixel electrode PE1 and the common electrode CE along the third direction DR3.

[0181] The hole injection layer HIL, the hole transport layer HTL, the first red light emitting layer REML1, the electron transport layer ETL, and the electron injection layer EIL may be a common layer commonly positioned in the first sub-intermediate layer SML1 and the second sub-intermediate layer SML2. In other words, the first sub-intermediate layer SML1 and the second sub-intermediate layer SML2 may share the hole injection layer HIL, the hole transport layer HTL, the first red light emitting layer REML1, the electron transport layer ETL, and the electron injection layer EIL.

[0182] The first sub-middle layer SML1 and the second sub-middle layer SML2 may include different numbers of light emitting layers. For example, the number of red light emitting layers included in the second sub-middle layer SML2 may be greater than the number of red light emitting layers included in the first sub-middle layer SML1. Figure 7 As shown in FIG. 1 , the first sub-intermediate layer SML1 may include one red light emitting layer (ie, the first red light emitting layer REML1 ), and the second sub-intermediate layer SML2 may include two red light emitting layers (ie, the first red light emitting layer REML1 and the second red light emitting layer REML2 ).

[0183] The first sub-middle layer SML1 and the second sub-middle layer SML2 may have different thicknesses. For example, the second sub-middle layer SML2 may be thicker than the first sub-middle layer SML1. For example, when the distance from the bottom surface of the first middle layer ML1 to the top surface of the uppermost light-emitting layer (i.e., the first red light-emitting layer REML1) of the first sub-middle layer SML1 in the third direction DR3 is defined as the first thickness T1 of the first sub-middle layer SML1, and the distance from the bottom surface of the first middle layer ML1 to the top surface of the uppermost light-emitting layer (i.e., the second red light-emitting layer REML2) of the second sub-middle layer SML2 in the third direction DR3 is defined as the second thickness T2 of the second sub-middle layer SML2, the second thickness T2 may be greater than the first thickness T1.

[0184] The first thickness T1 and the second thickness T2 may be defined as dimensions measured in the third direction DR3 .

[0185] The bottom surface of the first intermediate layer ML1 can be defined as the interface between the first pixel electrode PE1 and the first intermediate layer ML1 (for example, the interface between the first pixel electrode PE1 and the hole injection layer HIL of the first intermediate layer ML1), the top surface of the uppermost light-emitting layer of the first sub-intermediate layer SML1 (that is, the first red light-emitting layer REML1) can be defined as the interface between the uppermost light-emitting layer of the first sub-intermediate layer SML1 and the uppermost electron transport layer of the first sub-intermediate layer SML1 (that is, the electron transport layer ETL), and the top surface of the uppermost light-emitting layer of the second sub-intermediate layer SML2 (that is, the second red light-emitting layer REML2) can be defined as the interface between the uppermost light-emitting layer of the second sub-intermediate layer SML2 (that is, the second red light-emitting layer REML2) and the uppermost electron transport layer of the second sub-intermediate layer SML2 (that is, the electron transport layer ETL').

[0186] The topmost light-emitting layer of the first sub-intermediate layer SML1 (i.e., the first red light-emitting layer REML1) can be defined as the light-emitting layer of the first sub-intermediate layer SML1 which is farthest from the first pixel electrode PE1 in the third direction DR3, the topmost light-emitting layer of the second sub-intermediate layer SML2 (i.e., the second red light-emitting layer REML2) can be defined as the light-emitting layer of the second sub-intermediate layer SML2 which is farthest from the first pixel electrode PE1 in the third direction DR3, the topmost electron transport layer of the first sub-intermediate layer SML1 (i.e., the electron transport layer ETL) can be defined as the electron transport layer of the first sub-intermediate layer SML1 which is farthest from the first pixel electrode PE1 in the third direction DR3, and the topmost electron transport layer of the second sub-intermediate layer SML2 (i.e., the electron transport layer ETL') can be defined as the electron transport layer of the second sub-intermediate layer SML2 which is farthest from the first pixel electrode PE1 in the third direction DR3.

[0187] Figure 7 The first red light emitting layer REML1 and the second red light emitting layer REML2 may be respectively Figure 6 The first red light emitting layer REML1 and the second red light emitting layer REML2 are the same.

[0188] Reference Figure 7 The first sub-intermediate layer SML1 may have a 1-stage series structure including a red light-emitting layer (i.e., the first red light-emitting layer REML1), and the second sub-intermediate layer SML2 may have a 2-stage series structure including two red light-emitting layers (i.e., the first red light-emitting layer REML1 and the second red light-emitting layer REML2) respectively arranged in the first light-emitting unit EU2_1 and the second light-emitting unit EU2_2 and a charge generation layer (i.e., the charge generation layer CGL) is placed between the two red light-emitting layers.

[0189] Figure 8yes Figure 5 Detailed cross-sectional view of a first light-emitting element of a display device.

[0190] Figure 8 The first light emitting element ED1 and Figure 7 The difference between the corresponding part of the embodiment is that it also includes at least one of the first red light auxiliary layer AX1 and the second red light auxiliary layer AX2. Figure 8 The first light emitting element ED1 is highlighted with Figure 7 The difference of the first light emitting element ED1.

[0191] Reference Figure 8 , the first red light auxiliary layer AX1 can also be disposed between the hole transport layer HTL and the first red light emitting layer REML1, and the second red light auxiliary layer AX2 can also be disposed between the hole transport layer HTL' and the second red light emitting layer REML2. The first red light auxiliary layer AX1 can improve the light emission efficiency of the first red light emitting layer REML1, and the second red light auxiliary layer AX2 can improve the light emission efficiency of the second red light emitting layer REML2. In other words, the first red light auxiliary layer AX1 and the second red light auxiliary layer AX2 can improve the light emission efficiency of the first red light emitting layer REML1 and the second red light emitting layer REML2 by controlling the hole charge balance.

[0192] For example, the first light emitting element ED1 may further include at least one of an electron blocking layer and a buffer layer. The electron blocking layer and the buffer layer may be disposed between the hole transport layer HTL and the first red light emitting layer REML1. The electron blocking layer and the buffer layer may be disposed between the hole transport layer HTL' and the second red light emitting layer REML2. The electron blocking layer may prevent electrons from being injected into the hole transport layer HTL / HTL'. The buffer layer may compensate for the resonance distance according to the wavelength of light emitted from the first red light emitting layer REML1 or the second red light emitting layer REML2.

[0193] Fig. 9 yes Figure 5 Detailed cross-sectional view of a first light-emitting element of a display device.

[0194] Reference Fig. 9 , the first light emitting element ED1 may include a first pixel electrode PE1 , a common electrode CE and a first middle layer ML1 .

[0195] The first middle layer ML1 may be disposed between the first pixel electrode PE1 and the common electrode CE. The first middle layer ML1 may include a first sub-middle layer SML1 and a second sub-middle layer SML2.

[0196] The first sub intermediate layer SML1 may be disposed in the first sub emission region SEA1 of the first emission region EA1, and the second sub intermediate layer SML2 may be disposed in the second sub emission region SEA2 of the first emission region EA1.

[0197] The first sub-intermediate layer SML1 may include a first light emitting unit EU1_1 on the first pixel electrode PE1, a first charge generation layer CGL1 on the first light emitting unit EU1_1, and a second light emitting unit EU1_2 on the first charge generation layer CGL1. The first light emitting unit EU1_1 may include a hole injection layer HIL, a hole transport layer HTL, a first red light emitting layer REML1, and an electron transport layer ETL sequentially stacked in a third direction DR3. The first charge generation layer CGL1 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL sequentially stacked on the electron transport layer ETL along the third direction DR3. The second light emitting unit EU1_2 may include a hole transport layer HTL', a second red light emitting layer REML2, an electron transport layer ETL', and an electron injection layer EIL sequentially stacked on the positive charge generation layer pCGL along the third direction DR3. In other words, the first sub-intermediate layer SML1 may include a hole injection layer HIL, a hole transport layer HTL, a first red light emitting layer REML1, an electron transport layer ETL, a negative charge generating layer nCGL, a positive charge generating layer pCGL, a hole transport layer HTL', a second red light emitting layer REML2, an electron transport layer ETL' and an electron injection layer EIL sequentially stacked in the first sub-emission area SEA1 between the first pixel electrode PE1 and the common electrode CE along the third direction DR3.

[0198] The second sub-intermediate layer SML2 may include a first light emitting unit EU2_1 on the first pixel electrode PE1, a first charge generation layer CGL1 on the first light emitting unit EU2_1, a second light emitting unit EU2_2 on the first charge generation layer CGL1, a second charge generation layer CGL2 on the second light emitting unit EU2_2, and a third light emitting unit EU2_3 on the second charge generation layer CGL2. The first light emitting unit EU2_1 may include a hole injection layer HIL, a hole transport layer HTL, a first red light emitting layer REML1, and an electron transport layer ETL sequentially stacked on the first pixel electrode PE1 along a third direction DR3. The first charge generation layer CGL1 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL sequentially stacked on the electron transport layer ETL along the third direction DR3. The second light emitting unit EU2_2 may include a hole transport layer HTL', a second red light emitting layer REML2, and an electron transport layer ETL' sequentially stacked on the positive charge generation layer pCGL along the third direction DR3. The second charge generation layer CGL2 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL sequentially stacked on the electron transport layer ETL' along the third direction DR3. The third light emitting unit EU2_3 may include a hole transport layer HTL", a third red light emitting layer REML3, an electron transport layer ETL", and an electron injection layer EIL sequentially stacked on the positive charge generation layer pCGL of the second charge generation layer CGL2 along the third direction DR3. In other words, the second sub-intermediate layer SML2 may include a hole injection layer HIL, a hole transport layer HTL, a first red light emitting layer REML1, an electron transport layer ETL, a negative charge generation layer nCGL and a positive charge generation layer pCGL of the first charge generation layer CGL1, a hole transport layer HTL', a second red light emitting layer REML2, an electron transport layer ETL', a negative charge generation layer nCGL and a positive charge generation layer pCGL of the second charge generation layer CGL2, a hole transport layer HTL", a third red light emitting layer REML3, an electron transport layer ETL" and an electron injection layer EIL sequentially stacked in the second sub-emission area SEA2 between the first pixel electrode PE1 and the common electrode CE along the third direction DR3.

[0199] The hole injection layer HIL, the hole transport layer HTL, the first red light emitting layer REML1, the electron transport layer ETL, the negative charge generation layer nCGL and the positive charge generation layer pCGL of the first charge generation layer CGL1, the hole transport layer HTL', the second red light emitting layer REML2, the electron transport layer ETL' and the electron injection layer EIL may be common layers commonly positioned in the first sub-intermediate layer SML1 and the second sub-intermediate layer SML2. In other words, the first sub-intermediate layer SML1 and the second sub-intermediate layer SML2 may share the hole injection layer HIL, the hole transport layer HTL, the first red light emitting layer REML1, the electron transport layer ETL, the negative charge generation layer nCGL and the positive charge generation layer pCGL of the first charge generation layer CGL1, the hole transport layer HTL', the second red light emitting layer REML2, the electron transport layer ETL' and the electron injection layer EIL.

[0200] The first sub-middle layer SML1 and the second sub-middle layer SML2 may include different numbers of light emitting layers. For example, the number of red light emitting layers included in the second sub-middle layer SML2 may be greater than the number of red light emitting layers included in the first sub-middle layer SML1. Fig. 9 As shown in the figure, the first sub-intermediate layer SML1 may include two red light-emitting layers (i.e., the first red light-emitting layer REML1 and the second red light-emitting layer REML2), and the second sub-intermediate layer SML2 may include three red light-emitting layers (i.e., the first red light-emitting layer REML1, the second red light-emitting layer REML2 and the third red light-emitting layer REML3).

[0201] The first sub-middle layer SML1 and the second sub-middle layer SML2 may have different thicknesses. For example, the second sub-middle layer SML2 may be thicker than the first sub-middle layer SML1. For example, when the distance from the bottom surface of the first middle layer ML1 to the top surface of the uppermost light-emitting layer of the first sub-middle layer SML1 (i.e., the second red light-emitting layer REML2) is defined as the first thickness T1 of the first sub-middle layer SML1, and the distance from the bottom surface of the first middle layer ML1 to the top surface of the uppermost light-emitting layer of the second sub-middle layer SML2 (i.e., the third red light-emitting layer REML3) is defined as the second thickness T2 of the second sub-middle layer SML2, the second thickness T2 may be greater than the first thickness T1.

[0202] Fig. 9 The first red light emitting layer REML1 and the second red light emitting layer REML2 may be respectively Figure 6 The first red light emitting layer REML1 and the second red light emitting layer REML2 are the same. Fig. 9 The third red light emitting layer REML3 can be Figure 6 The first red light emitting layer REML1 or the second red light emitting layer REML2 is the same.

[0203] Reference Fig. 9 The first sub-intermediate layer SML1 may have a 2-stage series structure including two red light-emitting layers (i.e., the first red light-emitting layer REML1 and the second red light-emitting layer REML2) respectively arranged in the first light-emitting unit EU1_1 and the second light-emitting unit EU1_2, and one charge generation layer (i.e., the first charge generation layer CGL1) is placed between the two red light-emitting layers, and the second sub-intermediate layer SML2 may have a 3-stage series structure including three red light-emitting layers (i.e., the first red light-emitting layer REML1, the second red light-emitting layer REML2 and the third red light-emitting layer REML3) respectively arranged in the first light-emitting unit EU2_1, the second light-emitting unit EU2_2 and the third light-emitting unit EU2_3, and two charge generation layers (i.e., the first charge generation layer CGL1 and the second charge generation layer CGL2) are placed between the three red light-emitting layers.

[0204] Fig.10 yes Figure 5 Detailed cross-sectional view of a second light-emitting element of a display device.

[0205] Reference Fig.10 , the second light emitting element ED2 may include a second pixel electrode PE2 , a common electrode CE and a second middle layer ML2 .

[0206] The second middle layer ML2 may be disposed between the second pixel electrode PE2 and the common electrode CE. The second middle layer ML2 may include a first sub-middle layer SML1 and a second sub-middle layer SML2. The first sub-middle layer SML1 may be disposed in the first sub-emission region SEA1 of the second emission region EA2, and the second sub-middle layer SML2 may be disposed in the second sub-emission region SEA2 of the second emission region EA2.

[0207] The first sub-intermediate layer SML1 may include a first light emitting unit EU1 on the second pixel electrode PE2. The first light emitting unit EU1 may include a first blue light emitting layer BEML1. In other words, the first sub-intermediate layer SML1 may include a first blue light emitting layer BEML1 disposed in the first sub-emission area SEA1 between the second pixel electrode PE2 and the common electrode CE.

[0208] The second sub-intermediate layer SML2 may include a first light emitting unit EU2_1 on the second pixel electrode PE2, a charge generation layer CGL on the first light emitting unit EU2_1, and a second light emitting unit EU2_2 on the charge generation layer CGL. The first light emitting unit EU2_1 may include a first blue light emitting layer BEML1, and the second light emitting unit EU2_2 may include a second blue light emitting layer BEML2. In other words, the second sub-intermediate layer SML2 may include a first blue light emitting layer BEML1, a charge generation layer CGL, and a second blue light emitting layer BEML2 sequentially stacked in the second sub-emission area SEA2 between the second pixel electrode PE2 and the common electrode CE along the third direction DR3.

[0209] The first blue light emitting layer BEML1 may be a common layer commonly positioned in the first sub intermediate layer SML1 and the second sub intermediate layer SML2. In other words, the first sub intermediate layer SML1 and the second sub intermediate layer SML2 may share the first blue light emitting layer BEML1.

[0210] The first sub-middle layer SML1 and the second sub-middle layer SML2 may include different numbers of light-emitting layers. For example, the number of blue light-emitting layers included in the second sub-middle layer SML2 may be greater than the number of blue light-emitting layers included in the first sub-middle layer SML1. Fig.10 As shown in FIG. 1 , the first sub intermediate layer SML1 may include one blue light emitting layer (ie, the first blue light emitting layer BEML1 ), and the second sub intermediate layer SML2 may include two blue light emitting layers (ie, the first blue light emitting layer BEML1 and the second blue light emitting layer BEML2 ).

[0211] The first sub-middle layer SML1 and the second sub-middle layer SML2 may have different thicknesses. For example, the second thickness T2 of the second sub-middle layer SML2 may be greater than the first thickness T1 of the first sub-middle layer SML1. In other words, because the second sub-middle layer SML2 further includes a charge generation layer CGL and a second blue light emitting layer BEML2 compared to the first sub-middle layer SML1, the second sub-middle layer SML2 may be thicker than the first sub-middle layer SML1.

[0212] The first and second blue light emitting layers BEML1 and BEML2 may emit blue light.

[0213] The first blue light emitting layer BEML1 may include an organic material layer. The organic material layer of the first blue light emitting layer BEML1 may include a host material including CBP or mCP, and may include (4,6-F2ppy) 2 The phosphorescent material may be a dopant material of Irpic or L2BD111, but the present disclosure is not limited thereto.

[0214] The second blue light emitting layer BEML2 may include an organic material layer. The organic material layer of the second blue light emitting layer BEML2 may be the same as the organic material layer of the first blue light emitting layer BEML1.

[0215] Since the number of blue light-emitting layers included in the first sub-middle layer SML1 is different from the number of blue light-emitting layers included in the second sub-middle layer SML2, the first sub-middle layer SML1 and the second sub-middle layer SML2 can emit blue light with different gray levels (or brightness) according to the electric field between the second pixel electrode PE2 and the common electrode CE. For example, the sub-middle layer having a relatively small number of light-emitting layers can first emit light in response to the voltage (e.g., pixel voltage) applied to the second pixel electrode PE2. For example, when the pixel voltage is applied to the second pixel electrode PE2, the first sub-middle layer SML1 can emit blue light with a second gray level, and the second sub-middle layer SML2 can emit blue light with a first gray level lower than the second gray level or darker blue light. That is, for each given pixel voltage, the sub-middle layer having a relatively large number of light-emitting layers can emit blue light with a lower gray level. Therefore, even at a lower voltage, a wider range of gray levels can be presented in each pixel. As a result, the range of data voltages used to generate pixel voltages can be extended.

[0216] The second light emitting element ED2 may be similar to the Figures 7 to 9 The first light emitting element ED1 of any one of them has the same structure.

[0217] The fourth light emitting element may have the same configuration as the second light emitting element ED2.

[0218] Reference Fig.10 The first sub-intermediate layer SML1 may have a 1-stage series structure including a blue light-emitting layer (i.e., a first blue light-emitting layer BEML1), and the second sub-intermediate layer SML2 may have a 2-stage series structure including two blue light-emitting layers (i.e., a first blue light-emitting layer BEML1 and a second blue light-emitting layer BEML2) respectively arranged in the first light-emitting unit EU2_1 and the second light-emitting unit EU2_2 and a charge generation layer (i.e., a charge generation layer CGL) is placed between the two blue light-emitting layers.

[0219] Fig.11 yes Figure 5 Detailed cross-sectional view of a third light-emitting element of a display device.

[0220] Reference Fig.11 The third light emitting element ED3 may include a third pixel electrode PE3, a common electrode CE and a third middle layer ML3.

[0221] The third middle layer ML3 may be disposed between the third pixel electrode PE3 and the common electrode CE. The third middle layer ML3 may include a first sub-middle layer SML1 and a second sub-middle layer SML2. The first sub-middle layer SML1 may be disposed in the first sub-emission area SEA1 of the third emission area EA3, and the second sub-middle layer SML2 may be disposed in the second sub-emission area SEA2 of the third emission area EA3.

[0222] The first sub-intermediate layer SML1 may include a first light emitting unit EU1 on the third pixel electrode PE3. The first light emitting unit EU1 may include a first green light emitting layer GEML1. In other words, the first sub-intermediate layer SML1 may include a first green light emitting layer GEML1 disposed in the first sub-emission area SEA1 between the third pixel electrode PE3 and the common electrode CE.

[0223] The second sub-intermediate layer SML2 may include a first light emitting unit EU2_1 on the third pixel electrode PE3, a charge generation layer CGL on the first light emitting unit EU2_1, and a second light emitting unit EU2_2 on the charge generation layer CGL. The first light emitting unit EU2_1 may include a first green light emitting layer GEML1, and the second light emitting unit EU2_2 may include a second green light emitting layer GEML2. In other words, the second sub-intermediate layer SML2 may include a first green light emitting layer GEML1, a charge generation layer CGL, and a second green light emitting layer GEML2 sequentially stacked in the second sub-emission area SEA2 between the third pixel electrode PE3 and the common electrode CE along the third direction DR3.

[0224] The first green light emitting layer GEML1 may be a common layer commonly positioned in the first sub intermediate layer SML1 and the second sub intermediate layer SML2. In other words, the first sub intermediate layer SML1 and the second sub intermediate layer SML2 may share the first green light emitting layer GEML1.

[0225] The first sub-middle layer SML1 and the second sub-middle layer SML2 may include different numbers of light-emitting layers. For example, the number of green light-emitting layers included in the second sub-middle layer SML2 may be greater than the number of green light-emitting layers included in the first sub-middle layer SML1. Fig.11 As shown in FIG. 1 , the first sub intermediate layer SML1 may include one green light emitting layer (ie, the first green light emitting layer GEML1 ), and the second sub intermediate layer SML2 may include two green light emitting layers (ie, the first green light emitting layer GEML1 and the second green light emitting layer GEML2 ).

[0226] The first sub-middle layer SML1 and the second sub-middle layer SML2 may have different thicknesses. For example, the second thickness T2 of the second sub-middle layer SML2 may be greater than the first thickness T1 of the first sub-middle layer SML1. In other words, because the second sub-middle layer SML2 further includes a charge generation layer CGL and a second green light emitting layer GEML2 compared to the first sub-middle layer SML1, the second sub-middle layer SML2 may be thicker than the first sub-middle layer SML1.

[0227] The first green light emitting layer GEML1 and the second green light emitting layer GEML2 may emit green light.

[0228] The first green light emitting layer GEML1 may include an organic material layer. The organic material layer of the first green light emitting layer GEML1 may include a host material including CBP or mCP, and may include a host material including f-tris(2-phenylpyridine)iridium (Ir(ppy) 3 ) of the dopant material, but the present disclosure is not limited thereto. Optionally, the organic material layer of the first green light emitting layer GEML1 may include tris(8-hydroxyquinoline)aluminum (Alq 3 ) of the fluorescent material, but the present disclosure is not limited thereto.

[0229] The second green light emitting layer GEML2 may include an organic material layer. The organic material layer of the second green light emitting layer GEML2 may be the same as the organic material layer of the first green light emitting layer GEML1.

[0230] Since the number of green light-emitting layers included in the first sub-middle layer SML1 is different from the number of green light-emitting layers included in the second sub-middle layer SML2, the first sub-middle layer SML1 and the second sub-middle layer SML2 can emit green light with different gray levels (or brightness) according to the electric field between the third pixel electrode PE3 and the common electrode CE. For example, the sub-middle layer having a relatively small number of light-emitting layers can first emit light in response to the voltage (e.g., pixel voltage) applied to the third pixel electrode PE3. For example, when the pixel voltage is applied to the third pixel electrode PE3, the first sub-middle layer SML1 can emit green light with a second gray level, and the second sub-middle layer SML2 can emit green light with a first gray level lower than the second gray level or darker green light. That is, for each given pixel voltage, the sub-middle layer having a relatively large number of light-emitting layers can emit green light with a lower gray level. Therefore, even at a lower voltage, a wider range of gray levels can be presented in each pixel. As a result, the range of data voltages used to generate pixel voltages can be extended.

[0231] Reference Fig.11The first sub-intermediate layer SML1 may have a 1-stage series structure including a green light-emitting layer (i.e., the first green light-emitting layer GEML1), and the second sub-intermediate layer SML2 may have a 2-stage series structure including two green light-emitting layers (i.e., the first green light-emitting layer GEML1 and the second green light-emitting layer GEML2) respectively arranged in the first light-emitting unit EU2_1 and the second light-emitting unit EU2_2 and a charge generation layer (i.e., the charge generation layer CGL) is placed between the two green light-emitting layers.

[0232] The third light emitting element ED3 may be similar to Figures 7 to 9 The first light emitting element ED1 of any one of them has the same structure.

[0233] In the previous embodiment, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the second middle layer ML2 may have the same thickness as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1, respectively. For example, the relatively thick second sub-middle layer SML2 of the second middle layer ML2 may have the same thickness as the relatively thick second sub-middle layer SML2 of the first middle layer ML1. For example, the relatively thin first sub-middle layer SML1 of the second middle layer ML2 may have the same thickness as the relatively thin first sub-middle layer SML1 of the first middle layer ML1.

[0234] Furthermore, in the previous embodiment, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the second middle layer ML2 may respectively have the same number of light-emitting layers as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1. For example, the relatively thick second sub-middle layer SML2 of the second middle layer ML2 may include the same number of light-emitting layers as the also relatively thick second sub-middle layer SML2 of the first middle layer ML1. For example, the relatively thin first sub-middle layer SML1 of the second middle layer ML2 may include the same number of light-emitting layers as the also relatively thin first sub-middle layer SML1 of the first middle layer ML1.

[0235] In addition, in the previous embodiment, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the third middle layer ML3 and the first sub-middle layer SML1 and the second sub-middle layer SML2 of the fourth middle layer ML4 may also have the same thickness or height as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1, respectively.

[0236] In the previous embodiment, the light emitting layer commonly positioned in different sub-intermediate layers of the intermediate layer and formed as one body may be separated between different sub-emission regions. Figure 6, the first red light emitting layer REML1 of the first sub-intermediate layer SML1 and the first red light emitting layer REML1 of the second sub-intermediate layer SML2 may be separated by the interface between the first sub-emission region SEA1 and the second sub-emission region SEA2. In other words, the first red light emitting layer REML1 of the first sub-intermediate layer SML1 and the first red light emitting layer REML1 of the second sub-intermediate layer SML2 corresponding to the first sub-emission region SEA1 and the second sub-emission region SEA2, respectively, may not be connected but may be physically separated.

[0237] For example, refer to Fig.10 , the first blue light emitting layer BEML1 of the first sub-intermediate layer SML1 and the first blue light emitting layer BEML1 of the second sub-intermediate layer SML2 may be separated by the interface between the first sub-emission area SEA1 and the second sub-emission area SEA2. In other words, the first blue light emitting layer BEML1 of the first sub-intermediate layer SML1 and the first blue light emitting layer BEML1 of the second sub-intermediate layer SML2 corresponding to the first sub-emission area SEA1 and the second sub-emission area SEA2, respectively, may not be connected but may be physically separated.

[0238] For example, refer to Fig.11 , the first green light emitting layer GEML1 of the first sub-intermediate layer SML1 and the first green light emitting layer GEML1 of the second sub-intermediate layer SML2 may be separated by the interface between the first sub-emission region SEA1 and the second sub-emission region SEA2. In other words, the first green light emitting layer GEML1 of the first sub-intermediate layer SML1 and the first green light emitting layer GEML1 of the second sub-intermediate layer SML2 corresponding to the first sub-emission region SEA1 and the second sub-emission region SEA2, respectively, may not be connected but may be physically separated.

[0239] Fig.12 is a display device according to one or more embodiments of the present disclosure along Figure 4 A cross-sectional view taken along line II'.

[0240] Fig.12 The display device and Figure 5 The display device of FIG. 1 is different in that the first intermediate layer ML1, the second intermediate layer ML2, the third intermediate layer ML3 and the fourth intermediate layer ML4 have different thicknesses. In one or more embodiments, the fourth intermediate layer ML4 may have the same thickness as the second intermediate layer ML2.

[0241] Reference Fig.12, the intermediate layers of different pixels may have different thicknesses. For example, the first sub-intermediate layer SML1 of the first intermediate layer ML1 may have a different thickness from the first sub-intermediate layer SML1 of the second intermediate layer ML2 corresponding to the first sub-intermediate layer SML1 of the first intermediate layer ML1. For example, the third thickness T3 of the first sub-intermediate layer SML1 of the second intermediate layer ML2 may be greater than the first thickness T1 of the first sub-intermediate layer SML1 of the first intermediate layer ML1. In this example, the intermediate layers of different pixels may include different numbers of light-emitting layers. For example, the number of light-emitting layers included in the first sub-intermediate layer SML1 of the first intermediate layer ML1 may be different from the number of light-emitting layers included in the first sub-intermediate layer SML1 of the second intermediate layer ML2. For example, the number of light-emitting layers included in the first sub-intermediate layer SML1 of the second intermediate layer ML2 may be greater than the number of light-emitting layers included in the first sub-intermediate layer SML1 of the first intermediate layer ML1.

[0242] like Fig.12 As shown in the figure, the first thickness T1 of the first sub-middle layer SML1 of the first middle layer ML1, the second thickness T2 of the second sub-middle layer SML2 of the first middle layer ML1, the third thickness T3 of the first sub-middle layer SML1 of the second middle layer ML2, the fourth thickness T4 of the second sub-middle layer SML2 of the second middle layer ML2, the fifth thickness T5 of the first sub-middle layer SML1 of the third middle layer ML3, the sixth thickness T6 of the second sub-middle layer SML2 of the third middle layer ML3, the thickness of the first sub-middle layer SML1 of the fourth middle layer ML4, and the thickness of the second sub-middle layer SML2 of the fourth middle layer ML4 may all be different from each other. Fig.12 The first middle layer ML1 can be Figure 7 The first middle layer ML1 has the same construction, except Fig.12 The second middle layer ML2 includes a blue light emitting layer instead of a red light emitting layer, Fig.12 The second middle layer ML2 can be Figure 8 The first middle layer ML1 has the same construction as Fig.12 The third middle layer ML3 includes a green light emitting layer instead of a red light emitting layer, Fig.12 The third middle layer ML3 can be Fig. 9 The first middle layers ML1 have the same construction. Fig.12 The fourth intermediate layer can be Figure 8 The first middle layers ML1 have the same construction.

[0243] Fig.13 is a display device according to one or more embodiments of the present disclosure along Figure 4 A cross-sectional view taken along line II'.

[0244] Fig.13 The display device and Figure 5 The display device of FIG. 5 is different in that it further includes a color filter layer CFL to emit white light in addition to the first to fourth intermediate layers ML1 to ML2 to ML3 and ML4 .

[0245] The color filter layer CFL may be disposed on the encapsulation layer ENC. For example, the color filter layer CFL may be disposed on the second encapsulation inorganic film TFE3 of the encapsulation layer ENC.

[0246] The color filter layer CFL may include, for example, a light blocking layer BM, a plurality of color filters CF1 , CF2 , and CF3 , and an overcoat layer OC.

[0247] The light blocking layer BM may be disposed on the encapsulation layer ENC. The light blocking layer BM may include a plurality of holes OPT1, OPT2, and OPT3 disposed to overlap with the plurality of emission areas EA1, EA2, and EA3, respectively. For example, the first hole OPT1 may overlap with the first emission area EA1, the second hole OPT2 may overlap with the second emission area EA2, and the third hole OPT3 may overlap with the third emission area EA3. The area or size of the holes OPT1, OPT2, and OPT3 may be larger than the area or size of the emission areas EA1, EA2, and EA3 defined by the embankment PDL. Since the holes OPT1, OPT2, and OPT3 of the light blocking layer BM are formed to be larger than the emission areas EA1, EA2, and EA3, the light emitted from the emission areas EA1, EA2, and EA3 may become visible to the user not only in front of the display device 1 but also from the side of the display device 1.

[0248] The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black. However, the present disclosure is not limited thereto. The light blocking layer BM may improve color reproducibility by preventing light intrusion and color mixing between the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0249] Color filters CF1, CF2, and CF3 may be disposed to correspond to the emission areas EA1, EA2, and EA3, respectively. For example, color filters CF1, CF2, and CF3 may be disposed on the light blocking layer BM including holes OPT1, OPT2, and OPT3 corresponding to the emission areas EA1, EA2, and EA3.

[0250] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are set to correspond to different emission areas. The color filters CF1, CF2, and CF3 may include a colorant (such as a pigment or a dye) that can absorb light of a wavelength other than a specific wavelength range, and may be positioned to correspond to the color of light emitted from the emission areas EA1, EA2, and EA3, respectively. For example, the first color filter CF1 may be positioned to overlap with the first emission area EA1, and may be a red color filter that can transmit only red light through it, the second color filter CF2 may be positioned to overlap with the second emission area EA2, and may be a blue color filter that can transmit only blue light through it, and the third color filter CF3 may be positioned to overlap with the third emission area EA3, and may be a green color filter that can transmit only green light through it.

[0251] The color filters CF1, CF2 and CF3 may be spaced apart from each other on the light blocking layer BM. The color filters CF1, CF2 and CF3 may cover the holes OPT1, OPT2 and OPT3. The color filters CF1, CF2 and CF3 may have an area larger than the area of ​​the holes OPT1, OPT2 and OPT3, but only to the extent that they can be fully spaced apart from each other on the light blocking layer BM. However, the present disclosure is not limited thereto. Alternatively, the color filters CF1, CF2 and CF3 may be positioned to partially overlap each other. Different color filters may overlap each other on the light blocking layer BM that is not overlapped with the emission areas EA1, EA2 and EA3. Since the color filters CF1, CF2 and CF3 are positioned to overlap each other, the intensity of the reflected light of the external light may be reduced. In addition, by adjusting the layout, shape and area of ​​the color filters CF1, CF2 and CF3, the color of the reflected light of the external light may be controlled.

[0252] The overcoat layer OC may be disposed on the color filters CF1, CF2, and CF3 and may flatten the tops of the color filters CF1, CF2, and CF3. The overcoat layer OC may be a colorless transparent layer having no color in the visible wavelength range. For example, the overcoat layer OC may include a colorless transparent organic material such as an acrylic resin.

[0253] The first light emitting element ED1 may include a first pixel electrode PE1, a common electrode CE, and a first middle layer ML1. The first middle layer ML1 may be disposed between the first pixel electrode PE1 and the common electrode CE. The first middle layer ML1 may be located on the first pixel electrode PE1 to overlap the first pixel electrode PE1.

[0254] The second light emitting element ED2 may include a second pixel electrode PE2, a common electrode CE, and a second middle layer ML2. The second middle layer ML2 may be disposed between the second pixel electrode PE2 and the common electrode CE. The second middle layer ML2 may be located on the second pixel electrode PE2 to overlap the second pixel electrode PE2.

[0255] The third light emitting element ED3 may include a third pixel electrode PE3, a common electrode CE, and a third intermediate layer ML3. The third intermediate layer ML3 may be disposed between the third pixel electrode PE3 and the common electrode CE. The third intermediate layer ML3 may be located on the third pixel electrode PE3 to overlap the third pixel electrode PE3.

[0256] The first intermediate layer ML1, the second intermediate layer ML2, and the third intermediate layer ML3 may emit white light. For example, the first intermediate layer ML1 may have a series structure in which a plurality of light emitting units providing light of different colors are stacked in a vertical direction (e.g., a third direction DR3). For example, the second intermediate layer ML2 and the third intermediate layer ML3 may also have a series structure in which a plurality of light emitting units providing light of different colors are stacked in a vertical direction (e.g., a third direction DR3).

[0257] like Fig.13 As shown in , the intermediate layer located in one emission area may have different thicknesses. For example, the intermediate layer located on one pixel electrode may have different thicknesses in the emission area overlapping with the pixel electrode. For example, the first intermediate layer ML1 overlapping (or contacting) the first pixel electrode PE1 and disposed in the first emission area EA1 may have different thicknesses in the first emission area EA1, i.e., a first thickness T1 and a second thickness T2 (e.g., T2>T1).

[0258] For example, the second middle layer ML2 overlapping (or contacting) the second pixel electrode PE2 and disposed in the second emission area EA2 may have different thicknesses in the second emission area EA2, ie, a first thickness T1 and a second thickness T2 (eg, T2>T1).

[0259] For example, the third middle layer ML3 overlapping (or contacting) the third pixel electrode PE3 and disposed in the third emission area EA3 may have different thicknesses, ie, a first thickness T1 and a second thickness T2 (eg, T2 > T1 ), in the third emission area EA3 .

[0260] Here, the thickness of each intermediate layer refers to a dimension measured in the third direction DR3.

[0261] Each of the first middle layer ML1, the second middle layer ML2 and the third middle layer ML3 may include a plurality of sub-middle layers. Fig.13As shown in , the first middle layer ML1 may include a first sub-middle layer SML1 and a second sub-middle layer SML2 respectively disposed in the first sub-emission area SEA1 and the second sub-emission area SEA2 of the first emission area EA1. The second thickness T2 of the second sub-middle layer SML2 of the first middle layer ML1 may be greater than the first thickness T1 of the first sub-middle layer SML1 of the first middle layer ML1 (i.e., T2>T1).

[0262] For example, Fig.13 As shown in , the second middle layer ML2 may include a first sub-middle layer SML1 and a second sub-middle layer SML2 respectively disposed in the first sub-emission area SEA1 and the second sub-emission area SEA2 of the second emission area EA2. The second thickness T2 of the second sub-middle layer SML2 of the second middle layer ML2 may be greater than the first thickness T1 of the first sub-middle layer SML1 of the second middle layer ML2 (i.e., T2>T1).

[0263] For example, Fig.13 As shown in , the third middle layer ML3 may include a first sub-middle layer SML1 and a second sub-middle layer SML2 respectively disposed in the first sub-emission area SEA1 and the second sub-emission area SEA2 of the third emission area EA3. The second thickness T2 of the second sub-middle layer SML2 of the third middle layer ML3 may be greater than the first thickness T1 of the first sub-middle layer SML1 of the third middle layer ML3 (i.e., T2>T1).

[0264] Here, the thickness of each sub intermediate layer refers to a size of each sub intermediate layer measured in the third direction DR3.

[0265] In one or more embodiments, the dam PDL may further include a fourth emission area EA4 exposing the fourth pixel electrode PE4, the light blocking layer BM may further include a fourth hole arranged to overlap with the fourth emission area EA4, and the color filter layer CFL may further include a second color filter CF2 arranged to overlap with the fourth emission area EA4 and allowing only blue light to pass therethrough.

[0266] Fig.14 yes Fig.13 A cross-sectional view of a first light-emitting element of a display device.

[0267] Reference Fig.14 , the first light emitting element ED1 may include a first pixel electrode PE1 , a common electrode CE and a first middle layer ML1 .

[0268] The first middle layer ML1 may be disposed between the first pixel electrode PE1 and the common electrode CE. The first middle layer ML1 may include a first sub-middle layer SML1 and a second sub-middle layer SML2. The first sub-middle layer SML1 may be disposed in a first sub-emission area SEA1 of the first emission area EA1, and the second sub-middle layer SML2 may be disposed in a second sub-emission area SEA2 of the first emission area EA1.

[0269] The first sub-intermediate layer SML1 may include a first light emitting unit EU1_1 on the first pixel electrode PE1, a first charge generation layer CGL1 on the first light emitting unit EU1_1, a second light emitting unit EU1_2 on the first charge generation layer CGL1, a second charge generation layer CGL2 on the second light emitting unit EU1_2, and a third light emitting unit EU1_3 on the second charge generation layer CGL2.

[0270] The first light emitting unit EU1_1 may include a hole injection layer HIL, a hole transport layer HTL, a first blue light emitting layer BEML1, and an electron transport layer ETL sequentially stacked on the first pixel electrode PE1 along the third direction DR3. The first charge generation layer CGL1 may be disposed on the electron transport layer ETL. The second light emitting unit EU1_2 may include a hole transport layer HTL', a first red light emitting layer REML1, and an electron transport layer ETL' sequentially stacked on the first charge generation layer CGL1 along the third direction DR3. The second charge generation layer CGL2 may be disposed on the electron transport layer ETL'. The third light emitting unit EU1_3 may include a hole transport layer HTL", a first green light emitting layer GEML1, an electron transport layer ETL", and an electron injection layer EIL sequentially stacked on the second charge generation layer CGL2 along the third direction DR3. In other words, the first sub-intermediate layer SML1 may include a hole injection layer HIL, a hole transport layer HTL, a first blue light-emitting layer BEML1, an electron transport layer ETL, a first charge generation layer CGL1, a hole transport layer HTL', a first red light-emitting layer REML1, an electron transport layer ETL', a second charge generation layer CGL2, a hole transport layer HTL", a first green light-emitting layer GEML1, an electron transport layer ETL" and an electron injection layer EIL sequentially stacked in the first sub-emission area SEA1 between the first pixel electrode PE1 and the common electrode CE along the third direction DR3.

[0271] The second sub-intermediate layer SML2 may include a first light emitting unit EU2_1 on the first pixel electrode PE1, a first charge generation layer CGL1 disposed on the first light emitting unit EU2_1, a second light emitting unit EU2_2 on the first charge generation layer CGL1, a second charge generation layer CGL2 on the second light emitting unit EU2_2, a third light emitting unit EU2_3 disposed on the second charge generation layer CGL2, a third charge generation layer CGL3 on the third light emitting unit EU2_3, and a fourth light emitting unit EU2_4 on the third charge generation layer CGL3.

[0272] The first light-emitting unit EU2_1 may include a hole injection layer HIL, a hole transport layer HTL, a first blue light-emitting layer BEML1, and an electron transport layer ETL sequentially stacked on the first pixel electrode PE1 along the third direction DR3. The first charge generation layer CGL1 may be disposed on the electron transport layer ETL. The second light-emitting unit EU2_2 may include a hole transport layer HTL', a second blue light-emitting layer BEML2, and an electron transport layer ETL' sequentially stacked on the first charge generation layer CGL1 along the third direction DR3. The second charge generation layer CGL2 may be disposed on the electron transport layer ETL'. The third light-emitting unit EU2_3 may include a hole transport layer HTL", a second red light-emitting layer REML2, and an electron transport layer ETL" sequentially stacked on the second charge generation layer CGL2 along the third direction DR3. The third charge generation layer CGL3 may be disposed on the electron transport layer ETL". The fourth light emitting unit EU2_4 may be disposed on the third charge generation layer CGL3, and may include a hole transport layer HTL"', a second green light emitting layer GEML2, an electron transport layer ETL"', and an electron injection layer EIL sequentially stacked on the third charge generation layer CGL3 along the third direction DR3. In other words, the second sub-intermediate layer SML2 may include a second sub-emission region sequentially stacked between the first pixel electrode PE1 and the common electrode CE along the third direction DR3. The hole injection layer HIL, the hole transport layer HTL, the first blue light-emitting layer BEML1, the electron transport layer ETL, the first charge generation layer CGL1, the hole transport layer HTL', the second blue light-emitting layer BEML2, the electron transport layer ETL', the second charge generation layer CGL2, the hole transport layer HTL", the second red light-emitting layer REML2, the electron transport layer ETL", the third charge generation layer CGL3, the hole transport layer HTL'", the second green light-emitting layer GEML2, the electron transport layer ETL' and the electron injection layer EIL in the domain SEA2.

[0273] The hole injection layer HIL, the hole transport layer HTL, the first blue light emitting layer BEML1, the electron transport layer ETL, the first charge generating layer CGL1, the hole transport layer HTL', the electron transport layer ETL', the second charge generating layer CGL2, the hole transport layer HTL", the electron transport layer ETL" and the electron injection layer EIL may be common layers commonly positioned in the first sub-middle layer SML1 and the second sub-middle layer SML2. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 may share the hole injection layer HIL, the hole transport layer HTL, the first blue light emitting layer BEML1, the electron transport layer ETL, the first charge generating layer CGL1, the hole transport layer HTL', the electron transport layer ETL', the second charge generating layer CGL2, the hole transport layer HTL", the electron transport layer ETL" and the electron injection layer EIL.

[0274] The first and second blue light emitting layers BEML1 and BEML2 may emit blue light, the first and second red light emitting layers REML1 and REML2 may emit red light, and the first and second green light emitting layers GEML1 and GEML2 may emit green light.

[0275] The first sub-middle layer SML1 and the second sub-middle layer SML2 may have different numbers of light-emitting layers. For example, the number of light-emitting layers included in the second sub-middle layer SML2 may be greater than the number of light-emitting layers included in the first sub-middle layer SML1. Fig.14 As shown in the figure, the first sub-intermediate layer SML1 may include three light-emitting layers (i.e., a first blue light-emitting layer BEML1, a first red light-emitting layer REML1, and a first green light-emitting layer GEML1), and the second sub-intermediate layer SML2 may include four light-emitting layers (i.e., a first blue light-emitting layer BEML1, a second blue light-emitting layer BEML2, a second red light-emitting layer REML2, and a second green light-emitting layer GEML2).

[0276] The first sub-middle layer SML1 and the second sub-middle layer SML2 may have different thicknesses. For example, the second thickness T2 of the second sub-middle layer SML2 may be greater than the first thickness T1 of the first sub-middle layer SML1. For example, when the distance from the bottom surface of the first middle layer ML1 to the top surface of the uppermost light-emitting layer of the first sub-middle layer SML1 (i.e., the first green light-emitting layer GEML1) is defined as the first thickness T1, and the distance from the bottom surface of the first middle layer ML1 to the top surface of the uppermost light-emitting layer of the second sub-middle layer SML2 (i.e., the second green light-emitting layer GEML2) is defined as the second thickness T2, the second thickness T2 may be greater than the first thickness T1.

[0277] Reference Fig.14The first sub-intermediate layer SML1 may have a 3-stage series structure including three light-emitting layers (i.e., a first blue light-emitting layer BEML1, a first red light-emitting layer REML1, and a first green light-emitting layer GEML1) respectively arranged in the first light-emitting unit EU1_1, the second light-emitting unit EU1_2, and the third light-emitting unit EU1_3, and two charge generation layers (i.e., a first charge generation layer CGL1 and a second charge generation layer CGL2) are placed between the three light-emitting layers, and the second sub-intermediate layer SML2 may have a 4-stage series structure including four light-emitting layers (i.e., a first blue light-emitting layer BEML1, a second blue light-emitting layer BEML2, a second red light-emitting layer REML2, and a second green light-emitting layer GEML2) respectively arranged in the first light-emitting unit EU2_1, the second light-emitting unit EU2_2, the third light-emitting unit EU2_3, and the fourth light-emitting unit EU2_4, and three charge generation layers (i.e., a first charge generation layer CGL1, a second charge generation layer CGL2, and a third charge generation layer CGL3) are placed between the four light-emitting layers.

[0278] Since the number of light-emitting layers included in the first sub-middle layer SML1 is different from the number of light-emitting layers included in the second sub-middle layer SML2, the first sub-middle layer SML1 and the second sub-middle layer SML2 can emit white light with different gray levels (or brightness) according to the electric field between the first pixel electrode PE1 and the common electrode CE. For example, the sub-middle layer having a relatively small number of light-emitting layers can first emit light in response to the voltage (e.g., pixel voltage) applied to the first pixel electrode PE1. For example, when the pixel voltage is applied to the first pixel electrode PE1, the first sub-middle layer SML1 can emit white light with a second gray level, and the second sub-middle layer SML2 can emit white light with a first gray level lower than the second gray level or darker white light. That is, for each given pixel voltage, the sub-middle layer having a relatively large number of light-emitting layers can emit white light with a lower gray level. Therefore, even at a lower voltage, a wider range of gray levels can be presented in each pixel. As a result, the range of data voltages used to generate pixel voltages can be extended.

[0279] Fig.15 yes Fig.13 Detailed cross-sectional view of a second light-emitting element of a display device.

[0280] Reference Fig.15 , the second light emitting element ED2 may include a second pixel electrode PE2 , a common electrode CE and a second middle layer ML2 .

[0281] The second middle layer ML2 may be disposed between the second pixel electrode PE2 and the common electrode CE. The second middle layer ML2 may include a first sub-middle layer SML1 and a second sub-middle layer SML2. The first sub-middle layer SML1 may be disposed in the first sub-emission region SEA1 of the second emission region EA2, and the second sub-middle layer SML2 may be disposed in the second sub-emission region SEA2 of the second emission region EA2.

[0282] The first sub-intermediate layer SML1 may include a first light emitting unit EU1_1 on the second pixel electrode PE2, a first charge generation layer CGL1 on the first light emitting unit EU1_1, a second light emitting unit EU1_2 on the first charge generation layer CGL1, a second charge generation layer CGL2 on the second light emitting unit EU1_2, and a third light emitting unit EU1_3 on the second charge generation layer CGL2.

[0283] The first light emitting unit EU1_1 may include a hole injection layer HIL, a hole transport layer HTL, a first blue light emitting layer BEML1, and an electron transport layer ETL sequentially stacked on the second pixel electrode PE2 along the third direction DR3. The first charge generation layer CGL1 may be disposed on the electron transport layer ETL. The second light emitting unit EU1_2 may include a hole transport layer HTL', a first red light emitting layer REML1, and an electron transport layer ETL' sequentially stacked on the first charge generation layer CGL1 along the third direction DR3. The second charge generation layer CGL2 may be disposed on the electron transport layer ETL'. The third light emitting unit EU1_3 may include a hole transport layer HTL", a first green light emitting layer GEML1, an electron transport layer ETL", and an electron injection layer EIL sequentially stacked on the second charge generation layer CGL2 along the third direction DR3. In other words, the first sub-intermediate layer SML1 may include a hole injection layer HIL, a hole transport layer HTL, a first blue light-emitting layer BEML1, an electron transport layer ETL, a first charge generation layer CGL1, a hole transport layer HTL', a first red light-emitting layer REML1, an electron transport layer ETL', a second charge generation layer CGL2, a hole transport layer HTL", a first green light-emitting layer GEML1, an electron transport layer ETL" and an electron injection layer EIL sequentially stacked in the first sub-emission area SEA1 between the second pixel electrode PE2 and the common electrode CE along the third direction DR3.

[0284] The second sub-intermediate layer SML2 may include a first light emitting unit EU2_1 on the second pixel electrode PE2, a first charge generation layer CGL1 on the first light emitting unit EU2_1, a second light emitting unit EU2_2 on the first charge generation layer CGL1, a second charge generation layer CGL2 on the second light emitting unit EU2_2, a third light emitting unit EU2_3 disposed on the second charge generation layer CGL2, a third charge generation layer CGL3 on the third light emitting unit EU2_3, and a fourth light emitting unit EU2_4 on the third charge generation layer CGL3.

[0285] The first light-emitting unit EU2_1 may include a hole injection layer HIL, a hole transport layer HTL, a first blue light-emitting layer BEML1, and an electron transport layer ETL sequentially stacked on the second pixel electrode PE2 along the third direction DR3. The first charge generation layer CGL1 may be disposed on the electron transport layer ETL. The second light-emitting unit EU2_2 may include a hole transport layer HTL', a second blue light-emitting layer BEML2, and an electron transport layer ETL' sequentially stacked on the first charge generation layer CGL1 along the third direction DR3. The second charge generation layer CGL2 may be disposed on the electron transport layer ETL'. The third light-emitting unit EU2_3 may include a hole transport layer HTL", a second red light-emitting layer REML2, and an electron transport layer ETL" sequentially stacked on the second charge generation layer CGL2 along the third direction DR3. The third charge generation layer CGL3 may be disposed on the electron transport layer ETL". The fourth light emitting unit EU2_4 may include a hole transport layer HTL"', a second green light emitting layer GEML2, an electron transport layer ETL"' and an electron injection layer EIL sequentially stacked on the third charge generation layer CGL3 along the third direction DR3. In other words, the second sub-intermediate layer SML2 may include a hole injection layer HIL, a hole transport layer HTL, a first blue light emitting layer BEML1, an electron transport layer ETL, a first charge generation layer CGL1, a hole transport layer HTL', a second blue light emitting layer BEML2, an electron transport layer ETL', a second charge generation layer CGL2, a hole transport layer HTL", a second red light emitting layer REML2, an electron transport layer ETL", a third charge generation layer CGL3, a hole transport layer HTL"', a second green light emitting layer GEML2, an electron transport layer ETL"' and an electron injection layer EIL sequentially stacked in the second sub-emission area SEA2 between the second pixel electrode PE2 and the common electrode CE along the third direction DR3.

[0286] The hole injection layer HIL, the hole transport layer HTL, the first blue light emitting layer BEML1, the electron transport layer ETL, the first charge generating layer CGL1, the hole transport layer HTL', the electron transport layer ETL', the second charge generating layer CGL2, the hole transport layer HTL", the electron transport layer ETL" and the electron injection layer EIL may be common layers commonly positioned in the first sub-middle layer SML1 and the second sub-middle layer SML2. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 may share the hole injection layer HIL, the hole transport layer HTL, the first blue light emitting layer BEML1, the electron transport layer ETL, the first charge generating layer CGL1, the hole transport layer HTL', the electron transport layer ETL', the second charge generating layer CGL2, the hole transport layer HTL", the electron transport layer ETL" and the electron injection layer EIL.

[0287] The first and second blue light emitting layers BEML1 and BEML2 may emit blue light, the first and second red light emitting layers REML1 and REML2 may emit red light, and the first and second green light emitting layers GEML1 and GEML2 may emit green light.

[0288] The first sub-middle layer SML1 and the second sub-middle layer SML2 may include different numbers of light-emitting layers. For example, the number of light-emitting layers included in the second sub-middle layer SML2 may be greater than the number of light-emitting layers included in the first sub-middle layer SML1. Fig.15 As shown in the figure, the first sub-intermediate layer SML1 may include three light-emitting layers (i.e., a first blue light-emitting layer BEML1, a first red light-emitting layer REML1, and a first green light-emitting layer GEML1), and the second sub-intermediate layer SML2 may include four light-emitting layers (i.e., a first blue light-emitting layer BEML1, a second blue light-emitting layer BEML2, a second red light-emitting layer REML2, and a second green light-emitting layer GEML2).

[0289] The first sub-middle layer SML1 and the second sub-middle layer SML2 may have different thicknesses. For example, the second thickness T2 of the second sub-middle layer SML2 may be greater than the first thickness T1 of the first sub-middle layer SML1. For example, when the distance from the bottom surface of the second middle layer ML2 to the top surface of the uppermost light-emitting layer of the first sub-middle layer SML1 (i.e., the first green light-emitting layer GEML1) is defined as the first thickness T1, and the distance from the bottom surface of the second middle layer ML2 to the top surface of the uppermost light-emitting layer of the second sub-middle layer SML2 (i.e., the second green light-emitting layer GEML2) is defined as the second thickness T2, the second thickness T2 may be greater than the first thickness T1.

[0290] Reference Fig.15The first sub-intermediate layer SML1 may have a 3-stage series structure including three light-emitting layers (i.e., a first blue light-emitting layer BEML1, a first red light-emitting layer REML1, and a first green light-emitting layer GEML1) respectively arranged in the first light-emitting unit EU1_1, the second light-emitting unit EU1_2, and the third light-emitting unit EU1_3, and two charge generation layers (i.e., a first charge generation layer CGL1 and a second charge generation layer CGL2) are placed between the three light-emitting layers, and the second sub-intermediate layer SML2 may have a 4-stage series structure including four light-emitting layers (i.e., a first blue light-emitting layer BEML1, a second blue light-emitting layer BEML2, a second red light-emitting layer REML2, and a second green light-emitting layer GEML2) respectively arranged in the first light-emitting unit EU2_1, the second light-emitting unit EU2_2, the third light-emitting unit EU2_3, and the fourth light-emitting unit EU2_4, and three charge generation layers (i.e., a first charge generation layer CGL1, a second charge generation layer CGL2, and a third charge generation layer CGL3) are placed between the four light-emitting layers.

[0291] Since the number of light-emitting layers included in the first sub-middle layer SML1 is different from the number of light-emitting layers included in the second sub-middle layer SML2, the first sub-middle layer SML1 and the second sub-middle layer SML2 can emit white light with different gray levels (or brightness) according to the electric field between the second pixel electrode PE2 and the common electrode CE. For example, the sub-middle layer having a relatively small number of light-emitting layers can first emit light in response to the voltage (e.g., pixel voltage) applied to the second pixel electrode PE2. For example, when the pixel voltage is applied to the second pixel electrode PE2, the first sub-middle layer SML1 can emit white light with a second gray level, and the second sub-middle layer SML2 can emit white light with a first gray level lower than the second gray level or darker white light. That is, for each given pixel voltage, the sub-middle layer having a relatively large number of light-emitting layers can emit white light with a lower gray level. Therefore, even at a lower voltage, a wider range of gray levels can be presented in each pixel. As a result, the range of data voltages used to generate pixel voltages can be extended.

[0292] Fig.16 yes Fig.13 Detailed cross-sectional view of a third light-emitting element of a display device.

[0293] Reference Fig.16 The third light emitting element ED3 may include a third pixel electrode PE3, a common electrode CE and a third middle layer ML3.

[0294] The third middle layer ML3 may be disposed between the third pixel electrode PE3 and the common electrode CE. The third middle layer ML3 may include a first sub-middle layer SML1 and a second sub-middle layer SML2. The first sub-middle layer SML1 may be disposed in the first sub-emission area SEA1 of the third emission area EA3, and the second sub-middle layer SML2 may be disposed in the second sub-emission area SEA2 of the third emission area EA3.

[0295] The first sub-intermediate layer SML1 may include a first light emitting unit EU1_1 on the third pixel electrode PE3, a first charge generation layer CGL1 on the first light emitting unit EU1_1, a second light emitting unit EU1_2 on the first charge generation layer CGL1, a second charge generation layer CGL2 on the second light emitting unit EU1_2, and a third light emitting unit EU1_3 on the second charge generation layer CGL2.

[0296] The first light emitting unit EU1_1 may include a hole injection layer HIL, a hole transport layer HTL, a first blue light emitting layer BEML1, and an electron transport layer ETL sequentially stacked on the third pixel electrode PE3 along the third direction DR3. The first charge generation layer CGL1 may be disposed on the electron transport layer ETL. The second light emitting unit EU1_2 may include a hole transport layer HTL', a first red light emitting layer REML1, and an electron transport layer ETL' sequentially stacked on the first charge generation layer CGL1 along the third direction DR3. The second charge generation layer CGL2 may be disposed on the electron transport layer ETL'. The third light emitting unit EU1_3 may include a hole transport layer HTL", a first green light emitting layer GEML1, an electron transport layer ETL", and an electron injection layer EIL sequentially stacked on the second charge generation layer CGL2 along the third direction DR3. In other words, the first sub-intermediate layer SML1 may include a hole injection layer HIL, a hole transport layer HTL, a first blue light-emitting layer BEML1, an electron transport layer ETL, a first charge generation layer CGL1, a hole transport layer HTL', a first red light-emitting layer REML1, an electron transport layer ETL', a second charge generation layer CGL2, a hole transport layer HTL", a first green light-emitting layer GEML1, an electron transport layer ETL" and an electron injection layer EIL sequentially stacked in the first sub-emission area SEA1 between the third pixel electrode PE3 and the common electrode CE along the third direction DR3.

[0297] The second sub-intermediate layer SML2 may include a first light emitting unit EU2_1 on the third pixel electrode PE3, a first charge generation layer CGL1 on the first light emitting unit EU2_1, a second light emitting unit EU2_2 on the first charge generation layer CGL1, a second charge generation layer CGL2 on the second light emitting unit EU2_2, a third light emitting unit EU2_3 disposed on the second charge generation layer CGL2, a third charge generation layer CGL3 on the third light emitting unit EU2_3, and a fourth light emitting unit EU2_4 on the third charge generation layer CGL3.

[0298] The first light-emitting unit EU2_1 may include a hole injection layer HIL, a hole transport layer HTL, a first blue light-emitting layer BEML1, and an electron transport layer ETL sequentially stacked on the third pixel electrode PE3 along the third direction DR3. The first charge generation layer CGL1 may be disposed on the electron transport layer ETL. The second light-emitting unit EU2_2 may include a hole transport layer HTL', a second blue light-emitting layer BEML2, and an electron transport layer ETL' sequentially stacked on the first charge generation layer CGL1 along the third direction DR3. The second charge generation layer CGL2 may be disposed on the electron transport layer ETL'. The third light-emitting unit EU2_3 may include a hole transport layer HTL", a second red light-emitting layer REML2, and an electron transport layer ETL" sequentially stacked on the second charge generation layer CGL2 along the third direction DR3. The third charge generation layer CGL3 may be disposed on the electron transport layer ETL". The fourth light emitting unit EU2_4 may include a hole transport layer HTL"', a second green light emitting layer GEML2, an electron transport layer ETL"' and an electron injection layer EIL sequentially stacked on the third charge generation layer CGL3 along the third direction DR3. In other words, the second sub-intermediate layer SML2 may include a hole injection layer HIL, a hole transport layer HTL, a first blue light emitting layer BEML1, an electron transport layer ETL, a first charge generation layer CGL1, a hole transport layer HTL', a second blue light emitting layer BEML2, an electron transport layer ETL', a second charge generation layer CGL2, a hole transport layer HTL", a second red light emitting layer REML2, an electron transport layer ETL", a third charge generation layer CGL3, a hole transport layer HTL"', a second green light emitting layer GEML2, an electron transport layer ETL"' and an electron injection layer EIL sequentially stacked in the second sub-emission area SEA2 between the third pixel electrode PE3 and the common electrode CE along the third direction DR3.

[0299] The hole injection layer HIL, the hole transport layer HTL, the first blue light emitting layer BEML1, the electron transport layer ETL, the first charge generating layer CGL1, the hole transport layer HTL', the electron transport layer ETL', the second charge generating layer CGL2, the hole transport layer HTL", the electron transport layer ETL" and the electron injection layer EIL may be common layers commonly positioned in the first sub-middle layer SML1 and the second sub-middle layer SML2. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 may share the hole injection layer HIL, the hole transport layer HTL, the first blue light emitting layer BEML1, the electron transport layer ETL, the first charge generating layer CGL1, the hole transport layer HTL', the electron transport layer ETL', the second charge generating layer CGL2, the hole transport layer HTL", the electron transport layer ETL" and the electron injection layer EIL.

[0300] The first and second blue light emitting layers BEML1 and BEML2 may emit blue light, the first and second red light emitting layers REML1 and REML2 may emit red light, and the first and second green light emitting layers GEML1 and GEML2 may emit green light.

[0301] The first sub-middle layer SML1 and the second sub-middle layer SML2 may include different numbers of light-emitting layers. For example, the number of light-emitting layers included in the second sub-middle layer SML2 may be greater than the number of light-emitting layers included in the first sub-middle layer SML1. Fig.16 As shown in the figure, the first sub-intermediate layer SML1 may include three light-emitting layers (i.e., a first blue light-emitting layer BEML1, a first red light-emitting layer REML1, and a first green light-emitting layer GEML1), and the second sub-intermediate layer SML2 may include four light-emitting layers (i.e., a first blue light-emitting layer BEML1, a second blue light-emitting layer BEML2, a second red light-emitting layer REML2, and a second green light-emitting layer GEML2).

[0302] The first sub-middle layer SML1 and the second sub-middle layer SML2 may have different thicknesses. For example, the second thickness T2 of the second sub-middle layer SML2 may be greater than the first thickness T1 of the first sub-middle layer SML1. For example, when the distance from the bottom surface of the third middle layer ML3 to the top surface of the uppermost light-emitting layer of the first sub-middle layer SML1 (i.e., the first green light-emitting layer GEML1) is defined as the first thickness T1, and the distance from the bottom surface of the third middle layer ML3 to the top surface of the uppermost light-emitting layer of the second sub-middle layer SML2 (i.e., the second green light-emitting layer GEML2) is defined as the second thickness T2, the second thickness T2 may be greater than the first thickness T1.

[0303] Reference Fig.16The first sub-intermediate layer SML1 may have a 3-stage series structure including three light-emitting layers (i.e., a first blue light-emitting layer BEML1, a first red light-emitting layer REML1, and a first green light-emitting layer GEML1) respectively arranged in the first light-emitting unit EU1_1, the second light-emitting unit EU1_2, and the third light-emitting unit EU1_3, and two charge generation layers (i.e., a first charge generation layer CGL1 and a second charge generation layer CGL2) are placed between the three light-emitting layers, and the second sub-intermediate layer SML2 may have a 4-stage series structure including four light-emitting layers (i.e., a first blue light-emitting layer BEML1, a second blue light-emitting layer BEML2, a second red light-emitting layer REML2, and a second green light-emitting layer GEML2) respectively arranged in the first light-emitting unit EU2_1, the second light-emitting unit EU2_2, the third light-emitting unit EU2_3, and the fourth light-emitting unit EU2_4, and three charge generation layers (i.e., a first charge generation layer CGL1, a second charge generation layer CGL2, and a third charge generation layer CGL3) are placed between the four light-emitting layers.

[0304] Since the number of light-emitting layers included in the first sub-middle layer SML1 is different from the number of light-emitting layers included in the second sub-middle layer SML2, the first sub-middle layer SML1 and the second sub-middle layer SML2 can emit white light with different gray levels (or brightness) according to the electric field between the third pixel electrode PE3 and the common electrode CE. For example, the sub-middle layer having a relatively small number of light-emitting layers can first emit light in response to the voltage (e.g., pixel voltage) applied to the third pixel electrode PE3. For example, when the pixel voltage is applied to the third pixel electrode PE3, the first sub-middle layer SML1 can emit white light with a second gray level, and the second sub-middle layer SML2 can emit white light with a first gray level lower than the second gray level or darker white light. That is, for each given pixel voltage, the sub-middle layer having a relatively large number of light-emitting layers can emit white light with a lower gray level. Therefore, even at a lower voltage, a wider range of gray levels can be presented in each pixel. As a result, the range of data voltages used to generate pixel voltages can be extended.

[0305] exist Fig.13 In the embodiment of the present invention, the thicknesses of the first middle layer ML1, the second middle layer ML2 and the third middle layer ML3 may be the same as each other. In other words, the thicknesses of the first middle layer ML1, the second middle layer ML2 and the third middle layer ML3 may be the same as each other. Fig.12 Different than depicted in .

[0306] Fig.17 is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure.

[0307] Fig.17 The display device and Figure 4 The display device of the present invention differs in the shape of the intermediate layer and will be described below, highlighting the difference with Figure 4 The difference of display device 1.

[0308] Reference Fig.17 The first intermediate layer ML1 disposed in the first emission area EA1 between the first pixel electrode PE1 and the common electrode CE may include a first sub intermediate layer SML1 and a second sub intermediate layer SML2.

[0309] The first sub-middle layer SML1 of the first middle layer ML1 may be disposed in the first sub-emission region SEA1 of the first emission region EA1, and the second sub-middle layer SML2 of the first middle layer ML1 may be disposed in the second sub-emission region SEA2 of the first emission region EA1. As already mentioned above, the second sub-middle layer SML2 of the first middle layer ML1 may have a thickness greater than that of the first sub-middle layer SML1 of the first middle layer ML1. In addition, as already mentioned above, the second sub-middle layer SML2 of the first middle layer ML1 may include a greater number of light emitting layers than the first sub-middle layer SML1 of the first middle layer ML1. In a plan view, the first sub-middle layer SML1 of the first middle layer ML1 may be around the second sub-middle layer SML2 of the first middle layer ML1 (e.g., may surround the second sub-middle layer SML2 of the first middle layer ML1). For example, in a plan view, the second sub-middle layer SML2 of the first middle layer ML1 may have a rectangular shape, and the first sub-middle layer SML1 of the first middle layer ML1 may have a rectangular ring shape surrounding the second sub-middle layer SML2 of the first middle layer ML1.

[0310] The second middle layer ML2 disposed in the second emission area EA2 between the second pixel electrode PE2 and the common electrode CE may have the same configuration as the first middle layer ML1. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the second middle layer ML2 may have the same configuration as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1, respectively.

[0311] The third middle layer ML3 disposed in the third emission area EA3 between the third pixel electrode PE3 and the common electrode CE may have the same configuration as the first middle layer ML1. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the third middle layer ML3 may have the same configuration as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1, respectively.

[0312] The fourth intermediate layer ML4 disposed in the fourth emission area EA4 between the fourth pixel electrode PE4 and the common electrode CE may have the same configuration as the first intermediate layer ML1. In other words, the first sub-intermediate layer SML1 and the second sub-intermediate layer SML2 of the fourth intermediate layer ML4 may have the same configuration as the first sub-intermediate layer SML1 and the second sub-intermediate layer SML2 of the first intermediate layer ML1, respectively. In one or more embodiments, the fourth intermediate layer ML4 may have the same configuration as the second intermediate layer ML2. The fourth intermediate layer ML4 may emit light of the same color as the second intermediate layer ML2.

[0313] The first intermediate layer ML1 may emit red light, the second intermediate layer ML2 and the fourth intermediate layer ML4 may emit blue light, and the third intermediate layer ML3 may emit green light.

[0314] Fig.18 is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure.

[0315] Fig.18 The display device and Figure 4 The display device of the present invention differs in the shape of the intermediate layer and will be described below, highlighting the difference with Figure 4 The difference in display devices.

[0316] Reference Fig.18 The first intermediate layer ML1 disposed in the first emission area EA1 between the first pixel electrode PE1 and the common electrode CE may include a first sub intermediate layer SML1 and a second sub intermediate layer SML2.

[0317] The first sub-middle layer SML1 of the first middle layer ML1 may be disposed in the first sub-emission region SEA1 of the first emission region EA1, and the second sub-middle layer SML2 of the first middle layer ML1 may be disposed in the second sub-emission region SEA2 of the first emission region EA1. As already mentioned above, the second sub-middle layer SML2 of the first middle layer ML1 may have a thickness greater than that of the first sub-middle layer SML1 of the first middle layer ML1. In addition, as already mentioned above, the second sub-middle layer SML2 of the first middle layer ML1 may include a greater number of light emitting layers than the first sub-middle layer SML1 of the first middle layer ML1. In a plan view, the first sub-middle layer SML1 of the first middle layer ML1 may be around the second sub-middle layer SML2 of the first middle layer ML1 (e.g., may surround the second sub-middle layer SML2 of the first middle layer ML1). For example, in a plan view, the second sub-middle layer SML2 of the first middle layer ML1 may have a rhombus shape, and the first sub-middle layer SML1 of the first middle layer ML1 may have a rectangular ring shape surrounding the second sub-middle layer SML2 of the first middle layer ML1. Here, four vertices of the second sub-middle layer SML2 of the first middle layer ML1 may be positioned to face four sides of the first sub-middle layer SML1 of the first middle layer ML1. Four vertices of the second sub-middle layer SML2 of the first middle layer ML1 may contact four sides of the first sub-middle layer SML1 of the first middle layer ML1. Therefore, the first sub-middle layer SML1 of the first middle layer ML1 may be divided into four parts having a triangular shape.

[0318] The second middle layer ML2 disposed in the second emission area EA2 between the second pixel electrode PE2 and the common electrode CE may have the same configuration as the first middle layer ML1. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the second middle layer ML2 may have the same configuration as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1, respectively.

[0319] The third middle layer ML3 disposed in the third emission area EA3 between the third pixel electrode PE3 and the common electrode CE may have the same configuration as the first middle layer ML1. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the third middle layer ML3 may have the same configuration as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1, respectively.

[0320] The fourth middle layer ML4 disposed in the fourth emission area EA4 between the fourth pixel electrode PE4 and the common electrode CE may have the same configuration as the first middle layer ML1. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the fourth middle layer ML4 may have the same configuration as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1, respectively. At the same time, the fourth middle layer ML4 may have the same configuration as the second middle layer ML2. The fourth middle layer ML4 may emit light of the same color as the second middle layer ML2.

[0321] The first intermediate layer ML1 may emit red light, the second intermediate layer ML2 and the fourth intermediate layer ML4 may emit blue light, and the third intermediate layer ML3 may emit green light.

[0322] Fig.19 is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure.

[0323] Fig.19 The display device and Figure 4 The display device of the present invention differs in the shape of the intermediate layer and will be described below, highlighting the difference with Figure 4 The difference in display devices.

[0324] Reference Fig.19 The first intermediate layer ML1 disposed in the first emission area EA1 between the first pixel electrode PE1 and the common electrode CE may include a first sub intermediate layer SML1 and a second sub intermediate layer SML2.

[0325] The first sub-middle layer SML1 of the first middle layer ML1 may be disposed in the first sub-emission region SEA1 of the first emission region EA1, and the second sub-middle layer SML2 of the first middle layer ML1 may be disposed in the second sub-emission region SEA2 of the first emission region EA1. As already mentioned above, the second sub-middle layer SML2 of the first middle layer ML1 may have a thickness greater than that of the first sub-middle layer SML1 of the first middle layer ML1. In addition, as already mentioned above, the second sub-middle layer SML2 of the first middle layer ML1 may include a greater number of light emitting layers than the first sub-middle layer SML1 of the first middle layer ML1. In a plan view, the first sub-middle layer SML1 of the first middle layer ML1 may be around the second sub-middle layer SML2 of the first middle layer ML1 (e.g., may surround the second sub-middle layer SML2 of the first middle layer ML1). For example, in a plan view, the second sub-middle layer SML2 of the first middle layer ML1 may have a rectangular shape, and the first sub-middle layer SML1 of the first middle layer ML1 may have a rectangular ring shape surrounding the second sub-middle layer SML2 of the first middle layer ML1.

[0326] The second middle layer ML2 disposed in the second emission area EA2 between the second pixel electrode PE2 and the common electrode CE may have the same configuration as the first middle layer ML1. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the second middle layer ML2 may have the same configuration as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1, respectively. However, the second middle layer ML2 may have a size larger than that of the first middle layer ML1.

[0327] The third middle layer ML3 disposed in the third emission area EA3 between the third pixel electrode PE3 and the common electrode CE may have the same configuration as the first middle layer ML1. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the third middle layer ML3 may have the same configuration as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1, respectively. The third middle layer ML3 may have the same area as the first middle layer ML1.

[0328] The first intermediate layer ML1 may emit red light, the second intermediate layer ML2 may emit blue light, and the third intermediate layer ML3 may emit green light.

[0329] Fig. 20 is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure.

[0330] Fig. 20 The display device and Figure 4 The display device of the present invention differs in the shape of the intermediate layer and will be described below, highlighting the difference with Figure 4 The difference in display devices.

[0331] Reference Fig. 20 The first intermediate layer ML1 disposed in the first emission area EA1 between the first pixel electrode PE1 and the common electrode CE may include a first sub intermediate layer SML1 and a second sub intermediate layer SML2.

[0332] The first sub-middle layer SML1 of the first middle layer ML1 may be disposed in the first sub-emission region SEA1 of the first emission region EA1, and the second sub-middle layer SML2 of the first middle layer ML1 may be disposed in the second sub-emission region SEA2 of the first emission region EA1. As already mentioned above, the second sub-middle layer SML2 of the first middle layer ML1 may have a thickness greater than that of the first sub-middle layer SML1 of the first middle layer ML1. In addition, as already mentioned above, the second sub-middle layer SML2 of the first middle layer ML1 may include a greater number of light emitting layers than the first sub-middle layer SML1 of the first middle layer ML1. In a plan view, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1 may have a rectangular shape extending longer in the second direction DR2 than in the first direction DR1. The first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1 may be positioned to face each other in the first direction DR1.

[0333] The second middle layer ML2 disposed in the second emission area EA2 between the second pixel electrode PE2 and the common electrode CE may include a first sub-middle layer SML1 and a second sub-middle layer SML2. The first sub-middle layer SML1 of the second middle layer ML2 may be disposed in the first sub-emission area SEA1 of the second emission area EA2, and the second sub-middle layer SML2 of the second middle layer ML2 may be disposed in the second sub-emission area SEA2 of the second emission area EA2. As already mentioned above, the second sub-middle layer SML2 of the second middle layer ML2 may have a thickness greater than that of the first sub-middle layer SML1 of the second middle layer ML2. In addition, as already mentioned above, the second sub-middle layer SML2 of the second middle layer ML2 may include a greater number of light-emitting layers than the first sub-middle layer SML1 of the second middle layer ML2. In a plan view, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the second middle layer ML2 may have a rectangular shape extending longer in the second direction DR2 than in the first direction DR1. The first and second sub-middle layers SML1 and SML2 of the second middle layer ML2 may have sizes greater than those of the first and second sub-middle layers SML1 and SML2 of the first middle layer ML1 .

[0334] The third middle layer ML3 disposed in the third emission area EA3 between the third pixel electrode PE3 and the common electrode CE may have the same configuration as the first middle layer ML1. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the third middle layer ML3 may have the same configuration as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1, respectively.

[0335] In other words, in each unit pixel, the relatively thick second sub-intermediate layers SML2 of the first, second and third intermediate layers ML1, ML2 and ML3 may be located adjacent to each other.

[0336] The first intermediate layer ML1 may emit red light, the second intermediate layer ML2 may emit blue light, and the third intermediate layer ML3 may emit green light.

[0337] Fig.21 is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure.

[0338] Fig.21 The display device and Figure 4 The display device of the present invention differs in the shape of the intermediate layer and will be described below, highlighting the difference with Figure 4 The difference in display devices.

[0339] Reference Fig.21 The first intermediate layer ML1 disposed in the first emission area EA1 between the first pixel electrode PE1 and the common electrode CE may include a first sub intermediate layer SML1 and a second sub intermediate layer SML2.

[0340] The first sub-middle layer SML1 of the first middle layer ML1 may be disposed in the first sub-emission region SEA1 of the first emission region EA1, and the second sub-middle layer SML2 of the first middle layer ML1 may be disposed in the second sub-emission region SEA2 of the first emission region EA1. As already mentioned above, the second sub-middle layer SML2 of the first middle layer ML1 may have a thickness greater than that of the first sub-middle layer SML1 of the first middle layer ML1. In addition, as already mentioned above, the second sub-middle layer SML2 of the first middle layer ML1 may include a greater number of light emitting layers than the first sub-middle layer SML1 of the first middle layer ML1. In a plan view, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1 may have a rectangular shape extending longer in the first direction DR1 than in the second direction DR2. The first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1 may be positioned to face each other in the second direction DR2.

[0341] The second middle layer ML2 disposed in the second emission area EA2 between the second pixel electrode PE2 and the common electrode CE may include a first sub-middle layer SML1 and a second sub-middle layer SML2.

[0342] The first sub-middle layer SML1 of the second middle layer ML2 may be disposed in the first sub-emission region SEA1 of the second emission region EA2, and the second sub-middle layer SML2 of the second middle layer ML2 may be disposed in the second sub-emission region SEA2 of the second emission region EA2. As already mentioned above, the second sub-middle layer SML2 of the second middle layer ML2 may have a thickness greater than that of the first sub-middle layer SML1 of the second middle layer ML2. In addition, as already mentioned above, the second sub-middle layer SML2 of the second middle layer ML2 may include a greater number of light-emitting layers than the first sub-middle layer SML1 of the second middle layer ML2. In a plan view, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the second middle layer ML2 may have a rectangular shape that extends longer in the second direction DR2 than in the first direction DR1. The first sub-middle layer SML1 and the second sub-middle layer SML2 of the second middle layer ML2 may have a size greater than that of the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1.

[0343] The third middle layer ML3 disposed in the third emission area EA3 between the third pixel electrode PE3 and the common electrode CE may have the same configuration as the first middle layer ML1. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the third middle layer ML3 may have the same configuration as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1, respectively.

[0344] The first intermediate layer ML1 may emit red light, the second intermediate layer ML2 may emit blue light, and the third intermediate layer ML3 may emit green light.

[0345] Fig. 22 is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure.

[0346] Fig. 22 The display device and Figure 4 The display device of the present invention differs in the shape of the intermediate layer and will be described below, highlighting the difference with Figure 4 The difference in display devices.

[0347] Reference Fig. 22 The first intermediate layer ML1 disposed in the first emission area EA1 between the first pixel electrode PE1 and the common electrode CE may include a first sub intermediate layer SML1 and a second sub intermediate layer SML2.

[0348] The first sub-middle layer SML1 of the first middle layer ML1 may be disposed in the first sub-emission region SEA1 of the first emission region EA1, and the second sub-middle layer SML2 of the first middle layer ML1 may be disposed in the second sub-emission region SEA2 of the first emission region EA1. As already mentioned above, the second sub-middle layer SML2 of the first middle layer ML1 may have a thickness greater than that of the first sub-middle layer SML1 of the first middle layer ML1. In addition, as already mentioned above, the second sub-middle layer SML2 of the first middle layer ML1 may include a greater number of light emitting layers than the first sub-middle layer SML1 of the first middle layer ML1. In a plan view, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1 may have a rectangular shape extending longer in the second direction DR2 than in the first direction DR1. The first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1 may be positioned to face each other in the second direction DR2.

[0349] The second middle layer ML2 disposed in the second emission area EA2 between the second pixel electrode PE2 and the common electrode CE may have the same configuration as the first middle layer ML1. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the second middle layer ML2 may have the same configuration as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1, respectively.

[0350] The third middle layer ML3 disposed in the third emission area EA3 between the third pixel electrode PE3 and the common electrode CE may have the same configuration as the first middle layer ML1. In other words, the first sub-middle layer SML1 and the second sub-middle layer SML2 of the third middle layer ML3 may have the same configuration as the first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1, respectively. The third middle layer ML3 may be disposed between the first middle layer ML1 and the second middle layer ML2. The first middle layer ML1, the second middle layer ML2, and the third middle layer ML3 may be arranged in a row in the first direction DR1.

[0351] The first intermediate layer ML1 may emit red light, the second intermediate layer ML2 may emit blue light, and the third intermediate layer ML3 may emit green light.

[0352] Fig.23 is a plan view of a plurality of pixels of a display device according to one or more embodiments of the present disclosure, and Fig.24 It is along Fig.23 A cross-sectional view taken along line II-II'.

[0353] Reference Fig.23 and Fig.24The first middle layer ML1 disposed in the first emission area EA1 between the first pixel electrode PE1 and the common electrode CE may include a first sub-middle layer SML1, a second sub-middle layer SML2, and a third sub-middle layer SML3.

[0354] The first, second, and third sub-intermediate layers SML1, SML2, and SML3 of the first middle layer ML1 may be arranged in a row in the second direction DR2. The second sub-intermediate layer SML2 of the first middle layer ML1 may be disposed between the first and third sub-intermediate layers SML1 and SML3 of the first middle layer ML1.

[0355] The first, second, and third sub intermediate layers SML1, SML2, and SML3 of the first intermediate layer ML1 may be disposed in the first, second, and third sub emission regions SEA1, SEA2, and SEA3 of the first emission region EA1, respectively.

[0356] like Fig.24 As shown in , the first sub-intermediate layer SML1 of the first intermediate layer ML1 may include a first light emitting unit EU1_1, a first charge generation layer CGL1, and a second light emitting unit EU1_2 sequentially stacked on the first pixel electrode PE1 along the third direction DR3. The second sub-intermediate layer SML2 of the first intermediate layer ML1 may include a first light emitting unit EU2_1, a first charge generation layer CGL1, a second light emitting unit EU2_2, a second charge generation layer CGL2, and a third light emitting unit EU2_3 sequentially stacked on the first pixel electrode PE1 along the third direction DR3. The third sub-intermediate layer SML3 of the first intermediate layer ML1 may include a first light emitting unit EU3_1, a first charge generation layer CGL1, a second light emitting unit EU3_2, a second charge generation layer CGL2, a third light emitting unit EU3_3, a third charge generation layer CGL3, and a fourth light emitting unit EU3_4 sequentially stacked on the first pixel electrode PE1 along the third direction DR3.

[0357] like Fig.24As shown in the figure, the first light-emitting unit EU1_1 and the second light-emitting unit EU1_2 of the first sub-intermediate layer SML1 of the first intermediate layer ML1 may respectively include the first red light-emitting layer REML1 and the second red light-emitting layer REML2, and the first light-emitting unit EU2_1, the second light-emitting unit EU2_2 and the third light-emitting unit EU2_3 of the second sub-intermediate layer SML2 of the first intermediate layer ML1 may respectively include the first red light-emitting layer REML1, the second red light-emitting layer REML2 and the third red light-emitting layer REML3, and the first light-emitting unit EU3_1, the second light-emitting unit EU3_2, the third light-emitting unit EU3_3 and the fourth light-emitting unit EU3_4 of the third sub-intermediate layer SML3 of the first intermediate layer ML1 may respectively include the first red light-emitting layer REML1, the second red light-emitting layer REML2, the third red light-emitting layer REML3 and the fourth red light-emitting layer REML4.

[0358] In a plan view, the first sub-middle layer SML1, the second sub-middle layer SML2, and the third sub-middle layer SML3 of the first middle layer ML1 may have a rectangular shape extending longer in the second direction DR2 than in the first direction DR1. The first sub-middle layer SML1 and the second sub-middle layer SML2 of the first middle layer ML1 may be positioned to face each other in the second direction DR2, and the second sub-middle layer SML2 and the third sub-middle layer SML3 of the first middle layer ML1 may be positioned to face each other in the second direction DR2.

[0359] The first sub-middle layer SML1, the second sub-middle layer SML2, and the third sub-middle layer SML3 of the first middle layer ML1 may have different thicknesses. Fig.24 As shown in FIG. 1 , the second thickness T2 of the second sub-middle layer SML2 of the first middle layer ML1 may be greater than the first thickness T1 of the first sub-middle layer SML1 of the first middle layer ML1, and the third thickness T3 of the third sub-middle layer SML3 of the first middle layer ML1 may be greater than the second thickness T2 (i.e., T1 <T2<T3)。

[0360] The first sub-middle layer SML1, the second sub-middle layer SML2, and the third sub-middle layer SML3 of the first middle layer ML1 may include different numbers of light emitting layers. Fig.24 As shown in the figure, compared with the first sub-middle layer SML1 of the first middle layer ML1, the second sub-middle layer SML2 of the first middle layer ML1 may include a larger number of light-emitting layers (e.g., red light-emitting layers), and compared with the second sub-middle layer SML2 of the first middle layer ML1, the third sub-middle layer SML3 of the first middle layer ML1 may include a larger number of light-emitting layers (e.g., red light-emitting layers). Fig.24It is shown that the first sub-intermediate layer SML1 of the first intermediate layer ML1 includes two red light-emitting layers (i.e., the first red light-emitting layer REML1 and the second red light-emitting layer REML2), the second sub-intermediate layer SML2 of the first intermediate layer ML1 includes three red light-emitting layers (i.e., the first red light-emitting layer REML1, the second red light-emitting layer REML2 and the third red light-emitting layer REML3), and the third sub-intermediate layer SML3 of the first intermediate layer ML1 includes four red light-emitting layers (i.e., the first red light-emitting layer REML1, the second red light-emitting layer REML2, the third red light-emitting layer REML3 and the fourth red light-emitting layer REML4).

[0361] The second middle layer ML2 disposed in the second emission area EA2 between the second pixel electrode PE2 and the common electrode CE may include a first sub-middle layer SML1 , a second sub-middle layer SML2 , and a third sub-middle layer SML3 .

[0362] The first and third sub intermediate layers SML1, SML2, and SML3 of the second intermediate layer ML2 may be arranged in a row in the second direction DR2. The second sub intermediate layer SML2 of the second intermediate layer ML2 may be disposed between the first and third sub intermediate layers SML1 and SML3 of the second intermediate layer ML2.

[0363] The first, second, and third sub intermediate layers SML1, SML2, and SML3 of the second intermediate layer ML2 may be disposed in the first, second, and third sub emission regions SEA1, SEA2, and SEA3 of the second emission region EA2, respectively.

[0364] In a plan view, the first sub-middle layer SML1, the second sub-middle layer SML2, and the third sub-middle layer SML3 of the second middle layer ML2 may have a rectangular shape extending longer in the second direction DR2 than in the first direction DR1. The first sub-middle layer SML1 and the second sub-middle layer SML2 of the second middle layer ML2 may be positioned to face each other in the second direction DR2, and the second sub-middle layer SML2 and the third sub-middle layer SML3 of the second middle layer ML2 may be positioned to face each other in the second direction DR2.

[0365] The first sub-middle layer SML1, the second sub-middle layer SML2, and the third sub-middle layer SML3 of the second middle layer ML2 may have different thicknesses. For example, the thickness of the second sub-middle layer SML2 of the second middle layer ML2 may be greater than the thickness of the first sub-middle layer SML1 of the second middle layer ML2, and the thickness of the third sub-middle layer SML3 of the second middle layer ML2 may be greater than the thickness of the second sub-middle layer SML2 of the second middle layer ML2.

[0366] The first sub-middle layer SML1, the second sub-middle layer SML2, and the third sub-middle layer SML3 of the second middle layer ML2 may include different numbers of light-emitting layers. For example, compared with the first sub-middle layer SML1 of the second middle layer ML2, the second sub-middle layer SML2 of the second middle layer ML2 may include a larger number of light-emitting layers (e.g., blue light-emitting layers), and compared with the second sub-middle layer SML2 of the second middle layer ML2, the third sub-middle layer SML3 of the second middle layer ML2 may include a larger number of light-emitting layers (e.g., blue light-emitting layers).

[0367] The third middle layer ML3 disposed in the third emission area EA3 between the third pixel electrode PE3 and the common electrode CE may include a first sub-middle layer SML1 , a second sub-middle layer SML2 , and a third sub-middle layer SML3 .

[0368] The first, second and third sub intermediate layers SML1, SML2 and SML3 of the third intermediate layer ML3 may be arranged in a row in the second direction DR2. The second sub intermediate layer SML2 of the third intermediate layer ML3 may be disposed between the first and third sub intermediate layers SML1 and SML3 of the third intermediate layer ML3.

[0369] The first, second, and third sub intermediate layers SML1, SML2, and SML3 of the third intermediate layer ML3 may be disposed in the first, second, and third sub emission regions SEA1, SEA2, and SEA3 of the third emission region EA3, respectively.

[0370] In a plan view, the first sub-middle layer SML1, the second sub-middle layer SML2, and the third sub-middle layer SML3 of the third middle layer ML3 may have a rectangular shape extending longer in the second direction DR2 than in the first direction DR1. The first sub-middle layer SML1 and the second sub-middle layer SML2 of the third middle layer ML3 may be positioned to face each other in the second direction DR2, and the second sub-middle layer SML2 and the third sub-middle layer SML3 of the third middle layer ML3 may be positioned to face each other in the second direction DR2.

[0371] The first sub-middle layer SML1, the second sub-middle layer SML2, and the third sub-middle layer SML3 of the third middle layer ML3 may have different thicknesses. For example, the thickness of the second sub-middle layer SML2 of the third middle layer ML3 may be greater than the thickness of the first sub-middle layer SML1 of the third middle layer ML3, and the thickness of the third sub-middle layer SML3 of the third middle layer ML3 may be greater than the thickness of the second sub-middle layer SML2 of the third middle layer ML3.

[0372] The first sub-middle layer SML1, the second sub-middle layer SML2, and the third sub-middle layer SML3 of the third middle layer ML3 may include different numbers of light-emitting layers. For example, compared with the first sub-middle layer SML1 of the third middle layer ML3, the second sub-middle layer SML2 of the third middle layer ML3 may include a larger number of light-emitting layers (e.g., green light-emitting layers), and compared with the second sub-middle layer SML2 of the third middle layer ML3, the third sub-middle layer SML3 of the third middle layer ML3 may include a larger number of light-emitting layers (e.g., green light-emitting layers).

[0373] In each unit pixel, the third middle layer ML3 may be disposed between the first middle layer ML1 and the second middle layer ML2 .

[0374] The first intermediate layer ML1 may emit red light, the second intermediate layer ML2 may emit blue light, and the third intermediate layer ML3 may emit green light.

[0375] Reference Fig.23 and Fig.24 , the first sub-middle layer SML1 of the first middle layer ML1 may have a 2-stage series structure including two red light-emitting layers (i.e., the first red light-emitting layer REML1 and the second red light-emitting layer REML2) respectively disposed in the first light-emitting unit EU1_1 and the second light-emitting unit EU1_2, and a charge generation layer (i.e., the first charge generation layer CGL1) is disposed between the two red light-emitting layers, and the second sub-middle layer SML2 of the first middle layer ML1 may have three red light-emitting layers (i.e., the first red light-emitting layer REML1, the second red light-emitting layer REML2 and the third red light-emitting layer REML3) respectively disposed in the first light-emitting unit EU2_1, the second light-emitting unit EU2_2 and the third light-emitting unit EU2_3, and the two The third sub-intermediate layer SML3 may have a 3-stage series structure in which three charge generation layers (i.e., the first charge generation layer CGL1 and the second charge generation layer CGL2) are placed between the three red light-emitting layers, and the third sub-intermediate layer SML3 may have a 4-stage series structure including four red light-emitting layers (i.e., the first red light-emitting layer REML1, the second red light-emitting layer REML2, the third red light-emitting layer REML3 and the fourth red light-emitting layer REML4) which are respectively arranged in the first light-emitting unit EU3_1, the second light-emitting unit EU3_2, the third light-emitting unit EU3_3 and the fourth light-emitting unit EU3_4 and the three charge generation layers (i.e., the first charge generation layer CGL1, the second charge generation layer CGL2 and the third charge generation layer CGL3) are placed between the four red light-emitting layers.

[0376] Fig.25 is a cross-sectional view of a first light emitting element of a display device according to one or more embodiments of the present disclosure.

[0377] Reference Fig.25 , the common electrode CE of the first light-emitting element ED1 may be divided into parts corresponding to different sub-middle layers. The first light-emitting element ED1 may include a first pixel electrode PE1, a first middle layer ML1, and a first sub-common electrode (or first sub-electrode) SCE1 and a second sub-common electrode (or second sub-electrode) SCE2. The first sub-common electrode SCE1 and the second sub-common electrode SCE2 may be physically and / or electrically separated from each other, and different common voltages may be applied to the first sub-common electrode SCE1 and the second sub-common electrode SCE2. For example, a first common voltage may be applied to the first sub-common electrode SCE1, and a second common voltage different from the first common voltage may be applied to the second sub-common electrode SCE2. In this example, the brightness difference between the light emitted from the first sub-middle layer SML1 and the light emitted from the second sub-middle layer SML2 may be finely controlled.

[0378] The first sub intermediate layer SML1 may be disposed in the first sub emission area SEA1 between the first pixel electrode PE1 and the first sub common electrode SCE1.

[0379] The second sub middle layer SML2 may be disposed in the second sub emission area SEA2 between the first pixel electrode PE1 and the second sub common electrode SCE2.

[0380] At least one of the second light emitting element ED2, the third light emitting element ED3, and the fourth light emitting element may be Fig.25 In this case, the first sub-common electrode SCE1 and the second sub-common electrode SCE2 of the first light-emitting element ED1 may be respectively connected to the first sub-common electrode SCE1 and the second sub-common electrode SCE2 of any one of the second light-emitting element ED2, the third light-emitting element ED3, and the fourth light-emitting element having the same configuration as the first light-emitting element ED1.

[0381] The first sub-intermediate layer SML1 may have a 1-stage series structure including a red light-emitting layer (i.e., the first red light-emitting layer REML1) disposed in the first light-emitting unit EU1, and the second sub-intermediate layer SML2 may have a 2-stage series structure including two red light-emitting layers (i.e., the first red light-emitting layer REML1 and the second red light-emitting layer REML2) disposed in the first light-emitting unit EU2_1 and the second light-emitting unit EU2_2, respectively, and a charge generation layer (i.e., the charge generation layer CGL) is placed between the two red light-emitting layers.

[0382] Fig.26 is a graph comparing a relationship between a pixel voltage and a brightness of a display device according to one or more embodiments of the present disclosure and a relationship between a pixel voltage and a brightness of a display device according to a comparative example.

[0383] As already mentioned above, since the number of light-emitting layers included in the first sub-intermediate layer of the intermediate layer is different from the number of light-emitting layers included in the second sub-intermediate layer of the intermediate layer, the first sub-intermediate layer and the second sub-intermediate layer can emit light with different grayscales (or brightness) according to the electric field between the pixel electrode and the common electrode. For example, the first sub-intermediate layer and the second sub-intermediate layer can provide light with different brightness in response to a voltage (e.g., a pixel voltage) applied to the pixel electrode. For example, when a pixel voltage of 7.5V is applied to the pixel electrode, the first sub-intermediate layer having a relatively small number of light-emitting layers can emit light with a higher brightness (hereinafter, the first light), and the second sub-intermediate layer having a relatively large number of light-emitting layers can emit light with a brightness lower than that of the first light (hereinafter, the second light). In other words, the first light emitted from the first sub-intermediate layer can have a brightness higher than the brightness of the second light emitted from the second sub-intermediate layer.

[0384] When a pixel voltage of 2.5V or 5V is applied, the light emitting element of the display device of the comparative example is turned off, but the first sub-intermediate layer of the light emitting element of the display device according to one or more embodiments of the present disclosure emits light.

[0385] The display device of the comparative example exhibits the same minimum grayscale level (e.g., full black grayscale level) for pixel voltages of 2.5V and 5V, but the display device according to one or more embodiments of the present disclosure may exhibit different grayscale levels for pixel voltages of 2.5V and 5V. For example, the display device according to one or more embodiments of the present disclosure may display an image with a minimum grayscale level at a pixel voltage of 2.5V, and display an image with a higher grayscale level at a pixel voltage of 5V. For example, the first sub-middle layer and the second sub-middle layer of the display device according to one or more embodiments of the present disclosure may respectively display an image with a grayscale level higher than the minimum grayscale level and an image with a minimum grayscale level at a pixel voltage of 5V. Therefore, the display device according to one or more embodiments of the present disclosure may present a wider range of grayscale levels in each pixel even at a lower voltage. As a result, the available range of pixel voltages may be expanded.

[0386] Fig. 27 is a graph showing the change in brightness with respect to driving voltage for different series structures.

[0387] Reference Fig. 27 , the X-axis represents driving voltage, and the Y-axis represents brightness.

[0388] The first curve GR1 is a driving voltage-brightness curve (VL curve) for a 1-stage series structure including one light-emitting layer in one pixel, the second curve GR2 is a driving voltage-brightness curve for a 2-stage series structure including two light-emitting layers stacked in a third direction DR3 in one pixel, and the third curve GR3 may be a driving voltage-brightness curve for a 3-stage series structure including three light-emitting layers stacked in a third direction DR3 in one pixel.

[0389] Refer again Fig.26 , the display device according to one or more embodiments of the present disclosure can emit light even at a lower voltage. Fig. 27 As shown in , the available voltage range RN2 of the display device according to one or more embodiments of the present disclosure may be wider than the available voltage range RN1 of the display device of the comparative example.

[0390] Fig.28 is a graph comparing a driving current error rate of a display device according to one or more embodiments of the present disclosure with a driving current error rate of a display device according to a comparative example.

[0391] Reference Fig.28 , the X-axis represents the grayscale level, and the Y-axis represents the error rate of the driving current.

[0392] The first curve GR11 represents a characteristic curve of the display device of the comparative example, which shows the error rate of the driving current (Ids) applied to the light emitting element via the driving transistor DT when the threshold voltage (Vth) of the driving transistor DT is biased in the positive direction or negative direction from its normal magnitude.

[0393] When the threshold voltage of the driving transistor in the display device of the comparative example is biased in the positive direction from its normal value, it is observed that the error rate of the driving current in the high grayscale range is greater than 5%, and the error rate of the driving current in the low grayscale range is greater than 2%. Here, the bias deviation of the threshold voltage in the positive direction can be, for example, approximately +50mV.

[0394] When the threshold voltage of the driving transistor in the display device of the comparative example is biased in the negative direction from its normal value, it is observed that the error rate of the driving current in the high grayscale range is greater than 5%, and the error rate of the driving current in the low grayscale range is greater than 2%. Here, the negative bias deviation of the threshold voltage can be, for example, approximately -50mV.

[0395] The second curve GR22 represents a characteristic curve of a display device according to one or more embodiments of the present disclosure, which shows the error rate of the driving current (Ids) applied to the light-emitting element via the driving transistor DT when the threshold voltage (Vth) of the driving transistor DT is biased in a positive direction or a negative direction from its normal size.

[0396] When the threshold voltage of the driving transistor in the display device according to one or more embodiments of the present disclosure is biased in the positive direction from its normal value, it is observed that the error rate of the driving current in the high grayscale range is less than 5%, and the error rate of the driving current in the low grayscale range is less than 2%. Here, the bias deviation of the threshold voltage in the positive direction can be, for example, approximately +50mV.

[0397] When the threshold voltage of the driving transistor in the display device according to one or more embodiments of the present disclosure is biased in the negative direction from its normal value, it is observed that the error rate of the driving current in the high grayscale range is less than 5%, and the error rate of the driving current in the low grayscale range is less than 2%. Here, the negative bias deviation of the threshold voltage can be, for example, approximately -50mV.

[0398] The display device according to one or more embodiments of the present disclosure can reduce the error rate of the driving current of the driving transistor. Therefore, the brightness deviation between pixels can be prevented, regardless of the deviation of the threshold voltage between pixels. This improvement ensures that the image quality of the display device according to one or more embodiments of the present disclosure can be improved.

[0399] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles and scope of the present disclosure. Therefore, the embodiments of the present disclosure are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, comprising: substrate; a first electrode on the substrate; a second electrode, on the first electrode; as well as A first intermediate layer, in a first emission region, between the first electrode and the second electrode, wherein: The first intermediate layer includes a plurality of sub-intermediate layers in the first emission region; and The plurality of sub-intermediate layers of the first intermediate layer have different thicknesses.

2. The display device according to claim 1, wherein: The plurality of sub-intermediate layers of the first intermediate layer include different numbers of light emitting layers.

3. The display device according to claim 1, wherein: The thickness of the plurality of sub-intermediate layers of the first intermediate layer is a distance from a bottom surface of the first intermediate layer to a top surface of an uppermost light emitting layer of the plurality of sub-intermediate layers of the first intermediate layer.

4. The display device according to claim 3, wherein: The bottom surface of the first intermediate layer is an interface between the first electrode and the first intermediate layer.

5. The display device according to claim 3, wherein: The uppermost light emitting layer of the plurality of sub-intermediate layers of the first intermediate layer is a light emitting layer farthest from the first electrode among the plurality of sub-intermediate layers of the first intermediate layer.

6. The display device according to claim 3, wherein: The top surface of the uppermost light emitting layer of the plurality of sub-intermediate layers of the first intermediate layer is an interface between the uppermost light emitting layer of the plurality of sub-intermediate layers of the first intermediate layer and the uppermost electron transport layer of the plurality of sub-intermediate layers of the first intermediate layer.

7. The display device according to claim 1, wherein: The plurality of sub-intermediate layers of the first intermediate layer include different numbers of light emitting units.

8. The display device according to claim 7, wherein: Each of the plurality of sub-intermediate layers of the first intermediate layer further includes a charge generation layer located between adjacent light emitting units.

9. The display device according to claim 7, wherein: The first intermediate layer also includes a functional layer in each of the light emitting units.

10. The display device according to claim 1, further comprising: a third electrode, between the substrate and the second electrode; as well as A second intermediate layer, in a second emission region, between the second electrode and the third electrode, wherein: The second intermediate layer includes a plurality of sub-intermediate layers located in the second emission region; and The plurality of sub-intermediate layers of the second intermediate layer have different thicknesses.

11. The display device according to claim 10, wherein: The plurality of sub-intermediate layers of the second intermediate layer respectively have the same thickness as their corresponding plurality of sub-intermediate layers of the first intermediate layer.

12. The display device according to claim 11, wherein: The plurality of sub-intermediate layers of the second intermediate layer respectively include the same number of light-emitting layers as their corresponding plurality of sub-intermediate layers of the first intermediate layer.

13. The display device according to claim 10, wherein: The plurality of sub-intermediate layers of the second intermediate layer respectively have different thicknesses from their corresponding plurality of sub-intermediate layers of the first intermediate layer.

14. The display device according to claim 13, wherein: The plurality of sub-intermediate layers of the second intermediate layer respectively include different numbers of light-emitting layers from their corresponding plurality of sub-intermediate layers of the first intermediate layer.

15. The display device according to claim 1, wherein: The second electrode includes a plurality of sub-electrodes on the plurality of sub-intermediate layers of the first intermediate layer.

16. The display device according to claim 15, wherein: The plurality of sub-electrodes are separated from each other.

17. The display device according to claim 1, wherein: The first emission region includes a plurality of sub-emission regions respectively corresponding to the plurality of sub-middle layers of the first middle layer.

18. The display device according to claim 1, further comprising: A color filter is provided on the second electrode in the first emission region.

19. The display device according to claim 1, wherein: The plurality of sub-intermediate layers of the first intermediate layer include light emitting layers configured to emit light of the same color.

20. The display device according to claim 1, wherein: The plurality of sub-intermediate layers of the first intermediate layer include light emitting layers configured to emit light of different colors.

21. The display device according to claim 1, wherein: The plurality of sub-intermediate layers of the first intermediate layer are arranged in one direction.

22. The display device according to claim 1, wherein: The plurality of sub intermediate layers of the first intermediate layer include a first sub intermediate layer and a second sub intermediate layer having a thickness greater than that of the first sub intermediate layer and surrounding the second sub intermediate layer.

23. A display device, comprising: substrate; a first electrode on the substrate; a second electrode, on the first electrode; as well as an intermediate layer between the first electrode and the second electrode in the emission region, wherein: The intermediate layer comprises a plurality of sub-intermediate layers in the emission region; and At least two sub-intermediate layers among the plurality of sub-intermediate layers include different numbers of light-emitting layers.

24. The display device according to claim 23, wherein: The at least two sub-intermediate layers among the plurality of sub-intermediate layers have different thicknesses.

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