Display device and method of manufacturing same

Abstract

The invention relates to a method of manufacturing a display device and the display device. A method of manufacturing a display device according to an embodiment of the present invention includes: forming amorphous silicon on a substrate; forming a conductive protection layer on the amorphous silicon; doping with fluorine; and removing the conductive protection layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0086429 filed in the Korean Intellectual Property Office on July 4, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0003] A display device is a device that displays an image, and recently, an organic light emitting diode display device as a type of light emitting display device is attracting attention. A light emitting display device is self-luminous, and unlike a liquid crystal display device, a light emitting display device does not require a separate light source, so the light emitting display device can be made thinner and lighter than a typical liquid crystal display device. In addition, the light emitting display device generally exhibits high quality characteristics such as low power consumption, high brightness, and high response speed.

[0004] Typically, a light-emitting display device includes: a substrate; a plurality of thin film transistors disposed on the substrate; a plurality of insulating layers disposed on or between structures constituting the thin film transistors; and an organic light-emitting element connected to the thin film transistors. The light-emitting display device typically includes a plurality of pixels, and each pixel includes a plurality of transistors. The transistor may include a polycrystalline semiconductor. To form a polycrystalline semiconductor, an amorphous semiconductor undergoes a crystallization step by a heat treatment such as may be applied using a laser. Summary of the invention

[0005] The embodiments disclosed herein may provide a method of manufacturing a display device and may prevent the generation of static electricity during fluorine doping. The embodiments may also include a display device manufactured by the method.

[0006] A method of manufacturing a display device according to an embodiment of the present disclosure includes: forming amorphous silicon on a substrate; forming a conductive protective layer on the amorphous silicon, doping with fluorine; and removing the conductive protective layer.

[0007] The method may further include crystallizing the amorphous silicon after the removing the conductive protection layer.

[0008] Before forming the amorphous silicon on the substrate, the method may further include forming an insulating film on the substrate.

[0009] The conductive protection layer may include metal, and the metal may not form silicide with the amorphous silicon.

[0010] The metal may include molybdenum.

[0011] The conductive protection layer may include a transparent conductive oxide.

[0012] The transparent conductive oxide may include at least one selected from IGZO, ITO, and IZO.

[0013] The conductive protective layer may have to Thickness.

[0014] Through the fluorine doping, fluorine can be doped into the insulating film positioned below the amorphous silicon.

[0015] During the fluorine doping, fluorine may be positioned on the conductive protective layer.

[0016] The insulating film may be an inorganic layer.

[0017] The inorganic layer may include silicon nitride or silicon oxide.

[0018] The insulating film may include an organic layer positioned on the substrate and an inorganic layer positioned on the organic layer and in contact with the amorphous silicon, and the inorganic layer may include silicon oxide.

[0019] After the conductive protection layer is removed, fluorine may not be located on the amorphous silicon.

[0020] The removing of the conductive protection layer may be performed by wet etching.

[0021] A display device according to an embodiment includes: a substrate; an insulating film on the substrate; a semiconductor layer on the insulating film; a transistor including the semiconductor layer; and a light emitting element connected to the transistor, wherein the semiconductor layer is a crystal. The crystal includes silicon, and at least one of the insulating film and the upper portion of the semiconductor layer is doped with fluorine.

[0022] The insulating film may include an organic layer in contact with the substrate and an inorganic layer in contact with the semiconductor layer.

[0023] The inorganic layer may include silicon nitride or silicon oxide.

[0024] The inorganic layer may include a first inorganic layer including silicon nitride and a second inorganic layer including silicon oxide, and the second inorganic layer may directly contact the semiconductor layer.

[0025] The thickness of the first inorganic layer may be to And the width of the second inorganic layer can be to

[0026] According to an embodiment, a method of manufacturing a display device to prevent static electricity from being generated during fluorine doping and a display device manufactured by the method are provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a process flow chart showing a manufacturing process of a display device according to an embodiment.

[0028] Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 is a cross-sectional view illustrating a structure formed during a manufacturing process of a display device according to an embodiment.

[0029] Figure 7 A display device doped with fluorine and not including a conductive protective layer is shown.

[0030] Figure 8 is a cross-sectional view of a stacked structure in a display device according to an embodiment of the present disclosure.

[0031] Fig. 9 is a cross-sectional view schematically showing a display device according to an embodiment.

[0032] Fig.10 is an equivalent circuit diagram of one pixel in the light emitting display device according to the embodiment.

[0033] Fig.11 is a timing diagram of signals applied to one pixel of a light emitting display device according to an embodiment.

[0034] Fig.12 is a layout diagram showing one pixel region including a light emitting display device according to an embodiment.

[0035] Fig.13 It is along Fig.12 A cross-sectional view taken along line XX'. DETAILED DESCRIPTION

[0036] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can understand and implement the principles of the present disclosure.

[0037] The embodiments of the present disclosure may be embodied in many different forms and are not limited to the specific embodiments set forth herein.

[0038] In order to clearly describe the present disclosure, parts irrelevant to the description may be omitted.

[0039] Throughout the drawings and the specification, the same or similar reference numerals are assigned to the same or similar components. In addition, for ease of explanation, the size and thickness of each component shown in the drawings are shown, and the present disclosure is not necessarily limited to the size and thickness of each component shown. For example, the thickness of various layers and regions shown in the drawings may be enlarged or exaggerated to clearly express the various layers and regions.

[0040] In addition, when a component such as a layer, film, region, or plate is referred to as being "above" or "on" another component, this includes not only the case where the component is "directly on" another component, but also the case where the other component is in between. Conversely, a component is referred to as being "directly on" another component, which means that there are no other components in between. In addition, being "above" or "on" a reference component means being above or below the reference component in one orientation and does not necessarily mean being "above" or "on" the reference component in the opposite direction of gravity.

[0041] In addition, unless otherwise stated, throughout the specification, when a certain component is referred to as “comprising” an element, it means that the component may further include other elements.

[0042] Additionally, throughout the specification, reference to a “planar image” means when the target component is viewed from above a main surface thereof, and reference to a “cross-sectional image or view” means an image or view of a cut surface of the target component.

[0043] Hereinafter, a method of manufacturing a display device and embodiments of a display device manufactured by the method will be described in detail with reference to the accompanying drawings.

[0044] The manufacturing method according to the present embodiment is characterized by a fluorine doping process of a semiconductor layer of a display device; hereinafter, formation of the semiconductor layer and the fluorine doping process will be described.

[0045] Figure 1 is a process flow chart showing a manufacturing process of a display device according to an embodiment.

[0046] Reference Figure 1 , the method for manufacturing a display device according to the present embodiment includes: forming amorphous silicon on a substrate (S10); forming a conductive protective layer on the amorphous silicon (S20); doping with fluorine (S30); removing the conductive protective layer (S40); and crystallizing the amorphous silicon (S50). Forming the conductive protective layer (S20) on the semiconductor layer before doping with fluorine (S30) has an important effect. Specifically, as described in more detail below, the conductive protective layer can prevent static electricity from being generated during the fluorine doping process.

[0047] Now refer to Figures 2 to 6 An embodiment of a method of manufacturing a display device will be described. Figures 2 to 6is a cross-sectional view illustrating a structure formed during a manufacturing process of a display device according to an embodiment.

[0048] First, refer to Figure 2 , an amorphous silicon 100 is formed on a substrate SUB. In the example shown, a plurality of layers (specifically, an organic layer 200 and an inorganic layer 300) may be positioned between the substrate SUB and the amorphous silicon 100. Figure 2 1 and 2. In the embodiment of the present invention, one organic layer 200 and one inorganic layer 300 are shown, but a plurality of organic layers 200 and one or more inorganic layers 300 may be provided. The inorganic layer 300 may be in direct contact with the amorphous silicon 100, or alternatively, the inorganic layer 300 may be formed as Figure 2 , on the organic layer 200. The organic layer 200 may include polyimide, but this is only an example and is not limited thereto. The inorganic layer 300 may include silicon nitride or silicon oxide.

[0049] Next, refer to Figure 3 , a conductive protective layer 400 is formed on the amorphous silicon 100. If the conductive protective layer 400 is directly on the amorphous silicon 100, the conductive protective layer 400 preferably includes a material that does not form silicon and silicide. For example, the conductive protective layer 400 may include molybdenum or a transparent conductive oxide. The transparent conductive oxide may be at least one selected from indium gallium zinc oxide (IGZO), indium tin oxide (ITO), and indium zinc oxide (IZO), but is not limited thereto.

[0050] The conductive protection layer 400 may have a thickness of about and When the thickness of the conductive protective layer 400 is less than When the thickness of the conductive protective layer 400 exceeds When removing the conductive protection layer 400, the time required may reduce the productivity of the process.

[0051] Next, refer to Figure 4 , perform fluorine doping. Figure 4 As shown in FIG. 4 , fluorine may pass through the conductive protective layer 400 and the amorphous silicon 100 and be doped into the inorganic layer 300 positioned below the amorphous silicon 100. This doping may be accomplished using an accelerating voltage for an ion implantation process, and the applied voltage for the process may be between about 10 keV and 40 keV.

[0052] Fluorine doping can improve transient image sticking and hysteresis of transistors manufactured later in the process. Hysteresis is a phenomenon in which a transistor curve is shifted due to charge traps occurring in the insulating film due to the current and voltage stress of the transistor. However, in the case of the present embodiment, since fluorine can be doped into the insulating film 300, defects in the insulating film 300 can be minimized, thereby improving transient image sticking hysteresis. More specifically, Si-F bonds can be generated in the insulating film 300 by fluorine doping. When this occurs, because the Si-F bond is more reactive or stronger than the FF bond, the Si-F bond can remove defects by removing dangling bonds of Si in the insulating film 300 (e.g., the inorganic layer 300), and thereby provide passivation of the charge trap site.

[0053] The problem with the conventional fluorine doping process is that static electricity is generated during the fluorine doping process, and static electricity may cause the threshold voltage (Vth) to shift positively. That is, during doping, the local F+ ion concentration may accumulate due to negative (-) static charge, which may cause a positive shift in the threshold voltage (Vth). However, because the generation of static electricity is prevented by the conductive protective layer 400 in this embodiment, the problem of the positive shift of the threshold voltage (Vth) can be solved. That is, the (conductive) conductive protective layer 400 maintains the same potential as the potential of the amorphous silicon 100, does not generate static electricity, and prevents the accumulation of local F+ ion concentration caused by static electricity during the doping process.

[0054] like Figure 4 As shown in FIG, fluorine may be located on both the upper and lower surfaces of the conductive protective layer 400 during the doping process. That is, some fluorine may pass through the conductive protective layer 400 and be doped into the inorganic layer 300, and some fluorine may be located on the upper surface of the conductive protective layer.

[0055] Next, refer to Figure 5 , also refer to Figure 4 , the conductive protection layer 400 can be removed. For example, the conductive protection layer 400 can be removed by a wet etching process. Removing the conductive protection layer 400 also removes the fluorine located on the upper surface of the conductive protection layer 400. In addition, the fluorine is not located on the amorphous silicon 100. This is because the conductive protection layer 400 is removed after the upper surface of the amorphous silicon 100 is covered and protected by the conductive protection layer 400.

[0056] Next, refer to Figure 6 , also refer to Figure 4, crystalline silicon 110 is formed by crystallizing amorphous silicon 100. For example, the crystallization process can be performed by laser irradiation. Damage caused by early fluorine doping can be repaired by this crystallization process. That is, in the present embodiment, the crystallization process can repair the damage caused in the doping process because the doping is performed before the crystallization of the silicon layer. On the contrary, if fluorine doping is performed after the crystallization of the silicon layer, the damage generated during the doping process may not be repaired, or a separate additional process may be required to repair the damage.

[0057] As described above, in the method for manufacturing a display device according to the present embodiment, since the conductive protective layer 400 is formed on the amorphous silicon 100 before doping, the generation of static electricity during doping can be prevented. In addition, since the conductive protective layer 400 is removed after the fluorine doping process, fluorine may not be located on the upper surface of the amorphous silicon 100 or the crystalline silicon 110.

[0058] Figure 7 A display device doped with fluorine and not including a conductive protective layer is shown. Figure 7 FIG. 4 shows a structure formed during a manufacturing process for a display device, wherein the structure is doped with fluorine and does not include the conductive protective layer 400. Referring to FIG. Figure 7 , also refer to Figure 4 , when doping is performed without the conductive protective layer 400, the doped fluorine may remain on both the upper and lower surfaces of the amorphous silicon 100. In contrast, in the above-described embodiment, doping is performed after the conductive protective layer 400 is formed, and the conductive protective layer 400 is removed thereafter, so that fluorine is not located on the upper and lower surfaces of the amorphous silicon 100. Figure 5 or Figure 6 on the upper surface of the amorphous silicon 100 or the crystalline silicon 110 .

[0059] Figure 8 is a cross-sectional view of a stacked structure in a display device according to an embodiment of the present disclosure. Figure 8 The stacked structure includes a first organic layer 210, a first barrier layer 310, a second barrier layer 320, a second organic layer 220, a third barrier layer 330, a first buffer layer 340, a second buffer layer 341, and a semiconductor layer ACT. The semiconductor layer ACT may include crystalline silicon. Figure 8 can be considered as Figures 2 to 7 A specific example of a stacked structure, wherein Figures 2 to 7 The organic layer 200 and the inorganic layer 300 shown in FIG. 1 include a first organic layer 210 , a first barrier layer 310 , a second barrier layer 320 , a second organic layer 220 , a third barrier layer 330 , a first buffer layer 340 , and a second buffer layer 341 .

[0060] exist Figure 8In the embodiment, the first organic layer 210 and the second organic layer 220 may include polyimide. The first barrier layer 310, the second barrier layer 320, the third barrier layer 330, the first buffer layer 340 and the second buffer layer 341 may include silicon nitride or silicon oxide.

[0061] In a specific example, the first barrier layer 310 and the third barrier layer 330 may include silicon oxide. The thickness of the first barrier layer 310 and the third barrier layer 330 may be between 0.1 and 0.2 mm. and In addition, the second barrier layer 320 may include silicon nitride, specifically, without NH 3 SiN x (NH 3 Free SiN x ). The first buffer layer 340 may include silicon nitride and may have to The second buffer layer 341 may include silicon oxide and may have to Thickness.

[0062] exist Figure 8 In the embodiment of the present invention, the semiconductor layer ACT may directly contact the second buffer layer 341. Due to the doping as described above, the layer below the semiconductor layer ACT may contain fluorine. In addition, as described above, the conductive protection layer 400 may be positioned on the semiconductor layer ACT during fluorine doping, and the conductive protection layer 400 and the fluorine at the interface between the conductive protection layer 400 and the semiconductor layer ACT are removed so that the fluorine may not be on the semiconductor layer ACT.

[0063] The above manufacturing process may be a part of a process for manufacturing a display device, and Fig. 9 Schematically shows a cross-sectional view of a display device according to an embodiment. For ease of explanation, Fig. 9 A simplified diagram of a portion of a cross section is specifically shown, and the present disclosure is not limited thereto.

[0064] Reference Fig. 9 , Fig. 9 1. The substrate SUB is shown. In some embodiments, the substrate SUB may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetyl cellulose and cellulose acetate propionate. The substrate SUB may be a rigid substrate or a flexible substrate capable of bending, folding or curling. The substrate SUB may include a single layer or multiple layers. On the substrate SUB, at least one matrix layer including a polymer resin and at least one inorganic layer may be stacked sequentially or alternately.

[0065] The light blocking layer BML is positioned on the substrate SUB. The light blocking layer BML may include aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu) and / or metal oxides thereof, and may have a single-layer or multi-layer structure including aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu) and / or metal oxides thereof.

[0066] The buffer layer BUF is positioned on the light blocking layer BML. The buffer layer BUF may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) or amorphous silicon (Si). The buffer layer BUF may include a first opening OP1 overlapping a region of the light blocking layer BML. The source electrode SE covering the transistor may be connected to the light blocking layer BML through the first opening OP1.

[0067] The semiconductor layer ACT is positioned on the buffer layer BUF, and the buffer layer BUF may be doped with fluorine and may include fluorine as described above. Specifically, the buffer layer BUF may have been doped with fluorine through a conductive protective layer that is formed on the semiconductor layer ACT before the fluorine doping process and is removed after the fluorine doping process.

[0068] The semiconductor layer ACT may include polysilicon. The semiconductor layer ACT may include a channel region CA overlapping the gate electrode GE, and a source region SA and a drain region DA positioned at opposite sides of the channel region CA.

[0069] The gate insulating film GI is positioned on the semiconductor layer ACT. The gate insulating film GI may include silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y ), and the gate insulating film GI may have a layer including silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y ) of a single layer or a multi-layer structure. The gate insulating film GI may be positioned to overlap with the channel region CA of the semiconductor layer ACT.

[0070] A gate conductive layer including a gate electrode GE may be positioned on the gate insulating film GI. The gate conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or metal oxides thereof and may have a single layer or multilayer structure including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or metal oxides thereof. The gate electrode GE may be patterned during the same process as the process of patterning the gate insulating film GI, and may have a planar shape that is the same as the planar shape of the gate insulating film GI. The gate electrode GE may be positioned to overlap the semiconductor layer ACT and the substrate SUB in a direction perpendicular to the plane of the substrate SUB.

[0071] The interlayer insulating dielectric ILD may be a layer or a film positioned on the semiconductor layer ACT and the gate electrode GE. The interlayer insulating dielectric ILD may include silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ), and the interlayer insulating dielectric ILD may have a silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiO x N y ). In the case where the interlayer insulating dielectric ILD is a multilayer structure including silicon nitride and silicon oxide, the layer including silicon nitride may be positioned closer to the substrate SUB than the layer including silicon oxide.

[0072] The first opening OP1 extends through the interlayer insulating dielectric ILD in a region overlapping the light blocking layer BML, and the second opening OP2 passing through the interlayer insulating dielectric ILD overlaps the source area SA of the semiconductor layer ACT. A third opening OP3 passing through the interlayer insulating dielectric ILD may be included.

[0073] The data conductive layer including the source electrode SE and the drain electrode DE is positioned on the interlayer insulating dielectric ILD. The data conductive layer may include aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), or metal oxides thereof, and may have a single layer or multilayer structure including aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), or metal oxides thereof. The source electrode SE may contact the light blocking layer BML through the first opening OP1 and contact the source region SA of the semiconductor layer ACT through the second opening OP2. The drain electrode DE may contact the drain region DA of the semiconductor layer ACT through the third opening OP3.

[0074] The insulating film VIA is positioned on the data conductive layer. The insulating film VIA may include an organic insulating material such as a general polymer (such as polystyrene (PS)), polymethyl methacrylate (PMMA), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, a polyimide, and a siloxane polymer. The insulating film VIA may include a fourth opening OP4 overlapping the source electrode SE.

[0075] The first electrode 191 is positioned on the insulating film VIA. The pixel defining layer 350 is positioned on the insulating film VIA and the first electrode 191. The pixel defining layer 350 has an opening 355 overlapping the first electrode 191. The light emitting layer 360 may be positioned in the opening 355 in contact with the first electrode 191. The second electrode 270 may be positioned on the pixel defining layer 350 and the light emitting layer 360. The first electrode 191, the light emitting layer 360, and the second electrode 270 may constitute a light emitting element LED of a pixel in the display device.

[0076] In the following, reference will be made to Fig.10 and Fig.11 The structure and operation of the display device according to the embodiment are described in detail. However, the described structure and operation are only for example, and the present disclosure is not limited thereto. Fig.10 is an equivalent circuit diagram of one pixel in the light emitting display device according to the embodiment, and Fig.11 is a timing diagram of signals applied to one pixel of a light emitting display device according to an embodiment.

[0077] Reference Fig.10 , a pixel PX of the light-emitting display device includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7, a storage capacitor Cst, and a light-emitting element LED connected to various signal lines 127, 151, 152, 153, 158, 171, 172, and 741. The light-emitting display device may include a display area displaying an image, and a plurality of pixels including the pixel PX may be arranged in the display area in various forms.

[0078] Transistors T1, T2, T3, T4, T5, T6 and T7 include a driving transistor T1 (or a first transistor T1), a switching transistor T2 (or a second transistor T2) and a third transistor T3 connected to a scan line 151, all of which mainly control the size and timing of the current Iled driving the light-emitting element LED. Other transistors T4, T5, T6 and T7 are transistors (hereinafter referred to as compensation transistors) for the effective operation of the light-emitting element LED. Compensation transistors T4, T5, T6 and T7 may also be referred to as fourth transistors T4, fifth transistors T5, sixth transistors T6 and seventh transistors T7.

[0079] A plurality of signal lines 127, 151, 152, 153, 158, 171, 172, and 741 connected to the pixel PX include a scan line 151, a previous scan line 152, an emission control line 153, a bypass control line 158, and a data line 171, a driving voltage line 172, an initialization voltage line 127, and a common voltage line 741. The bypass control line 158 may be a part of the previous scan line 152 or the bypass control line 158 may be electrically connected to the previous scan line 152. Alternatively, the bypass control line 158 may be a part of the scan line 151 or the bypass control line 158 may be electrically connected to the scan line 151.

[0080] The scan line 151 , which may be connected to a gate driver (not shown), transmits the scan signal Sn to the gate of the second transistor T2 and the gate of the third transistor T3 .

[0081] The previous scan line 152 , which may be connected to the gate driver, transmits a previous scan signal Sn- 1 to the gate of the fourth transistor T4 , which may also be applied to a pixel positioned at a previous stage.

[0082] The emission control line 153 , which may be connected to a light emitting control unit (not shown), transmits a light emitting control signal EM to the gates of the fifth transistor T5 and the sixth transistor T6 for controlling the time when the light emitting element LED emits light.

[0083] The bypass control line 158 transmits the bypass signal GB to the gate of the seventh transistor T7.

[0084] The data line 171 transmits a data voltage Dm generated by a data driver (not shown) and serves as a Fig.10 The brightness of the light emitting element LED of the light emitting diode in the embodiment varies according to the data voltage Dm.

[0085] The driving voltage line 172 applies a driving voltage ELVDD. The initialization voltage line 127 transmits an initialization voltage Vint to initialize the driving transistor T1 as described below. The common voltage line 741 applies a common voltage ELVSS. A constant voltage may be applied to the driving voltage line 172, the initialization voltage line 127, and the common voltage line 741.

[0086] Hereinafter, the transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 in the pixel PX will be further described.

[0087] The driving transistor T1 is a transistor that adjusts the amount of the output driving current Id according to the applied data voltage Dm. Specifically, the output driving current Id is applied to the light emitting element LED to adjust the brightness of the light emitting element LED according to the data voltage Dm. To this end, the first electrode S1 of the driving transistor T1 is configured to receive the driving voltage ELVDD. The first electrode S1 of the driving transistor T1 is connected to the driving voltage line 172 via the fifth transistor T5. In addition, the first electrode S1 of the driving transistor T1 is also connected to the second electrode D2 of the second transistor T2 to receive the data voltage Dm.

[0088] The second electrode D1 (output electrode) of the driving transistor T1 is connected to output current toward the light emitting element LED. Fig.10 In the embodiment of FIG. 5 , the second electrode D1 of the driving transistor T1 is connected to the anode of the light emitting element LED via the sixth transistor T6 .

[0089] The gate electrode G1 is connected to one electrode (second storage electrode E2) of the storage capacitor Cst. Therefore, the voltage of the gate electrode G1 depends on the voltage stored in the storage capacitor Cst, and the driving current Id output from the driving transistor T1 changes accordingly with the change of the voltage stored in the storage capacitor Cst.

[0090] The second transistor T2 is a transistor that receives the data voltage Dm into the pixel PX. The gate electrode G2 of the second transistor T2 is connected to the scan line 151, and the first electrode S2 of the second transistor T2 is connected to the data line 171. The second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on according to the scan signal Sn transmitted through the scan line 151, the data voltage Dm transmitted through the data line 171 is applied to the first electrode S1 of the driving transistor T1.

[0091] The third transistor T3 is a transistor that transmits a compensation voltage (voltage of Dm+Vth) obtained by changing the data voltage Dm by the driving transistor T1 to the second storage electrode E2 of the storage capacitor Cst. The gate electrode G3 of the third transistor T3 is connected to the scan line 151, and the first electrode S3 of the third transistor T3 is connected to the second electrode D1 of the driving transistor T1. The second electrode D3 of the third transistor T3 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. The third transistor T3 is turned on according to the scan signal Sn received through the scan line 151, connects the gate electrode G1 of the driving transistor T1 and the second electrode D1 of the driving transistor T1, and also connects the second electrode D1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst.

[0092] The fourth transistor T4 is used to initialize the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G4 of the fourth transistor T4 is connected to the previous scan line 152, and the first electrode S4 of the fourth transistor T4 is connected to the initialization voltage line 127. The second electrode D4 of the fourth transistor T4 is connected to the second storage electrode E2 of the storage capacitor Cst, the second electrode D3 of the third transistor T3, and the gate electrode G1 of the driving transistor T1. The fourth transistor T4 applies the initialization voltage Vint to the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 according to the previous scan signal Sn-1 transmitted through the previous scan line 152, so that the initialization voltage Vint is transmitted to the second storage electrode E2. Therefore, the gate voltage of the gate electrode G1 of the driving transistor T1 and the storage capacitor Cst can be initialized. The initialization voltage Vint can be, for example, Fig.10 In the example of , the voltage that turns on the driving transistor T1 has a low voltage value.

[0093] The fifth transistor T5 is used to transmit the driving voltage ELVDD to the driving transistor T1. The gate electrode G5 of the fifth transistor T5 is connected to the emission control line 153, and the first electrode S5 of the fifth transistor T5 is connected to the driving voltage line 172. The second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1.

[0094] The sixth transistor T6 is used to transmit the driving current Id output from the driving transistor T1 to the light emitting element LED. The gate electrode G6 of the sixth transistor T6 is connected to the emission control line 153, and the first electrode S6 of the sixth transistor T6 is connected to the second electrode D1 of the driving transistor T1. The second electrode D6 of the sixth transistor T6 is connected to the anode of the light emitting element LED.

[0095] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light control signal EM transmitted through the emission control line 153. When the fifth transistor T5 and the sixth transistor T6 are turned on, the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, and the driving transistor T1 outputs the driving current Id according to the voltage of the gate electrode G1 of the driving transistor T1 (that is, the voltage of the second storage electrode E2 of the storage capacitor Cst). The output driving current Id is transmitted to the light emitting element LED through the sixth transistor T6. As a result, the current Iled flows through the light emitting element LED, and the light emitting element LED emits light.

[0096] The seventh transistor T7 is used to initialize the anode of the light emitting element LED. The gate electrode G7 of the seventh transistor T7 is connected to the bypass control line 158, the first electrode S7 of the seventh transistor T7 is connected to the anode of the light emitting element LED, and the second electrode D7 of the seventh transistor T7 is connected to the initialization voltage line 127. The bypass signal GB may be applied at the same timing as the previous scan signal Sn-1, and the bypass control line 158 may be connected to the previous scan line 152. Alternatively, the bypass control line 158 may transmit a signal GB separated from the previous scan signal Sn-1, and the bypass control line 158 may not be connected to the previous scan line 152. When the seventh transistor T7 is turned on according to the bypass signal GB, the initialization voltage Vint is applied to the anode of the light emitting element LED and initialized.

[0097] The first storage electrode E1 of the storage capacitor Cst is connected to the driving voltage line 172, and the second storage electrode E2 is connected to the gate electrode G1 of the driving transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. As a result, the second storage electrode E2 of the storage capacitor Cst determines the voltage of the gate electrode G1 of the driving transistor T1. When the first transistor T1, the second transistor T2, and the third transistor T3 are turned on, and the fifth transistor T5 and the sixth transistor T6 are turned off, the second storage electrode E2 receives the data voltage Dm through the second electrode D3 of the third transistor T3. When the fourth transistor T4 is turned on, the second storage electrode E2 receives the initialization voltage Vint through the second electrode D4 of the fourth transistor T4.

[0098] The anode of the light emitting element LED is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7. The cathode of the light emitting element LED receives the common voltage ELVSS from the common voltage line 741.

[0099] exist Fig.10 In the embodiment of FIG. 1 , the pixel circuit includes seven transistors T1 to T7 and one storage capacitor Cst, but the embodiment according to the present disclosure is not limited thereto, and the number of transistors, capacitors and connections thereof may be variously changed.

[0100] Will refer to Fig.10 and Fig.11 The operation of one pixel of the light emitting display device according to the embodiment is described.

[0101] Reference Fig.10 and Fig.11During the initialization period, the previous scan signal Sn-1 of a low level is supplied to the pixel PX through the previous scan line 152. This turns on the fourth transistor T4, and the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst through the fourth transistor T4. As a result, the driving transistor T1 and the storage capacitor Cst are initialized. When the voltage of the initialization voltage Vint is low, the driving transistor T1 can be turned on.

[0102] During the initialization period, the low level bypass signal GB is also applied to the seventh transistor T7. Thereafter, the seventh transistor T7 is turned on and applies the initialization voltage Vint to the anode of the light emitting element LED. As a result, the anode of the light emitting element LED is also initialized.

[0103] After the initialization period, the voltages of the low-level previous scan signal Sn-1 and the bypass signal GB are increased, and the low-level scan signal Sn is supplied to the pixel PX through the scan line 151 during the data write period. The second transistor T2 and the third transistor T3 are turned on by the low-level scan signal Sn. When the second transistor T2 is turned on, the data voltage Dm passes through the second transistor T2 and is input to the first electrode S1 of the driving transistor T1.

[0104] In addition, during the data write cycle, the third transistor T3 is turned on, and as a result, the second electrode D1 of the driving transistor T1 is electrically connected to the gate electrode G1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G1 and the second electrode D1 of the driving transistor T1 are connected to form a diode connection. In addition, because a low voltage (initialization voltage Vint) is applied to the gate electrode G1 during the initialization period, the driving transistor T1 is turned on. As a result, the data voltage Dm input to the first electrode S1 of the driving transistor T1 passes through the channel of the driving transistor T1, is output from the second electrode D1, passes through the third transistor T3, and is stored in the second storage electrode E2 of the storage capacitor Cst. The transmission performed by the driving transistor T1 changes the voltage applied to the second storage electrode E2 according to the threshold voltage (Vth) of the driving transistor T1. Specifically, the data voltage Dm is applied to the first electrode S1 of the driving transistor T1, and when the initialization voltage Vint is applied to the gate electrode G1 of the driving transistor T1, the voltage output to the second electrode D1 may be Vgs+Vth. Here, since the gate-source voltage (Vgs) of the driving transistor T1 is the difference between the voltages applied to the gate electrode G1 and the first electrode S1 of the driving transistor T1, the gate-source voltage (Vgs) may have a value of Dm-Vint. Therefore, the voltage output from the second electrode D1 stored in the second storage electrode E2 may have a value of Dm-Vint+Vth.

[0105] Afterwards, during the light emission period, the emission control signal EM supplied from the emission control line 153 drops to a low level value, and the fifth transistor T5 and the sixth transistor T6 are turned on. As a result, the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1, and the second electrode D1 of the driving transistor T1 is connected to the light emitting element LED. The driving transistor T1 generates a driving current Id according to the voltage difference between the voltage of the gate electrode G1 and the voltage of the first electrode S1 (ie, the driving voltage ELVDD). The driving current Id of the driving transistor T1 may have a value proportional to the square of Vgs-Vth. Here, the value of the gate-source voltage (Vgs) is the same as the voltage difference across the storage capacitor Cst, and because the value of the gate-source voltage (Vgs) is the value of Vg-Vs (which is the source voltage of the driving transistor T1), it has a value of Dm-Vint+Vth-ELVDD. Here, if the value of Vgs-Vth is obtained by subtracting the value of the threshold voltage (Vth), the value of Dm-Vint-ELVDD is obtained. That is, the driving current Id of the driving transistor T1 has a current as output that is independent of the threshold voltage (Vth) of the driving transistor T1. Therefore, even if the driving transistors T1 in different pixels PX have different threshold voltages (Vth) due to process variations, the output current of the driving transistor T1 can be kept constant, thereby improving the uniformity of characteristics.

[0106] In the above calculation formula, in the case of a P-type transistor using a polycrystalline semiconductor, the value of the threshold voltage (Vth) may have a value slightly greater than 0 or a negative value. In addition, the expressions of + and - may change according to the direction of the calculated voltage. However, the fact that the drive current Id as the output current of the drive transistor T1 may have a value independent of the threshold voltage (Vth) does not change.

[0107] When the light emission period ends, the initialization period may start again and the same operation of the pixel PX as described above may be repeated from the beginning.

[0108] One of the first and second electrodes of each of the transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 may be a source electrode, and the other may be a drain electrode, depending on the direction of applied voltage or current.

[0109] According to the above embodiment, the seventh transistor T7 in the initialization interval can initialize the anode of the light-emitting element LED, and can prevent the small amount of current output when the driving transistor T1 is actually not turned on from flowing to the light-emitting element LED. At this time, the small amount of current can be discharged to the initialization voltage Vint terminal as a bypass current Ibp through the seventh transistor T7. As a result, the light-emitting element LED does not emit unnecessary light, so that the black level can be displayed more clearly and the contrast can be improved. In this case, the bypass signal GB can have a timing different from the timing of the previous scanning signal Sn-1.

[0110] According to an embodiment, the seventh transistor T7 may be omitted.

[0111] In the following, reference will be made to Fig.12 and Fig.13 To describe according to Fig.10 and Fig.11 A pixel PX of a light-emitting display device of an embodiment. Fig.12 is a layout diagram showing one pixel region including a light emitting display device according to an embodiment, and Fig.13 is along Fig.12 A cross-sectional view taken along line XX'.

[0112] Reference Fig.12 , also refer to Fig.10 , the light emitting display device according to the embodiment includes a scan line 151 extending along a first direction DR1 and transmitting a scan signal Sn and a previous scan line 152 transmitting a previous scan signal Sn-1. In the example shown, the bypass signal GB is also transmitted through the previous scan line 152. The layout shown further includes an emission control line 153 transmitting an emission control signal EM and an initialization voltage line 127 transmitting an initialization voltage Vint.

[0113] The light emitting display device includes a data line 171 and a driving voltage line 172 extending in a second direction DR2 perpendicular to the first direction DR1. The data line 171 transmits a data voltage Dm, and the driving voltage line 172 transmits a driving voltage ELVDD.

[0114] The light-emitting display device further includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a storage capacitor Cst, and a light-emitting element LED. The channel of each of the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is located in the semiconductor layer 130 that extends long. In addition, at least some of the first electrodes and the second electrodes of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 are also located in the semiconductor layer 130. The semiconductor layer 130 ( Fig.12 The semiconductor layer 130 may include a polycrystalline semiconductor such as polysilicon or an oxide semiconductor.

[0115] The region of the semiconductor layer 130 in which the transistor is formed may include a channel doped with N-type impurities or P-type impurities and a first doped region and a second doped region located on opposite sides of the channel and having a higher doping concentration than the doped impurities in the channel. The first doped region and the second doped region may correspond to the first electrode and the second electrode of the transistor T1, T2, T3, T4, T5, T6 or T7, respectively. When one of the first doped region and the second doped region is a source region, the other may be a drain region. In addition, the region of the semiconductor layer between the first electrode and the second electrode of different transistors in the semiconductor layer 130 may be doped so that the two transistors are electrically connected to each other.

[0116] Each of the channels of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 overlaps with a gate electrode of the transistor T1, T2, T3, T4, T5, T6, or T7, and the gate electrode of each transistor T1, T2, T3, T4, T5, T6, and T7 may overlap with a channel located between a first electrode and a second electrode of the transistor T1, T2, T3, T4, T5, T6, or T7. The plurality of transistors T1, T2, T3, T4, T5, T6, and T7 may have substantially the same stacked structure.

[0117] Hereinafter, the driving transistor T1 will be described in detail, and the remaining transistors T2, T3, T4, T5, T6, and T7 will be briefly described. The driving transistor T1 includes a channel, a first gate electrode 155, a first electrode S1, and a second electrode D1. The channel of the driving transistor T1 is between the first electrode S1 and the second electrode D1 and Fig.12 The first gate electrode 155 overlaps with the first gate electrode 155 in a plan view. On the contrary, the first gate electrode 155 overlaps with the channel. The first electrode S1 and the second electrode D1 are respectively positioned at opposite sides of the channel.

[0118] The extension portion of the storage line 126 is insulated and positioned above the first gate electrode 155. The extension portion of the storage line 126 overlaps the first gate electrode 155 in a plan view, and the second gate insulating layer 142 (refer to Fig.13 ) is interposed between the extended portion of the storage line 126 and the first gate electrode 155 to form a storage capacitor Cst. The extended portion of the storage line 126 is a first storage electrode ( Fig.10 The first storage electrode E1 in the embodiment of the present invention is formed, and the first gate electrode 155 forms a second storage electrode ( Fig.10 The second storage electrode E2 in the embodiment of the present invention.

[0119] An opening 56 is formed in an extension portion of the storage line 126 so that the first gate electrode 155 can be connected to the first data connection member 71. An upper surface of the first gate electrode 155 within the opening 56 and the first data connection member 71 are electrically connected through the contact hole 61. The first data connection member 71 is connected to the second electrode D3 of the third transistor T3 to form the first gate electrode 155 of the driving transistor T1 and the second electrode D3 of the third transistor T3.

[0120] The gate electrode of the second transistor T2 may be a portion of the scan line 151. The data line 171 is connected to the first electrode S2 of the second transistor T2 through the contact hole 62. The first electrode S2 and the second electrode D2 of the second transistor T2 may be positioned on the semiconductor layer 130.

[0121] The third transistor T3 may include two adjacent transistors. Fig.12 In the pixel PX of FIG. 1 , a third transistor T3 is shown on the left side and bottom side of the bent portion of the semiconductor layer 130. Each of the two parts is used as a third transistor T3, and a first electrode S3 of one third transistor T3 is connected to a second electrode D3 of another third transistor T3. The gate electrodes of the two transistors T3 may be a portion of the scan line 151 or a portion protruding upward from the scan line 151. This structure may be referred to as a dual-gate structure and may be used to block leakage current. The first electrode S3 of the third transistor T3 is connected to the first electrode S6 of the sixth transistor T6 and the second electrode D1 of the driving transistor T1. The second electrode D3 of the third transistor T3 is connected to the first data connection member 71 through the contact hole 63.

[0122] The fourth transistor T4 also includes two fourth transistors T4, and the two fourth transistors T4 are formed where the previous scan line 152 and the semiconductor layer 130 meet. The gate electrode of the fourth transistor T4 may be a portion of the previous scan line 152. The first electrode S4 of one fourth transistor T4 is connected to the second electrode D4 of the other fourth transistor T4. This structure may be referred to as a double gate structure and may be used to block leakage current. The second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through the contact hole 65, and the second electrode D4 of the fourth transistor T4 is connected to the first data connection member 71 through the contact hole 63.

[0123] As described above, by using the double gate structure for the third transistor T3 and the fourth transistor T4 , the generation of leakage current can be effectively prevented by blocking the electron movement path of the channel in the off state.

[0124] The gate electrode of the fifth transistor T5 may be a part of the emission control line 153. The driving voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through the contact hole 67, and the second electrode D5 is connected to the first electrode S1 of the driving transistor T1 through the semiconductor layer 130.

[0125] The gate electrode of the sixth transistor T6 may be a part of the emission control line 153. The second electrode D6 of the sixth transistor T6 is connected through the third data connection member 73 via the contact hole 69, and the first electrode S6 is connected to the second electrode D1 of the driving transistor T1 through the semiconductor layer 130.

[0126] The gate electrode of the seventh transistor T7 may be a portion of the previous scan line 152. The first electrode S7 of the seventh transistor T7 is connected to the second electrode D6 of the sixth transistor T6, and the second electrode D7 is connected to the first electrode S4 of the fourth transistor T4.

[0127] The storage capacitor Cst includes a first storage electrode E1 and a second storage electrode E2 overlapping each other, and a second gate insulating layer 142 is interposed between the first storage electrode E1 and the second storage electrode E2. The second storage electrode E2 corresponds to the first gate electrode 155 of the driving transistor T1, and the first storage electrode E1 may be an extension of the storage line 126. Here, the second gate insulating layer 142 becomes a dielectric, and the capacitance is determined by the charge stored in the storage capacitor Cst and the voltage between the first storage electrode E1 and the second storage electrode E2. By using the first gate electrode 155 as the second storage electrode E2, a space for forming the storage capacitor Cst in a narrow area can be ensured by occupying a large area of ​​the channel of the driving transistor T1 in the pixel PX. The driving voltage line 172 is connected to the first storage electrode E1 through the contact hole 68. Therefore, the storage capacitor Cst stores a charge corresponding to the difference between the driving voltage ELVDD transmitted to the first storage electrode E1 through the driving voltage line 172 and the gate voltage Vg of the first gate electrode 155.

[0128] The second data connection member 72 is connected to the initialization voltage line 127 through the contact hole 64 .

[0129] The first electrode of the light emitting element LED is connected to the third data connecting member 73 through the contact hole 81. The first electrode may be a pixel electrode.

[0130] The parasitic capacitor control pattern 79 may be positioned between the dual gate electrodes of the third transistor T3. A parasitic capacitor exists in the pixel PX, and if the voltage applied to the parasitic capacitor changes, the image quality characteristics may also change. The driving voltage line 172 is connected to the parasitic capacitor control pattern 79 through the contact hole 66. Therefore, the image quality characteristics can be prevented from changing by applying the driving voltage ELVDD as a constant DC voltage to the parasitic capacitor. The parasitic capacitor control pattern 79 may be positioned in a different region than shown, and a voltage other than the driving voltage ELVDD may be applied.

[0131] One end of the first data connection member 71 is connected to the first gate electrode 155 through the contact hole 61 , and the other end is connected to the second electrode D3 of the third transistor T3 through the contact hole 63 , and the second electrode D3 of the third transistor T3 is connected to the second electrode D4 of the fourth transistor T4 .

[0132] One end of the second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through the contact hole 65 , and the other end is connected to the initialization voltage line 127 through the contact hole 64 .

[0133] The third data connection member 73 is connected to the second electrode D6 of the sixth transistor T6 through the contact hole 69 .

[0134] In the following, reference will be made to Fig.12 and Fig.13 A cross-sectional structure of a light emitting display device according to an embodiment is described in a stacking order.

[0135] Reference Fig.12 and Fig.13 , the light-emitting display device according to the embodiment includes a substrate 111. The substrate 111 may include a plastic layer and a barrier layer. The plastic layer and the barrier layer may have a form in which the plastic layer and the barrier layer are alternately stacked. The plastic layer may include a material selected from the group consisting of polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), polyarylethersulfone, and combinations thereof. The barrier layer may include at least one of silicon oxide, silicon nitride, and aluminum oxide, but is not limited thereto, and may include any inorganic material.

[0136] The buffer layer BUF may be positioned on the substrate 111. The buffer layer BUF may include an inorganic insulating material such as silicon oxide, silicon nitride, or aluminum oxide or may include an organic insulating material such as polyimide acrylic. As described above, the buffer layer BUF may be doped with fluorine and may contain fluorine.

[0137] The semiconductor layer 130 including channels of the transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 , first electrodes, and second electrodes is positioned on the buffer layer BUF.

[0138] A first gate insulating layer 141 covering the semiconductor layer 130 is positioned on the semiconductor layer 130 .

[0139] A first gate conductor including a first gate electrode 155 , a scan line 151 , a previous scan line 152 , and an emission control line 153 is positioned on the first gate insulating layer 141 .

[0140] A second gate insulating layer 142 covering the first gate conductor is positioned on the first gate conductor.

[0141] The first gate insulating layer 141 and the second gate insulating layer 142 may include an organic insulating material or an inorganic insulating material such as silicon nitride, silicon oxide, and aluminum oxide.

[0142] A second gate conductor including a storage line 126 , an initialization voltage line 127 , and a parasitic capacitor control pattern 79 is positioned on the second gate insulating layer 142 .

[0143] An interlayer insulating layer 160 covering the second gate conductor is positioned on the second gate conductor. The interlayer insulating layer 160 may include an inorganic insulating material such as silicon nitride, silicon oxide, and aluminum oxide, or an organic insulating material.

[0144] A data conductor including a data line 171, a driving voltage line 172, a first data connection member 71, a second data connection member 72, and a third data connection member 73 is positioned over the interlayer insulating layer 160. The first data connection member 71 may be connected to the first gate electrode 155 through the contact hole 61.

[0145] A passivation layer 180 covering the data conductor is positioned on the data conductor. The passivation layer 180 may be a planarization layer, and may include an organic insulating material or an inorganic insulating material.

[0146] The first electrode 191 is positioned on the passivation layer 180. The first electrode 191 is connected to the third data connection member 73 through a contact hole 81 formed in the passivation layer 180.

[0147] The pixel defining layer 350 is positioned on the passivation layer 180 and the first electrode 191. The pixel defining layer 350 has an opening 351 overlapping the first electrode 191. The light emitting layer 370 is positioned in the opening 351. The second electrode 270 is positioned on the light emitting layer 370 and the pixel defining layer 350. The first electrode 191, the light emitting layer 370, and the second electrode 270 form a light emitting element LED.

[0148] The first electrode 191 may be a pixel electrode, and the second electrode 270 may be a common electrode. According to an embodiment, the pixel electrode may be an anode as a hole injection electrode, and the common electrode may be a cathode as an electron injection electrode. Conversely, the pixel electrode may be a cathode and the common electrode may be an anode. When holes and electrons are injected into the light emitting layer 370 from the pixel electrode and the common electrode, respectively, the excitons generated by the recombination of the injected holes and electrons emit light when they fall from an excited state to a ground state.

[0149] The encapsulation layer 700 protecting the light emitting element LED is positioned on the second electrode 270. As shown in the figure, the encapsulation layer 700 may contact the second electrode 270, but according to an embodiment, the encapsulation layer 70 may be alternatively spaced apart from the second electrode 270. The encapsulation layer 700 may be a thin film encapsulation layer in which an inorganic layer and an organic layer are stacked and may include three layers consisting of an inorganic layer, an organic layer, and an inorganic layer. According to an embodiment, a capping layer and a functional layer may be positioned between the second electrode 270 and the encapsulation layer 700.

[0150] Although specific embodiments have been described in detail above, the scope of the present disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art using the concepts disclosed herein and defined in the appended claims are also included in the scope of the appended claims.

Claims

1. A method for manufacturing a display device, wherein: The method comprises: forming amorphous silicon on a substrate; forming a conductive protective layer on the amorphous silicon; doping with fluorine; and The conductive protective layer is removed.

2. The method according to claim 1, wherein: The method further comprises: After the removing of the conductive protection layer, the amorphous silicon is crystallized.

3. The method according to claim 1, wherein: The conductive protection layer includes a metal that does not form silicide with the amorphous silicon.

4. The method according to claim 3, wherein: The metal includes molybdenum.

5. The method according to claim 1, wherein: The conductive protection layer includes a transparent conductive oxide.

6. The method according to claim 5, wherein: The transparent conductive oxide includes at least one selected from indium gallium zinc oxide, indium tin oxide, and indium zinc oxide.

7. The method according to claim 1, wherein: The thickness of the conductive protective layer is and between.

8. The method according to claim 1, wherein: The method further includes: before forming the amorphous silicon on the substrate, forming an insulating film on the substrate.

9. A display device, wherein: The display device comprises: substrate; an insulating film positioned on the substrate; A semiconductor layer, located on the insulating film; A transistor comprising the semiconductor layer; and A light emitting element is connected to the transistor, wherein: The semiconductor layer includes crystalline silicon, and At least one of the insulating film and an upper portion of the semiconductor layer is doped with fluorine.

10. The display device according to claim 9, wherein: The insulating film includes an organic film in contact with the substrate; and The inorganic film is in contact with the semiconductor layer.

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