Power and data routing structures for organic light emitting diode displays

Abstract

The invention relates to a power and data routing structure for organic light emitting diode displays. The organic light emitting diode display may have a fillet. A negative power path may be used to distribute a negative voltage to the cathode layer, while a positive power path may be used to distribute a positive power voltage to each pixel in the display. The positive power path may have a cutout occupied by the negative power path to reduce the resistance of the negative power path located in the fillet of the display. To mitigate reflections caused by a positive power path formed over closely spaced data lines, a positive power path may be omitted in a fillet of a display, a shielding layer may be formed over the positive power path in the fillet, or a non-linear gate line may be formed over the positive power path.

Description

[0001] This application is a divisional application of Chinese patent application 201910460227.7, whose application date is May 30, 2019 and whose invention name is “Power and data routing structure for organic light emitting diode display”.

[0002] This patent application claims priority to U.S. Patent Application No. 16 / 375,756 filed on April 4, 2019 and U.S. Provisional Patent Application No. 62 / 688,971 filed on June 22, 2018, which are hereby incorporated by reference in their entirety. Technical Field

[0003] The present invention relates generally to electronic devices, and more particularly to electronic devices having organic light emitting diode displays. Background Art

[0004] An electronic device typically includes a display. For example, the electronic device may have an organic light emitting diode display based on organic light emitting diode pixels. Each pixel may have a pixel circuit including a corresponding light emitting diode. A thin film transistor circuit in the pixel circuit may be used to control the application of current to the light emitting diode in the pixel. The thin film transistor circuit may include a drive transistor. The drive transistor and the light emitting diode in the pixel circuit may be coupled in series between a positive power supply and a negative power supply.

[0005] Signals in an OLED display, such as power signals, may experience undesirable voltage drops due to resistive losses in the conductive paths used to distribute these signals. If care is not taken, these voltage drops can prevent the OLED display from functioning properly. Challenges may also arise when distributing power and data signals in displays with layouts where signal routing space is limited.

[0006] It would therefore be desirable to be able to provide an improved way to distribute signals, such as power signals and data signals, across a display, such as an organic light emitting diode display. Summary of the invention

[0007] An organic light emitting diode display may have a thin film transistor circuit formed on a substrate. The display and substrate may have rounded corners. A pixel defining layer may be formed on the thin film transistor circuit. An opening in the pixel defining layer may be provided with an emissive material that overlaps a corresponding anode of the organic light emitting diode.

[0008] The cathode layer may cover the pixel array. The negative power path may be used to distribute the second power supply voltage to the cathode layer, and the positive power path may be used to distribute the positive power supply voltage to each pixel in the pixel array. The positive power path may have a cutout between the two portions occupied by the negative power path to reduce the resistance of the negative power path located in a rounded corner of the display.

[0009] The negative power path can be formed by a metal layer, which can be shorted to the cathode layer using a portion of the metal layer forming the anode of the diode. Extending the negative power path into the cutout area of ​​the positive power path can increase the contact area between the negative power path and the anode metal layer, and can increase the contact area between the anode metal layer and the cathode layer.

[0010] To mitigate reflections caused by positive power paths formed over closely spaced data lines, the positive power paths may be omitted in the rounded corner areas of the display. A shielding layer may be formed over the positive power paths in the rounded corner areas to mitigate reflections. A non-straight gate line may be formed over the positive power paths in the rounded corner areas to mitigate reflections. An anti-reflective layer or a light absorbing organic layer may also be incorporated into the display to mitigate reflections. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram of an illustrative electronic device with a display according to one embodiment.

[0012] Figure 2 is a diagram of an exemplary organic light emitting diode pixel circuit according to one embodiment.

[0013] Figure 3 is a diagram of an exemplary organic light emitting diode display according to one embodiment.

[0014] Figure 4 is a cross-sectional side view of a portion of an active area of ​​an exemplary organic light emitting diode display according to an embodiment.

[0015] Figure 5 is a top view of a rounded corner of an illustrative organic light emitting diode display showing a second power supply voltage distribution path and a positive power supply distribution path according to one embodiment.

[0016] Figure 6 is a diagram showing how to short the second supply voltage distribution path to the cathode layer along the right edge of the display according to one embodiment Figure 5 A cross-sectional side view of the display is shown.

[0017] Figure 7 A diagram showing how to short-circuit a second power supply voltage distribution path to a cathode layer along a rounded corner of a display according to one embodiment Figure 5 A cross-sectional side view of the display is shown.

[0018] Figure 8 FIG. 1 is a diagram showing a contact area between a cathode layer and an anode metal layer and a contact area between the anode metal layer and a second supply voltage distribution path according to one embodiment. Figure 5A top view of an illustrative display with rounded corners.

[0019] Fig. 9 is a top view of a rounded corner of an illustrative organic light emitting diode display showing a second power supply voltage distribution path having an expanded width to occupy a cutout area of ​​a positive power supply distribution path according to one embodiment.

[0020] Fig.10 A diagram showing how to short-circuit a second power supply voltage distribution path to a cathode layer along a rounded corner of a display according to one embodiment Fig. 9 A cross-sectional side view of the display is shown.

[0021] Fig.11 FIG. 1 is a diagram showing a contact area between a cathode layer and an anode metal layer and a contact area between the anode metal layer and a second supply voltage distribution path according to one embodiment. Fig. 9 A top view of an illustrative display with rounded corners.

[0022] Fig.12 is a top view of a rounded corner of an illustrative organic light emitting diode display showing how a positive supply voltage distribution path may be formed over a data line according to one embodiment.

[0023] Fig.13 is a diagram showing a depression in the positive supply voltage distribution path according to one embodiment. Fig.12 A cross-sectional side view of an exemplary display.

[0024] Fig.14 is a top view of a rounded corner of an illustrative organic light emitting diode display showing how a positive supply voltage distribution path may be omitted to achieve reflection reduction according to one embodiment.

[0025] Fig.15 According to one embodiment, there is no positive supply voltage distribution path Fig.14 A cross-sectional side view of an exemplary display.

[0026] Fig.16 is a top view of a rounded corner of an illustrative organic light emitting diode display showing how a shielding layer may be formed over a positive supply voltage distribution path to achieve reflection mitigation according to one embodiment.

[0027] Fig.17 According to one embodiment, a shielding layer Fig.16 A cross-sectional side view of an exemplary display.

[0028] Fig.18 is an exemplary shielding layer according to one embodiment (such as Fig.16 Top view of a shielding layer with holes in it.

[0029] Fig.19 is a top view of a rounded corner of an illustrative organic light emitting diode display having a non-linear gate line formed above a positive power supply voltage distribution path according to one embodiment.

[0030] Fig. 20 is a cross-sectional side view of an illustrative display including an anti-reflective layer between a metal layer and a dielectric layer in a rounded corner portion according to one embodiment.

[0031] Fig.21 is a cross-sectional side view of an illustrative display including an antireflective layer between a metal layer and a dielectric layer in a rounded corner portion and having a plurality of dielectric layers between the metal layers according to one embodiment.

[0032] Fig. 22 is a cross-sectional side view of an illustrative display including a light absorbing organic layer between a metal layer and a dielectric layer in a rounded corner portion according to one embodiment.

[0033] Fig.23 is a cross-sectional side view of an illustrative display including an anti-reflective layer over a metal layer and a dielectric layer in a rounded corner portion according to one embodiment.

[0034] Fig.24 is a cross-sectional side view of an illustrative display including a light absorbing organic layer over a metal layer and a dielectric layer in a rounded corner portion according to one embodiment.

[0035] Fig.25 is a cross-sectional side view of an illustrative display including a light absorbing organic layer over a metal layer in rounded corner portions according to one embodiment. DETAILED DESCRIPTION

[0036] Figure 1 An exemplary electronic device of the type that may be provided with an organic light emitting diode display is shown. The electronic device 10 may be a computing device such as a laptop computer, a computer monitor including an embedded computer, a tablet computer, a cellular phone, a media player, or other handheld or portable electronic device, a smaller device (such as a wristwatch device, a pendant device, a headset or earpiece device, a device embedded in glasses or other devices worn on a user's head, or other wearable or miniature devices), a display, a computer display including an embedded computer, a computer display not including an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which an electronic device with a display is installed in an information kiosk or a car), or other electronic device.

[0037] The device 10 may include a control circuit 16. The control circuit 16 may include storage and processing circuits for supporting the operation of the device 10. The storage and processing circuits may include storage devices such as non-volatile memory (e.g., flash memory or other electrically programmable read-only memory configured to form a solid-state drive), volatile memory (e.g., static or dynamic random access memory), etc. The processing circuits in the control circuit 16 may be used to collect inputs from sensors and other input devices, and may be used to control output devices. The processing circuits may be based on one or more microprocessors, microcontrollers, digital signal processors, baseband processors and other wireless communication circuits, power management units, audio chips, application-specific integrated circuits, etc.

[0038] To support communications between device 10 and external devices, control circuitry 16 may communicate using communication circuitry 21. Circuitry 21 may include an antenna, radio frequency transceiver circuitry, and other wireless communications circuitry and / or wired communications circuitry. Circuitry 21, which may sometimes be referred to as control circuitry and / or control and communications circuitry, may support two-way wireless communications between device 10 and external devices via a wireless link (e.g., circuitry 21 may include radio frequency transceiver circuitry, such as wireless local area network transceiver circuitry configured to support communications via a wireless local area network link, near field communications transceiver circuitry configured to support communications via a near field communications link, cellular telephone transceiver circuitry configured to support communications via a cellular telephone link, or transceiver circuitry configured to support communications via any other appropriate wired or wireless communications link). For example, communication may be performed via a wireless link. link, Wireless communications may be supported by a wireless link, a 60 GHz link or other millimeter wave link, a cellular telephone link, or other wireless communications link. Device 10 may include power circuitry for transmitting and / or receiving wired and / or wireless power, if desired, and may include a battery or other energy storage device. For example, device 10 may include a coil and a rectifier to receive wireless power provided to circuits in device 10.

[0039] Device 10 may include input-output devices, such as device 12. Input-output device 12 may be used to collect user input, to collect information about the user's surroundings, and / or to provide output to the user. Device 12 may include one or more displays, such as display 14. Display 14 may be an organic light emitting diode display, a liquid crystal display, an electrophoretic display, an electrowetting display, a plasma display, a micro-electromechanical system display, a display having an array of pixels formed by crystalline semiconductor light emitting diode die (sometimes referred to as micro-LEDs), and / or other displays. Display 14 may have an array of pixels configured to display an image to a user. Display pixels may be formed on a substrate such as a flexible substrate (e.g., display 14 may be formed by a flexible display panel). An array of conductive electrodes for a capacitive touch sensor in display 14 and / or indium tin oxide electrodes or other transparent conductive electrodes overlapping display 14 may be used to form a two-dimensional capacitive touch sensor for display 14 (e.g., display 14 may be a touch-sensitive display).

[0040] Sensors 17 in input-output device 12 may include force sensors (e.g., strain gauges, capacitive force sensors, resistive force sensors, etc.), audio sensors (such as microphones), touch and / or proximity sensors (such as capacitive sensors, for example, two-dimensional capacitive touch sensors integrated into display 14, two-dimensional capacitive touch sensors overlapping display 14 and / or touch sensors forming buttons, touch pads, or other input devices not associated with the display), and other sensors. If desired, sensor 17 may include optical sensors (such as optical sensors that emit and detect light), ultrasonic sensors, optical touch sensors, optical proximity sensors and / or other touch sensors and / or proximity sensors, monochrome and color ambient light sensors, image sensors, fingerprint sensors, temperature sensors, sensors for measuring three-dimensional contactless gestures ("air gestures"), pressure sensors, sensors for detecting position, orientation and / or motion (for example, accelerometers, magnetic sensors such as compass sensors, gyroscopes and / or inertial measurement units that include some or all of these sensors), health sensors, radio frequency sensors, depth sensors (for example, structured light sensors and / or depth sensors based on stereo imaging devices), optical sensors such as self-mixing sensors and optical detection and ranging (lidar) sensors that collect time-of-flight measurements, humidity sensors, moisture sensors, gaze tracking sensors, and / or other sensors. In some arrangements, device 10 may use sensors 17 and / or other input-output devices to collect user input (e.g., buttons may be used to collect button press inputs, touch sensors overlapping a display may be used to collect touch screen inputs, a touchpad may be used to collect touch inputs, a microphone may be used to collect audio inputs, an accelerometer may be used to monitor when a finger contacts an input surface and thereby may be used to collect finger press inputs, etc.).

[0041] If desired, electronic device 10 may include additional components (e.g., see other devices 19 in input-output devices 12). Additional components may include tactile output devices, audio output devices such as speakers, light emitting diodes for status indicators, light sources such as light emitting diodes that illuminate portions of the housing and / or display structure, other optical output devices, and / or other circuits for collecting input and / or providing output. Device 10 may also include a battery or other energy storage device, a connector port for supporting wired communication with auxiliary devices and for receiving wired power, and other circuits.

[0042] Display 14 may be an organic light emitting diode display, in which each display pixel includes a respective organic light emitting diode. Figure 2 A schematic diagram of an exemplary organic light emitting diode pixel is shown in FIG. Figure 2As shown, the display pixel 22 may include a light emitting diode 38. A positive power supply voltage ELVDD may be provided to a positive power supply terminal 34, and a second power supply voltage ELVSS may be provided to a negative power supply terminal 36. The diode 38 has an anode (terminal AN) and a cathode (terminal CD). The state of the drive transistor 32 controls the amount of current flowing through the diode 38, and thus controls the amount of emitted light 40 from the display pixel 22. Since the cathode CD of the diode 38 is coupled to the negative power supply terminal 36, the cathode terminal CD of the diode 38 may sometimes be referred to as the negative terminal of the diode 38.

[0043] To ensure that transistor 32 remains in a desired state between consecutive frames of data, display pixel 22 may include a storage capacitor, such as storage capacitor Cst. A first terminal of storage capacitor Cst may be coupled to the gate of transistor 32 at node A and a second terminal of storage capacitor Cst may be coupled to anode AN of diode 38 at node B. The voltage on storage capacitor Cst is applied to the gate of transistor 32 at node A to control transistor 32. One or more switching transistors, such as switching transistor 30, may be used to load data into storage capacitor Cst. When switching transistor 30 is turned off, data line D is isolated from storage capacitor Cst, and the gate voltage on node A is equal to the data value stored in storage capacitor Cst (i.e., the data value from the previous frame of display data displayed on display 14). When gate line G (sometimes referred to as a scan line) in a row associated with display pixel 22 is asserted, switching transistor 30 will be turned on and a new data signal on data line D will be loaded into storage capacitor Cst. The new signal on capacitor Cst is applied to the gate of transistor 32 at node A, thereby adjusting the state of transistor 32 and the corresponding amount of light 40 emitted by light emitting diode 38 .

[0044] If necessary, use Figure 2 A circuit for controlling the operation of the light emitting diodes of the pixels 22 in the display 14 (e.g., a display pixel circuit (such as a display pixel circuit)) is formed by using a configuration other than the configuration of (e.g., a configuration including a circuit for compensating for a threshold voltage variation in the drive transistor 32, a configuration in which an emission enable transistor is coupled in series with the drive transistor 32, a configuration having a plurality of switch transistors controlled by a plurality of corresponding scan lines, a configuration having a plurality of capacitors, etc.) Figure 2 transistors, capacitors, etc. in display pixel circuits). Figure 2 The circuits of pixel 22 are merely illustrative.

[0045] like Figure 3As shown, display 14 may include layers, such as substrate layer 24. Substrate 24 and other layers in display 14 (if desired) may be formed of material layers such as glass layers, polymer layers (e.g., flexible polyimide sheets or other flexible polymers), etc. Substrate 24 may be planar and / or may have one or more curved portions. Substrate 24 may have a rectangular shape with left and right vertical edges and upper and lower horizontal edges, or may have a non-rectangular shape. In a configuration in which substrate 24 has a rectangular shape with four corners, these corners may be rounded if desired. If desired, display substrate 24 may have a tail portion, such as tail 24T.

[0046] Display 14 may have an array of pixels 22. Pixels 22 form an active area AA of display 14 that displays images to a user. Inactive boundary portions of display 14, such as inactive areas IA along one or more edges of substrate 24, do not contain pixels 22 and do not display images to a user (i.e., inactive areas IA are devoid of pixels 22).

[0047] Each pixel 22 may have a light emitting diode such as Figure 2 The organic light emitting diode 38 and the associated thin film transistor circuit (e.g., Figure 2 24). The array of pixels 22 may be formed by rows and columns of pixel structures (e.g., pixels formed by structures on a display layer such as substrate 24). There may be any suitable number of rows and columns in the array of pixels 22 (e.g., ten or more, one hundred or more, or one thousand or more). Display 14 may include pixels 22 of different colors. For example, display 14 may include red pixels that emit red light, green pixels that emit green light, and blue pixels that emit blue light. If desired, a configuration in which display 14 includes pixels of other colors may be used. The use of a pixel arrangement having red pixels, green pixels, and blue pixels is merely illustrative.

[0048] like Figure 3 As shown in the example of , display substrate 24 may have a tail portion, such as tail portion 24T, having a narrower width than a portion of substrate 24 containing active area AA. This arrangement helps tail portion 24T be contained within a housing of device 10. If desired, tail portion 24T may be curved under the remainder of display 14 when display 14 is mounted within an electronic device housing.

[0049] Display driver circuitry 20 of display 14 may be mounted on a printed circuit board coupled to tail portion 24T or may be mounted on tail portion 24T. Signal paths such as signal path 26 may couple display driver circuitry 20 to control circuitry 16. Circuitry 20 may include one or more display driver integrated circuits and / or thin-film transistor circuits. During operation, control circuitry (e.g., Figure 1 The control circuit 16) can provide information about the image to be displayed on the display 14 to circuits such as display driver circuits 20. In order to display an image on the display pixels 22, the display driver circuit 20 can provide corresponding image data to the data lines D, while issuing clock signals and other control signals to supporting display driver circuits such as gate driver circuits (GIP) 18. The gate driver circuit 18 can generate gate line signals (sometimes referred to as scan signals, emission enable signals, etc.), or other control signals for the pixels 22. Lines such as gate lines G can be used to transmit the gate line signals to the pixels 22. There can be one or more gate lines for each row of pixels 22. The gate driver circuit 18 may include integrated circuits and / or thin film transistor circuits and may be arranged along the edges of the display 14 (for example, along the edges such as Figure 3 The circuit 20 may be positioned at the left and / or right edge of the display 14 as shown) or elsewhere in the display 14 (e.g., as part of the circuit 20 on the tail 24T, along the bottom edge of the display 14, etc.). Figure 3 The configuration is for illustrative purposes only.

[0050] The display driver circuit 20 provides data signals to a plurality of corresponding data lines D. Figure 3 In the exemplary arrangement of FIG. 1 , data lines D extend vertically through display 14 . Data lines D are associated with corresponding columns of pixels 22 .

[0051] use Figure 3 In an exemplary configuration of the display 14, gate lines G (sometimes referred to as scan lines, emission lines, etc.) extend horizontally through the display 14. Each gate line G is associated with a corresponding row of display pixels 22. If desired, there may be multiple horizontal control lines such as gate lines G associated with each row of pixels 22. The gate driver circuit 18 can assert the gate signals on the gate lines G in the display 14. For example, the gate driver circuit 18 can receive clock signals and other control signals from the display driver circuit 20, and can assert the gate signals on the gate lines G in sequence starting with the gate line signals G in the first row of display pixels 22 in response to the received signals. When each gate line is asserted, data from the data line D is loaded into the corresponding row of display pixels. In this way, the control circuits such as the display driver circuit 20 in the device 10 can provide the pixels 22 with signals for directing the pixels 22 to generate light for displaying a target image on the display 14.

[0052] Thin-film transistor circuits may be used to form circuitry for pixel 22 and display driver circuitry (if desired) such as circuitry 18 and / or 20. Thin-film transistors in display 14 may generally be formed using any suitable type of thin-film transistor technology (e.g., silicon transistors such as polysilicon thin-film transistors, semiconductor oxide transistors such as indium gallium zinc oxide transistors, etc.).

[0053] Conductive paths (e.g., one or more signal lines, blanket conductive films, and other patterned conductive structures) may be provided in display 14 to route data signals D and power signals such as positive power signal ELVDD and negative power signal ELVSS to pixels 22. Figure 3 As shown, these signals may be provided to pixels 22 in active area AA using signal routing paths that receive signals D, ELVDD, and ELVSS from tail portion 24T of display 14 .

[0054] Any desired signal path arrangement may be used to provide power supply signals ELVDD and ELVSS to pixels 22. Vertical and / or horizontal conductive paths may provide a positive power supply signal ELVDD to each pixel (e.g., an anode) in the display. For example, the display may include a plurality of vertical conductive paths, each of which provides a positive power supply signal to a corresponding column of pixels. Alternatively, the display may include a plurality of vertical and horizontal conductive paths (sometimes referred to as a grid) that provide a positive power supply signal to pixels in the display. The display may include an L-shaped or other curved conductive path for providing a positive power supply signal to a pixel.

[0055] The negative power signal ELVSS may be provided to a blanket cathode layer formed over the entire display. The cathode layer may cover all pixels 22 in the active area AA of the display 14, and may have a portion extending into the inactive area IA of the display 14, which is coupled to a negative power path that provides the second power supply voltage ELVSS to the cathode layer. The cathode layer may be thin enough to make it transparent, thereby obtaining a relatively large sheet resistance. In order to reduce the sheet resistance of the cathode, and thereby allow the second power supply voltage ELVSS to be assigned to the cathode terminal of the diode 38 in the pixel 22 with the lowest IR loss, the display 14 may be provided with a supplementary conductive path. For example, a vertical and / or horizontal conductive path (e.g., a grid) formed in the active area of ​​the display may be connected to a negative power supply path in the inactive area of ​​the display to reduce resistance. These examples of conductive paths for distributing power signals ELVDD and ELVSS are merely illustrative. Any desired conductive path arrangement may be used to distribute power signals ELVDD and ELVSS to the display.

[0056] Figure 4A cross-sectional side view of a portion of active area AA of display 14 is shown in FIG. 1 , which illustrates an exemplary configuration that may be used to form pixel 22. Figure 4 As shown, display 14 may have a substrate such as substrate 24. Thin-film transistors, capacitors, and other thin-film transistor circuits 50 (e.g., pixel circuits such as Figure 2 2) may be formed on substrate 24. Pixel 22 may include an organic light emitting diode 38. An anode AN of diode 38 may be formed by metal layer 58 (sometimes referred to as an anode metal layer). Each diode 38 may have a cathode CD formed by a conductive cathode structure such as cathode layer 60. Layer 60 may be, for example, a thin metal layer, such as a magnesium silver layer having a thickness of 10nm-18nm, greater than 8nm, less than 25nm, etc. Layer 60 may cover all pixels 22 in active area AA of display 14 and may have a portion extending to inactive area IA of display 14 (e.g., such that layer 60 is coupled to a negative power supply path that provides second power supply voltage ELVSS to layer 60).

[0057] Each diode 38 has an organic light emitting emission layer (sometimes referred to as an emission material or emission layer structure), such as emission layer 56. Emission layer 56 is an electroluminescent organic layer that emits light 40 in response to an applied current through diode 38. In a color display, the emission layer 56 in the pixel array in the display includes a red light emission layer for emitting red light in red pixels, a green light emission layer for emitting green light in green pixels, and a blue light emission layer for emitting blue light in blue pixels. In addition to the emission organic layer in each diode 38, each diode 38 may also include additional layers for improving diode performance, such as electron injection layers, electron transport layers, hole transport layers, and hole injection layers. Layers such as these layers can be formed of organic materials (e.g., materials on the upper and lower surfaces of the electroluminescent material in layer 56).

[0058] Layer 52 (sometimes referred to as a pixel definition layer) has an array of openings that contain corresponding portions of the emissive material of layer 56. An anode AN is formed at the bottom of each of these openings and overlaps emissive layer 56. Thus, the shape of the diode opening in pixel definition layer 52 defines the shape of the light emitting area of ​​diode 38.

[0059] Pixel definition layer 52 may be formed from a photosensitive material that is patterned photolithographically (e.g., a dielectric material that can be processed to form photolithographically defined openings, such as photosensitive polyimide, photosensitive polyacrylate, etc.), may be formed from a material deposited through a shadow mask, or may be formed from a material that is otherwise patterned onto substrate 24. If desired, the walls of the diode openings in pixel definition layer 52 may be sloped, such as Figure 4The side wall 64 may also have a curved portion, multiple portions inclined at different angles, and the like.

[0060] Thin film circuit 50 may include transistors, such as exemplary transistor 32. Thin film transistor circuits such as Figure 4 The exemplary thin film transistor 32 may have an active area (channel area) formed by a patterned semiconductor layer such as layer 70. Layer 70 may be formed by a semiconductor layer such as a polysilicon layer or a semiconductor oxide material (e.g., indium gallium zinc oxide) layer. Source-drain terminals 72 may contact opposite ends of semiconductor layer 70. Gate 76 may be formed by a patterned gate metal layer or other conductive layer and may overlap semiconductor 70. Gate insulator 78 may be interposed between gate 76 and semiconductor layer 70. Buffer layers such as dielectric layer 84 may be formed on substrate 24 below shield 74. Dielectric layers such as dielectric layer 82 may cover shield 74. Dielectric layer 80 may be formed between gate 76 and source-drain terminals 72. Layers such as layers 84, 82, 78, and 80 may be formed of dielectrics such as silicon oxide, silicon nitride, other inorganic dielectric materials, or other dielectrics. Additional dielectric layers such as organic planarization layers PLN1 and PLN2 may be included in thin-film transistor structures such as transistor 32 and may help planarize display 14 .

[0061] Display 14 may have multiple layers of conductive material embedded in the dielectric layer of display 14, such as metal layers for routing signals through pixel 22. Shielding layer 74 may be formed from a first metal layer (for example). Gate layer 76 may be formed from a second metal layer. Source-drain terminals such as terminal 72 and other structures such as signal line 86 may be formed from portions of a third metal layer such as metal layer 89. Metal layer 89 may be formed on dielectric layer 80 and may be covered with a planarizing dielectric layer PLN1. A fourth layer of metal (such as metal layer 91) may be used to form a diode via portion 88 and signal line 90. In active area AA, a fifth metal layer such as anode metal layer 58 may form an anode AN of diode 38. The fifth metal layer in each pixel may have a portion, such as via portion 58P coupled to via portion 88, so that one source-drain terminal of transistor 32 is coupled to anode AN of diode 38. A sixth metal layer (e.g., a capping film) such as cathode metal layer 60 may be used to form cathode CD of light emitting diode 38. Anode layer 58 may be interposed between metal layer 91 and cathode layer 60. Layers such as layers 58, 91, 89, 76, and 74 may be embedded within a dielectric layer of display 14 that is supported on substrate 24. If desired, fewer metal layers may be provided within display 14 or display 14 may have more metal layers. Figure 4 The configuration of is merely exemplary, and other arrangements for thin film transistor circuitry 50 may be used if desired.

[0062] Minimizing ohmic losses (sometimes referred to as IR losses) is desirable when distributing power signals to pixels 22 to ensure that display 14 operates efficiently and produces an image with uniform brightness over display 14. Ohmic losses may be minimized by incorporating low resistance signal paths into display 14.

[0063] Some of the layers of display 14, such as cathode layer 60, may be thin. Cathode layer 60 may be formed of a metal such as magnesium silver. To ensure that cathode CD is thin enough to be transparent, layer 60 may be approximately 10 nm-18 nm thick (or other suitable thickness). In this type of configuration, the sheet resistance of layer 60 may be relatively large (e.g., approximately 10 ohms / square). In order to reduce the sheet resistance of the cathode, and thereby allow second supply voltage ELVSS to be distributed to the cathode terminal of diode 38 in pixel 22 with minimal IR losses, display 14 may be provided with a supplemental conductive path. Such a path may also help to enable Figure 4 Display 14 (or displays having other types of thin film stacks) accommodates display geometries having geometries that limit signal distribution (e.g., displays having rounded corners, etc.).

[0064] In one exemplary configuration, portions of metal layer 89 and / or metal layer 91 may be used to form a signal path, such as signal path 90, that acts as a supplemental ELVSS path (i.e., a signal path that may operate in parallel with the ELVSS path formed by cathode layer 60) and thereby help minimize voltage drops and IR losses when operating display 14. Metal layer 91 and / or metal layer 89 may be shorted to cathode layer 60 along one or more edges of display 14 (e.g., along the left edge, right edge, and bottom edge, along two or more edges, along three or more edges, etc.), and may provide a low resistance path between the source of signal ELVSS on tail 24T and the corresponding edge of cathode layer 60 (i.e., a lower resistance may be experienced when distributing a signal to the edge of layer 60 via a signal line in layer 91 than when distributing a signal to this portion of layer 60 via a thin metal within layer 60 itself). Reducing IR losses when powering layer 60 may help reduce power losses when driving diode 38 in active area AA. Using portions of layer 91 and / or layer 89 to form portions of a negative power path for distributing ELVSS in display 14 may also make it possible to reduce the width of inactive area IA. Portions of layer 91 and / or layer 89 may also be used to form supplemental conductive paths for distributing ELVDD in display 14.

[0065] As previously described, substrate 24 (and accordingly, the active area of ​​the display) may have a rectangular shape with four corners. One or more of the corners may be rounded (e.g., all corners may be rounded). The active area may optionally have a notched area without pixels along the upper edge of the display. Figure 5 is a top view of an exemplary display with rounded corners. Specifically, Figure 5 An arrangement of conductive paths for distributing the power supply voltages ELVDD and ELVSS is shown.

[0066] like Figure 5 As shown, the display 14 may include a first power distribution path 92 for distributing a positive power supply voltage ELVDD and a second power distribution path 94 for distributing a second power supply voltage ELVSS. The first power distribution path 92 (sometimes referred to as a positive power supply voltage distribution path, an ELVDD distribution path, a power line, a power rail, a conductive path, a power line, a positive power supply path, etc.) may be provided with a positive power supply voltage ELVDD from a tail portion 24T of the display 14. The second power distribution path 94 (sometimes referred to as a second power supply voltage distribution path, an ELVSS distribution path, a power line, a power rail, a conductive path, a power line, a negative power supply path, etc.) may be provided with a second power supply voltage ELVSS from a tail portion 24T of the display 14.

[0067] The positive supply voltage distribution path 92 has a horizontal portion 92H extending along the lower edge of the active area of ​​the display. The positive supply voltage distribution path 92 also has a rounded portion 92R that is rounded along the corners of the active area of ​​the display. The rounded portion 92R of the distribution path 92 is interposed between the gate driver circuit 18 (GIP) of the display and the active area AA. The rounded portion 92R may extend far enough to provide the ELVDD signal to all peripheral columns of display pixels in the display (e.g., to the rightmost column of pixels in the display). The positive supply voltage distribution path 92 may be shorted to a vertical ELVDD distribution path (such as vertical ELVDD distribution path 110) that extends through the active area of ​​the display. For clarity, Figure 5 Only some of the vertical ELVDD distribution paths are shown in FIG. The vertical ELVDD distribution paths 110 may optionally be connected to the horizontal ELVDD distribution paths 112. The horizontal ELVDD distribution paths 112 and the vertical ELVDD distribution paths 110 combine to form an ELVDD distribution grid. For clarity, Figure 5 Only some of the horizontal ELVDD distribution paths are shown in FIG. If desired, the horizontal ELVDD distribution paths may be omitted. The vertical distribution paths and / or the horizontal distribution paths may be coupled to the array of pixels 22 in the active area.

[0068] The second power supply voltage distribution path 94 has a horizontal portion 94H extending along the lower edge of the active area of ​​the display. The horizontal portion 92H of the positive power supply voltage distribution path 92 is interposed between the horizontal portion 94H and the active area AA. The horizontal portion 94H of the ELVSS distribution path 94 may have a width 116. The second power supply voltage distribution path 94 also has a rounded portion 94R along the rounded corners of the active area of ​​the display. The gate driver circuit 18 is interposed between the rounded portion 94R of the distribution path 94 and the rounded portion 92R of the distribution path 92. The rounded portion 94R is interposed between the horizontal portion 94H and the vertical portion 94V. The gate driver circuit 18 is interposed between the vertical portion 94V of the distribution path 94 and the active area AA.

[0069] The second supply voltage distribution path 94 can be shorted to the cathode layer of the active area of ​​the blanket display. Specifically, the ELVSS distribution path 94 can be electrically connected to the cathode layer through the anode metal layer. Although this layer of anode metal does not actually form an anode, the anode metal layer can be formed from the same metal layer as the anode in the pixel 22 (and is therefore referred to herein as anode metal or anode metal layer).

[0070] Figure 6 is along Figure 5 1. A cross-sectional side view taken along line 102 in FIG. 4 shows how the ELVSS distribution path is shorted to the cathode layer along an edge of the display (eg, the right edge of the display). Figure 6 A pixel 22 (a pixel adjacent to the edge of the active area) is shown with an anode AN formed of a metal layer 58, an emitter layer 56, and a cathode 60 (CD). For simplicity, thin film transistor circuitry 50 (e.g., such as Figure 4 The details of the thin film transistor circuit 50 in FIG. Figure 6 Clearly shown in.

[0071] like Figure 6As shown, the gate driver circuit 18 is inserted between the pixel 22 (and the thin film transistor circuit 50) and the ELVSS distribution path 94. In order to couple the ELVSS distribution path 94 to the cathode layer 60, the anode metal layer 58 includes an additional portion 114. Portion 114 of the metal layer 58 is formed in the same deposition step as the anode AN (and is therefore formed of the same material as the anode AN). As previously discussed, portion 114 may be referred to as anode metal, even if it does not form a pixel anode. The anode metal 114 may be formed above the gate driver circuit 18 and adjacent to the pixel defining layer 52. The first portion of the anode metal 114 is inserted between the gate driver circuit 18 and the cathode layer 60. The first portion of the anode metal may directly contact the cathode layer 60 on one side within the contact area 122. The second portion of the anode metal 114 is formed above the ELVSS distribution path 94 within the contact area 124 and is in direct contact with the ELVSS distribution path 94. In this way, the anode metal electrically connects the cathode layer 60 to the ELVSS distribution path 94. If desired, one or more intervening dielectric layers (eg, organic dielectric layers or other desired dielectric layers) may be formed between the anode metal 114 and the gate driver circuitry 18 .

[0072] Figure 7 is along Figure 5 1, which shows how the ELVSS distribution path is shorted to the cathode layer along the edge of the display (eg, along the bottom edge of a rounded display). Figure 7 A pixel 22 (a pixel adjacent to the edge of the active area) is shown with an anode AN formed of a metal layer 58, an emitter layer 56, and a cathode 60 (CD). For simplicity, thin film transistor circuitry 50 (e.g., such as Figure 5 The details of the thin film transistor circuit 50 in FIG. Figure 7 Clearly shown in.

[0073] like Figure 7 As shown, ELVDD distribution path 92 is interposed between pixel 22 (and thin film transistor circuit 50) and ELVSS distribution path 94. Figure 6 Similar to the discussion, anode metal 114 is used to couple ELVSS distribution path 94 to cathode layer 60. Portion 114 of metal layer 58 may be referred to as anode metal, even though it does not form a pixel anode. Anode metal 114 may be formed adjacent to pixel defining layer 52. Anode metal 114 may be formed over one or more dielectric layers. For example, anode metal 114 may be formed over a dielectric layer such as Figure 4Anode metal 114 is formed on a planarization layer (e.g., an organic planarization layer) of PLN2 and / or PLN1 as shown. A first portion of anode metal 114 can directly contact cathode layer 60 on one side within contact region 122. A second portion of anode metal 114 is formed on ELVSS distribution path 94 within contact region 124 and directly contacts ELVSS distribution path 94. In this way, anode metal 114 electrically connects cathode layer 60 to ELVSS distribution path 94.

[0074] Figure 8 yes Figure 5 A top view of an exemplary display of FIG. 1 showing the cathode to anode metal contact area and the anode metal to ELVSS distribution path contact area. Figure 8 As shown, cathode layer 60 extends through the active area of ​​the display into the inactive area. Although only the portion of cathode layer 60 in the inactive area is shaded, it should be understood that the cathode layer is formed as a blanket layer across the entire display. Cathode layer 60 overlaps anode metal 114. Cathode layer 60 and anode metal 114 have contact area 122. Anode metal 114 overlaps ELVSS distribution path 94. Anode metal 114 and ELVSS distribution path 94 have contact area 124.

[0075] Figure 5-Figure 8 The arrangement of the ELVSS distribution path 94 in is only exemplary. In some embodiments (e.g., when the invalid area space is limited), as Figure 5-Figure 8 The arrangement shown may cause undesirable temperature rise in the rounded corner area of ​​the display. Limited dead space limits the area available for ELVSS distribution paths. Figure 5-Figure 8 For an ELVSS distribution path arrangement, the high resistance and high current density can cause the temperature of the display to increase beyond desired levels (especially when the brightness level of the display is high). To avoid this temperature increase, a portion of the ELVDD distribution path can be removed and the ELVSS distribution path can be enlarged. This reduces the ELVSS distribution path resistance, thereby improving the thermal performance of the display. Increasing the size of the ELVSS distribution path also increases the size of the cathode to anode metal contact area and the size of the ELVSS distribution path to the anode metal contact area, providing additional improvements in thermal performance. Figure 9-11 This type of implementation is shown in .

[0076] like Fig. 9As shown, the display 14 may include a first power distribution path 92 for distributing a positive power supply voltage ELVDD and a second power distribution path 94 for distributing a second power supply voltage ELVSS. The first power distribution path 92 (sometimes referred to as a positive power supply voltage distribution path, an ELVDD distribution path, a power line, a power rail, a conductive path, a power line, a positive power supply path, etc.) may be provided with a positive power supply voltage ELVDD from a tail portion 24T of the display 14. The second power distribution path 94 (sometimes referred to as a second power supply voltage distribution path, an ELVSS distribution path, a power line, a power rail, a conductive path, a power line, a negative power supply path, etc.) may be provided with a second power supply voltage ELVSS from a tail portion 24T of the display 14.

[0077] The positive power supply voltage distribution path 92 has a horizontal portion 92H extending along the lower edge of the active area of ​​the display. The positive power supply voltage distribution path 92 also has a rounded portion 92R along the rounded corners of the active area of ​​the display. The rounded portion 92R of the distribution path 92 is interposed between the gate driver circuit 18 (GIP) of the display and the active area AA. However, unlike Figure 5 (wherein the continuous conductive path forms both the horizontal portion 92H and the rounded portion 92R of the ELVDD distribution path 92) The difference is that Fig. 9 In the embodiment of the present invention, the horizontal portion 92H and the rounded portion 92R are formed separately. In other words, the ELVDD distribution path 92 may have a cutout (discontinuity) 118 between the horizontal portion 92H and the rounded portion 92R.

[0078] The second power supply voltage distribution path 94 has a horizontal portion 94H extending along the lower edge of the active area of ​​the display. Fig. 9 In the embodiment, the horizontal portion 94H of the ELVSS distribution path 94 is extended to occupy the cutout area of ​​the ELVDD distribution path 92. By enlarging the size of the horizontal distribution path 94H, the width 120 (relative to the width of the horizontal distribution path 94H) can be increased. Figure 5 The width 116 of the horizontal distribution path 94H in the second power supply voltage distribution path 94). The horizontal portion 94H of the second power supply voltage distribution path 94 has a portion directly adjacent to the active area (without an intervening ELVDD distribution path and without an intervening gate driver circuit). The horizontal portion 94H also has a portion adjacent to the rounded portion 92R of the ELVSS distribution path 92 and adjacent to the gate driver circuit 18. The second power supply voltage distribution path 94 also has a rounded portion 94R along the rounded corners of the active area of ​​the display. The gate driver circuit 18 is inserted between the rounded portion 94R of the distribution path 94 and the rounded portion 92R of the distribution path 92. The rounded portion 94R is inserted between the horizontal portion 94H and the vertical portion 94V. The gate driver circuit 18 is inserted between the vertical portion 94V of the distribution path 94 and the active area AA.

[0079] The second power supply voltage distribution path 94 can be shorted to a cathode layer that blankets the active area of ​​the display. Specifically, the ELVSS distribution path 94 can be electrically connected to the cathode layer through an anode metal layer.

[0080] like Figure 5 As discussed in , vertical distribution paths and horizontal distribution paths (such as vertical distribution path 110 and horizontal distribution path 112) can be used to electrically connect ELVDD distribution path 92 to each pixel in the display. Fig. 9 In, with Figure 5 Those similar vertical distribution paths 110 and horizontal distribution paths 112 shown can be used to electrically connect the horizontal portion 92H of the distribution path to the fillet portion 92R of the distribution path. For example, the vertical distribution path can be coupled to the horizontal portion 92H. The horizontal distribution path can be coupled to both the vertical distribution path and the fillet portion 92R. The fillet portion 92R can then be coupled to an additional vertical distribution path. On the contrary or in addition, an L-shaped distribution path (such as an L-shaped distribution path 126) can be adopted to electrically connect the horizontal portion 92H of the distribution path to the fillet portion 92R of the distribution path.

[0081] along Fig. 9 A cross-sectional side view taken along line 106 is shown with respect to Figure 5 A cross-sectional side view taken along line 102 ( Figure 6 As shown in Figure 6 As shown, anode metal is used to short the ELVSS distribution path to the cathode layer along the edge of the display.

[0082] Fig.10 is along Fig. 9 , which shows how the ELVSS distribution path is shorted to the cathode layer along the edge of the display (eg, along the bottom edge of a rounded display). Fig.10 A pixel 22 (a pixel adjacent to the edge of the active area) is shown with an anode AN formed of a metal layer 58, an emitter layer 56, and a cathode 60 (CD). For simplicity, thin film transistor circuitry 50 (e.g., such as Figure 5 The details of the thin film transistor circuit 50 in FIG. Fig.10 Clearly shown in.

[0083] The ELVDD distribution path 92 is interposed between the pixel 22 (and the thin film transistor circuit 50) and the ELVSS distribution path 94. Figure 7 Different in Fig.10, the ELVSS distribution path 94 is directly adjacent to the active area of ​​the display. Anode metal 114 is used to couple the ELVSS distribution path 94 to the cathode layer 60. Portion 114 of metal layer 58 may be referred to as anode metal, even though it does not form a pixel anode. Anode metal 114 may be formed adjacent to pixel defining layer 52. Anode metal 114 may be formed on one or more dielectric layers. For example, anode metal 114 may be formed on a dielectric layer such as Figure 4 1 and 1. Anode metal 114 is formed on a planarization layer (e.g., an organic planarization layer) of PLN2 and / or PLN1 as shown. A first portion of anode metal 114 can directly contact cathode layer 60 on one side within contact region 122. A second portion of anode metal 114 is formed on ELVSS distribution path 94 within contact region 124 and directly contacts ELVSS distribution path 94. In this way, anode metal electrically connects cathode layer 60 to ELVSS distribution path 94.

[0084] Removing portions of ELVDD distribution path 92 and enlarging the ELVSS distribution path can increase the size of the anode metal contact area. Figure 7 In FIG. 1 , the width of the cathode layer to the anode metal contact area 122 is width 132, and the width of the anode metal to the ELVSS distribution path contact area 124 is width 134. Fig.10 In the embodiment, the width of the cathode layer to the anode metal contact area 122 is greater than Figure 7 The width 132 in the example is 136. Similarly, in Fig.10 In the embodiment, the width of the anode metal to ELVSS distribution path contact area 124 is greater than Figure 7 The width of 134 is 138. In addition, Figure 7 In FIG. 1 , the pixel defining layer 52 extends a distance 142 into the inactive area of ​​the display. The distance 142 also defines the distance between the anode metal 114 and the active area of ​​the display. Fig.10 In the embodiment, the pixel defining layer 52 extends into the inactive area of ​​the display by a distance 144 less than Figure 7 The distance 144 also defines the distance between the anode metal 114 and the active area of ​​the display. Figure 7 Compared with Fig.10 In the embodiment of the present invention, the distance between anode metal 114 and the active area of ​​the display is smaller. Distance 144 can be any desired distance (e.g., less than 500 microns, less than 200 microns, less than 100 microns, less than 50 microns, less than 30 microns, greater than 10 microns, greater than 30 microns, between 25 and 75 microns, between 10 and 150 microns, etc.).

[0085] Fig.11 yes Fig. 9A top view of an exemplary display of FIG. 1 showing the cathode to anode metal contact area and the anode metal to ELVSS distribution path contact area. Fig.11 As shown, the cathode layer 60 extends through the active area of ​​the display into the inactive area. Although only the portion of the cathode layer 60 in the inactive area is shaded, it should be understood that the cathode layer is formed as a blanket layer across the entire display. The cathode layer 60 overlaps the anode metal 114. The cathode layer 60 and the anode metal 114 have a contact area 122. It can be seen that Figure 9-11 The arrangement produces a Figure 5-Figure 8 The anode metal 114 also overlaps the ELVSS distribution path 94. The anode metal 114 has a contact area 124 with the ELVSS distribution path 94. It can be seen that Figure 9-11 The arrangement produces a Figure 5-Figure 8 The arrangement has a large contact area 124. Figure 5-Figure 8 Compared to displays of Figure 9-11 The thermal performance of the display is improved.

[0086] Forming a display with rounded corners and minimized dead area requires fanning out the data lines (eg, from the tail region 24T of the display) to reach all columns of pixels in the display. Fig.12 A top view of an exemplary display is shown with data lines D (e.g., coupled to tail region 24T). Positive supply voltage distribution path 92 may be formed over data lines D. Gate lines G (each gate line G being associated with a corresponding row of pixels 22) may be coupled between gate driver circuit 18 and active region AA.

[0087] Fig.13 yes Fig.12 A cross-sectional side view of a display. Fig.13 As shown, data line D may be formed on substrate 24. Additional layers may be formed on the data line. A metal layer for forming ELVDD distribution path 92 is formed on the data line. A gate line G is then formed on the ELVDD distribution path. A dielectric layer 140 may be interposed between each metal layer. Fig.13 In the example of FIG. 1 , one dielectric layer is interposed between the data line D and the ELVDD distribution path 92, and one dielectric layer is interposed between the ELVDD distribution path 92 and the gate line G. This example is merely illustrative, and more than one dielectric layer may be interposed between the conductive layers if desired. One or more dielectric layers may also be formed over the gate line G. The dielectric layer 140 may be formed of any desired material. The dielectric layer 140 may be formed of a planarization layer such as Figure 4 The same material as the PLN2 and / or PLN1 in the pixel defining layer (such as Figure 4The pixel defining layer 52 may be formed of the same material as that of the pixel defining layer 52 in the embodiment of the present invention, or may be formed of any other desired material.

[0088] Due to limited dead area space in the rounded corner regions of the display, the data lines D may be positioned close together. The close spacing between the data lines may result in undesired reflections from the rounded corner regions of the display. For example, because the data lines are positioned close together, the cover layer may have a depression (e.g., a topological structure imparted by the data lines). Fig.13 146 is shown in FIG. If the data lines are further apart, the recess 146 will have shallower sidewalls (eg, the upper surface of the ELVDD distribution path 92 will be closer to a plane). However, when the data lines are as shown in FIG. Fig.13 When shown close together, the recesses 146 may have more acutely angled sidewalls. Because the ELVDD distribution path 92 is reflective, the sharply formed recesses 146 may cause the rounded corner areas of the display to appear different from the rest of the display. Figure 14-Figure 19 An illustrative arrangement is shown that may be used to mitigate reflections from the recess 146 to ensure that the display has a uniform appearance across the display.

[0089] Fig.14 is a top view of an exemplary display having the ELVDD distribution path removed in the rounded corner area to reduce visible reflections from the ELVDD distribution path. Fig.14 As shown, the exemplary display has data lines D coupled to the tail region 24T and gate lines G coupled between the gate driver circuit 18 and the active region AA. Fig.12 and Fig.13 As discussed, the visible reflections caused by the tight data line spacing are reflections from the ELVDD distribution path. Fig.14 As shown, removing the ELVDD distribution path in the rounded corner area alleviates the reflection caused by the data line.

[0090] Columns of pixels in the rounded corner areas of the display may still receive a positive supply voltage (even if the positive supply voltage distribution path is removed below the columns of pixels in the rounded corner areas). To provide the columns of pixels in the rounded corner areas with a positive supply voltage, vertical, horizontal, and / or L-shaped distribution paths (e.g., as described in connection with FIG. 1 ) may be used that pass through the active area of ​​the display. Fig. 9In one embodiment, the horizontal distribution path and the vertical distribution path may form an ELVDD distribution grid that distributes the positive supply voltage across the entire active area of ​​the display. The pixel columns in the rounded corner area will receive the positive supply voltage from the ELVDD distribution grid (even if the ELVDD distribution path 92 is removed in the rounded corner area). Alternatively, an L-shaped distribution path may be used to provide the positive supply voltage to the pixel columns in the rounded corner area.

[0091] Fig.15 yes Fig.14 A cross-sectional side view of a display. Fig.15 As shown, data line D can be formed on substrate 24. Additional layers can be formed above the data line. Gate line G is formed above the data line without an intervening ELVDD distribution path. Fig.15 There is no reflective ELVDD distribution path in the display, so the undesired reflection caused by the data line D is reduced. One or more dielectric layers 140 can be interposed between each metal layer. One or more dielectric layers can also be formed over the gate line G.

[0092] Fig.16 is a top view of an exemplary display having an additional metal layer formed over the ELVDD distribution path to mitigate visible reflections from the ELVDD distribution path. Fig.16 As shown, the exemplary display has a data line D coupled to the tail region 24T and a gate line G coupled between the gate driver circuit 18 and the active region AA. The ELVDD distribution path 92 is formed above the data line. Fig.12 and Fig.13 As discussed, the visible reflections caused by the tight data line spacing are reflections from the ELVDD distribution path 92. Fig.16 As shown, an additional metal layer 148 is formed over the ELVDD distribution path in the rounded corner area to mitigate reflections caused by the data line. The additional metal layer 148 may not completely overlap the ELVDD distribution path. For example, a portion of the ELVDD distribution path closest to the edge of the active area may not be covered by layer 148.

[0093] The additional metal layer 148 may be an anode metal layer. Although the anode metal layer does not actually form an anode for the pixel, the anode metal layer may be formed from the same metal layer as the pixel anode (and therefore referred to herein as anode metal or anode metal layer). The metal layer 148 may be formed in the same deposition step as the pixel anode AN (and therefore formed from the same material as the pixel anode). For example, Fig.16 The metal layer 148 in Figure 6 , Figure 7 and Fig.10The anode metal 114 shown in FIG. Fig.16 The anode metal 148 in the display may cover the gate driver circuit 18 and the data line D. The anode metal 148 may contact the cathode layer and the ELVSS distribution path (such as the contact Figure 6 , Figure 7 and Fig.10 shown). Although Fig.16 , but the ELVDD distribution path 92 may be omitted in embodiments where the anode metal 148 is formed on the data line in the fillet region (eg, Fig.14 ).

[0094] Fig.17 yes Fig.16 A cross-sectional side view of a display. Fig.16 As shown, data line D may be formed on substrate 24. Additional layers may be formed on the data line. A metal layer for forming ELVDD distribution path 92 is formed on the data line. A gate line G is then formed on the ELVDD distribution path. Anode metal 148 is formed on gate line G. A dielectric layer 140 may be interposed between each metal layer. Fig.17 In the example of FIG. 1 , one dielectric layer is interposed between the data line D and the ELVDD distribution path 92, one dielectric layer is interposed between the ELVDD distribution path 92 and the gate line G, and one dielectric layer is interposed between the gate line G and the anode metal 148. This example is merely illustrative, and more than one dielectric layer may be interposed between the conductive layers if necessary. Fig.17 Forming anode metal 148 over ELVDD distribution path 92 as shown may prevent reflections from recess 146 from being visible to a viewer. One or more dielectric layers may also be formed over anode metal 148.

[0095] Fig.17 The dielectric layer 140 in the display may be formed of any desired material. In some embodiments, one or more of the dielectric layers may be formed of a material (e.g., an organic material) that is capable of trapping moisture (e.g., during manufacturing). If the anode metal 148 is formed continuously over the dielectric layer 140, the trapped moisture may leak into the active area AA and may damage the display pixels. To ensure that any moisture trapped within the dielectric layer 140 can evaporate, the anode metal 148 may be provided with holes 150, such as Fig.18 Any desired number of holes may be provided in the anode metal 148. Each hole may have any desired shape and size.

[0096] Figure 16-Figure 18The example of forming the additional metal layer 148 from an anode metal in FIG. 1 is merely illustrative. The metal layer 148 (sometimes referred to as the shielding layer 148 ) may be formed from any desired material (eg, an opaque dielectric material, a non-anode metal material, etc.).

[0097] Fig.19 Another arrangement for mitigating reflections caused by data line D is shown in FIG. Fig.13 ), the gate line G is formed above the ELVDD distribution path 92. Therefore, the gate line can be used to help mitigate reflections from the ELVDD distribution path. The width of the gate line can be increased to increase the amount of area shielded by the gate line. However, even with the increased gate line width, reflections may still be visible.

[0098] The shape of the gate line is changed from a straight line shape (e.g. Fig.12 ) is changed to Fig.19 The non-linear shape shown can mitigate periodic light reflections from the underlying ELVDD distribution path. Fig.12 The gate line 92 may be referred to as a straight gate line because a portion of the gate line overlapping the ELVDD distribution path 92 is straight. Fig.19 The gate line 92 may be referred to as a non-linear gate line because a portion of the gate line overlapping the ELVDD distribution path 92 is non-linear.

[0099] Fig.19 The gate lines in the embodiment may have any desired non-straight shape. For example, each gate line may have multiple curved portions. Each curved portion may have the same curvature radius as one or more other curved portions, or may have a unique curvature radius. Each curved portion may have any desired length. In another example, each gate line may have multiple straight segments arranged at an angle relative to each other. Each straight segment may have any desired length and any desired angle relative to adjacent straight segments. In another example, each gate line may have a combination of curved portions and straight portions. Fig.19 The non-straight shape of the gate lines in may be described as serpentine, non-straight, following a tortuous path, having a sine wave shape, wavy, having a sawtooth shape, etc.

[0100] Figure 20-Figure 25 Additional embodiments for mitigating reflections in rounded corner areas of a display are shown. Fig. 20 As shown, dielectric layer 202 may be formed on metal layers 204 and 206 (eg, on a substrate layer). Dielectric layer 202 may be formed by contacting a planarization layer (eg, Figure 4 The same material as the PLN2 and / or PLN1 in the pixel defining layer (such as Figure 4The metal layers 204 and 206 may be formed of the same material as the pixel defining layer 52 in FIG. 1 , or may be formed of any other desired material. The metal layers 204 and 206 may be gate lines, data lines, or any other desired type of signal lines.

[0101] Metal layer 208 may be formed on dielectric layer 202. Metal layer 208 may be an ELVDD distribution path (eg, Fig.13 The ELVDD distribution path 92 in the display) or any other desired metal layer in the display. Due to the presence of metal layers 204 and 206, metal layer 208 has a contact Fig.13 Similar depressions are shown. Fig. 20 In order to help reduce the reflection caused by the metal layer 208, an anti-reflection film 210 is formed on the metal layer 208. The anti-reflection film 210 can be deposited on the metal layer 208 or can be formed by surface treatment of the metal layer 208. The anti-reflection film may sometimes be referred to as an anti-reflection coating or an anti-reflection layer. The anti-reflection layer may be formed of one or more of niobium oxide, niobium nitride, titanium oxide, titanium nitride, silicon nitride, chromium oxide, etc. The anti-reflection layer may reflect less than 1% of the incident light, less than 5% of the incident light, less than 10% of the incident light, less than 20% of the incident light, less than 40% of the incident light, etc.

[0102] The dielectric layer 212 may be formed on the anti-reflection layer 210. The dielectric layer 212 may be formed by contacting a planarization layer such as Figure 4 The same material as the PLN2 and / or PLN1 in the pixel defining layer (such as Figure 4 The pixel defining layer 52 may be formed of the same material as that of the pixel defining layer 52 in the embodiment of the present invention, or may be formed of any other desired material.

[0103] Fig. 20 The example of a single dielectric layer 202 formed between metal layers 204 / 206 and metal layer 208 in FIG. 2 is merely illustrative. Fig.21 2 is a cross-sectional side view of an illustrative display having a first dielectric layer 202-1 formed above metal layer 204 but below metal layer 206. In other words, metal layer 204 is interposed between a first portion of dielectric layer 202-1 and a substrate. A second portion of dielectric layer 202-1 is interposed between metal layer 206 and the substrate. An additional dielectric layer 202-2 is formed above metal layer 206. A first portion of dielectric layer 202-1 is interposed between metal layer 204 and a first portion of dielectric layer 202-2. Metal layer 206 is interposed between a second portion of dielectric layer 202-1 and a second portion of dielectric layer 202-2. Both dielectric layer 202-1 and dielectric layer 202-2 may be formed by interfacing with a planarization layer such as Figure 4 The same material as the PLN2 and / or PLN1 in the pixel defining layer (such as Figure 4 The dielectric layer 202-1 and the dielectric layer 202-2 may be formed of different materials. The metal layer 208, the anti-reflection layer 210 and the dielectric layer 212 are formed on the dielectric layer 202-2, which is similar to the above-mentioned. Fig. 20 Similar to that shown and discussed in .

[0104] Fig. 20 and Fig.21 The examples of anti-reflective coatings shown in are illustrative only. In another possible arrangement, light absorbing organic materials may be incorporated into the display to mitigate reflections from the metal layer. Fig. 22 2 is a cross-sectional side view of an illustrative display including a light absorbing organic layer 214. Layer 214 may sometimes be referred to as light absorbing layer 214, black matrix layer 214, organic layer 214, etc. Layer 214 may be formed of any desired organic material. The light absorbing layer may absorb more than 95% of incident light, more than 90% of incident light, more than 80% of incident light, more than 70% of incident light, more than 60% of incident light, etc. The light absorbing layer may reflect less than 1% of incident light, less than 5% of incident light, less than 10% of incident light, less than 20% of incident light, less than 40% of incident light, etc.

[0105] like Fig. 22 As shown, a black matrix layer 214 may be interposed between the metal layer 208 and the dielectric layer 212 . Fig.23 is a cross-sectional side view of a display showing how an anti-reflective layer 210 may be formed over a dielectric layer 212. In this case, the dielectric layer 212 is interposed between the metal layer 208 and the anti-reflective layer 210. Similarly, Fig.24 2 is a cross-sectional side view of a display showing how a black matrix layer 214 may be formed over a dielectric layer 212. In this case, the dielectric layer 212 is interposed between the metal layer 208 and the black matrix layer 214.

[0106] In one possible embodiment, Fig.25 As shown in FIG. 2 , dielectric layer 212 may be replaced by black matrix layer 214. In other words, the black matrix layer is formed in direct contact with metal layer 208 without the presence of an additional dielectric layer.

[0107] It should be pointed out that in Figure 22-Figure 25 In any of the embodiments of the present invention, the dielectric layer 202 can be split into two dielectric layers, such as Fig.21 In addition, Figure 20-Figure 25 In any of the embodiments of the present invention, additional signal lines (metal lines) may be optionally formed onto the upper layer (e.g., Figure 20-22 On the dielectric layer 212 in, Fig.23 On the anti-reflection layer 210 or Fig.24 and Fig.25 on the black matrix layer 214 in the embodiment of the present invention).

[0108] The foregoing embodiments may be combined in any desired manner. Fig.14 or Fig.16 In the embodiment of Fig.19 In another example, the non-straight gate lines may be Fig.14 As shown in FIG. 1 , the ELVDD distribution path is removed in the area above the data line, and this area (not covered by the ELVDD distribution path) can be as shown in FIG. Fig.16 is shown covered by an additional metal shield. Fig. 9 Displays with extended ELVSS distribution paths Figure 14-Figure 19 Any combination of the embodiments shown in . Figure 20-Figure 25 Antireflection layers or light absorbing layers of the type shown may be used with Figure 14-Figure 19 Any of the embodiments shown can be combined.

[0109] According to one embodiment, an organic light emitting diode display is provided, which includes: a thin film transistor circuit; a substrate having an active area, the active area having a pixel array formed by the thin film transistor circuit; a first metal power path located on the substrate that carries a positive power supply voltage to the active area, the first metal power path having a first portion, a second portion, and a cutout between the first portion and the second portion; and a second metal power path located on the substrate that carries a second power supply voltage to the active area, the second metal power path having a first portion formed in the cutout of the first metal power path.

[0110] According to another embodiment, at least some of the first portions of the second metal power supply paths are directly adjacent to the active area.

[0111] According to another embodiment, the first portion of the second metal power path is a horizontal portion, and the second metal power path has a vertical portion and a rounded portion interposed between the vertical portion and the horizontal portion.

[0112] According to another embodiment, an organic light emitting diode display includes a gate driver circuit, the gate driver circuit is inserted between the active area and the vertical portion of the second metal power path, the second portion of the first metal power path and the gate driver circuit are inserted between the active area and the rounded portion of the second metal power path, and the first metal power path is not inserted between at least some of the horizontal portions of the active area and the second metal power path.

[0113] According to another embodiment, the first portion of the first metal power path is a horizontal portion and the second portion of the first metal power path is a rounded portion.

[0114] According to another embodiment, an organic light emitting diode display includes a plurality of conductive paths within an active area, the plurality of conductive paths electrically connecting a horizontal portion of a first metal power path to a rounded portion of the first metal power path.

[0115] According to another embodiment, an organic light emitting diode display includes a pixel defining layer located on a thin film transistor circuit, the pixel defining layer having openings, each of the openings containing an anode and an organic emission layer of an organic light emitting diode, and each of the openings is associated with a corresponding one of the pixels; a cathode layer covering the pixel array; and a metal layer having multiple portions forming an anode of the organic light emitting diode and an additional portion electrically connecting the cathode layer to a second metal power supply path.

[0116] According to another embodiment, the additional portion of the metal layer covers and is electrically connected to the vertical portion of the second metal power path, the fillet portion of the metal cathode power path, and the horizontal portion of the second metal power path.

[0117] According to another embodiment, an organic light emitting diode display includes a plurality of data lines covered by a rounded portion of a first metal power path; and a plurality of gate lines formed on the rounded portion of the first metal power path, at least one of the plurality of gate lines having a plurality of bent portions.

[0118] According to another embodiment, additional portions of the metal layer extend over the plurality of gate lines and the rounded portions of the first metal power trace.

[0119] According to another embodiment, an organic light emitting diode display includes a plurality of data lines covered by a rounded portion of a first metal power path; and an anti-reflection layer formed on the rounded portion of the first metal power path.

[0120] According to another embodiment, an organic light emitting diode display includes a plurality of data lines covered by a rounded corner portion of a first metal power path; and a light absorbing organic layer formed on the rounded corner portion of the first metal power path.

[0121] According to one embodiment, an organic light emitting diode display is provided, which includes: a thin film transistor circuit; a substrate having an active area, the active area having a pixel array formed by the thin film transistor circuit; a positive power supply voltage distribution path located on the substrate having a first portion and a second portion formed separately from the first portion; a plurality of conductive paths located in the active area electrically connecting the first portion to the second portion; and a second power supply voltage distribution path located on the substrate having a first portion interposed between the first portion and the second portion of the positive power supply voltage distribution path.

[0122] According to another embodiment, the plurality of conductive paths includes a plurality of horizontal conductive paths and a plurality of vertical conductive paths.

[0123] According to another embodiment, the plurality of conductive paths includes a plurality of L-shaped conductive paths.

[0124] According to one embodiment, an organic light emitting diode display having a pixel array is provided, the organic light emitting diode display comprising: a substrate; a thin film transistor circuit located on the substrate; a pixel defining layer located on the thin film transistor circuit, the pixel defining layer having openings, each of the openings containing an anode of an organic light emitting diode and an organic emission layer, and each of the openings being associated with a corresponding one of the pixels; a cathode layer covering the pixel array; a plurality of data lines; and a second metal power path located on the substrate, the anode of the organic light emitting diode being formed by a metal layer, an additional portion of the metal layer electrically connecting the cathode layer to the second metal power path, and the additional portion of the metal layer covering the plurality of data lines.

[0125] According to another embodiment, an organic light emitting diode display includes a first metal power path on a substrate, a portion of the first metal power path being interposed between an additional portion of a metal layer and a plurality of data lines.

[0126] According to another embodiment, an organic light emitting diode display includes a plurality of gate lines interposed between a first metal power supply path and an additional portion of the metal layer.

[0127] According to another embodiment, at least one gate line of the plurality of gate lines is non-linear beneath the additional portion of the metal layer.

[0128] According to another embodiment, at least one gate line of the plurality of gate lines has a plurality of bent portions under the additional portion of the metal layer.

[0129] According to another embodiment, the additional portion of the metal layer has a plurality of holes.

[0130] According to another embodiment, the substrate has an active area with an array of pixels, and the additional portion of the metal layer covers a portion of the first metal power trace extending adjacent to a rounded corner of the active area.

[0131] According to another embodiment, an organic light emitting diode display includes a first metal power path on a substrate, the first metal power path having a cutout region interposed between a plurality of data lines and an additional portion of a metal layer.

[0132] The foregoing is merely illustrative and various modifications may be made to the embodiments described. The foregoing embodiments may be implemented independently or in any combination.

Claims

1. A display comprising: a substrate having an active area with a pixel array, wherein the active area has rounded corners; A thin film transistor circuit, wherein the thin film transistor circuit is on the substrate; a pixel defining layer on the thin film transistor circuit, wherein the pixel defining layer has openings, each opening containing an anode and an organic emissive layer for an organic light emitting diode, and each opening being associated with a corresponding one of the pixels; a plurality of data lines coupled to the pixel columns in the rounded corner portion; as well as A metal layer has a portion covering the plurality of data lines, wherein the metal layer has a plurality of holes.

2. The display of claim 1, wherein the anode for the organic light emitting diode is formed by an additional portion of the metal layer.

3. The display according to claim 2, further comprising: A cathode layer covers the pixel array.

4. The display according to claim 3, further comprising: A metal negative power path on the substrate.

5. The display of claim 4 wherein the portion of the metal layer electrically connects the cathode layer to the metal negative power path.

6. The display according to claim 1, further comprising: A metal positive power path is on the substrate, wherein a portion of the metal positive power path is interposed between the portion of the metal layer and the plurality of data lines.

7. The display according to claim 6, further comprising: At least one gate line is interposed between the metal positive power path and the portion of the metal layer.

8. The display according to claim 1, further comprising: A metal positive power supply path is on the substrate, wherein the metal positive power supply path has a cutout region between the plurality of data lines and the portion of the metal layer.

9. The display of claim 1 , wherein the active area has a first edge and a second edge orthogonal to the first edge, wherein the rounded portion is between the first edge and the second edge, and wherein the portion of the metal layer covers the plurality of data lines in the inactive area of ​​the display adjacent to the rounded portion.

10. A display comprising: Thin film transistor circuits; A substrate having an active area, wherein the active area has a pixel array formed by the thin film transistor circuit; a data line coupled to the pixel array; a metal positive power path on the substrate, the metal positive power path transmitting a positive power voltage to the active area, wherein the metal positive power path has a rounded corner portion formed on at least some of the data lines; as well as An anti-reflective layer is formed over the rounded portion of the metal positive power path.

11. The display of claim 10 wherein the anti-reflective layer comprises an anti-reflective coating on the metal positive power path.

12. The display of claim 10, wherein the antireflective layer comprises a material selected from the group consisting of niobium oxide, niobium nitride, titanium oxide, silicon nitride, and chromium oxide.

13. The display of claim 10 wherein the antireflective layer reflects less than 20% of incident light.

14. The display of claim 10 wherein the antireflective layer is a light absorbing organic layer.

15. The display of claim 14 wherein the light absorbing organic layer absorbs greater than 90% of incident light.

16. The display of claim 10, wherein the anti-reflective layer is in direct contact with the rounded corner portion of the metal positive power path.

17. The display according to claim 10, further comprising: A dielectric layer is interposed between the anti-reflective layer and the rounded portion of the metal positive power path.

18. A display comprising: Thin film transistor circuits; A substrate having an active area, wherein the active area has a pixel array formed by the thin film transistor circuit; a metal positive power path on the substrate, the metal positive power path delivering a positive power voltage to the active area, wherein the metal positive power path has a first portion, a second portion, and a cutout between the first portion and the second portion; as well as a metal negative power path on the substrate, the metal negative power path transmitting a negative power voltage to the active area, wherein the metal negative power path has a vertical portion, a horizontal portion formed in the cutout of the metal positive power path, and a rounded portion between the vertical portion and the horizontal portion, wherein the second portion of the metal positive power path is between the active area and the rounded portion of the metal negative power path, and wherein the metal positive power path is not between the active area and at least some of the horizontal portions of the metal negative power path.

19. The display according to claim 18, further comprising: A gate driver circuit is provided, wherein the gate driver circuit is interposed between the active area and the vertical portion of the metal negative power path.

20. The display of claim 18, wherein the first portion of the metal positive power path is a horizontal portion, and wherein the second portion of the metal positive power path is a rounded portion.

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