Stretchable display device and method for manufacturing same

Abstract

A stretchable display device and a method for manufacturing the same are provided. The display device includes a substrate including a plurality of island patterns and a first bridge pattern connecting a first island pattern and a second island pattern adjacent to each other among the plurality of island patterns; and a plurality of pixel light-emitting chips, wherein one of the plurality of pixel light-emitting chips is located on a corresponding island pattern of the plurality of island patterns. Each of the plurality of pixel light emitting chips includes: a transistor layer including a plurality of transistors; and a light emitting element layer on the transistor layer and including a plurality of light emitting elements.

Description

Technical Field

[0001] One or more embodiments of the present disclosure relate to a stretchable display device and a method for manufacturing the stretchable display device. Background Art

[0002] As information-oriented society develops, more and more demands are placed on display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of the light-emitting display device include an organic light-emitting display device composed of an organic light-emitting element, an inorganic light-emitting display device composed of an inorganic light-emitting element (such as an inorganic semiconductor), and a micro-light-emitting display device composed of a micro-light-emitting element.

[0004] Recently, a light-emitting display device has been developed as a display device that can be stretched vertically and / or horizontally. The stretchable display device includes a non-stretch portion in which pixel circuits are respectively arranged and a stretch portion that connects adjacent non-stretch portions to each other. Because the stretch portion and the non-stretch portion are distinguished, it is difficult to expand the area of ​​the non-stretch portion, which makes it difficult to manufacture a stretchable display device with a high pixel integration. Summary of the invention

[0005] Aspects and features of embodiments of the present disclosure provide a stretchable display device with high pixel integration.

[0006] Aspects and features of embodiments of the present disclosure provide a method for manufacturing a stretchable display device with high pixel integration.

[0007] However, the embodiments of the present disclosure are not limited to the embodiments set forth herein. The above and other embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to one or more embodiments of the present disclosure, a display device is provided. The display device includes: a substrate including a plurality of island patterns and a first bridge pattern, wherein the first bridge pattern connects a first island pattern and a second island pattern adjacent to each other among the plurality of island patterns; and a plurality of pixel light-emitting chips, wherein each of the plurality of pixel light-emitting chips is located on a corresponding island pattern among the plurality of island patterns. Each of the plurality of pixel light-emitting chips includes: a transistor layer including a plurality of transistors; and a light-emitting element layer on the transistor layer and including a plurality of light-emitting elements.

[0009] The plurality of pixel light emitting chips may correspond one-to-one to the plurality of island patterns.

[0010] The plurality of light-emitting elements may include a light-emitting element of a first pixel, a light-emitting element of a second pixel, and a light-emitting element of a third pixel. Each of the plurality of pixel light-emitting chips may further include: a first light conversion layer on the light-emitting element of the first pixel and configured to convert light emitted from the light-emitting element of the first pixel into light of a first wavelength band; a second light conversion layer on the light-emitting element of the second pixel and configured to convert light emitted from the light-emitting element of the second pixel into light of a second wavelength band; and a light-transmitting layer on the light-emitting element of the third pixel and configured to transmit light emitted from the light-emitting element of the third pixel.

[0011] The display device may further include: a first scan line on the first island pattern, the second island pattern, and the first bridge pattern; and a first scan pad connected to the first scan line and on the first island pattern.

[0012] One of the plurality of pixel light emitting chips may further include a first chip pad electrically connected to the first scanning pad.

[0013] The first scanning pad and the first chip pad may overlap each other in a third direction, which is a thickness direction of the substrate.

[0014] The transistor layer may include: a first insulating layer on a first chip pad; a gate electrode of a first transistor among a plurality of transistors, on the first insulating layer and electrically connected to the first chip pad; a second insulating layer on the gate electrode of the first transistor; an active layer of the first transistor on the second insulating layer; and a third insulating layer on the active layer of the first transistor.

[0015] The plurality of light emitting elements of the light emitting element layer may be on the third insulating layer.

[0016] The display device may further include: a first data line on the first island pattern, the second island pattern, and the first bridge pattern; and a first data pad connected to the first data line and located on the first island pattern.

[0017] One of the plurality of pixel light emitting chips may further include a second chip pad electrically connected to the first data pad.

[0018] The first data pad and the second chip pad may overlap each other in a third direction, which is a thickness direction of the substrate.

[0019] The transistor layer may include: a first insulating layer, on the second chip pad; a first connecting electrode and a gate electrode of a second transistor among a plurality of transistors, on the first insulating layer; a second insulating layer, on the first connecting electrode and the gate electrode of the second transistor; an active layer of the second transistor, on the second insulating layer, and connected to the first connecting electrode through a contact hole penetrating the second insulating layer; and a third insulating layer, on the active layer of the second transistor.

[0020] The plurality of light emitting elements of the light emitting element layer may be located on the third insulating layer.

[0021] The display device may further include: a first power line on the first island pattern, the second island pattern, and the first bridge pattern; and a first power pad connected to the first power line and located on the first island pattern.

[0022] One of the plurality of pixel light emitting chips may further include a third chip pad electrically connected to the first power pad.

[0023] The transistor layer may include: a first insulating layer on the third chip pad; a second connecting electrode on the first insulating layer and connected to the third chip pad through a contact hole penetrating the first insulating layer; a second insulating layer on the second connecting electrode; and a third connecting electrode on the second insulating layer and connected to the second connecting electrode through a contact hole penetrating the second insulating layer.

[0024] Each of the plurality of light emitting elements of the light emitting element layer may include a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence. The third connection electrode may be electrically connected to the second semiconductor layer.

[0025] According to one or more embodiments of the present disclosure, a display device is provided, the display device comprising: a substrate, comprising a first island pattern and a second island pattern adjacent to each other in a first direction, a third island pattern adjacent to the first island pattern in a second direction intersecting the first direction, a first bridge pattern connecting the first island pattern and the second island pattern, and a second bridge pattern connecting the first island pattern and the third island pattern in the second direction; a first scan line, located on the first island pattern and the first bridge pattern, and configured to receive a first scan signal; a first data line, located on the first island pattern and the second bridge pattern, and configured to receive a first data voltage; a first scan pad, located on the first island pattern and connected to the first scan line; a first data pad, located on the first island pattern and connected to the first data line; and a pixel light-emitting chip, comprising a pad layer, a transistor layer, and a light-emitting element layer, the pad layer comprising a first chip pad electrically connected to the first scan pad and a second chip pad electrically connected to the first data pad, the transistor layer comprising a plurality of transistors located on the pad layer, and the light-emitting element layer being located on the transistor layer and comprising a plurality of light-emitting elements.

[0026] According to one or more embodiments of the present disclosure, a method for manufacturing a display device is provided, the method comprising the following steps: forming a plurality of pixel light-emitting chips, each of the plurality of pixel light-emitting chips comprising a chip pad layer, a transistor layer and a light-emitting element layer, the chip pad layer comprising a plurality of chip pads, the transistor layer being located on the chip pad layer, and the light-emitting element layer being located on the transistor layer; forming a substrate comprising a plurality of island patterns and bridge patterns, each of the bridge patterns connecting mutually adjacent island patterns among the plurality of island patterns; and attaching the plurality of pixel light-emitting chips to the plurality of island patterns, respectively.

[0027] The steps of forming a plurality of pixel light-emitting chips include: sequentially forming a second semiconductor material layer, an active material layer and a first semiconductor material layer on a semiconductor substrate; forming a first insulating layer on the first semiconductor material layer, and forming an active pattern of a transistor on the first insulating layer; forming a second insulating layer on the active pattern, and forming a gate electrode of the transistor on the second insulating layer; forming a third insulating layer on the gate electrode, and forming a plurality of chip pads on the third insulating layer; removing the semiconductor substrate; and patterning the second semiconductor material layer, the active material layer and the first semiconductor material layer to form a light-emitting element layer including a plurality of light-emitting elements.

[0028] According to the aforementioned and other embodiments of the present disclosure, the pixel light-emitting chip may be a chip in which a pixel layer including a plurality of transistors, a light-emitting element layer including a plurality of light-emitting elements, and an optical layer including a plurality of light-conversion layers are integrated. Therefore, even if the area of ​​the island pattern corresponding to the non-stretched portion is reduced to realize a high-resolution display device, it is only necessary to attach a plurality of pixel light-emitting chips to the plurality of island patterns, respectively. Therefore, a stretchable display device with high pixel integration can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other embodiments and features of the present disclosure will become more apparent by describing embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 and Figure 2 is a perspective view showing a stretchable display device according to one or more embodiments; Figure 3 is a block diagram illustrating a stretchable display device according to one or more embodiments; Figure 4 is an equivalent circuit diagram showing a first pixel according to one or more embodiments; Figure 5 is a layout diagram showing a display panel, a display circuit board, and a display driving circuit according to one or more embodiments; Figure 6 It is shown Figure 5 A layout diagram of a display area of ​​a display panel; Figure 7 It is shown Figure 6 A perspective view of a first island pattern and a pixel light emitting chip in region A; Figure 8 It is shown Figure 6 An exploded perspective view of a first island pattern and a pixel light emitting chip in region A; Fig. 9 It is shown Figure 6 A layout diagram of an example of a plurality of scan lines, a plurality of data lines, a plurality of power lines, a plurality of bridges and a plurality of pixel pads in an area A; Fig.10 It is shown Figure 6 A layout diagram of a first island pattern in region A and first to third light emitting regions of a pixel light emitting chip; Fig.11 It is shown along Fig. 9 and Fig.10 A cross-sectional view of an example of a first island pattern and a pixel light-emitting chip taken along line ZZ'; Fig.12 It is shown along Fig. 9 and Fig.10 A cross-sectional view of an example of a first island pattern and a pixel light-emitting chip taken along line YY'; Fig.13 It is shown along Fig. 9 and Fig.10 A cross-sectional view of an example of a first island pattern and a pixel light-emitting chip taken along line XX'; Fig.14 is a flow chart illustrating a method for manufacturing a stretchable display device according to one or more embodiments; Fig.15 and Fig.16 are an exploded perspective view and a perspective view respectively illustrating a method for manufacturing a stretchable display device according to one or more embodiments; Fig.17 It is shown in detail Fig.14 A flowchart of an example of step S100; and Figures 18 to 26 Is used to describe Fig.14 FIG. 5 is a cross-sectional view of an example of step S100 . DETAILED DESCRIPTION

[0030] By referring to the detailed description and the accompanying drawings of the embodiments, the aspects and features of the embodiments of the present disclosure and their implementation methods can be more easily understood. Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments can be implemented in various different forms and should not be construed as being limited to the embodiments shown here. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects and features of the present disclosure will be fully conveyed to those skilled in the art. Therefore, the processes, elements and techniques that are not required for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described.

[0031] Unless otherwise specified, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written descriptions, and therefore, descriptions thereof will not be repeated. In addition, parts not related to the description of one or more embodiments may not be shown to make the description clear.

[0032] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. In addition, the use of cross-hatching and / or shading is often provided in the drawings to clarify the boundaries between adjacent elements. As such, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the illustrated elements, and / or any other characteristics, attributes, properties, etc. of the elements.

[0033] Various embodiments are described herein with reference to schematically illustrated cross-sectional views of embodiments and / or intermediate structures. As such, variations in the shapes of the drawings caused by, for example, manufacturing techniques and / or tolerances are contemplated. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the specific illustrated shapes of the regions, but will include deviations in shapes caused by, for example, manufacturing.

[0034] For example, an implanted region illustrated as a rectangle may have rounded or curved features and / or a gradient of implant concentration at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions illustrated in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to be limiting. In addition, as will be appreciated by those skilled in the art, the described embodiments may be modified in a variety of different ways, all without departing from the spirit or scope of the present disclosure.

[0035] In the detailed description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various embodiments. However, it is apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid making the various embodiments unnecessarily obscure.

[0036] For ease of explanation, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used here to describe the relationship of one element or feature to other elements or features as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element described as "below" or "below" or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the example terms "below" and "below" can cover both the above and below orientations. The device can be oriented otherwise (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used here should be interpreted accordingly. Similarly, when a first part is described as being arranged "on" a second part, this means that the first part is arranged on the upper or lower side of the second part, without being limited to its upper side based on the direction of gravity.

[0037] Furthermore, in this specification, the phrase "on a plane" or "in a plan view" means viewing a target portion from the top, and the phrase "in section" means viewing a section formed by vertically cutting the target portion from the side.

[0038] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "bonded to" another element, layer, region, or component, the element, layer, region, or component may be directly formed on, directly on, directly connected to, or directly bonded to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly bonded to the other element, layer, region, or component such that one or more intervening elements, layers, regions, or components may be present. For example, when a layer, region, or component is referred to as being "electrically connected to" or "electrically bonded to" another layer, region, or component, the layer, region, or component may be directly electrically connected to or directly electrically bonded to the other layer, region, and / or component, or there may be intervening layers, regions, or components. However, "directly connected / directly coupled" means that one component is directly connected or directly coupled to another component without intervening components. At the same time, other expressions describing the relationship between components, such as "between", "directly between" or "adjacent to" and "directly adjacent to", can be similarly interpreted. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0039] For the purpose of the present disclosure, when expressions such as "at least one of ...," "one of ...," and "selected from ...," are before (or after) a list of elements, the entire list of elements is modified without modifying the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one of the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XYY, XZ, YZ, and ZZ) or any variation thereof. Similarly, expressions such as "at least one of A and B" may include A, B, or A and B. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, expressions such as "A and / or B" may include A, B, or A and B. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0040] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part.

[0041] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0042] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "a (kind / person)" are also intended to include plural forms. It will also be understood that when the terms "include", "comprise", "have", "have" and variations thereof are used in this specification, the stated features, wholes, steps, operations, elements and / or components are indicated, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups are not excluded.

[0043] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms rather than terms of degree, and are intended to account for the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. As used herein, "about" or "approximately" includes the value and means: within the acceptable deviation range of the specific value determined by those of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0044] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described order.

[0045] In addition, any numerical range disclosed and / or described herein is intended to include all sub-ranges of the same numerical precision contained in the range. For example, the range of "1.0 to 10.0" is intended to include all sub-ranges between the minimum value 1.0 and the maximum value 10.0 (and including the minimum value 1.0 and the maximum value 10.0), for example, with a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described here is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to modify this specification (including claims) to explicitly describe any sub-range contained in the range explicitly described here. All such ranges are intended to be inherently described in this specification so that the modification of any such sub-range explicitly described will meet the requirements.

[0046] Any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware may be used to implement the electronic or electrical devices and / or any other related devices or components according to one or more embodiments of the present disclosure described herein. For example, the various components of these devices may be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0047] In addition, the various components of these devices can be processes or threads that run on one or more processors, execute computer program instructions in one or more computing devices, and interact with other system components to perform the various functions described herein. Computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device (such as, for example, a random access memory (RAM)). Computer program instructions can also be stored in other non-temporary computer-readable media, such as, for example, a CD-ROM, a flash drive, etc. In addition, it should be recognized by those skilled in the art that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed throughout one or more other computing devices without departing from the spirit and scope of the present disclosure.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having, for example, a meaning consistent with their meaning in the context (background) of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0049] Figure 1 and Figure 2 is a perspective view illustrating a stretchable display device according to one or more embodiments.

[0050] Reference Figure 1 and Figure 2 The display device 10 is a device for displaying moving images or still images. The display device 10 can be used as a display screen of various devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs).

[0051] The display device 10 may have a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have a certain curvature, but the present disclosure is not limited thereto. The corner of the display device 10 may be a right angle. The planar shape of the display panel 100 may be similar to a quadrilateral. However, the present disclosure is not limited thereto, and the display device 10 may be formed in a shape similar to another polygonal shape, a circular shape, or an elliptical shape in a plan view. The display panel 100 may be formed to be flat, but is not limited thereto.

[0052] The display device (or referred to as “stretchable display device”) 10 includes a display panel 100 and a lower cover 900 .

[0053] The display panel 100 may be a light-emitting display panel including a light-emitting element. For example, the display panel 100 may be an organic light-emitting display panel including an organic light-emitting diode (OLED) having an organic light-emitting layer, a micro light-emitting diode (microLED) display panel including microLEDs made of inorganic materials, or a quantum dot light-emitting display panel using a quantum dot light-emitting diode including a quantum dot light-emitting layer. Hereinafter, the display panel 100 will be mainly described as a microLED display panel including microLEDs.

[0054] The lower cover 900 may form an appearance of a bottom surface of the display device 10. The lower cover 900 may cover side surfaces and a bottom surface of the display panel 100. The lower cover 900 may include plastic, metal, or both plastic and metal.

[0055] Figure 1 The stretchable display device 10 is shown stretched in the first direction DR1. When the left side of the stretchable display device 10 is held with one hand and stretched to the left, while the right side of the stretchable display device 10 is held with another hand and stretched to the right, the stretchable display device 10 can be stretched in the first direction DR1. When the display device 10 is stretched in the first direction DR1, the display area DAA (e.g., Figure 3 ) The maximum length of the display area DAA in the first direction DR1 may increase. That is, when the display device 10 is stretched in the first direction DR1, the area of ​​the display area DAA may increase.

[0056] Figure 2 The stretchable display device 10 stretched in the second direction DR2 is shown. When the upper side of the stretchable display device 10 is held with one hand and stretched upward, while the lower side of the stretchable display device 10 is held with another hand and stretched downward, the stretchable display device 10 can be stretched in the second direction DR2. When the stretchable display device 10 is stretched in the second direction DR2, the maximum length of the display area DAA in the second direction DR2 can be increased. That is, when the stretchable display device 10 is stretched in the second direction DR2, the area of ​​the display area DAA can be increased.

[0057] In summary, the stretching of the display device 10 is performed by an external force, and when the external force is removed, the display device 10 may shrink and return to its original state. Figure 1 and Figure 2 The stretchable display device 10 is shown to be stretched in the first direction DR1 and the second direction DR2, but the present disclosure is not limited thereto. The stretchable display device 10 may also be stretched in an oblique direction between the first direction DR1 and the second direction DR2.

[0058] Figure 3 is a block diagram illustrating a stretchable display device according to one or more embodiments.

[0059] Reference Figure 3 The display device 10 according to one or more embodiments includes a display panel 100, a display driving circuit 200, and a display circuit board 300 (see, for example, Figure 5 ).

[0060] The display panel 100 includes a display area DAA configured to display an image and a non-display area NDA not configured to display an image.

[0061] The display area DAA includes a plurality of unit pixels PXG, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0062] Each of the plurality of unit pixels PXG includes a plurality of pixels PX1, PX2, and PX3. The unit pixel PXG refers to a minimum pixel group that can represent a color.

[0063] Each of the plurality of pixels PX1, PX2, and PX3 includes a light emitting element that emits light. A plurality of scan lines SL and a plurality of emission control lines EL may extend in a first direction DR1 while being arranged along a second direction DR2. A plurality of data lines DL may extend in a second direction DR2 and may be arranged along the first direction DR1. The plurality of scan lines SL include a plurality of write scan lines GWL and a plurality of control scan lines GCL.

[0064] Each of the plurality of pixels PX1, PX2, and PX3 may be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of emission control lines EL, and at least any one of the plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 may receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL, and emit light from the light emitting element according to the data voltage.

[0065] The non-display area NDA includes a scan driver 110 and an emission driver 120. Figure 3 , the scan driver 110 is disposed on the left side of the display area DAA and the emission driver 120 is disposed on the right side of the display area DAA, but the present disclosure is not limited thereto. For example, the scan driver 110 and the emission driver 120 may be disposed on both the left and right sides of the display area DAA.

[0066] The scan driver 110 includes a write scan signal output unit 111 and a control scan signal output unit 112. Each of the write scan signal output unit 111 and the control scan signal output unit 112 may receive a scan timing control signal SCS from the timing controller 210. The write scan signal output unit 111 may generate write scan signals in response to the scan timing control signal SCS of the timing controller 210, and sequentially output them to the write scan lines GWL. The control scan signal output unit 112 may generate control scan signals in response to the scan timing control signal SCS, and sequentially output them to the control scan lines GCL.

[0067] The emission driver 120 may receive an emission timing control signal ECS from the timing controller 210. The emission driver 120 may generate emission control signals in response to the emission timing control signal ECS and sequentially output them to the emission control lines EL.

[0068] The display driving circuit 200 includes a timing controller 210 and a data driver 220 .

[0069] The timing controller 210 may receive digital video data DATA and a timing signal from the outside. The timing controller 210 may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signal. The timing controller 210 may output the scan timing control signal SCS to the scan driver 110, and output the emission timing control signal ECS to the emission driver 120. The timing controller 210 may output the digital video data DATA and the data timing control signal DCS to the data driver 220.

[0070] The data driver 220 may receive the digital video data DATA and the data timing control signal DCS from the timing controller 210. The data driver 220 converts the digital video data DATA into analog data voltages in response to the data timing control signal DCS and outputs them to the data lines DL. Thus, the pixels PX1, PX2, and PX3 are selected by the write scan signal of the scan driver 110, and the data voltages may be supplied to the selected pixels PX1, PX2, and PX3.

[0071] The power supply unit 310 in the display circuit board 300 can generate a plurality of panel power voltages by an external power voltage. For example, the power supply unit 310 can generate a first power voltage VSS, a second power voltage VDD, and a third power voltage VINT, and supply them to the display panel 100. Figure 4 Descriptions of the first power voltage VSS, the second power voltage VDD, and the third power voltage VINT are provided. The power supply unit 310 may be formed as an integrated circuit (IC).

[0072] Figure 4 is an equivalent circuit diagram illustrating a first pixel according to one or more embodiments.

[0073] Reference Figure 4 , the first pixel PX1 according to one or more embodiments may be connected to the kth (k is a positive integer) initialization scan line GILk, the kth write scan line GWLk, and the kth emission line ELk. In addition, the first pixel PX1 may be connected to the first power line VSL supplied with the first power voltage VSS, the second power line VDL applied with the second power voltage VDD, and the third power line VIL applied with the third power voltage VINT.

[0074] The first pixel PX1 includes at least one light emitting element LEL and a pixel circuit unit PDU. The pixel circuit unit PDU includes a driving transistor DT, at least one switching element and a capacitor C1. The at least one switching element may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5 and a sixth transistor ST6, but the present disclosure is not limited thereto.

[0075] The driving transistor DT may include a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current Ids (hereinafter, referred to as “driving current”) flowing between the first electrode and the second electrode of the driving transistor DT according to a data voltage applied to the gate electrode of the driving transistor DT.

[0076] The light emitting element LEL emits light in response to the driving current Ids. As the driving current Ids increases, the amount of light emitted from the light emitting element LEL may increase.

[0077] The light emitting element LEL may be an organic light emitting diode (OLED) including an organic light emitting layer disposed between the anode electrode AND and the cathode electrode CAT. Alternatively, the light emitting element LEL may be a micro light emitting diode including a semiconductor made of an inorganic material disposed between the anode electrode AND and the cathode electrode CAT. Alternatively, the light emitting element LEL may be a quantum dot light emitting element including a quantum dot light emitting layer disposed between the anode electrode AND and the cathode electrode CAT.

[0078] The anode electrode AND of the light emitting element LEL may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6 , and the cathode electrode CAT thereof may be connected to the first power line VSL.

[0079] The first transistor ST1 is turned on by the initialization scan signal of the kth initialization scan line GILk to connect the gate electrode of the driving transistor DT to the third power line VIL. Therefore, the third power voltage VINT of the third power line VIL can be applied to the gate electrode of the driving transistor DT. The first transistor ST1 may include a plurality of sub-transistors ST1-1 and ST1-2 to prevent current leakage of the gate electrode of the driving transistor DT.

[0080] The second transistor ST2 is turned on by the write scan signal of the kth write scan line GWLk to connect the first electrode of the driving transistor DT to the jth (j is a positive integer) data line DLj. Therefore, the data voltage of the jth data line DLj may be applied to the first electrode of the driving transistor DT.

[0081] The third transistor ST3 is turned on by the write scan signal of the kth write scan line GWLk to connect the gate electrode of the driving transistor DT to its second electrode. When the gate electrode of the driving transistor DT is connected to its second electrode, the driving transistor DT is driven as a diode (e.g., the driving transistor DT is diode-connected). The third transistor ST3 may include a plurality of sub-transistors ST3-1 and ST3-2 to prevent current leakage of the gate electrode of the driving transistor DT.

[0082] The fourth transistor ST4 is turned on by the write scan signal of the kth write scan line GWLk to connect the anode electrode AND of the light emitting element LEL to the third power line VIL. The third power voltage VINT of the third power line VIL may be applied to the anode electrode AND of the light emitting element LEL.

[0083] The fifth transistor ST5 is turned on by the emission control signal of the k-th emission line ELk to connect the first electrode of the driving transistor DT to the second power line VDL. The sixth transistor ST6 is disposed between the second electrode of the driving transistor DT and the anode electrode AND of the light emitting element LEL. The sixth transistor ST6 is turned on by the emission control signal of the k-th emission line ELk to connect the second electrode of the driving transistor DT to the anode electrode AND of the light emitting element LEL. When both the fifth transistor ST5 and the sixth transistor ST6 are turned on, the driving current Ids of the driving transistor DT according to the data voltage applied to the gate electrode of the driving transistor DT may flow to the light emitting element LEL.

[0084] The capacitor C1 is formed between the gate electrode of the driving transistor DT and the second power line VDL. A first capacitor electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and a second capacitor electrode thereof may be connected to the second power line VDL.

[0085] When the first electrode of the driving transistor DT and each of the first to sixth transistors ST1 to ST6 is a source electrode, the second electrode thereof may be a drain electrode. Alternatively, when the first electrode of the driving transistor DT and each of the first to sixth transistors ST1 to ST6 is a drain electrode, the second electrode thereof may be a source electrode.

[0086] The active layer of each of the driving transistor DT and the first to sixth transistors ST1 to ST6 may be formed of at least one of polysilicon, amorphous silicon, and an oxide semiconductor. Figure 4, the first transistor ST1 to the sixth transistor ST6 and the driving transistor DT have been mainly described as being formed of a P-type MOSFET, but the present disclosure is not limited thereto. For example, the first transistor ST1 to the sixth transistor ST6 and the driving transistor DT may be formed as an N-type MOSFET. Alternatively, some of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may be formed as a P-type MOSFET, and the remaining transistors may be formed as an N-type MOSFET.

[0087] Because the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 can be combined with Figure 4 The described equivalent circuit diagram of the first pixel PX1 is substantially the same, so descriptions of equivalent circuit diagrams of the second pixel PX2 and the third pixel PX3 will be omitted.

[0088] Figure 5 is a layout diagram illustrating a display panel, a display circuit board, and a display driving circuit according to one or more embodiments.

[0089] Reference Figure 5 , the display panel 100 according to one or more embodiments includes a main area MA and a sub area SBA protruding from one side of the main area MA.

[0090] The main area MA may include a display area DAA that displays an image and a non-display area NDA that is a peripheral area of ​​the display area DAA. The display area DAA may occupy most of the main area MA. The display area DAA may be set at the center of the main area MA. The non-display area NDA may be an area outside the display area DAA and around the display area DAA along the edge or periphery of the display area DAA. In other words, the non-display area NDA may be defined as an edge area of ​​the display panel 100.

[0091] The sub-region SBA may protrude from one side of the main region MA in the opposite direction of the second direction DR2. For example, one side of the main region MA may be the lower side of the main region MA. Figure 5 As shown in , the length of the sub-region SBA in the first direction DR1 may be smaller than the length of the main region MA in the first direction DR1, and the length of the sub-region SBA in the second direction DR2 may be smaller than the length of the main region MA in the second direction DR2, but the present disclosure is not limited thereto.

[0092] The sub-region SBA may be bent, and may be disposed under the display panel 100. In this case, the sub-region SBA may overlap the main region MA of the display panel 100 in the third direction DR3.

[0093] A display pad (also called a “solder pad” or a “solder pad”) DPD may be disposed at one side edge of the sub-region SBA. The one side edge of the sub-region SBA may be a lower side edge of the sub-region SBA.

[0094] The display circuit board 300 may be attached to the display pad DPD of the sub-area SBA. The display circuit board 300 may be attached to the display pad DPD of the sub-area SBA by using a conductive adhesive member such as an anisotropic conductive film or anisotropic conductive paste. The display circuit board 300 may be a flexible printed circuit board (FPCB) that is bendable, a rigid printed circuit board (PCB) that is strong and hardly bends, or a composite printed circuit board having both a rigid printed circuit board and a flexible printed circuit board. The power supply unit 310 may be provided on the display circuit board 300.

[0095] The display driving circuit 200 may be disposed in the sub-area SBA of the display panel 100. The display driving circuit 200 may receive the digital video data DATA and a timing signal, and may generate and output a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for driving the display panel 100. The display driving circuit 200 may be formed as an integrated circuit (IC).

[0096] Figure 6 It is shown Figure 5 Layout diagram of the display area of ​​the display panel.

[0097] Reference Figure 6 , the substrate SUB of the display panel 100 (eg, see Fig.11 ) may include a plurality of island patterns IP and a plurality of bridge patterns BP to reduce tensile stress applied to the substrate SUB in a stretching direction when the display device 10 is stretched.

[0098] Each of the plurality of island patterns IP may have a rectangular shape, a diamond shape, and / or a square shape in a plan view. Each of the plurality of island patterns IP may have a first side and a second side extending in a first oblique direction DD1 and a third side and a fourth side extending in a second oblique direction DD2, the first oblique direction DD1 being a direction between the first direction DR1 and the second direction DR2, and the second oblique direction DD2 being orthogonal to the first oblique direction DD1. Each of the plurality of island patterns IP may be connected to four bridge patterns BP. For example, each of the plurality of island patterns IP may be connected to the bridge pattern BP at a corresponding vertex of the island pattern IP.

[0099] The plurality of island patterns IP may include first, second, third, and fourth island patterns IP1, IP2, IP3, and IP4. The first, second, third, and fourth island patterns IP1, IP2, IP3, and IP4 may be defined as one island pattern group IPG.

[0100] The first and second island patterns IP1 and IP2 may be disposed adjacent to each other in the first direction DR1, and the third and fourth island patterns IP3 and IP4 may be disposed adjacent to each other in the first direction DR1. The first and third island patterns IP1 and IP3 may be disposed adjacent to each other in the second direction DR2, and the second and fourth island patterns IP2 and IP4 may be disposed adjacent to each other in the second direction DR2.

[0101] The plurality of bridge patterns BP may include first to twelfth bridge patterns BP1 to BP12. The plurality of bridge patterns BP may extend in the first direction DR1 or the second direction DR2.

[0102] Each of the first bridge pattern BP1, the second bridge pattern BP2, the third bridge pattern BP3, and the fourth bridge pattern BP4 refers to a pattern that connects the island patterns adjacent in the first direction DR1 or the second direction DR2 in the same island pattern group IPG. The first bridge pattern BP1 may connect the first island pattern IP1 and the second island pattern IP2 of the island pattern group IPG. The second bridge pattern BP2 may connect the first island pattern IP1 and the third island pattern IP3 of the island pattern group IPG. The third bridge pattern BP3 may connect the second island pattern IP2 and the fourth island pattern IP4 of the island pattern group IPG. The fourth bridge pattern BP4 may connect the third island pattern IP3 and the fourth island pattern IP4 of the island pattern group IPG.

[0103] Each of the fifth bridge pattern BP5, the sixth bridge pattern BP6, the seventh bridge pattern BP7, and the eighth bridge pattern BP8 refers to a pattern that connects island patterns that are adjacent to each other in the first direction DR1 and belong to different island pattern groups IPG. The fifth bridge pattern BP5 may connect the first island pattern IP1 of the island pattern group IPG to the second island pattern IP2 of another island pattern group IPG adjacent thereto in the first direction DR1 (e.g., on the left side). The sixth bridge pattern BP6 may connect the third island pattern IP3 of the island pattern group IPG to the fourth island pattern IP4 of another island pattern group IPG adjacent thereto in the first direction DR1 (e.g., on the left side). The seventh bridge pattern BP7 may connect the second island pattern IP2 of the island pattern group IPG to the first island pattern IP1 of another island pattern group IPG adjacent thereto in the first direction DR1 (e.g., on the right side). The eighth bridge pattern BP8 may connect the fourth island pattern IP4 of the island pattern group IPG to the third island pattern IP3 of another island pattern group IPG adjacent thereto in the first direction DR1 (e.g., on the right side).

[0104] Each of the ninth bridge pattern BP9, the tenth bridge pattern BP10, the eleventh bridge pattern BP11, and the twelfth bridge pattern BP12 refers to a pattern connecting island patterns that are adjacent to each other in the second direction DR2 and belong to different island pattern groups IPG. The ninth bridge pattern BP9 may connect the first island pattern IP1 of the island pattern group IPG to the third island pattern IP3 of another island pattern group IPG adjacent thereto in the second direction DR2 (e.g., on the upper side). The tenth bridge pattern BP10 may connect the second island pattern IP2 of the island pattern group IPG to the fourth island pattern IP4 of another island pattern group IPG adjacent thereto in the second direction DR2 (e.g., on the upper side). The eleventh bridge pattern BP11 may connect the third island pattern IP3 of the island pattern group IPG to the first island pattern IP1 of another island pattern group IPG adjacent thereto in the second direction DR2 (e.g., on the lower side). The twelfth bridge pattern BP12 may connect the fourth island pattern IP4 of the island pattern group IPG to the second island pattern IP2 of another island pattern group IPG adjacent thereto in the second direction DR2 (e.g., on the lower side).

[0105] The first to fifth gaps G1 to G5 may exist in the island pattern group IPG.

[0106] The first gap G1 may be defined by the first island pattern IP1 , the first bridge pattern BP1 , the second island pattern IP2 , the third bridge pattern BP3 , the fourth island pattern IP4 , the fourth bridge pattern BP4 , the third island pattern IP3 , and the second bridge pattern BP2 .

[0107] The second gap G2 may be defined by the fifth bridge pattern BP5, the first island pattern IP1, the second bridge pattern BP2, the third island pattern IP3, and the sixth bridge pattern BP6. The third gap G3 may be defined by the seventh bridge pattern BP7, the second island pattern IP2, the third bridge pattern BP3, the fourth island pattern IP4, and the eighth bridge pattern BP8. The second gap G2 of the island pattern group IPG may be connected to the third gap G3 of another island pattern group IPG adjacent thereto in the first direction DR1 (e.g., on the left). The third gap G3 of the island pattern group IPG may be connected to the second gap G2 of another island pattern group IPG adjacent thereto in the first direction DR1 (e.g., on the right).

[0108] The fourth gap G4 may be defined by the ninth bridge pattern BP9, the first island pattern IP1, the first bridge pattern BP1, the second island pattern IP2, and the tenth bridge pattern BP10. The fifth gap G5 may be defined by the eleventh bridge pattern BP11, the third island pattern IP3, the fourth bridge pattern BP4, the fourth island pattern IP4, and the twelfth bridge pattern BP12. The fourth gap G4 of the island pattern group IPG may be connected to the fifth gap G5 of another island pattern group IPG adjacent thereto in the second direction DR2 (e.g., on the upper side). The fifth gap G5 of the island pattern group IPG may be connected to the fourth gap G4 of another island pattern group IPG adjacent thereto in the second direction DR2 (e.g., on the lower side).

[0109] like Figure 6 As shown in , the display area DAA can be easily stretched in the first direction DR1 and the second direction DR2 due to the gaps G1 to G5 defined by the plurality of island patterns IP and the plurality of bridge patterns BP. Although the display area DAA includes the plurality of island patterns IP, the plurality of bridge patterns BP, and the plurality of gaps G1 to G5, the non-display area NDA does not include any of the plurality of island patterns IP, the plurality of bridge patterns BP, and the plurality of gaps G1 to G5. Therefore, when the display device 10 is stretched, the elongation of the display area DAA can be higher than the elongation of the non-display area NDA.

[0110] Multiple pixel light emitting chips LEC (or multiple pixel light emitting modules, see e.g. Figure 7 ) can be respectively arranged on a plurality of island patterns IP. A plurality of pixel light emitting chips LEC can be arranged on a plurality of island patterns IP in a one-to-one correspondence. Because a plurality of pixel light emitting chips LEC are arranged on a plurality of island patterns IP that are not stretched and not on a plurality of bridge patterns BP that are stretched, even when the display device 10 is stretched, a plurality of pixel light emitting chips LEC can be stably positioned on a plurality of island patterns IP.

[0111] Figure 7 It is shown Figure 6 A perspective view of a first island pattern and a pixel light-emitting chip in area A. Figure 8 It is shown Figure 6 An exploded perspective view of a first island pattern and a pixel light emitting chip in area A.

[0112] Reference Figure 7 and Figure 8 , a plurality of pixel pads PPD and pixel light emitting chips LEC are disposed on the first island pattern IP1.

[0113] The plurality of pixel pads PPD include a plurality of scan pads SP1, SP2, and EP, a plurality of data pads DP1, DP2, and DP3, and a plurality of power pads VP1, VP2, and VP3. The plurality of scan pads SP1, SP2, and EP, the plurality of data pads DP1, DP2, and DP3, and the plurality of power pads VP1, VP2, and VP3 may be referred to as first to ninth pixel pads, respectively.

[0114] Each of the plurality of pixel light-emitting chips LEC includes a pad layer (or referred to as a chip pad layer) PDL including a plurality of chip pads CP1 to CP9, a pixel circuit layer (or referred to as a transistor layer) CIL in which a plurality of transistors are arranged, a light-emitting element layer EML in which a plurality of light-emitting elements are arranged, and an optical layer OPL including a plurality of light-emitting areas OL1, OL2, and OL3.

[0115] The plurality of chip pads CP1 to CP9 may be electrically connected to the plurality of pixel pads PPD by using a conductive adhesive member such as an anisotropic conductive film. Alternatively, the plurality of chip pads CP1 to CP9 may be electrically connected to the plurality of pixel pads PPD by solder bonding or melt bonding.

[0116] Each of the plurality of pixel light emitting chips LEC may include a unit pixel PXG. The unit pixel PXG may include a first pixel PX1 that emits a first light through a first light exit area OL1, a second pixel PX2 that emits a second light through a second light exit area OL2, and a third pixel PX3 that emits a third light through a third light exit area OL3. In this case, the pixel circuit layer CIL of each of the plurality of pixel light emitting chips LEC may include three pixel circuit units PDU, the light emitting element layer EML of each of the plurality of pixel light emitting chips LEC may include three light emitting elements LEL, and the optical layer OPL of each of the plurality of pixel light emitting chips LEC may include three light exit areas OL1, OL2, and OL3.

[0117] The first light may be light of a red band, the second light may be light of a green band, and the third light may be light of a blue band. The red band may be a band of light having a main peak wavelength in the range of approximately 600 nm to 750 nm, the green band may be a band of light having a main peak wavelength in the range of approximately 480 nm to 560 nm, and the blue band may be a band of light having a main peak wavelength in the range of approximately 370 nm to 460 nm. However, the present disclosure is not limited thereto.

[0118] The plurality of chip pads CP1 to CP9 may be respectively disposed on the plurality of pixel pads PPD. The plurality of chip pads CP1 to CP9 may be disposed on the plurality of pixel pads PPD in a one-to-one correspondence manner. The plurality of chip pads CP1 to CP9 may overlap with the plurality of pixel pads PPD in the third direction DR3.

[0119] The plurality of chip pads CP1 to CP9 may include first to ninth chip pads CP1 to CP9. When each of the plurality of pixel light emitting chips LEC includes three pixels PX1, PX2, and PX3, the first chip pad CP1 may be disposed on a first data pad DP1 corresponding to a pad of the first pixel PX1. The first chip pad CP1 may be disposed to correspond to the first data pad DP1. The first chip pad CP1 may overlap the first data pad DP1 in the third direction DR3.

[0120] The second chip pad CP2 may be disposed on the second data pad DP2 corresponding to the pad of the second pixel PX2. The second chip pad CP2 may be disposed to correspond to the second data pad DP2. The second chip pad CP2 may overlap the second data pad DP2 in the third direction DR3.

[0121] The third chip pad CP3 may be disposed on the third data pad DP3 corresponding to the pad of the third pixel PX3. The third chip pad CP3 may be disposed to correspond to the third data pad DP3. The third chip pad CP3 may overlap the third data pad DP3 in the third direction DR3.

[0122] The fourth chip pad CP4 may be disposed on the first scan pad SP1 corresponding to the fourth pixel pad. The fourth chip pad CP4 may be disposed to correspond to the first scan pad SP1. The fourth chip pad CP4 may overlap the first scan pad SP1 in the third direction DR3.

[0123] The fifth chip pad CP5 may be disposed on the emission pad EP corresponding to the fifth pixel pad. The fifth chip pad CP5 may be disposed to correspond to the emission pad EP. The fifth chip pad CP5 may overlap the emission pad EP in the third direction DR3 (eg, the thickness direction of the pixel light emitting chip LEC).

[0124] The sixth chip pad CP6 may be disposed on the second scan pad SP2 corresponding to the sixth pixel pad. The sixth chip pad CP6 may be disposed to correspond to the second scan pad SP2. The sixth chip pad CP6 may overlap the second scan pad SP2 in the third direction DR3.

[0125] The seventh chip pad CP7 may be disposed on the second power pad VP2 corresponding to the seventh pixel pad. The seventh chip pad CP7 may be disposed to correspond to the second power pad VP2. The seventh chip pad CP7 may overlap the second power pad VP2 in the third direction DR3.

[0126] The eighth chip pad CP8 may be disposed on the first power pad VP1 corresponding to the eighth pixel pad. The eighth chip pad CP8 may be disposed to correspond to the first power pad VP1. The eighth chip pad CP8 may overlap the first power pad VP1 in the third direction DR3.

[0127] The ninth chip pad CP9 may be disposed on the third power pad VP3 corresponding to the ninth pixel pad. The ninth chip pad CP9 may be disposed to correspond to the third power pad VP3. The ninth chip pad CP9 may overlap the third power pad VP3 in the third direction DR3.

[0128] The pixel circuit layer CIL includes a plurality of pixel circuit units PDU. Figure 4 As shown in FIG, each of the plurality of pixel circuit units PDU includes a driving transistor DT, at least one switching element and a capacitor C1. The at least one switching element may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5 and a sixth transistor ST6, but the present disclosure is not limited thereto.

[0129] For example, the plurality of pixel circuit units PDU may include a pixel circuit unit PDU of a first pixel PX1, a pixel circuit unit PDU of a second pixel PX2, and a pixel circuit unit PDU of a third pixel PX3. The pixel circuit unit PDU of the first pixel PX1, the pixel circuit unit PDU of the second pixel PX2, and the pixel circuit unit PDU of the third pixel PX3 are connected to different data lines. Specifically, the pixel circuit unit PDU of the first pixel PX1 may be connected to the first chip pad CP1 to receive the first data line RDL (see Fig. 9 ), the pixel circuit unit PDU of the second pixel PX2 may be connected to the second chip pad CP2 to receive the second data line GDL (see Fig. 9 ), the pixel circuit unit PDU of the third pixel PX3 may be connected to the third chip pad CP3 to receive the data voltage of the third data line BDL (see Fig. 9 ) data voltage.

[0130] The light emitting element layer EML includes a plurality of light emitting elements LEL. For example, the plurality of light emitting elements LEL may include a light emitting element LEL of a first pixel PX1, a light emitting element LEL of a second pixel PX2, and a light emitting element LEL of a third pixel PX3. In this case, the light emitting element LEL of the first pixel PX1 may emit light in response to a driving current of the pixel circuit unit PDU of the first pixel PX1. The light emitting element LEL of the second pixel PX2 may emit light in response to a driving current of the pixel circuit unit PDU of the second pixel PX2. The light emitting element LEL of the third pixel PX3 may emit light in response to a driving current of the pixel circuit unit PDU of the third pixel PX3.

[0131] The optical layer OPL includes a plurality of light exit areas OL1 to OL3. The plurality of light exit areas OL1 to OL3 include a first light exit area OL1, a second light exit area OL2, and a third light exit area OL3, through which light of the light emitting element LEL of the first pixel PX1 is emitted, through which light of the light emitting element LEL of the second pixel PX2 is emitted, and through which light of the light emitting element LEL of the third pixel PX3 is emitted.

[0132] like Figure 7 and Figure 8 As shown in , each of the multiple pixel light-emitting chips LEC includes a pad layer PDL, a pixel circuit layer CIL, a light-emitting element layer EML and an optical layer OPL, the pad layer PDL includes multiple chip pads CP1 to CP9 connected to multiple pixel pads PPD respectively arranged on multiple island patterns IP, a pixel circuit unit PDU of the first pixel PX1 to the third pixel PX3 is arranged in the pixel circuit layer CIL, a light-emitting element LEL of the first pixel PX1 to the third pixel PX3 is arranged in the light-emitting element layer EML, and the optical layer OPL includes the first light emitting area OL1, the second light emitting area OL2 and the third light emitting area OL3 of the first pixel PX1 to the third pixel PX3. That is, the pixel light-emitting chip LEC can be a chip in which the pixel circuit layer CIL, the light-emitting element layer EML and the optical layer OPL are integrated. Therefore, even if the area of ​​the island pattern IP corresponding to the non-stretched portion is reduced to realize a high-resolution display device, the multiple pixel light-emitting chips LEC only need to be attached to the multiple island patterns IP respectively. Therefore, a stretchable display device with high pixel integration can be provided.

[0133] To simplify the description, although Figure 7 and Figure 8 It is shown that the area of ​​the pixel light emitting chip LEC is smaller than the area of ​​the first island pattern IP1, but the present disclosure is not limited thereto. For example, the area of ​​the pixel light emitting chip LEC may be larger than the area of ​​the first island pattern IP1.

[0134] Fig. 9 It is shown Figure 6 Layout diagram of an example of multiple scan lines, multiple data lines, multiple power lines, multiple bridges, and multiple pixel pads in area A. Fig.10 It is shown Figure 6 A layout diagram of a first island pattern in region A and first to third light emitting regions of a pixel light emitting chip.

[0135] Reference Fig. 9 and Fig.10, the first data line RDL, the second data line GDL, the third data line BDL, the first power line VSL, and the second power line VDL extend in the second direction DR2 so that they can be arranged in the ninth bridge pattern BP9, the first island pattern IP1, and the second bridge pattern BP2. The first data line RDL may be a line for supplying a data voltage to the first pixel PX1 of the pixel light emitting chip LEC. The second data line GDL may be a line for supplying a data voltage to the second pixel PX2 of the pixel light emitting chip LEC. The third data line BDL may be a line for supplying a data voltage to the third pixel PX3 of the pixel light emitting chip LEC. The first power line VSL may be a line for supplying a first power voltage VSS, and the second power line VDL may be a line for supplying a second power voltage VDD.

[0136] Since the kth write scan line GWLk, the kth initialization scan line GILk, the kth emission line ELk, and the third power line VIL extend in the first direction DR1, they may be arranged in the fifth bridge pattern BP5, the first island pattern IP1, and the first bridge pattern BP1. The kth write scan line GWLk may be a line for supplying a write scan signal to the first pixel PX1, the second pixel PX2, and the third pixel PX3 of the pixel light emitting chip LEC. The kth initialization scan line GILk may be a line for supplying an initialization scan signal to the first pixel PX1, the second pixel PX2, and the third pixel PX3 of the pixel light emitting chip LEC. The third power line VIL may be a line for supplying a third power voltage VINT.

[0137] The first data line RDL extending from the ninth bridge pattern BP9 and the first data line RDL extending from the second bridge pattern BP2 may be directly connected to the first data pad DP1. The second data line GDL extending from the ninth bridge pattern BP9 and the second data line GDL extending from the second bridge pattern BP2 may be directly connected to the second data pad DP2. The third data line BDL extending from the ninth bridge pattern BP9 and the third data line BDL extending from the second bridge pattern BP2 may be directly connected to the third data pad DP3. The first power line VSL extending from the ninth bridge pattern BP9 and the first power line VSL extending from the second bridge pattern BP2 may be directly connected to the first power pad VP1. The second power line VDL extending from the ninth bridge pattern BP9 and the second power line VDL extending from the second bridge pattern BP2 may be directly connected to the second power pad VP2.

[0138] In the first island pattern IP1 , first to second to third to fourth bridge lines BRL1 , BRL2 , BRL3 , BRL4 , first to second to third to fourth bridge lines BEL1 , BEL2 , BEL3 , and BEL4 may be arranged.

[0139] One end of the first bridge line BRL1 may be connected to the kth write scan line GWLk extending from the fifth bridge pattern BP5 through the first bridge contact hole BRH1. The other end of the first bridge line BRL1 may be connected to the first bridge connection line BEL1 connected to the first scan pad SP1 through the first bridge contact hole BRH1. The kth write scan line GWLk extending from the first bridge pattern BP1 may be directly connected to the first scan pad SP1.

[0140] One end and the other end of the second bridge line BRL2 may be connected to the kth initialization scan line GILk through a second bridge contact hole BRH2. A middle of the second bridge line BRL2 may be connected to the second bridge connection line BEL2 connected to the second scan pad SP2 through a fifth bridge contact hole BRH5.

[0141] One end of the third bridge line BRL3 may be connected to the third bridge connection line BEL3 through the third bridge contact hole BRH3. The other end thereof may be connected to the kth emission line ELk extending from the first bridge pattern BP1 through the third bridge contact hole BRH3. The kth emission line ELk extending from the fifth bridge pattern BP5 may be directly connected to the emission pad EP.

[0142] One end of the fourth bridge wire BRL4 may be connected to the third power line VIL extending from the fifth bridge pattern BP5 through the fourth bridge contact hole BRH4. The other end of the fourth bridge wire BRL4 may be connected to the third power line VIL extending from the first bridge pattern BP1 through the fourth bridge contact hole BRH4. The fourth bridge connection wire BEL4 directly connected to the third power pad VP3 may be directly connected to the third power line VIL extending from the first bridge pattern BP1.

[0143] The first data line RDL, the second data line GDL, the third data line BDL, the first power line VSL, the second power line VDL, the kth write scan line GWLk, the kth initialization scan line GILk, the kth emission line ELk, the third power line VIL, the first bridge connection line BEL1, the second bridge connection line BEL2, the third bridge connection line BEL3, and the fourth bridge connection line BEL4 may be formed by the first metal layer. The first bridge line BRL1, the second bridge line BRL2, the third bridge line BRL3, and the fourth bridge line BRL4 may be formed by the second metal layer. Therefore, the first bridge line BRL1, the second bridge line BRL2, the third bridge line BRL3, and the fourth bridge line BRL4 may cross the first data line RDL, the second data line GDL, the third data line BDL, the first power line VSL, and the second power line VDL.

[0144] Fig.11 It is shown along Fig. 9 and Fig.10 A cross-sectional view of an example of a first island pattern and a pixel light-emitting chip taken along line ZZ'. Fig.12It is shown along Fig. 9 and Fig.10 A cross-sectional view of an example of a first island pattern and a pixel light-emitting chip taken along line YY′. Fig.13 It is shown along Fig. 9 and Fig.10 A cross-sectional view of an example of a first island pattern and a pixel light-emitting chip taken along line XX'.

[0145] Reference Figures 11 to 13 , the substrate SUB may be made of an insulating material such as a polymer resin. For example, the substrate SUB may be formed of polyimide. The substrate SUB may be a flexible substrate that can be bent, folded, and / or rolled.

[0146] The first insulating layer INS1 may be disposed on the substrate SUB. The first insulating layer INS1 may be formed of an inorganic layer such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and / or aluminum oxide.

[0147] The first metal layer MTL1 may be disposed on the first insulating layer INS1. The first metal layer MTL1 includes a first data line RDL, a second data line GDL, a third data line BDL, a first power line VSL, a second power line VDL, a kth write scan line GWLk, a kth initialization scan line GILk, a kth emission line ELk, a third power line VIL, a first bridge connection line BEL1, a second bridge connection line BEL2, a third bridge connection line BEL3, and a fourth bridge connection line BEL4. The first metal layer may be formed as a single layer or a multilayer made of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or an alloy thereof.

[0148] The second insulating layer INS2 may be disposed on the first metal layer MTL1. The second insulating layer INS2 may be formed of an inorganic layer such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and / or aluminum oxide.

[0149] The second metal layer MTL2 may be disposed on the second insulating layer INS2. The second metal layer MTL2 includes a plurality of scan pads SP1, SP2, and EP, a plurality of data pads DP1, DP2, and DP3, a plurality of power pads VP1, VP2, and VP3, a first bridge line BRL1, a second bridge line BRL2, a third bridge line BRL3, and a fourth bridge line BRL4. The second metal layer MTL2 may be formed as a single layer or a multilayer made of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or alloys thereof.

[0150] The first data pad DP1 may be connected to the first data line RDL through a first data contact hole DH1 penetrating the second insulating layer INS2. The first power pad VP1 may be connected to the first power line VSL through a first power contact hole VH1 penetrating the second insulating layer INS2. The emission pad EP may be connected to the kth emission line ELk through an emission contact hole EH penetrating the second insulating layer INS2. The second power pad VP2 may be connected to the second power line VDL through a second power contact hole VH2 penetrating the second insulating layer INS2.

[0151] The first bridge line BRL1 may be connected to the kth write scan line GWLk through a first bridge contact hole BRH1 penetrating the second insulating layer INS2 and may be connected to the first bridge connection line BEL1 connected to the first scan pad SP1 through another first bridge contact hole BRH1 penetrating the second insulating layer INS2.

[0152] The second bridge line BRL2 may be connected to the kth initialization scan line GILk through a second bridge contact hole BRH2 penetrating the second insulating layer INS2 and may be connected to the second bridge connection line BEL2 through a fifth bridge contact hole BRH5 penetrating the second insulating layer INS2.

[0153] The third bridge line BRL3 may be connected to the third bridge connection line BEL3 through a third bridge contact hole BRH3 penetrating the second insulating layer INS2 and may be connected to the kth emission line ELk through another third bridge contact hole BRH3 penetrating the second insulating layer INS2.

[0154] The fourth bridge line BRL4 may be connected to the third power line VIL through a fourth bridge contact hole BRH4 penetrating the second insulating layer INS2 and may be connected to the third power line VIL through another fourth bridge contact hole BRH4 penetrating the second insulating layer INS2.

[0155] The conductive adhesive member CAD may be disposed on the plurality of scan pads SP1, SP2, and EP, the plurality of data pads DP1, DP2, and DP3, and the plurality of power pads VP1, VP2, and VP3. For example, the conductive adhesive member CAD may be as follows: Figures 11 to 13 The anisotropic conductive film shown in FIG. 1 includes a plurality of conductive balls CB, but the present disclosure is not limited thereto.

[0156] A pad layer PDL including a plurality of chip pads CP1 to CP9 may be disposed on the conductive adhesive member CAD. The plurality of chip pads CP1 to CP9 may be formed as a single layer or multiple layers made of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or alloys thereof.

[0157] The third insulating layer INS3 may be disposed on the pad layer PDL including the plurality of chip pads CP1 to CP9. The third insulating layer INS3 may be formed of an inorganic layer such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and / or aluminum oxide. Alternatively, the third insulating layer INS3 may be an organic layer such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0158] The third metal layer MTL3 may be disposed on the third insulating layer INS3. The third metal layer MTL3 may be connected to the plurality of connection electrodes DCE1, VCE1, VCE2, and ECE1. The plurality of connection electrodes DCE1, VCE1, VCE2, and ECE1 include a first data connection electrode DCE1, a first power connection electrode VCE1, a second power connection electrode VCE2, and a first emission connection electrode ECE1. The third metal layer MTL3 may be formed as a single layer or a multilayer made of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or alloys thereof.

[0159] The fourth insulating layer INS4 may be disposed on the third metal layer MTL3. The fourth insulating layer INS4 may be formed of an inorganic layer such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and / or aluminum oxide.

[0160] The fourth metal layer MTL4 may be disposed on the fourth insulating layer INS4. The fourth metal layer MTL4 may include the third power connection electrode VCE3 and one electrode of the capacitor C1. The fourth metal layer MTL4 may be formed as a single layer or multiple layers made of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or an alloy thereof.

[0161] The fifth insulating layer INS5 may be disposed on the fourth metal layer MTL4. The fifth insulating layer INS5 may be formed of an inorganic layer such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and / or aluminum oxide.

[0162] The fifth metal layer MTL5 may be disposed on the fifth insulating layer INS5. The fifth metal layer MTL5 may include a gate electrode of the driving transistor DT, a gate electrode GE2 of the second transistor ST2, a gate electrode GE6 of the sixth transistor ST6, and a fourth power connection electrode VCE4. In addition, the fifth metal layer MTL5 may include a gate electrode of the first transistor ST1, a gate electrode of the third transistor ST3, a gate electrode of the fourth transistor ST4, a gate electrode GE5 of the fifth transistor ST5, and another electrode of the capacitor C1. The fifth metal layer MTL5 may be formed as a single layer or a multilayer made of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or alloys thereof.

[0163] The sixth insulating layer INS6 may be disposed on the fifth metal layer MTL5. The sixth insulating layer INS6 may be formed of an inorganic layer such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and / or aluminum oxide.

[0164] The active layer ACT may be disposed on the sixth insulating layer INS6. The active layer ACT may include an active pattern of the driving transistor DT, an active pattern ACT2 of the second transistor ST2, and an active pattern ACT6 of the sixth transistor ST6. In addition, the active layer ACT may include an active pattern of the first transistor ST1, an active pattern of the third transistor ST3, an active pattern of the fourth transistor ST4, and an active pattern ACT5 of the fifth transistor ST5. The active layer ACT may be formed of polysilicon and / or an oxide semiconductor.

[0165] The active pattern of the driving transistor DT may include a channel region overlapping the gate electrode in the third direction DR3, a source region disposed on one side of the channel region, and a drain region disposed on the other side of the channel region. The active pattern ACT2 of the second transistor ST2 may include a channel region overlapping the gate electrode GE2 in the third direction DR3, a source region disposed on one side of the channel region, and a drain region disposed on the other side of the channel region. The active pattern ACT6 of the sixth transistor ST6 may include a channel region overlapping the gate electrode GE6 in the third direction DR3, a source region disposed on one side of the channel region, and a drain region disposed on the other side of the channel region. The active pattern ACT6 of the sixth transistor ST6 may be connected to the first semiconductor layer SEM1 of the light emitting element LEL through an active contact hole AH penetrating the seventh insulating layer INS7.

[0166] The seventh insulating layer INS7 may be disposed on the active layer ACT. The seventh insulating layer INS7 may be an organic layer such as acryl resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0167] The light emitting element LEL may be disposed on the seventh insulating layer INS7.

[0168] The first data link electrode DCE1 may be connected to the source region of the active pattern ACT2 of the second transistor ST2 through the second data contact hole DH2 penetrating the fourth, fifth and sixth insulating layers INS4, INS5 and INS6. Each of the chip pads CP1 to CP9 may be electrically connected to the active pattern of the corresponding transistor.

[0169] The first emission connection electrode ECE1 may be connected to the gate electrode GE6 of the sixth transistor ST6 through a second scanning contact hole EH2 penetrating the fourth and fifth insulating layers INS4 and INS5. The fifth chip pad CP5 may be connected to the first emission connection electrode ECE1 through a first scanning contact hole EH1 penetrating the third insulating layer INS3.

[0170] The first power connection electrode VCE1 may be connected to the eighth chip pad CP8 through a contact hole penetrating the third insulating layer INS3. The first power connection electrode VCE1 may be connected to the third power connection electrode VCE3 through a third power contact hole VH3 penetrating the fourth insulating layer INS4. The third power connection electrode VCE3 may be connected to the fourth power connection electrode VCE4 through a fifth power contact hole VH5 penetrating the fifth insulating layer INS5. The fourth power connection electrode VCE4 may be connected to the common electrode layer CEL through a sixth power contact hole VH6 penetrating the sixth insulating layer INS6 and the seventh insulating layer INS7.

[0171] The second power connection electrode VCE2 may be connected to the seventh chip pad CP7 through a contact hole penetrating the third insulating layer INS3. The second power connection electrode VCE2 may be connected to the source region of the active pattern ACT5 of the fifth transistor ST5 through a fourth power contact hole VH4 penetrating the fourth insulating layer INS4, the fifth insulating layer INS5, and the sixth insulating layer INS6.

[0172] Each of the light emitting elements LEL includes a first semiconductor layer SEM1, an active layer MQW, and a second semiconductor layer SEM2. In one or more embodiments, the light emitting element LEL may include a superlattice layer.

[0173] The first semiconductor layer SEM1 may be disposed on the seventh insulating layer INS7. The first semiconductor layer SEM1 may be formed of GaN doped with a first conductive type dopant such as Mg, Zn, Ca, Sr, and / or Ba.

[0174] An electron blocking layer may be additionally disposed on the first semiconductor layer SEM1. The electron blocking layer may be a layer for suppressing or preventing too many electrons from flowing into the active layer MQW. The electron blocking layer may be AlGaN and / or p-AlGaN doped with p-type Mg.

[0175] The active layer MQW may be disposed on the first semiconductor layer SEM1. The active layer MQW may emit light through recombination of electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0176] The active layer MQW may include a material having a single quantum well structure or a multiple quantum well structure. When the active layer MQW includes a material having a multiple quantum well structure, the active layer MQW may have a structure in which a plurality of well layers and barrier layers are alternately stacked. At this time, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN and / or AlGaN, but the present disclosure is not limited thereto. Alternatively, the active layer MQW may have a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked, and may include other III to V semiconductor materials depending on the wavelength band of the emitted light.

[0177] When the active layer MQW includes InGaN, the color of the emitted light may vary according to the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer may shift to the red band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer may shift to the blue band. For example, the active layer MQW of the light emitting element LEL emitting blue band light may include about 10wt% to 20wt% of indium.

[0178] In one or more embodiments, a superlattice layer may be additionally disposed on the active layer MQW. The superlattice layer may be a layer for relieving stress between the second semiconductor layer SEM2 and the active layer MQW. The superlattice layer may be formed of InGaN and / or GaN.

[0179] The second semiconductor layer SEM2 may be disposed on the active layer MQW. The second semiconductor layer SEM2 may be doped with a second conductive dopant such as Si, Ge, Sn, etc. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si.

[0180] The common electrode layer CEL may be commonly connected to the second semiconductor layer SEM2 of the plurality of light emitting elements LEL. The common electrode layer CEL may receive a first power voltage VSS through a first power line VSL, a first power pad VP1, a first power connection electrode VCE1, a third power connection electrode VCE3, a fourth power connection electrode VCE4, and a common connection electrode. The common electrode layer CEL may be formed of a transparent conductive oxide (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO). Alternatively, the common electrode layer CEL may be formed of a transparent conductive oxide (TCO) or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), and / or an alloy of magnesium (Mg) and / or silver (Ag).

[0181] The common electrode layer CEL may be disposed on the side insulating layer SINS, and the side insulating layer SINS is disposed on one side of the light emitting element LEL. The side insulating layer SINS may be a layer for insulating the common electrode layer CEL from the side surface of the light emitting element layer EML. The side insulating layer SINS may be formed of an inorganic layer such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and / or aluminum oxide.

[0182] The optical layer OPL includes a first light conversion layer QDL1, a second light conversion layer QDL2, and a light transmitting layer TPL.

[0183] The first light conversion layer QDL1 may be disposed in the first light exit region OL1 of the first pixel PX1. The first light conversion layer QDL1 may convert a portion of the light in the blue band incident from the light emitting element LEL into light in the red band. The first light conversion layer QDL1 may include a first matrix resin BRS1 and first wavelength conversion particles WCP1. The first matrix resin BRS1 may include a light-transmitting organic material. For example, the first matrix resin BRS1 may include an epoxy resin, an acrylic resin, a cardo resin, and / or an imide resin. The first wavelength conversion particles WCP1 may convert a portion of the light in the blue band incident from the light emitting element LEL into light in the red band. The first wavelength conversion particles WCP1 may be quantum dots (QDs), quantum rods, fluorescent materials, and / or phosphorescent materials.

[0184] The second light conversion layer QDL2 may be disposed in the second light emitting region OL2 of the second pixel PX2. The second light conversion layer QDL2 may convert a portion of the light in the blue band incident from the light emitting element LEL into light in the green band. The second light conversion layer QDL2 may include a second matrix resin BRS2 and second wavelength conversion particles WCP2. The second matrix resin BRS2 may include a light-transmitting organic material. For example, the second matrix resin BRS2 may include an epoxy resin, an acrylic resin, a cardo resin and / or an imide resin. The second wavelength conversion particles WCP2 may convert a portion of the light in the blue band incident from the light emitting element LEL into light in the green band. The second wavelength conversion particles WCP2 may be quantum dots (QDs), quantum rods, fluorescent materials and / or phosphorescent materials.

[0185] The light-transmitting layer TPL is disposed in the third light-emitting region OL3 of the third pixel PX3. The light-transmitting layer TPL may include a light-transmitting organic material. For example, the light-transmitting layer TPL may include epoxy resin, acrylic resin, cardo resin, imide resin, etc. The light-transmitting layer TPL may include substantially the same material as the first base resin BRS1 and the second base resin BRS2.

[0186] A plurality of color filters may be disposed on the first light conversion layer QDL1, the second light conversion layer QDL2, and the light-transmitting layer TPL. For example, a first color filter that transmits light in the red band and absorbs or blocks light in other bands may be disposed on the first light conversion layer QDL1. A second color filter that transmits light in the green band and absorbs or blocks light in other bands may be disposed on the second light conversion layer QDL2. A third color filter that transmits light in the blue band and absorbs or blocks light in other bands may be disposed on the light-transmitting layer TPL.

[0187] Fig.14 is a flowchart illustrating a method for manufacturing a stretchable display device according to one or more embodiments. Fig.15 and Fig.16 1 and 2 are an exploded perspective view and a perspective view respectively illustrating a method for manufacturing a stretchable display device according to one or more embodiments.

[0188] In the following, reference will be made to Figures 14 to 16 A method for manufacturing a stretchable display device according to one or more embodiments is described in detail.

[0189] First, if Fig.15 As shown in FIG. , a plurality of pixel light emitting chips LEC are formed. Fig.14 Step S100). Figures 17 to 26 A method for forming a plurality of pixel light emitting chips LEC is described.

[0190] Next, in order to realize the stretchable display device 10, a substrate SUB including a plurality of island patterns IP and a plurality of bridge patterns BP is provided. Fig.14 Step S200).

[0191] The substrate SUB including the plurality of island patterns IP and the plurality of bridge patterns BP may be provided by forming the plurality of gaps G1 to G5 through a laser process or an etching process.

[0192] Then, if Figures 11 to 13 As shown in FIG, a first insulating layer INS1 is formed on a substrate SUB, and a first metal layer MTL1 is formed on the first insulating layer INS1. The first metal layer MTL1 includes data lines RDL, GDL and BDL, a kth write scan line GWLk, a kth initialization scan line GILk, a kth emission line ELk, and power lines VSL, VDL and VIL.

[0193] Then, if Figures 11 to 13As shown in FIG. 1 , a second insulating layer INS2 is formed on the first metal layer MTL1, contact holes DH1, VH1, EH and VH2 are formed in the second insulating layer INS2, and a second metal layer MTL2 is formed on the second insulating layer INS2. The second metal layer MTL2 includes a pixel pad PPD, a first bridge line BRL1, a second bridge line BRL2, a third bridge line BRL3 and a fourth bridge line BRL4. The pixel pad PPD includes a plurality of scan pads SP1, SP2 and EP, a plurality of data pads DP1, DP2 and DP3 and a plurality of power pads VP1, VP2 and VP3.

[0194] Third, attach the pixel light-emitting chips LEC to the island patterns IP ( Fig.14 Step S300).

[0195] The plurality of pixel light emitting chips LEC may be disposed in one-to-one correspondence with the plurality of island patterns IP. The plurality of pixel light emitting chips LEC may be disposed on the plurality of non-stretchable island patterns IP, and may not be disposed on the plurality of stretchable bridge patterns BP.

[0196] In this case, the chip pads CP1 to CP9 of the pixel light emitting chip LEC may be electrically connected to the corresponding pixel pads PPD of the island pattern IP through the conductive adhesive member CAD, fusion bonding, and / or soldering.

[0197] Fig.17 It is shown in detail Fig.14 Flow chart of an example of step S100. Figures 18 to 26 Is used to describe Fig.14 FIG. 5 is a cross-sectional view of an example of step S100 . Figures 18 to 26 It is along Fig.10 A cross-sectional view taken along line Y-Y'.

[0198] First, if Fig.18 As shown in FIG, a second semiconductor material layer SEML2, an active material layer MQWL and a first semiconductor material layer SEML1 are sequentially formed on a semiconductor substrate SSUB ( Fig.17 Step S110).

[0199] The semiconductor substrate SSUB may be a sapphire substrate, but the present disclosure is not limited thereto. The second semiconductor material layer SEML2, the active material layer MQWL, and the first semiconductor material layer SEML1 may be entirely disposed on one surface of the semiconductor substrate SSUB. In one or more embodiments, a third semiconductor material layer SEML3 may be disposed between the semiconductor substrate SSUB and the second semiconductor material layer SEML2.

[0200] Secondly, if Figures 19 to 21As shown in FIG. 1 , a seventh insulating layer INS7 is formed on the first semiconductor material layer SEML1, and an active layer ACT ( Fig.17 Step S120).

[0201] Specifically, Fig.19 As shown in FIG. 1 , an active material layer ACTL including amorphous silicon is formed on the seventh insulating layer INS7. Then, as shown in FIG. Fig. 20 As shown in , by irradiating the active material layer ACTL with laser, amorphous silicon is recrystallized and becomes polycrystalline silicon. Fig.21 As shown in FIG. 1 , the active material layer ACTL is patterned by a photolithography process to form an active layer ACT including active patterns ACT2 and ACT6 of transistors DT, ST2 and ST6 .

[0202] Third, if Fig. 22 As shown in FIG. 1 , a sixth insulating layer INS6 is formed on the active layer ACT, and a fifth metal layer MTL5 ( Fig.17 Step S130).

[0203] The sixth insulating layer INS6 may be deposited by chemical vapor deposition. The gate electrode of the driving transistor DT of the fifth metal layer MTL5, the gate electrode GE2 of the second transistor ST2, the gate electrode GE6 of the sixth transistor ST6, the fourth power connection electrode VCE4, the gate electrode of the first transistor ST1, the gate electrode of the third transistor ST3, the gate electrode of the fourth transistor ST4, the gate electrode GE5 of the fifth transistor ST5, and the other electrode of the capacitor C1 may be patterned by a photolithography process.

[0204] Fourth, if Fig. 22 As shown in FIG. 1 , a fifth insulating layer INS5 is formed on the fifth metal layer MTL5, and a fourth metal layer MTL4 ( Fig.17 Step S140).

[0205] The fifth insulating layer INS5 may be deposited by chemical vapor deposition. The third power connection electrode VCE3 of the fourth metal layer MTL4 and one electrode of the capacitor C1 may be patterned by a photolithography process.

[0206] Fifth, if Fig. 22 As shown in FIG. 1 , a fourth insulating layer INS4 is formed on the fourth metal layer MTL4, and a third metal layer MTL3 ( Fig.17 Step S150).

[0207] The fourth insulating layer INS4 may be deposited by chemical vapor deposition. The plurality of connection electrodes DCE1, VCE1, VCE2, and ECE1 of the third metal layer MTL3 may be patterned by a photolithography process.

[0208] Sixth, if Fig. 22 As shown in FIG. 1 , a third insulating layer INS3 is formed on the third metal layer MTL3 , and a plurality of chip pads CP1 to CP9 ( Fig.17 Step S160).

[0209] The third insulating layer INS3 may be deposited by chemical vapor deposition. The plurality of chip pads CP1 to CP9 may be patterned by a photolithography process.

[0210] Seventh, such as Fig.23 As shown in FIG. 1 , a passivation layer PVX is formed on a plurality of chip pads CP1 to CP9 , a first transfer substrate TSUB1 is attached to the passivation layer PVX, and a semiconductor substrate SSUB ( Fig.17 Step S170).

[0211] The passivation layer PVX may be an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0212] The first transfer substrate TSUB1 may be attached to the organic layer via an adhesion promoter or the like.

[0213] The semiconductor substrate SSUB may be separated by irradiating laser or removed through a polishing process.

[0214] Eighth, such as Fig.24 As shown in FIG. , the first semiconductor material layer SEML1, the active material layer MQWL and the second semiconductor material layer SEML2 are patterned to form a plurality of light emitting elements LEL ( Fig.17 Step S180). In addition, although Fig.17 Not depicted, but Fig.24 As shown in , a side insulating layer SINS is formed on a side surface of the light emitting element LEL, and a common electrode layer CEL is formed on the light emitting element LEL.

[0215] The first semiconductor material layer SEML1 , the active material layer MQWL, and the second semiconductor material layer SEML2 may be patterned through a photolithography process.

[0216] Ninth, such as Fig.25 As shown in FIG. , an optical layer OPL is formed on a plurality of light emitting elements LEL. Fig.17 Step S190).

[0217] Specifically, a first light conversion layer QDL1 is formed on the light emitting element LEL of the first pixel PX1. Then, a second light conversion layer QDL2 is formed on the light emitting element LEL of the second pixel PX2. Thereafter, a light transmitting layer TPL is formed on the light emitting element LEL of the third pixel PX3.

[0218] Alternatively, the first matrix resin BRS1, the second matrix resin BRS2, ​​and the light-transmitting layer TPL may be formed on the corresponding light-emitting elements LEL of the first pixel PX1, the second pixel PX2, and the third pixel PX3 with the same material at the same time (e.g., in parallel). Then, the first wavelength conversion particles WCP1 may be injected into the first matrix resin BRS1, and then the second wavelength conversion particles WCP2 may be injected into the second matrix resin BRS2.

[0219] Then, if Fig.26 As shown in FIG. 1 , the second transfer substrate is attached to the optical layer OPL, and the passivation layer PVX and the first transfer substrate TSUB1 are removed to expose a plurality of chip pads CP1 to CP9 ( Fig.17 Step S191).

[0220] The second transfer substrate may be attached to the optical layer OPL via a tackifier, etc. In this case, the adhesion between the second transfer substrate and the optical layer OPL may be higher than the adhesion between the first transfer substrate TSUB1 and the passivation layer PVX. Therefore, even if the first transfer substrate TSUB1 is detached, the adhesion between the second transfer substrate and the optical layer OPL may be maintained.

[0221] The passivation layer PVX may be removed through an ashing process or an etching process.

[0222] However, it should be understood that the aspects and features of the embodiments of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the claims and their equivalents included therein.

Claims

1. A display device, comprising: A substrate including a plurality of island patterns and a first bridge pattern, wherein the first bridge pattern connects first and second island patterns adjacent to each other among the plurality of island patterns; as well as a plurality of pixel light emitting chips, each of the plurality of pixel light emitting chips being located on a corresponding island pattern among the plurality of island patterns, Wherein, each of the plurality of pixel light emitting chips comprises: a transistor layer including a plurality of transistors; and The light emitting element layer is on the transistor layer and includes a plurality of light emitting elements.

2. The display device according to claim 1, wherein: The plurality of pixel light emitting chips correspond one to one to the plurality of island patterns.

3. The display device according to claim 1, wherein: The plurality of light emitting elements include a light emitting element of a first pixel, a light emitting element of a second pixel, and a light emitting element of a third pixel, and Among them, each of the multiple pixel light-emitting chips also includes: a first light conversion layer, which is on the light-emitting element of the first pixel and is constructed to convert the light emitted from the light-emitting element of the first pixel into light of a first band; a second light conversion layer, which is on the light-emitting element of the second pixel and is constructed to convert the light emitted from the light-emitting element of the second pixel into light of a second band; and a light-transmitting layer, which is on the light-emitting element of the third pixel and is constructed to transmit the light emitted from the light-emitting element of the third pixel.

4. The display device according to claim 1, further comprising: a first scanning line on the first island pattern, the second island pattern and the first bridge pattern; as well as The first scanning pad is connected to the first scanning line and is on the first island pattern.

5. The display device according to claim 4, wherein: One of the plurality of pixel light emitting chips further includes a first chip pad electrically connected to the first scanning pad.

6. The display device according to claim 5, wherein: The first scanning pad and the first chip pad overlap each other in a third direction, which is a thickness direction of the substrate.

7. The display device according to claim 5, wherein: The transistor layer includes: a first insulating layer, on the first chip pad; A gate electrode of a first transistor among the plurality of transistors is on the first insulating layer and electrically connected to the first chip pad; a second insulating layer, on the gate electrode of the first transistor; an active layer of the first transistor on the second insulating layer; and A third insulating layer is on the active layer of the first transistor.

8. The display device according to claim 7, wherein: The plurality of light emitting elements of the light emitting element layer are on the third insulating layer.

9. The display device according to claim 1, further comprising: a first data line on the first island pattern, the second island pattern and the first bridge pattern; as well as The first data pad is connected to the first data line and is located on the first island pattern.

10. The display device according to claim 9, wherein: One of the plurality of pixel light emitting chips further includes a second chip pad electrically connected to the first data pad.

11. The display device according to claim 10, wherein: The first data pad and the second chip pad overlap each other in a third direction, which is a thickness direction of the substrate.

12. The display device according to claim 10, wherein: The transistor layer includes: a first insulating layer, on the second chip pad; A first connecting electrode and a gate electrode of a second transistor among the plurality of transistors are on the first insulating layer; a second insulating layer on the first connecting electrode and the gate electrode of the second transistor; an active layer of the second transistor on the second insulating layer and connected to the first connection electrode through a contact hole penetrating the second insulating layer; and A third insulating layer is on the active layer of the second transistor.

13. The display device according to claim 12, wherein: The plurality of light emitting elements of the light emitting element layer are located on the third insulating layer.

14. The display device according to claim 1, further comprising: a first power line on the first island pattern, the second island pattern and the first bridge pattern; as well as The first power pad is connected to the first power line and is located on the first island pattern.

15. The display device according to claim 14, wherein: One of the plurality of pixel light emitting chips further includes a third chip pad electrically connected to the first power pad.

16. The display device according to claim 15, wherein: The transistor layer includes: a first insulating layer, on the third chip pad; a second connecting electrode, on the first insulating layer and connected to the third chip pad via a contact hole penetrating the first insulating layer; a second insulating layer on the second connecting electrode; and The third connection electrode is on the second insulating layer and connected to the second connection electrode through a contact hole penetrating the second insulating layer.

17. The display device according to claim 16, wherein: Each of the plurality of light emitting elements of the light emitting element layer includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, and Wherein, the third connecting electrode is electrically connected to the second semiconductor layer.

18. A display device, comprising: a substrate comprising a first island pattern and a second island pattern adjacent to each other in a first direction, a third island pattern adjacent to the first island pattern in a second direction intersecting the first direction, a first bridge pattern connecting the first island pattern and the second island pattern, and a second bridge pattern connecting the first island pattern and the third island pattern in the second direction; a first scanning line located on the first island pattern and the first bridge pattern and configured to receive a first scanning signal; a first data line located on the first island pattern and the second bridge pattern and configured to receive a first data voltage; a first scanning pad, located on the first island pattern and connected to the first scanning line; a first data pad located on the first island pattern and connected to the first data line; and A pixel light-emitting chip comprises a pad layer, a transistor layer and a light-emitting element layer, wherein the pad layer comprises a first chip pad electrically connected to the first scanning pad and a second chip pad electrically connected to the first data pad, the transistor layer comprises a plurality of transistors located on the pad layer, and the light-emitting element layer is located on the transistor layer and comprises a plurality of light-emitting elements.

19. A method for manufacturing a display device, the method comprising the following steps: Forming a plurality of pixel light-emitting chips, each of the plurality of pixel light-emitting chips comprises a chip pad layer, a transistor layer and a light-emitting element layer, the chip pad layer comprises a plurality of chip pads, the transistor layer is located on the chip pad layer, and the light-emitting element layer is located on the transistor layer; forming a substrate including a plurality of island patterns and bridge patterns, each of the bridge patterns connecting mutually adjacent island patterns among the plurality of island patterns; as well as The plurality of pixel light emitting chips are attached to the plurality of island patterns, respectively.

20. The method according to claim 19, wherein: The steps of forming the plurality of pixel light emitting chips include: sequentially forming a second semiconductor material layer, an active material layer and a first semiconductor material layer on a semiconductor substrate; forming a first insulating layer on the first semiconductor material layer, and forming an active pattern of a transistor on the first insulating layer; forming a second insulating layer on the active pattern, and forming a gate electrode of the transistor on the second insulating layer; forming a third insulating layer on the gate electrode, and forming the plurality of chip pads on the third insulating layer; removing the semiconductor substrate; and The second semiconductor material layer, the active material layer, and the first semiconductor material layer are patterned to form the light emitting element layer including a plurality of light emitting elements.

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