Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a display area and a peripheral area surrounding the display area, the peripheral area comprises a leading-out wire area located on one side of the display area, and the leading-out wire area comprises a bending area. The first blocking dam and the second blocking dam surround the display area, and the second blocking dam is located on the side, away from the display area, of the first blocking dam. And the at least one isolation groove is positioned on one side, far away from or close to the display area, of the second blocking dam. And a power line electrically connected to the plurality of sub-pixels of the display area to provide a constant voltage signal to the plurality of sub-pixels. The outgoing line area is provided with at least one power supply pin which is electrically connected with the power line and extends along the direction far away from the display area; the first part is located on the first blocking dam and close to the display area, the second part is located between the second blocking dam and the bending area, at least part of the switching electrode is located between the first part and the second part, and the first part and the second part are in different layers with the switching electrode and are electrically connected through the switching electrode.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, display devices using OLED as the light-emitting element and thin film transistor (TFT) for signal control have become the mainstream products in the current display field.

[0003] However, there is a growing dark spot (GDS) problem on the lower frame of display products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiments of the present disclosure provide a display substrate and a display device to solve the problem of GDS existing in the lower frame of a display product.

[0006] On the one hand, the embodiments of the present disclosure provide a display substrate, comprising: a substrate substrate, comprising a display area and a peripheral area surrounding the display area, the peripheral area comprising a lead-out area located on one side of the display area, the lead-out area comprising a bending area; a plurality of sub-pixels located on one side of the substrate substrate and located in the display area; a first blocking dam located on the substrate substrate, located in the peripheral area and surrounding the display area; a second blocking dam located on the substrate substrate, located in the peripheral area and surrounding the display area, the second blocking dam being located on a side of the first blocking dam away from the display area; and at least one isolation groove located on a side of the second blocking dam away from or close to the second blocking dam. on one side of the display area; a power line electrically connected to the plurality of sub-pixels and configured to provide a constant voltage signal to the plurality of sub-pixels; at least one power pin located in the lead-out area and extending in a direction away from the display area and electrically connected to the power line; the at least one power pin includes a first portion located on the first blocking dam close to the display area, a second portion located between the second blocking dam and the bending area, and a switching electrode at least partially located between the first portion and the second portion, the first portion and the second portion are located on different layers from the switching electrode, and the first portion and the second portion are electrically connected via the switching electrode.

[0007] In an exemplary embodiment, in a direction away from the base substrate, the display substrate includes a driving structure layer, a transfer layer, a flat layer and a display structure layer arranged in sequence; the driving structure layer includes a pixel driving circuit, the display structure layer includes a first electrode, a pixel definition layer, an organic light-emitting layer and a second electrode, the pixel definition layer includes a plurality of pixel openings, the pixel openings expose the first electrode, the organic light-emitting layer is arranged in the pixel openings, one end of the organic light-emitting layer is electrically connected to the first electrode, and the other end of the organic light-emitting layer is electrically connected to the second electrode; the anode is electrically connected to the pixel driving circuit through the transfer electrode.

[0008] In an exemplary embodiment, the switching electrode is arranged in the same layer as the anode; the first part and the second part are electrically connected through the switching electrode, including: the switching electrode is electrically connected to the first part through a first via hole, the switching electrode is electrically connected to the second part through a second via hole, and the first via hole and the second via hole pass through the flat layer.

[0009] In an exemplary embodiment, the display substrate also includes an isolation column layer, which is located above the pixel definition layer, and the transfer electrode is arranged in the same layer as the isolation column layer; the first part and the second part are electrically connected through the transfer electrode, including: the transfer electrode is electrically connected to the first part through a first via hole, and the transfer electrode is electrically connected to the second part through a second via hole, and the first via hole and the second via hole pass through the pixel definition layer and the planar layer.

[0010] In an exemplary embodiment, a touch layer is further included which is arranged above the display structure layer. The touch layer includes a first wiring layer. The switching electrode is arranged in the same layer as the first wiring layer.

[0011] In an exemplary embodiment, the driving structure layer includes a first gate metal layer and a second gate metal layer arranged in sequence along a direction away from the base substrate; the transfer electrode is arranged on the same layer as any one of the first gate metal layer and the second gate metal layer, or the transfer electrode includes a stacked structure arranged on the same layer as the first gate metal layer and the second gate metal layer.

[0012] In an exemplary embodiment, the driving structure layer also includes a third gate metal layer arranged above the second gate metal layer; the transfer electrode is arranged on the same layer as any one of the first gate metal layer, the second gate metal layer and the third gate metal layer, or the transfer electrode includes a stacked structure arranged on the same layer as at least two of the first gate metal layer, the second gate metal layer and the third gate metal layer.

[0013] In an exemplary embodiment, the material of the pixel definition layer includes an inorganic material.

[0014] In an exemplary embodiment, the orthographic projection of the transfer electrode on the substrate overlaps with the orthographic projection of the at least one isolation groove on the substrate; the at least one isolation groove includes a first isolation groove and a second isolation groove, and on the plane of the substrate, the first isolation groove is located between the first blocking dam and the second blocking dam, and the second isolation groove is located between the second blocking dam and the bending area.

[0015] In an exemplary embodiment, the first isolation groove surrounds the display area, or the first isolation groove is located on a side of the display area close to the bending area; the second isolation groove surrounds the display area, or the second isolation groove is located on a side of the display area close to the bending area.

[0016] In an exemplary embodiment, an auxiliary switching electrode is further included. The auxiliary switching electrode is arranged in the same layer as the first part and the second part, and the auxiliary switching electrode is interconnected with the first part and the second part.

[0017] In an exemplary embodiment, the first part and the second part are electrically connected through the switching electrode, including: at least one of the first part and the second part is connected to the switching electrode through a via, and the switching electrode is connected to the auxiliary switching electrode through a via.

[0018] In an exemplary embodiment, the lead-out line area also includes an integrated circuit area located on a side of the bending area away from the display area; the power line includes a plurality of first power lines and a first power bus, the plurality of first power lines are located in the display area and are electrically connected to the plurality of sub-pixels, and are configured to transmit a first voltage signal to the plurality of sub-pixels; the first power bus is located in the lead-out line area and between the bending area and the display area, the first power bus extends along a first direction and is electrically connected to the plurality of first power lines; the at least one power pin includes two first power pins, and the two first power pins are located on both sides of the integrated circuit area along the first direction.

[0019] In an exemplary embodiment, the power line also includes a second power line located in the peripheral area and surrounding the display area, and the at least one power pin includes two second power pins, and the two second power pins are located on both sides of the two first power pins along the first direction.

[0020] In an exemplary embodiment, the peripheral area further includes a binding area located on a side of the lead-out area away from the display area, and the binding area includes a plurality of binding pads; the first power pin and the second power pin are connected to different binding pads.

[0021] In an exemplary embodiment, the first blocking dam includes a first dam base and a second dam base, the second blocking dam includes a third dam base and a fourth dam base, the first dam base, the third dam base and the planarizing layer are arranged on the same layer, and the second dam base, the fourth dam base and the pixel definition layer are arranged on the same layer.

[0022] On the other hand, an embodiment of the present disclosure provides a display device including the display substrate as described above.

[0023] The display substrate provided by the embodiment of the present disclosure, the power pin in the lead-out area includes a first part, a second part and a transfer electrode, and the transfer electrode is electrically connected to the first part and the second part, respectively. By arranging the first part, the second part and the transfer electrode in different layers, during the preparation process, the number of wet etching and development experienced by the first part and the second part is different from the number of wet etching and development experienced by the transfer electrode. By flexibly adjusting parameters such as the position and material of the transfer electrode, the transfer electrode will not form a "roof" structure at the edge, thereby not affecting the film morphology of the subsequent packaging layer, and avoiding GDS defects in the display substrate.

[0024] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings.

[0025] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0027] Figure 1 It is a structural schematic diagram of a display substrate;

[0028] Figure 2 It is a schematic diagram of the planar structure of a display area in a display substrate;

[0029] Figure 3 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0030] Figure 4is a schematic structural diagram of a display substrate in an exemplary embodiment;

[0031] Figure 5 In an exemplary embodiment Figure 4 A cross-sectional view of a display substrate along the BB direction;

[0032] Figure 6 is a schematic structural diagram of an edge of a first power line in an exemplary embodiment;

[0033] Figure 7 In yet another exemplary embodiment Figure 4 A cross-sectional view of a display substrate along the BB direction;

[0034] Figure 8 In yet another exemplary embodiment Figure 4 A cross-sectional view of a display substrate along the BB direction;

[0035] Fig. 9 In yet another exemplary embodiment Figure 4 A cross-sectional view of a display substrate along the BB direction;

[0036] Fig.10 In yet another exemplary embodiment Figure 4 A cross-sectional view of a display substrate along the BB direction;

[0037] Fig.11 In yet another exemplary embodiment Figure 4 A cross-sectional view of a display substrate along the BB direction;

[0038] Fig.12 FIG. 4 is a cross-sectional view of a display substrate in a display area in an exemplary embodiment. DETAILED DESCRIPTION

[0039] The present disclosure describes multiple embodiments, but the description is exemplary rather than restrictive, and it is apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0040] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in the present disclosure may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present disclosure may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0041] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be appreciated by those of ordinary skill in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.

[0042] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0043] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in this disclosure means two or more.

[0044] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the circumstances.

[0045] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0046] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0047] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0048] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0049] Figure 1 Schematic diagram of the structure of a display substrate. Figure 1As shown, the display substrate may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting element connected to the circuit unit, the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scan signal line, the data signal line and the light emitting signal line. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be constructed in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number.

[0050] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display area in a display substrate. Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting element, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting element. The light-emitting element in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting element is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0051] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.

[0052] In an exemplary embodiment, a pixel unit may include four sub-pixels. For example, the four sub-pixels may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel emitting white (W) light. For another example, the four sub-pixels may include a red sub-pixel, a blue sub-pixel, and two green sub-pixels. In an exemplary embodiment, the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a square shape, a diamond shape, etc., which is not limited in the present disclosure.

[0053] Figure 3 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Figure 3 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 6 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT and first power line VDD).

[0054] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0055] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the gate electrode of the third transistor T3 .

[0056] The gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initial voltage to the gate electrode of the third transistor T3 to initialize the charge amount of the gate electrode of the third transistor T3.

[0057] The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode.

[0058] The gate electrode of the third transistor T3 is connected to the second node N2, that is, the gate electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its gate electrode and the first electrode.

[0059] The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.

[0060] The gate electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The gate electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting element EL. The fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors. When the on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting element EL emit light.

[0061] The gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting element EL. When the on-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transmits the initial voltage to the first electrode of the light emitting element EL to initialize or release the charge accumulated in the first electrode of the light emitting element EL.

[0062] In an exemplary embodiment, the light-emitting element EL may be an OLED, including a stacked first electrode, an organic light-emitting layer, and a second electrode, or may be a QLED, including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode. In this embodiment, the first electrode may be an anode and the second electrode may be a cathode, and the present disclosure does not limit this.

[0063] In an exemplary embodiment, the second electrode of the light emitting element EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low level signal, and the signal of the first power line VDD is a continuously provided high level signal.

[0064] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0065] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS for short), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current. The low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO for short) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0066] Taking the case where all 7 transistors are P-type transistors as an example, the operation process of the pixel driving circuit may include:

[0067] The first stage A1 is called the reset stage. The signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scanning signal line S2 is a low-level signal, which turns on the first transistor T1 and the seventh transistor T7. The first transistor T1 is turned on so that the initial voltage of the initial signal line INIT is provided to the second node N2, the storage capacitor C is initialized, and the original data voltage in the storage capacitor is cleared. The seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization. The signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6. In this stage, the OLED does not emit light.

[0068] The second stage A2 is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals, and the data signal line D outputs the data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scanning signal line S1 is a low level signal, which turns on the second transistor T2 and the fourth transistor T4. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage of the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, where Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The signal of the second scanning signal line S2 is a high level signal, which turns off the first transistor T1 and the seventh transistor T7. The signal of the light emitting signal line E is a high level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0069] The third stage A3 is called the light-emitting stage. The signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light-emitting signal line E is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6. Since the voltage Vd-|Vth| is written to the second end of the storage capacitor C in the previous stage, the third transistor T3 can still remain in the on state in this stage. The power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.

[0070] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0071] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0072] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0073] A display device includes: a driving circuit layer arranged on a substrate, a light-emitting element arranged on the driving circuit layer, and an encapsulation layer arranged on the light-emitting element, wherein the encapsulation layer is used to protect the light-emitting element. Studies have shown that the encapsulation effect of the encapsulation layer has a great influence on the display performance of the display device. If the encapsulation layer fails, such as a gap or a break in the encapsulation layer, water vapor in the atmosphere will enter the light-emitting element along the gap, causing the organic material in the light-emitting element to oxidize and fail, forming a failure area that cannot emit light. As water vapor continues to invade the light-emitting element along the gap, the failure area gradually expands, causing the display device to have poor display, which is called a growing dark spot (GDS). The GDS that occurs at a fixed position on the lower frame of the display device is called a GDSX defect.

[0074] Figure 4 FIG. 1 is a schematic diagram showing the structure of a substrate in an exemplary embodiment. Figure 4 As shown, the display substrate includes: a base substrate, the base substrate includes a display area 100 and a peripheral area surrounding the display area 100. The peripheral area includes: a first peripheral area 200 located on one side of the display area 100 along the second direction Y, and a second peripheral area 300 located outside the display area 100 and away from the first peripheral area 200. The first peripheral area 200 and the second peripheral area 300 are connected to surround the display area 100. The display area 100 includes at least a plurality of sub-pixels Pxij arranged regularly, for example, the plurality of sub-pixels Pxij may be arranged in an array along a first direction X and a second direction Y, the first direction X and the second direction Y intersect, for example, the second direction Y may be perpendicular to the first direction X. The plurality of sub-pixels Pxij are configured to display dynamic pictures or still images, and the display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display panel may be deformable, for example, curled, bent, folded or rolled up. The display panel includes an upper frame and a lower frame arranged opposite to each other along the second direction Y, and a left frame and a right frame arranged opposite to each other along the first direction X, wherein the lower frame is the frame on the side where the first peripheral area 200 is located. Figure 4 The structure at the lower border is highlighted.

[0075] In an exemplary embodiment, the shape of the display area 100 may be a quadrilateral, a circle, an ellipse, a polygon of other shapes or an irregular shape, etc., and the corner shape of the display area 100 may be a rounded corner, which is not limited by the present disclosure. In an exemplary embodiment, the edge shape of the display area at different frames varies with the shape of the display area, for example, it may be a straight line, a curve, a broken line, etc., which is not limited by the present disclosure. In an exemplary embodiment, the first peripheral area 200 may include a lead-out area 210 and a binding area 230 sequentially located on one side of the display area 100 along the second direction Y, and the lead-out area 210 includes a bending area 220. The lead-out area 210 is connected to the display area 100, and may include at least a plurality of data lead-out lines Sx. Signal lines such as power lines and data lines Dx located in the display area 100 may pass through the lead-out area 210 in a fan-out routing manner and be connected to the corresponding signal providing end. Figure 4 As shown, the lead-out area 210 includes a first lead-out area 210A, a bending area 220, a second lead-out area 210B, a multiplexing circuit area 400, a third lead-out area 210C and an integrated circuit area 500 which are sequentially arranged away from the display area 100. The first lead-out area 210A is connected to the display area 100, the bending area 220 is connected to the first lead-out area 210A, the second lead-out area 210B is connected to the bending area 220, the multiplexing circuit area 400 is connected to the second lead-out area 210B, the third lead-out area 210C is connected to the multiplexing circuit area 400, and the integrated circuit area 500 is connected to the third lead-out area 210C. The bending area 220 may include a composite insulating layer provided with a groove, which is configured to bend the substrate of the side of the bending area 220 away from the display area 100 to the back of the display area 100. An integrated circuit (e.g., a driver IC, not shown) can be bound and connected to the integrated circuit area 500. The integrated circuit, multiple signal lines (e.g., data lead lines Sx) can be connected to the integrated circuit after passing through the first lead line area 210A and the second lead line area 210B. The integrated circuit can send signals to the sub-pixels Pxij of the display area 10 through the multiplexing circuit set in the multiplexing circuit area 400. The binding area 230 can include at least a plurality of bonding pads (Bonding Pad). Multiple signal lines can be connected to corresponding bonding pads 231 after passing through the first lead line area 210A, the second lead line area 210B, and the third lead line area 210C to receive corresponding electrical signals. The integrated circuit can be connected to the corresponding bonding pads 231. For example, a flexible circuit board (not shown) can be bound and connected to the display substrate through the bonding pads 231. After the binding area 230 is bent, the flexible circuit board can be bent to the back of the display area 100.

[0076] In an exemplary embodiment, the second peripheral area 300 includes at least a plurality of driving circuits, such as a gate driving circuit, and a plurality of signal transmission lines of the plurality of driving circuits may pass through the lead-out area 210 in a fan-out routing manner and be electrically connected to the pads of the corresponding integrated circuit area 500 to receive corresponding signals and drive the sub-pixels Pxij.

[0077] In an exemplary embodiment, the peripheral area of ​​the base substrate further includes a first barrier dam 410 and a second barrier dam 420, the first barrier dam 410 and the second barrier dam 420 surround the display area 100, and the second barrier dam 420 is located on a side of the first barrier dam 410 away from the display area 100. A first isolation groove F1 is provided on a side of the second barrier dam 420 close to the display area 100, and a second isolation groove F2 is provided on a side of the second barrier dam 420 away from the display area 100. Figure 4 In the example, the first isolation groove F1 and the second isolation groove F2 surround the display area 100. In other embodiments, the first isolation groove F1 and the second isolation groove F2 may be located only in the lead-out area 210. In other embodiments, only the first isolation groove F1 or the second isolation groove F2 may be provided. In an exemplary embodiment, the base substrate further includes a power line for transmitting a constant voltage signal to the plurality of sub-pixels Pxij. Figure 4 As shown, the power line may include a first power line 330 and a first power bus 310. The first power line 330 is located in the display area 100 and is electrically connected to a plurality of sub-pixels Pxij. The power line 330 is configured to transmit a first voltage signal to the plurality of sub-pixels Pxij. The first power bus 310 is located in the lead-out area 210 and is located between the bending area 220 and the display area 100. The first power bus 310 extends along a first direction X and is electrically connected to a plurality of first power lines 330. The first voltage signal may be a high voltage signal, such as a positive voltage signal. At least one first power pin 320 is also provided in the lead-out area 210. The first power pin 320 extends in a direction away from the display area 100. One end of the first power pin 320 is electrically connected to the first power bus 310, and the other end of the first power pin 320 is connected to a corresponding binding pin 231 in the binding area 230 to receive the first power signal.

[0078] like Figure 4As shown, the power line may also include a second power line 340 located in the peripheral area and surrounding the display area 100. The second power line 340 may be electrically connected to the cathodes of the plurality of sub-pixels Pxij and configured to transmit a second voltage signal to the plurality of sub-pixels Pxij. The second voltage signal may be a low voltage signal, such as a negative voltage signal. At least one second power pin 350 is also provided in the lead-out area 210. The second power pin 350 extends in a direction away from the display area 100. One end of the second power pin 350 is electrically connected to the second power line 340, and the other end of the second power pin 350 is connected to the corresponding binding pin 231 in the binding area 230 to receive the second power signal.

[0079] like Figure 4 As shown, the first power pin 320 extends to the binding area 230 after passing through the first blocking dam 410 and the second blocking dam 420. At the dotted area E, the first power pin 320 passes through the first isolation groove F1 and the second isolation groove F2. The first power pin 320 is prone to packaging failure at both ends of the first power pin 320 in the dotted area E along the first direction X. The second power pin 350 is also prone to packaging failure at the corresponding position where it passes through the first isolation groove F1 and the second isolation groove F2.

[0080] Figure 5 In an exemplary embodiment Figure 4 A cross-sectional view of a display substrate along the BB direction. Figure 5As shown, in a direction perpendicular to the display substrate, the display substrate of the display area 100 includes a base substrate 10, a driving structure layer 20 disposed on the base substrate 10, a display structure layer 30 disposed on the driving structure layer 20, and an encapsulation layer 40 disposed on the display structure layer 30. The driving structure layer 20 of the display area 100 includes a pixel driving circuit, and the display structure layer 30 includes a plurality of light-emitting elements located in the display area 100, the light-emitting elements are connected to the corresponding pixel driving circuits, the light-emitting elements are configured to emit light, and the pixel driving circuit is configured to drive the light-emitting elements. In an exemplary embodiment, the display unit includes a pixel driving circuit and a corresponding light-emitting element, and the pixel driving circuit may include a plurality of thin film transistors (TFTs) and storage capacitors, which is not limited in the present disclosure. The display structure layer 30 includes a first electrode 35, a pixel definition layer 36, an organic light emitting layer 37, and a second electrode 38. The pixel definition layer 36 includes a plurality of pixel openings, the pixel openings expose the first electrode 35, and the organic light emitting layer 37 is disposed in the pixel openings. One end of the organic light emitting layer 37 is electrically connected to the first electrode 35, and the other end of the organic light emitting layer 37 is electrically connected to the second electrode 38. In an exemplary embodiment, a first passivation layer 31, a first flat layer 32, and a transfer layer 33 are sequentially disposed on the driving structure layer 20, and vias are formed on the first passivation layer 31 and the first flat layer 32. The vias on the first passivation layer 31 and the first flat layer 32 expose the driving transistors in the pixel driving circuit, and the transfer layer 33 is electrically connected to the corresponding driving transistors through the vias. A second flat layer 34 is disposed on the transfer layer 33, and a via is formed on the second flat layer 34. The via on the second flat layer 34 exposes the transfer layer 33, and the first electrode 35 of the light-emitting element is electrically connected to the transfer layer 33 through the via on the second flat layer 34, thereby connecting to the corresponding pixel driving circuit. In an exemplary embodiment, the first electrode 35 can be an anode, which is not limited in the present disclosure. The "A and B are arranged in the same layer" mentioned in the present disclosure means that when the display panel is prepared, A and B are formed simultaneously through the same patterning process.

[0081] In an exemplary embodiment, the display substrate of the lead-out area 210 may include a base substrate 10, a driving structure layer 20 disposed on the base substrate 10, and an encapsulation layer 40 disposed on the driving structure layer 20. The first power pin 320 may be disposed on the same layer as the transfer layer 33, and the first blocking dam 410 and the second blocking dam 420 are located on the first power pin 320. The first blocking dam 410 includes a first dam base 411 and a second dam base 412, and the second blocking dam 420 includes a third dam base 421 and a fourth dam base 422. The first dam base 411 and the third dam base 421 may be disposed on the same layer as the second planar layer 34, and the second dam base 412 and the fourth dam base 422 may be disposed on the same layer as the pixel definition layer 36. Figure 5As shown, in order to form the first barrier dam 410 and the second barrier dam 420, in the process of forming the first passivation layer 31 and the first flat layer 32, the first passivation layer 31 and the first flat layer 32 in the area where the first barrier dam 410 and the second barrier dam 420 are located and in the vicinity thereof are removed. After the second flat layer 34 is formed, the first isolation groove F1 between the first barrier dam 410 and the second barrier dam 420 and the second isolation groove F2 on the side of the second barrier dam 420 away from the display area 100 will expose the edges of the first power pin 320 and the second power pin 350 in the area. After the encapsulation layer 40 is subsequently formed, the display substrate is prone to encapsulation failure in the edge weak area. For example, there is a weak area ( Figure 5 Crack)

[0082] In an exemplary embodiment, the encapsulation layer 40 may adopt a stacked structure of a first encapsulation layer 41, a second encapsulation layer 42, and a third encapsulation layer 43, wherein the first encapsulation layer 41 is made of an inorganic material, covers the display area 100, and wraps the first barrier dam 410 and the second barrier dam 420 in the lead-out area 210. The second encapsulation layer 42 is made of an organic material, covers the display area 100, and is located on the side of the first barrier dam 410 close to the display area 100. The third encapsulation layer 43 is made of an inorganic material, covering the first encapsulation layer 41 and the second encapsulation layer 42. The encapsulation layer 40 can ensure that external water vapor cannot enter the light-emitting element. In other embodiments, the encapsulation layer 40 may also adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic, which is not limited by the present disclosure.

[0083] Figure 6 FIG. 1 is a schematic diagram of the structure of the edge of the first power line in an exemplary embodiment, illustrating Figure 4 The edge of the first power pin 320 in the middle dotted line area E along the first direction X. Figure 6As shown, for the first power pin 320 using the Ti / Al / Ti multilayer composite structure, when the second flat layer 34 is subsequently developed, and in the subsequent process of etching the anode, the edge of the first power pin 320 will be eroded by the anode etching solution. Since the etching rate of the etching solution to etch Al is greater than the etching rate of Ti, a side pit will be formed at the edge of the eroded first power pin 320, and the Ti layer above the Al layer protrudes from the Al layer for a distance, forming a "roof" structure. When the pixel definition layer 36 is subsequently developed, the size of the side pit will also be deepened, and the material of the pixel definition layer 36 is likely to remain in the side pit. In the subsequent process of forming the first encapsulation layer 41 and the third encapsulation layer 43 by chemical vapor deposition (CVD), the "roof" structure blocks the vapor-deposited particles, so that the side pit cannot be filled with the encapsulation material, forming a cavity 501. Thus, when cracks 502 appear in the first encapsulation layer 41 and the third encapsulation layer 43, external water vapor can enter the cavity 501 through the crack 502, causing water vapor to flow around the edge of the first power line 310. And because the second planar layer 34 of organic material itself is water vapor conductive, the water vapor can be transferred from the cavity 501 to the second planar layer 34 until it diffuses to the display area 100, causing dark spots to appear in the display area 100 due to water and oxygen erosion. Figure 5 and Figure 6 Taking the first power pin 320 as an example, the edge of the second power pin 350 may also form an “eaves” structure, which will not be described in detail here.

[0084] The embodiment of the present disclosure provides a display substrate, including a substrate, including a display area and a peripheral area surrounding the display area, the peripheral area including a lead-out area located on one side of the display area, the lead-out area including a bending area; a plurality of sub-pixels located on one side of the substrate and located in the display area; a first blocking dam located on the substrate, located in the peripheral area and surrounding the display area; a second blocking dam located on the substrate, located in the peripheral area and surrounding the display area, the second blocking dam located on a side of the first blocking dam away from the display area; at least one isolation groove located on the second blocking dam away from or close to the display area; a power line electrically connected to the plurality of sub-pixels and configured to provide a constant voltage signal to the plurality of sub-pixels; at least one power pin located in the lead-out area and extending in a direction away from the display area and electrically connected to the power line; the at least one power pin includes a first portion located near the display area of ​​the first blocking dam, a second portion located between the second blocking dam and the bending area, and a switching electrode at least partially located between the first portion and the second portion, the first portion and the second portion are located in different layers from the switching electrode, and the first portion and the second portion are electrically connected through the switching electrode.

[0085] The display substrate provided by the embodiment of the present disclosure, the power pin in the lead-out area includes a first part, a second part and a transfer electrode, and the transfer electrode is electrically connected to the first part and the second part, respectively. By arranging the first part, the second part and the transfer electrode in different layers, during the preparation process, the number of wet etching and development experienced by the first part and the second part is different from the number of wet etching and development experienced by the transfer electrode. By flexibly adjusting parameters such as the position and material of the transfer electrode, the transfer electrode will not form a "roof" structure at the edge, thereby not affecting the film morphology of the subsequent packaging layer, and avoiding GDS defects in the display substrate.

[0086] Figure 7 In yet another exemplary embodiment Figure 4 A cross-sectional view of a display substrate along line BB. Figure 7 and Figure 5 The difference is the structure of the power cord. The rest of the structure can refer to the above Figure 5 The description will not be repeated here.

[0087] like Figure 7As shown, the first power pin 320 of the lead-out area 210 includes a first portion 81 located near the display area 100 of the first blocking dam 410, a second portion 82 located between the second blocking dam 420 and the bending area 220, and a switching electrode 91 located at least partially between the first portion 81 and the second portion 82. The first portion 81 and the second portion 82 are located in different layers from the switching electrode 91, and the first portion 81 and the second portion 82 are electrically connected through the switching electrode 91. The first portion 81 and the second portion 82 are arranged in the same layer as the switching layer 33, and the switching electrode 91 is arranged in the same layer as the first electrode 35, which is the anode of the light-emitting element. The first portion 81 is connected to the switching electrode 91 through the first via K1, and the second portion 82 is connected to the switching electrode 91 through the second via K2.

[0088] In the exemplary embodiment, the orthographic projections of the first portion 81 and the second portion 82 on the base substrate 10 are respectively located within the range of the orthographic projections of the second planar layer 34 on the base substrate 10, and the first via hole K1 and the second via hole K2 are located in the second planar layer 34. The transfer electrode 91 passes between the first dam base 411 and the second dam base 412, and the transfer electrode 91 passes between the third dam base 421 and the fourth dam base 422.

[0089] In an exemplary embodiment, the thickness of the transfer electrode 91 may be greater than or equal to 90 nanometers (nm) and less than or equal to 110 nm. For example, the thickness of the transfer electrode 91 may be about 100 nm. The thickness of the transfer electrode 91 may be the distance between the surface of the transfer electrode 91 close to the base substrate 10 and the surface of the transfer electrode 91 away from the base substrate 10 in a direction perpendicular to the base substrate 10. The thickness of the transfer electrode 91 may be set as needed, and the present disclosure is not limited thereto.

[0090] In this embodiment, the first portion 81 and the second portion 82 are covered by the second flat layer 34, and there is no routing of the power pin under the first blocking dam 410 and the second blocking dam 420, so the end face shape of the power pin will not be affected in the process of forming the second flat layer 34, the first electrode 35 and the pixel definition layer 36. The transfer electrode 91 is arranged in the same layer as the first electrode 35, and the number of wet etching and development in the subsequent process is less, so that the "eaves" structure will not be formed, and the film morphology of the subsequent encapsulation layer will not be affected, which can avoid the display substrate from having GDS defects.

[0091] Figure 8 In yet another exemplary embodiment Figure 4 A cross-sectional view of a display substrate along line BB. Figure 8 and Figure 7 The difference is that the display substrate further includes an isolation column layer 39, and the film layer where the transfer electrode 91 is located is different. The rest of the structure can refer to the above description. Figure 7 The description will not be repeated here.

[0092] like Figure 8 As shown, the display substrate also includes an isolation column layer 39 located on the side of the pixel definition layer 36 away from the base substrate 10, and the switching electrode 91 is arranged in the same layer as the isolation column layer 39. The switching electrode 91 is located on the side of the first blocking dam 410 and the second blocking dam 420 away from the base substrate 10.

[0093] In an exemplary embodiment, the material of the isolation column layer 39 may be a metal material, and the material of the pixel definition layer 36 may be an inorganic material. The pixel definition layer 36 made of an inorganic material helps to avoid crosstalk between light-emitting elements of different colors and improve the display effect.

[0094] In an exemplary embodiment, the thickness of the switching electrode 91 may be greater than or equal to 450 nm and less than or equal to 550 nm, for example, the thickness of the switching electrode 91 may be about 500 nm. The thickness of the switching electrode 91 may be set as required, and the present disclosure is not limited thereto.

[0095] In an exemplary embodiment, the light emitting element may be formed by using a photolithography OLED (AP technology) method, that is, using a spacer column to perform patterning using a photolithography process to form light emitting elements of different colors. Figure 8 As shown, taking the display substrate including red, green and blue light-emitting elements as an example, after forming the isolation column layer, the red organic light-emitting layer can be first evaporated in the pixel opening, and deposited to form a cathode and a first packaging layer to form a red light-emitting element; then, the red organic light-emitting layer, cathode and first packaging layer in the pixel openings of the green light-emitting element and the blue light-emitting element are removed by a photolithography process, the green organic light-emitting layer is evaporated, and the cathode and the first packaging layer are deposited to form a green light-emitting element; then, the green organic light-emitting layer, cathode and first packaging layer in the pixel opening of the blue light-emitting element are removed by a photolithography process, the blue organic light-emitting layer is evaporated, and the cathode and the first packaging layer are deposited to form a blue light-emitting element, and finally the second packaging layer 42 and the third packaging layer 43 are deposited to form.

[0096] In this embodiment, the first portion 81 and the second portion 82 are covered by the second flat layer 34, and there is no routing of the power pin under the first blocking dam 410 and the second blocking dam 420, so the end face shape of the power pin will not be affected in the process of forming the second flat layer 34, the first electrode 35 and the pixel definition layer 36. The transfer electrode 91 is located on the side of the pixel definition layer 36 away from the base substrate 10, and the number of wet etching and development in the subsequent process is less, so the "eaves" structure will not be formed, and the film morphology of the subsequent encapsulation layer will not be affected, which can avoid the display substrate from having GDS defects.

[0097] Fig. 9 In yet another exemplary embodiment Figure 4 A cross-sectional view of a display substrate along line BB. Fig. 9 and Figure 8 The difference is that the display substrate further includes an auxiliary switching electrode 83, and the rest of the structure can refer to the above Figure 8 The description will not be repeated here.

[0098] like Fig. 9 As shown, the auxiliary transfer electrode 83 is arranged in the same layer as the first part 81 and the second part 82, and is arranged to connect the first part 81 and the second part 82. In this embodiment, the auxiliary transfer electrode 83 is equivalent to adding a connection path between the first part 81 and the second part 82, which helps to improve the connection reliability of the power pin and reduce the voltage drop of the power line. Although the auxiliary transfer electrode 83 is located below the first blocking dam 410 and the second blocking dam 420, since the transfer electrode 91 is electrically connected to the auxiliary transfer electrode 83, the voltage drop of the power pin and the power line can be reduced while ensuring the packaging effect, thereby improving the display effect of the display substrate.

[0099] In an exemplary embodiment, the orthographic projection of the pixel definition layer 36 on the base substrate 10 covers the orthographic projection of the auxiliary transfer electrode 83 on the base substrate 10. The material of the pixel definition layer 36 may be an inorganic material. The pixel definition layer 36 of inorganic material may form a protective layer above the auxiliary transfer electrode 83 to prevent the auxiliary transfer electrode 83 from being corroded in subsequent processes. In conjunction with the transfer electrode 91, this helps to avoid subsequent effects on the film morphology of the encapsulation layer 40.

[0100] Fig.10 In yet another exemplary embodiment Figure 4 A cross-sectional view of a display substrate along line BB. Fig.10 and Fig. 9 The difference is that the display substrate further includes a touch layer, the film position of the switching electrode 91, and the connection method between the switching electrode 91 and the first part 81 and the second part 82 are different. The rest of the content can refer to the aforementioned Fig. 9 The description will not be repeated here.

[0101] like Fig.10As shown, the display substrate also includes a touch layer arranged on the side of the encapsulation layer 40 away from the base substrate 10, forming a touch structure on a thin film encapsulation (Touch on Thin Film Encapsulation, referred to as Touch on TFE) structure. By integrating the touch layer on the display panel, the display panel does not need an external touch module (TSP), has the advantages of being thin and light, foldable, etc., and can meet the product requirements of flexible folding, narrow frame, etc. In an exemplary embodiment, the touch layer may include a first wiring layer (TMA) 51, a touch interlayer insulation layer (TLD) 52, a second wiring layer (TMB) 53 and a touch protection layer (TOC) 54, and a plurality of touch electrodes and a plurality of sensing electrodes may be located in the first wiring layer 51 and the second wiring layer 53, and the present disclosure is not limited to this.

[0102] In an exemplary embodiment, the transfer electrode 91 may be disposed in the same layer as the first wiring layer 51, and the orthographic projection of the transfer electrode 91 on the base substrate 10 may at least partially overlap with the second portion 82 and the auxiliary transfer electrode 83, and the orthographic projection of the transfer electrode 91 on the base substrate 10 may not overlap with the first portion 81. The transfer electrode 91 may be connected to the second portion 82 through the second via K2, and the second via K2 may expose the surface of the second portion 82 after penetrating the encapsulation layer 40, the pixel definition layer 36, and the second planar layer 34. The transfer electrode 91 may be connected to the auxiliary transfer electrode 83 through the third via K3, and the third via K3 may expose the surface of the auxiliary transfer electrode 83 after penetrating the encapsulation layer 40 and the pixel definition layer 36. In this embodiment, the transfer electrode 91 covers the weak area on the side of the second blocking dam 420 away from the display area 100, which can effectively protect the weak area and avoid package failure.

[0103] In an exemplary embodiment, the orthographic projection of the switching electrode 91 on the base substrate 10 may also overlap with the first portion 81 , and the switching electrode 91 may be connected to the first portion 81 through a first via hole (not shown), which is not limited in the present disclosure.

[0104] In an exemplary embodiment, the thickness of the switching electrode 91 may be greater than or equal to 225 nm and less than or equal to 275 nm, for example, the thickness of the switching electrode 91 may be about 250 nm. The thickness of the switching electrode 91 may be set as required, and the present disclosure is not limited thereto.

[0105] Fig.11 In yet another exemplary embodiment Figure 4 A cross-sectional view of a display substrate along line BB. Fig.11 and Figure 7 The difference between the two is that the position of the switching electrode 91 is different, and the pixel definition layer 36 can form a protective layer on the first part 81 and the second part 82. The rest of the content can refer to the above description. Fig. 9 The description will not be repeated here.

[0106] In an exemplary embodiment, the switching electrode 91 may be located on a side of the first portion 81 and the second portion 82 close to the base substrate 10 . For example, the switching electrode 91 may be located on the driving structure layer 20 . Fig.11 In the example, each sub-pixel includes a thin film transistor and a capacitor. In some examples, the driving structure layer 20 of the display area 100 may include: a semiconductor layer, a first gate metal layer, a second gate metal layer and a first source and drain metal layer arranged on the substrate 10. A first gate insulating layer 11 may be arranged between the semiconductor layer and the first gate metal layer, a second gate insulating layer 12 may be arranged between the first gate metal layer and the second gate metal layer, and an interlayer insulating layer 13 may be arranged between the second gate metal layer and the first source and drain metal layer. The first source and drain metal layer and the transfer layer 33 are connected by vias arranged on the first passivation layer 31 and the first flat layer 32. Among them, the first gate insulating layer 11, the second gate insulating layer 12 and the interlayer insulating layer 13 may be inorganic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer may be arranged on the side of the semiconductor layer close to the substrate, and the buffer layer may prevent harmful substances in the substrate from invading the interior of the display panel, and may also increase the adhesion of the film layer in the display panel on the substrate. In other examples, a bottom shielding metal layer (BSM) may be provided on the side of the buffer layer close to the substrate, and the bottom shielding metal layer may be configured to at least partially cover the active layer of the thin film transistor of the pixel circuit to prevent external light from affecting the performance of the thin film transistor. In other examples, a second source-drain metal layer may be provided between the first source-drain metal layer and the transfer layer 33, and the transfer layer 33 is connected through the second source-drain metal layer, the first source-drain metal layer, and the transistor.

[0107] like Fig.11 As shown, the capacitor may include a first electrode plate and a second electrode plate that are arranged opposite to each other, the first electrode plate may be located in the first gate metal layer, and the second electrode plate may be located in the second gate metal layer. The transfer electrode 91 may be arranged in the same layer as any one of the first gate metal layer and the second gate metal layer, or the transfer electrode 91 may include a stacked structure arranged in the same layer as the first gate metal layer and the second gate metal layer. Usually, the materials of the first gate metal layer and the second gate metal layer are different from the materials of the source / drain metal layer and the transfer layer 33, and are not a Ti / Al / Ti multilayer composite structure. Therefore, by arranging the transfer electrode 91 in the same layer as at least any one of the first gate metal layer and the second gate metal layer, even if the transfer electrode 91 undergoes subsequent etching and development processes, no "eaves" structure will be generated at the edge, and the film morphology of the subsequent encapsulation layer will not be affected, which can avoid the display substrate from having poor GDS.

[0108] Fig.12 is a cross-sectional view of a display substrate in a display area in an exemplary embodiment. Fig.12 As shown, in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include: a base substrate 10, and a driving structure layer 20, a light emitting structure layer 30, a packaging structure layer 40 and a touch control layer 50 sequentially arranged on the substrate. Fig.12 In the figure, each sub-pixel includes a first transistor 21, a second transistor 22, and a capacitor 23. The transistor types of the first transistor 21 and the second transistor 22 may be different. The first transistor 21 may be a low-temperature polysilicon thin film transistor, and the second transistor 22 may be an oxide thin film transistor.

[0109] In some examples, the driving structure layer 20 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a transfer layer disposed on the base substrate 10 . A first gate insulating (GI) layer 101 may be provided between the first semiconductor layer and the first gate metal layer, and a second gate insulating layer 102 may be provided between the first gate metal layer and the second gate metal layer; a first interlayer insulating (ILD) layer 103 and a first buffer layer 104 may be provided between the second gate metal layer and the second semiconductor layer, and the first buffer layer 104 may be located on the side of the first interlayer insulating layer 103 away from the substrate 10; a third gate insulating layer 105 may be provided between the second semiconductor layer and the third gate metal layer; a second interlayer insulating layer 106 may be provided between the third gate metal layer and the first source-drain metal layer; a passivation (PVX) layer 31 and a first flat (PLN) layer 32 may be provided between the first source-drain metal layer and the transition layer 33, and the first flat layer 32 may be located on the side of the passivation layer 31 away from the substrate 10; a second flat layer 34 may be provided on the side of the transition layer away from the substrate 10. Among them, the first gate insulating layer 101, the second gate insulating layer 102, the first interlayer insulating layer 103, the first buffer layer 104, the third gate insulating layer 105, the transfer layer 33 and the passivation layer 31 can be inorganic insulating layers, and the first flat layer 32 and the second flat layer 34 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a second buffer layer can be provided on the side of the first semiconductor layer close to the substrate substrate, and the second buffer layer can prevent harmful substances in the substrate from invading the interior of the display substrate, and can also increase the adhesion of the film layer in the display substrate on the substrate. In other examples, a bottom light-shielding metal layer can be provided on the side of the second buffer layer close to the substrate. In other examples, the passivation layer can be omitted between the first source and drain metal layer and the transfer layer, and only the first flat layer can be provided between the first source and drain metal layer and the transfer layer. In other examples, the first buffer layer can be omitted between the second gate metal layer and the second semiconductor layer, and only the first interlayer insulating layer 103 can be provided.

[0110] In some examples, such as Fig.12As shown, the first semiconductor layer in the display area may include at least: a first active layer 2100 of the first transistor 21. The first active layer 2100 of the first transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2103 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least: a first gate electrode 213 of the first transistor 21, and a first electrode plate 2310 of the capacitor 23. The orthographic projection of the first gate electrode 213 of the first transistor 21 on the substrate 10 may cover the orthographic projection of the channel region 2103 of the first active layer 2100 on the substrate 10. The second gate metal layer may include at least: a second electrode plate 2320 of the capacitor 23, and a third gate electrode 2240 of the second transistor 22. The orthographic projections of the second electrode plate 2320 and the first electrode plate 2310 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, the two may overlap. The second semiconductor layer may include at least: a second active layer 2200 of the second transistor 22. The third gate metal layer may include at least: a second gate 2230 of the second transistor 22. The orthographic projection of the second gate 2230 of the second transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 2200 on the substrate 10. The orthographic projection of the third gate 2240 of the second transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 2200 on the substrate 10. The third gate 2240 may be the bottom gate of the second transistor 22, and the second gate 2230 may be the top gate of the second transistor 22.

[0111] In some examples, such as Fig.12As shown, the first source-drain metal layer may include at least: a first source 211 and a first drain 212 of the first transistor 21 , and a second source 2210 and a second drain 2220 of the second transistor 22 . The second interlayer insulating layer 106 may be provided with a plurality of pixel vias (for example, including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 in the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 2100; the second interlayer insulating layer 106, the third gate insulating layer 105, the first buffer layer 104, the first interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 in the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 2100. The second interlayer insulating layer 106 and the third gate insulating layer 105 in the third pixel via and the fourth pixel via may be removed to expose at least a portion of the surface of both ends of the second active layer 2200. The first source 211 of the first transistor 21 can be electrically connected to the first area 2101 of the first active layer 2100 through the first pixel via hole, and the first drain 212 can be electrically connected to the second area 2102 of the first active layer 2100 through the second pixel via hole. The second source 2210 of the second transistor 22 can be electrically connected to one end of the second active layer 2200 through the third pixel via hole, and the second drain 2220 of the second transistor 22 can be electrically connected to the other end of the second active layer 2200 through the fourth pixel via hole. The transfer layer 33 is electrically connected to the first drain 212 of the first transistor 21 of the pixel circuit through the fifth pixel via hole opened in the passivation layer 31 and the first flat layer 32. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the transfer layer 33.

[0112] In some examples, the touch layer 50 in the display area may further include a touch buffer layer (TBL) 150 disposed on a side of the first wiring layer 51 close to the base substrate 10. The touch buffer layer 150 and the touch interlayer insulating layer 53 may be inorganic insulating layers, and the protective layer 54 may be an organic insulating layer. This embodiment is not limited to this.

[0113] In some examples, the transfer electrode 91 may be disposed in the same layer as any one of the first gate metal layer, the second gate metal layer, and the third gate metal layer, or the transfer electrode 91 may include a stacked structure disposed in the same layer as at least two of the first gate metal layer, the second gate metal layer, and the third gate metal layer. This embodiment is not limited to this. In an exemplary embodiment, Figures 7 to 12 The structures of the display substrates in the embodiment can be arbitrarily combined with each other, and the present disclosure does not impose any limitation on this.

[0114] The embodiments of the present disclosure also provide a display device, including the display substrate described in any of the above embodiments. The display device can be: an OLED display, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function, and the embodiments of the present disclosure are not limited thereto.

[0115] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present disclosure. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present disclosure.

Claims

1. A display substrate, comprising: A substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a lead-out area located at one side of the display area, and the lead-out area comprises a bending area; A plurality of sub-pixels are located on one side of the base substrate and in the display area; A first blocking dam is located on the base substrate, in a peripheral area and surrounding the display area; a second blocking dam, located on the base substrate, in a peripheral area and surrounding the display area, the second blocking dam being located on a side of the first blocking dam away from the display area; at least one isolation groove located at a side of the second blocking dam away from or close to the display area; a power line electrically connected to the plurality of sub-pixels and configured to provide a constant voltage signal to the plurality of sub-pixels; At least one power pin is located in the lead-out area and extends in a direction away from the display area, and is electrically connected to the power line; the at least one power pin includes a first portion located on the first blocking dam close to the display area, a second portion located between the second blocking dam and the bending area, and a switching electrode at least partially located between the first portion and the second portion, the first portion and the second portion are located on different layers from the switching electrode, and the first portion and the second portion are electrically connected via the switching electrode.

2. The display substrate according to claim 1, characterized in that: In a direction away from the base substrate, the display substrate comprises a driving structure layer, a transfer layer, a flat layer and a display structure layer which are arranged in sequence; The driving structure layer includes a pixel driving circuit, the display structure layer includes a first electrode, a pixel definition layer, an organic light-emitting layer and a second electrode, the pixel definition layer includes a plurality of pixel openings, the pixel openings expose the first electrode, the organic light-emitting layer is arranged in the pixel openings, one end of the organic light-emitting layer is electrically connected to the first electrode, and the other end of the organic light-emitting layer is electrically connected to the second electrode; the anode is electrically connected to the pixel driving circuit through the switching electrode.

3. The display substrate according to claim 2, characterized in that: The switching electrode is arranged in the same layer as the anode; The first part and the second part are electrically connected through the switching electrode, the switching electrode is electrically connected to the first part through a first via hole, the switching electrode is electrically connected to the second part through a second via hole, and the first via hole and the second via hole penetrate the planar layer; The orthographic projection of the switching electrode on the base substrate overlaps with the orthographic projection of the first blocking dam on the base substrate, the orthographic projection of the second blocking dam on the base substrate, and the orthographic projection of the at least one isolation trench on the base substrate, and the at least one isolation trench penetrates the planar layer.

4. The display substrate according to claim 2, characterized in that: The display substrate further comprises an isolation column layer, the isolation column layer is located on a side of the pixel definition layer away from the base substrate, and the switching electrode is arranged in the same layer as the isolation column layer; The first part and the second part are electrically connected through the switching electrode, including: the switching electrode is electrically connected to the first part through a first via hole, the switching electrode is electrically connected to the second part through a second via hole, and the first via hole and the second via hole penetrate the pixel definition layer and the planar layer; The orthographic projection of the switching electrode on the base substrate overlaps with the orthographic projection of the first blocking dam on the base substrate, the orthographic projection of the second blocking dam on the base substrate, and the orthographic projection of the at least one isolation trench on the base substrate, and the at least one isolation trench penetrates the planar layer.

5. The display substrate according to claim 2, characterized in that: It also includes a touch layer arranged above the display structure layer, the touch layer includes a first wiring layer, and the switching electrode is arranged in the same layer as the first wiring layer.

6. The display substrate according to claim 2, characterized in that: The driving structure layer includes a first gate metal layer and a second gate metal layer arranged in sequence along a direction away from the base substrate; the transfer electrode is arranged on the same layer as any one of the first gate metal layer and the second gate metal layer, or the transfer electrode includes a stacked structure arranged on the same layer as the first gate metal layer and the second gate metal layer.

7. The display substrate according to claim 6, characterized in that: The driving structure layer also includes a third gate metal layer arranged above the second gate metal layer; the transfer electrode is arranged on the same layer as any one of the first gate metal layer, the second gate metal layer and the third gate metal layer, or the transfer electrode includes a stacked structure arranged on the same layer as at least two of the first gate metal layer, the second gate metal layer and the third gate metal layer.

8. The display substrate according to any one of claims 2 to 7, characterized in that: The material of the pixel definition layer includes an inorganic material.

9. The display substrate according to claim 1, characterized in that: The orthographic projection of the transfer electrode on the substrate overlaps with the orthographic projection of the at least one isolation groove on the substrate; the at least one isolation groove includes a first isolation groove and a second isolation groove, and on the plane of the substrate, the first isolation groove is located between the first blocking dam and the second blocking dam, and the second isolation groove is located between the second blocking dam and the bending area.

10. The display substrate according to claim 9, characterized in that: The first isolation groove surrounds the display area, or the first isolation groove is located on a side of the display area close to the bending area; the second isolation groove surrounds the display area, or the second isolation groove is located on a side of the display area close to the bending area.

11. The display substrate according to claim 1, characterized in that: The power pin further includes an auxiliary switching electrode, which is disposed in the same layer as the first portion and the second portion, and the auxiliary switching electrode is interconnected with the first portion and the second portion.

12. The display substrate according to claim 11, characterized in that: The first part and the second part are electrically connected through the switching electrode, including: at least one of the first part and the second part is connected to the switching electrode through a via hole, and the switching electrode is connected to the auxiliary switching electrode through a via hole.

13. The display substrate according to claim 1, characterized in that: The lead-out area further includes an integrated circuit area located on a side of the bending area away from the display area; the power line includes a plurality of first power lines and a first power bus, the plurality of first power lines are located in the display area and are electrically connected to the plurality of sub-pixels, and are configured to transmit a first voltage signal to the plurality of sub-pixels; the first power bus is located in the lead-out area and between the bending area and the display area, the first power bus extends along a first direction, and is electrically connected to the plurality of first power lines; The at least one power pin includes two first power pins, and the two first power pins are located at two sides of the integrated circuit area along the first direction.

14. The display substrate according to claim 13, characterized in that: The power line also includes a second power line located in the peripheral area and surrounding the display area. The at least one power pin includes two second power pins located on both sides of the two first power pins along the first direction.

15. The display substrate according to claim 14, characterized in that: The peripheral area further includes a binding area located on a side of the lead-out area away from the display area, and the binding area includes a plurality of binding pads; the first power pin and the second power pin are connected to different binding pads.

16. The display substrate according to claim 2, characterized in that: The first blocking dam includes a first dam base and a second dam base, the second blocking dam includes a third dam base and a fourth dam base, the first dam base, the third dam base and the planar layer are arranged in the same layer, and the second dam base, the fourth dam base and the pixel definition layer are arranged in the same layer.

17. A display device comprising the display substrate according to any one of claims 1 to 16.

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