Content rich error notification

Abstract

A data storage device includes a controller. The controller is coupled to a host device. The controller is configured to determine a quality of a Peripheral Component Interconnect Express (PCIe) link, wherein the quality of the PCIe link is greater than or less than a threshold quality and transmit an error notification to the host device via a sideband when the quality of the PCIe link is less than the threshold quality. The sideband is a different communication channel than the PCIe link. The error notification includes additional information about an event that occurs in the data storage device that causes the quality of the PCIe link.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Non-Provisional Application No. 17 / 875,741, filed on July 28, 2022, entitled “Informative Error Notice,” and the entire contents of that application are hereby incorporated by reference for all purposes. Background Art Technical Field

[0003] Embodiments of the present disclosure relate generally to data storage devices, such as solid-state drives (SSDs), and more particularly to reporting errors to a host device in a peripheral component interconnect (PCI) express (PCLe) link between the host device and the data storage device, wherein the data storage device and the host device are coupled together.

[0004] Description of Related Art

[0005] The PCIe link is the main communication link between the data storage device and the host device, wherein the data storage device and the host device are coupled together. The PCIe link is a complex serial data communication link, which may require link negotiation to establish lane width and speed. Errors caused by PCIe link negotiation and / or signal integrity may cause the host device to assume that the data storage device is not present in the computing system. These errors are catastrophic to the operation of the computing system, wherein, when the data storage device is a boot device, these errors may cause the host device to fail to boot or cause the operating system to crash. In other words, because the host device may not detect that the data storage device is present in the computing system, the required data (e.g., boot data) may not be sent from the data storage device to the host device.

[0006] In the above example, a boot failure or operating system crash may be caused by the host device's inability to initiate a transaction (e.g., a read / write command). The PCIe protocol is a command-response protocol in which the host device initiates a transaction. The host device transmits a command to the data storage device and expects a response from the data storage device, where the response is associated with the transmitted command. If no response is received or an incomprehensible response is received, the host device can retry the transaction by transmitting a command associated with the failed response. After retrying a predetermined number of transactions, the host device gives up and declares the data storage device lost.

[0007] Therefore, there is a need in the art to transmit meaningful error notifications (from a data storage device to a host device) to a host device to which the data storage device is coupled via a communication channel other than a PCIe link. Summary of the invention

[0008] The present disclosure relates generally to data storage devices, such as solid-state drives (SSDs), and more particularly to reporting errors to a host device in a peripheral component interconnect (PCI) express (PCLe) link between a host device and a data storage device, wherein the data storage device and the host device are coupled. A data storage device includes a controller. The controller is coupled to a host device. The controller is configured to determine a quality of a peripheral component interconnect express (PCIe) link, wherein the quality of the PCIe link is greater than or less than a threshold quality and transmit an error notification to the host device via a sideband when the quality of the PCIe link is less than the threshold quality. A sideband is a different communication channel than the PCIe link. The error notification includes additional information about an event that occurred in the data storage device that caused the quality of the PCIe link.

[0009] In one embodiment, a data storage device includes a controller. The controller is coupled to a host device. The controller is configured to determine the quality of a peripheral component interconnect express (PCIe) link, wherein the quality of the PCIe link is greater than or less than a threshold quality and transmit an error notification to the host device via a sideband when the quality of the PCIe link is less than the threshold quality.

[0010] In another embodiment, a data storage device includes a controller. The controller is coupled to a host device. The controller includes an error detection module and an error reporting module coupled to the error detection module. The error detection module is configured to detect transmission errors in a peripheral component interconnect express (PCIe) link between the host device and the data storage device. The error reporting module is configured to collect the detected transmission errors from the error detection module, determine the quality of the PCIe link based on the collected detected transmission errors, wherein the quality of the PCIe link is greater than or less than a threshold quality, and transmit an error notification to the host device via a sideband when the quality of the PCIe link is less than the threshold quality.

[0011] In another embodiment, a data storage device includes a device for detecting the quality of a peripheral component interconnect express (PCIe) link between the data storage device and a host device coupled to the data storage device and a device for transmitting an error notification to the host device via a sideband different from the PCIe link. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Thus, a detailed understanding of the manner in which the above-described features of the present disclosure are understood, a more particular description of the present disclosure, the above brief overview, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0013] Figure 1 is a schematic block diagram illustrating a storage system according to certain embodiments, in which a data storage device may be used as a storage device for a host device.

[0014] Figure 2 is a schematic block diagram illustrating a storage system according to certain embodiments, in which a data storage device can communicate with a host device coupled to the data storage device when a peripheral component interconnect (PCI) express (PCIe) link operates suboptimally.

[0015] Figure 3 is a flow chart illustrating a method for reporting errors to a host device when a PCIe link operates suboptimally, according to certain embodiments.

[0016] Figure 4 is a flow chart illustrating a method for reporting errors to a host device when a PCIe link operates suboptimally, according to certain embodiments.

[0017] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION

[0018] Hereinafter, reference is made to the embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. On the contrary, any combination of the following features and elements (whether or not related to different embodiments) is considered to realize and practice the present disclosure. In addition, although the embodiments of the present disclosure can achieve advantages that are superior to other possible solutions and / or superior to the prior art, whether a specific advantage is achieved by a given embodiment is not a limitation to the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative, and are not considered to be elements or limitations of the appended claims, unless explicitly stated in the claims. Similarly, reference to "the present disclosure" should not be interpreted as a summary of any inventive subject matter disclosed herein, and should not be considered to be elements or limitations of the appended claims, unless explicitly stated in the claims.

[0019] The present disclosure relates generally to data storage devices, such as solid-state drives (SSDs), and more particularly to reporting errors to a host device in a peripheral component interconnect (PCI) express (PCLe) link between a host device and a data storage device, wherein the data storage device and the host device are coupled. A data storage device includes a controller. The controller is coupled to a host device. The controller is configured to determine a quality of a peripheral component interconnect express (PCIe) link, wherein the quality of the PCIe link is greater than or less than a threshold quality and transmit an error notification to the host device via a sideband when the quality of the PCIe link is less than the threshold quality. A sideband is a different communication channel than a PCIe link. The error notification includes additional information about an event that occurred in the data storage device that caused the quality of the PCIe link.

[0020] Figure 1 1 is a schematic block diagram illustrating a storage system 100 having a data storage device 106 that can be used as a storage device for a host device 104 according to certain embodiments. For example, the host device 104 can utilize a non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes a host DRAM 138. In some examples, the storage system 100 can include multiple storage devices, such as the data storage device 106, that can operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 that are configured as a redundant array of inexpensive / independent disks (RAID) that are collectively used as a mass storage device for the host device 104.

[0021] Host device 104 may store data to and / or retrieve data from one or more storage devices, such as data storage device 106. Figure 1 As shown, host device 104 can communicate with data storage device 106 via interface 114. Host device 104 can include any of a variety of devices, including a computer server, a network attached storage (NAS) unit, a desktop computer, a notebook (i.e., laptop) computer, a tablet computer, a set-top box, a telephone handset such as a so-called "smart" phone, a so-called "smart" tablet computer, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, or other device capable of sending or receiving data from a data storage device.

[0022] Data storage device 106 includes controller 108, NVM 110, power supply 111, volatile memory 112, interface 114, and write buffer 116. In some examples, for clarity, data storage device 106 may include Figure 1. For example, the data storage device 106 may include a printed circuit board (PCB) to which the components of the data storage device 106 are mechanically attached, and the printed board includes conductive traces that electrically interconnect the components of the data storage device 106, etc. In some examples, the physical size and connector configuration of the data storage device 106 may conform to one or more standard form factors. Some exemplary standard form factors include, but are not limited to, a 3.5" data storage device (e.g., an HDD or SSD), a 2.5" data storage device, a 1.8" data storage device, a peripheral component interconnect (PCI), a PCI extension (PCI-X), a PCI Express (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe Mini Card, MiniPCI, etc.). In some examples, the data storage device 106 can be directly coupled (e.g., directly soldered or inserted into a connector) to a motherboard of the host device 104.

[0023] The interface 114 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. The interface 114 may operate according to any suitable protocol. For example, the interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, Non-Volatile Memory Express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. The interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to the controller 108, thereby providing an electrical connection between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of the interface 114 may also allow the data storage device 106 to receive power from the host device 104. For example, as Figure 1 As shown, power supply 111 may receive power from host device 104 via interface 114 .

[0024] NVM 110 may include multiple memory devices or memory cells. NVM 110 may be configured to store and / or retrieve data. For example, a memory cell of NVM 110 may receive data and a message from controller 108 indicating that the memory cell stores the data. Similarly, the memory cell may receive a message from controller 108 indicating that the memory cell retrieves data. In some examples, each of the memory cells may be referred to as a die. In some examples, NVM 110 may include multiple dies (e.g., multiple memory cells). In some examples, each memory cell may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0025] In some examples, each memory cell may include any type of non-volatile memory device, such as a flash memory device, a phase change memory (PCM) device, a resistive random access memory (ReRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (F-RAM), a holographic memory device, and any other type of non-volatile memory device.

[0026] NVM 110 may include multiple flash memory devices or memory cells. NVM flash memory devices may include NAND or NOR-based flash memory devices, and may store data based on the charge contained in the floating gate of the transistor for each flash memory cell. In NVM flash memory devices, the flash memory device may be divided into multiple dies, wherein each of the multiple dies includes multiple physical or logical blocks, which may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. The rows of NVM cells may be electrically connected using word lines to define pages in multiple pages. The corresponding cells in each of the multiple pages may be electrically connected to the corresponding bit lines. In addition, the NVM flash memory device may be a 2D or 3D device, and may be a single-level cell (SLC), a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). The controller 108 may write data to and read data from the NVM flash memory device at the page level, and erase data from the NVM flash memory device at the block level.

[0027] The power supply 111 can provide power to one or more components of the data storage device 106. When operating in standard mode, the power supply 111 can use power provided by an external device such as the host device 104 to power one or more components. For example, the power supply 111 can use power received from the host device 104 via the interface 114 to power one or more components. In some examples, the power supply 111 may include one or more power storage components that are configured to power one or more components when operating in a shutdown mode, such as when power is stopped from being received from an external device. In this way, the power supply 111 can be used as an onboard backup power supply. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, and the like. In some examples, the amount of power that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of such one or more power storage components. In other words, as the amount of power stored by one or more power storage components increases, the cost and / or size of the one or more power storage components also increases.

[0028] Volatile memory 112 may be used by controller 108 to store information. Volatile memory 112 may include one or more volatile memory devices. In some examples, controller 108 may use volatile memory 112 as a cache. For example, controller 108 may store cached information in volatile memory 112 until the cached information is written to NVM 110. Figure 1 As shown, the volatile memory 112 may consume power received from the power supply 111. Examples of the volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)).

[0029] The controller 108 can manage one or more operations of the data storage device 106. For example, the controller 108 can manage reading data from the NVM 110 and / or writing data to the NVM. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 can initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command. The controller 108 can determine at least one operating characteristic of the storage system 100 and store the at least one operating characteristic to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data associated with the write command in an internal memory or write buffer 116 before sending the data to the NVM 110.

[0030] Figure 2 2 is a schematic block diagram illustrating a storage system 200 according to some embodiments, wherein a data storage device 204 can communicate with a host device 202 coupled to the data storage device 204 when a peripheral component interconnect (PCI) express (PCIe) link 224 operates suboptimally. Aspects of the storage system 200 can be similar to Figure 1 It should be understood that the described embodiments may be applied to a computing system having a controller that provides meaningful feedback about a communication link between a host device and the controller.

[0031] The data storage device 204 includes a controller 206 and an NVM 222. The controller 206 includes a host interface module (HIM) 208, an error reporting module 212, a command scheduler 214, a data path 216, a flash interface module (FIM) 218, and one or more processors 220. The HIM 208 is coupled to the host device 202 so that the host device 202 can send data and commands to the controller 206 via a PCIe link 224 that couples the HIM 208 to the host device 202 or the controller 206 can obtain data and commands from the host device 202 via a PCIe link 224 that couples the HIM 208 to the host device 202.

[0032] HIM208 includes an error detection module 210. The error detection module 210 can be configured to detect errors in the PCIe link 224. It should be understood that the error can be an NVMe error. The error detection module 210 can collect events related to the detected errors and provide the collected events and / or the detected errors to the error reporting module 212. For example, the detected errors can include receiving one or more PCIe packets that have been previously responded to from the host device 202 through the data storage device 204, the amount of transmission noise greater than the transmission noise threshold tolerance, etc. The error inclusion module 212 can be configured to transmit an error notification or error indication to the host device 202 via a communication link 226, wherein the communication link 226 is different from the PCIe link 224. For example, the communication link 226 can be a sideband bus, wherein the sideband bus is a system management (MS) bus, a distributed antenna system (DAS) signal, a general purpose input / output (GPIO) bus, or an improved internal integrated circuit (I3C) signal. It should be understood that other sideband buses not listed may be applicable to the described embodiments.

[0033] The one or more processors 220 may generate information about the error, such as what caused the error, when the error occurred, which components the error affected, etc. The generated information may be provided to the error reporting module 212 and sent to the host device 202 when an associated error notification or error indication is sent. In some embodiments, the information produced is not sent with the error notification, but after the error notification has been sent. In addition, the error notification may include one or more of an error code associated with the quality of the PCIe link 224, an indication to recalibrate a receiver (RX) equalizer of the host device 202, an indication to reinitialize the PCIe link 224, diagnostic data associated with the PCIe link 224, an indication to drive the data storage device 204 to cycle reset, etc. In some examples, the error notification may be transmitted as a predefined pulse sequence in response to an error type previously communicated with the host device 202. It should be understood that the examples of responses and / or error codes listed previously are not intended to be limiting, but rather to provide examples of possible embodiments.

[0034] Furthermore, since the error notification is sent via the communication link 226, the error notification may be received by the host device 202 even if the PCIe link 224 is not functioning properly, so that the data storage device 204 appears to be unresponsive to the host device 202. In some examples, the host device 202 may use the NVMe-Management Interface (MI) via a Management Component Transport Protocol (MCTP) for out-of-band communication (i.e., sideband communication) (e.g., the communication link 226). Features such as Vital Product Data (VPD) and NVMe log pages may be used to transmit the state of the data storage device 204 after a successful alert from the data storage device 204 to the host device 202. Additionally, specific PCIe diagnostic data may be passed to the host device 202, which may allow diagnostic tools on the host device 202 side to be adjusted to accommodate PCIe link and protocol layer (e.g., PCIe protocol / NVMe protocol) issues.

[0035] The command scheduler 214 can be configured to schedule and process read and write commands to the NVM 222 based on the read and write commands received from the host device 202. The command scheduler 214 sends the scheduled and processed read and write commands to the FIM 218, where the FIM 218 accesses the NVM 222 to read data from the NVM 222 and write data to the NVM 222. The data path 216 can include an error correction code (ECC) engine, an encryption / decryption module, an encoder / decoder, etc. The data to be programmed to the NVM 222 is processed via the data path 216, and the data read from the NVM 222 is processed via the data path 216. For example, before the write data is programmed to the NVM 222, the write data associated with the received write command can be encrypted, encoded, and set with ECC encoding. Similarly, before the data read from the NVM 222 is provided to the host device 202, the data read from the NVM 222 is decoded, decrypted, and processed using the ECC engine.

[0036] Figure 3 is a diagram showing that according to certain embodiments, when a PCIe link (such as Figure 2 PCIe link 224) is running suboptimally to a host device (such as Figure 2 Flow chart of a method 300 for reporting an error to a host device 202). For exemplary purposes, reference may be made to Figure 2 Aspects of the storage system 200.

[0037] At box 302, power is applied to the data storage device 204. At box 304, the PCIe link between the controller 206 and the host device 202 is initialized. At box 306, the controller 206 determines whether the PCIe link initialization is successful using the error detection module 210 provided in the HIM 208. Successful PCIe link initialization may also include PCIe link errors. However, based on the number and / or type of PCIe link errors, the quality of the PCIe link may be determined and the quality of the PCIe link may be compared to a threshold PCIe link quality. If at box 306, the quality of the PCIe link is less than the threshold PCIe link quality, so that the PCIe link initialization is unsuccessful, then at box 308, the error reporting module 212 issues an alarm # signal via a sideband signal (e.g., communication link 226). At box 310, an error notification is sent to the host device 202, wherein the error notification may also include additional information about what has occurred to cause the PCIe link initialization to fail or what kind of error exists in the PCIe link. At block 312, the host device 202 may retry the PCIe link initialization using different settings (such as resetting or adjusting a receiver (RX) equalizer), restart the PCIe link initialization process, or perform other applicable corrective actions.

[0038] If at box 306, the PCIe link initialization is successful (i.e., greater than or equal to the threshold PCIe link quality), the error detection module 210 determines whether there are any PCIe link errors observed at box 314. For example, a PCIe link error may be caused by repeating the transmission of a previously completed command. If there are no PCIe link errors observed at box 314, the method 300 proceeds to 316, where the data storage device is successfully powered on. However, if there are any PCIe link errors observed at box 314, the error reporting module 212 issues an alert # signal via a sideband signal (e.g., communication link 226) at box 308. At box 310, an error notification is sent to the host device 202, wherein the error notification may also include additional information about what happened to cause the PCIe link initialization to fail or what kind of error exists in the PCIe link. At box 312, the host device 202 can retry the PCIe link initialization using different settings (such as resetting or adjusting the RX equalizer), restart the PCIe link initialization process, or perform other applicable corrective actions.

[0039] Figure 4 is a diagram showing that according to certain embodiments, when a PCIe link (such as Figure 2 PCIe link 224) is running suboptimally to a host device (such as Figure 2 Flow chart of a method 400 for reporting an error to a host device 202). For exemplary purposes, reference may be made to Figure 2 Aspects of the storage system 200.

[0040] At block 402, power is applied to the data storage device 204. At block 404, a PCIe link between the controller 206 and the host device 202 is initialized. At block 406, the controller 206 determines whether the PCIe link initialization is successful using the error detection module 210 disposed in the HIM 208. Successful PCIe link initialization may also include PCIe link errors. However, based on the number and / or type of PCIe link errors, the quality of the PCIe link may be determined and the quality of the PCIe link may be compared to a threshold PCIe link quality. If, at block 406, the quality of the PCIe link is less than the threshold PCIe link quality, such that the PCIe link initialization is unsuccessful, then at block 408, the error reporting module 212 pulses the DAS signal in a predefined sequence via a sideband signal (e.g., the communication link 226). It should be understood that the predefined sequence can be pre-provided to the host device 202 as a list of one or more predefined sequences, each of which corresponds to an error type, so that the host device 202 understands what kind of error has occurred based on the received predefined sequence. At box 410, the host device 202 can retry the PCIe link initialization using different settings (such as resetting or adjusting the RX equalizer), restart the PCIe link initialization process, or perform other applicable corrective actions. However, if at box 406, the PCIe link initialization is successful, then at box 412, the data storage device is successfully powered on.

[0041] By using a sideband channel / signal to notify a host device of an error condition when a primary communication link (e.g., a PCIe link) is inoperative or functions suboptimally, the ability to recover from errors due to degradation of the primary communication link may be improved, which may improve overall computing system quality.

[0042] In one embodiment, a data storage device includes a controller. The controller is coupled to a host device. The controller is configured to determine a quality of a peripheral component interconnect express (PCIe) link, wherein the quality of the PCIe link is greater than or less than a threshold quality and transmit an error notification to the host device via a sideband when the quality of the PCIe link is less than the threshold quality.

[0043] Determining the quality of the PCIe link includes determining whether the PCIe link initialization is successful or unsuccessful after the PCIe link has been initialized. The controller is further configured to receive a PCIe packet through the PCIe link and determine whether the quality of the PCIe link is greater than or less than a threshold quality when the PCIe link is initialized successfully. The controller is further configured to determine that the quality of the PCIe link is less than the threshold quality and to send an alarm signal to the host device via a sideband before transmitting an error notification. The sideband is a system management (MS) bus. The controller is further configured to send an alarm signal to the host device via a sideband before transmitting an error notification when the PCIe link initialization is unsuccessful. The sideband is a general input / output (GPIO) signal. The transmission error notification includes transmitting a predefined pulse sequence via a GPIO signal when the PCIe link is initialized successfully. The transmission error notification includes transmitting a device status of a data storage device. The error notification includes one or more of an error code associated with the quality of the PCIe link, an indication to recalibrate a receiver (RX) equalizer, an indication to reinitialize the PCIe link, and PCIe diagnostic data.

[0044] In another embodiment, a data storage device includes a controller. The controller is coupled to a host device. The controller includes an error detection module and an error reporting module coupled to the error detection module. The error detection module is configured to detect transmission errors in a peripheral component interconnect express (PCIe) link between the host device and the data storage device. The error reporting module is configured to collect the detected transmission errors from the error detection module, determine the quality of the PCIe link based on the collected detected transmission errors, wherein the quality of the PCIe link is greater than or less than a threshold quality, and transmit an error notification to the host device via a sideband when the quality of the PCIe link is less than the threshold quality.

[0045] The controller includes one or more processors. The one or more processors are configured to add additional information about an event that occurs in a data storage device that causes the quality of a PCIe link. The sideband is a system management (MS) bus, a distributed antenna system (DAS) signal, a general purpose input / output (GPIO) signal, or an improved internal integrated circuit (I3C) signal. When the data storage device appears to be unresponsive to the host device, an error notification can be transmitted to the host device. The detected transmission error corresponds to receiving one or more PCIe packets that have been previously responded to. The controller also includes a host interface module (HIM). The error detection module is set in the HIM. The error reporting module is outside the HIM.

[0046] In another embodiment, a data storage device includes a device for detecting the quality of a peripheral component interconnect express (PCIe) link between the data storage device and a host device coupled to the data storage device and a device for transmitting an error notification to the host device via a sideband different from the PCIe link.

[0047] The means for transmitting the error notification includes means for issuing an alarm signal and means for sending an error code corresponding to the error notification. The means for transmitting the error notification includes means for pulsing the sideband signal in a predefined sequence corresponding to the error notification.

[0048] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be envisaged without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

1. A data storage device, comprising: A controller, wherein the controller is coupled to a host device, wherein the controller is configured to: determining a quality of a peripheral component interconnect express (PCIe) link, wherein the quality of the PCIe link is greater than or less than a threshold quality; and An error notification is transmitted to the host device via a sideband when the quality of the PCIe link is less than the threshold quality. 2 . The data storage device of claim 1 , wherein determining the quality of the PCIe link comprises determining whether PCIe link initialization is successful or unsuccessful after the PCIe link has been initialized.

3. The data storage device according to claim 2, wherein the controller is further configured to: When the PCIe link is successfully initialized, receiving a PCIe packet from the host device via the PCIe link; and A determination is made as to whether the quality of the PCIe link is greater than or less than the threshold quality.

4. The data storage device according to claim 3, wherein the controller is further configured to: determining that the quality of the PCIe link is less than the threshold quality; and Prior to transmitting the error notification, an alarm signal is sent to the host device via the sideband.

5. The data storage device of claim 4, wherein the sideband is a system management (MS) bus.

6. The data storage device of claim 2, wherein the controller is further configured to, when the PCIe link initialization is unsuccessful, send an alarm signal to the host device via the sideband before transmitting the error notification.

7. The data storage device of claim 2, wherein the sideband is a general purpose input / output (GPIO) signal. 8 . The data storage device of claim 7 , wherein transmitting the error notification comprises transmitting a predefined pulse sequence to the host device via the GPIO signal when the PCIe link initialization is unsuccessful.

9. The data storage device of claim 1, wherein transmitting the error notification comprises transmitting a device status of the data storage device.

10. A data storage device according to claim 1, wherein the error notification includes one or more of an error code associated with the quality of the PCIe link, an indication to recalibrate a receiver (RX) equalizer, an indication to reinitialize the PCIe link, and PCIe diagnostic data.

11. A data storage device, comprising: A controller, wherein the controller is coupled to a host device, wherein the controller comprises: An error detection module, wherein the error detection module is configured to: detecting a transmission error in a peripheral component interconnect express (PCIe) link between the host device and the data storage device; and an error reporting module, the error reporting module being coupled to the error detection module, wherein the error reporting module is configured to: collecting detected transmission errors from the error detection module; determining a quality of the PCIe link based on the collected detected transmission errors, wherein the quality of the PCIe link is greater than or less than a threshold quality; and When the quality of the PCIe link is less than the threshold quality, an error notification is transmitted to the host device via a sideband.

12. The data storage device of claim 11, wherein the controller comprises one or more processors, and wherein the one or more processors are configured to add additional information about an event occurring in the data storage device that caused the quality of the PCIe link.

13. The data storage device of claim 11, wherein the sideband is a system management (MS) bus, a distributed antenna system (DAS) signal, a general purpose input / output (GPIO) signal, or an improved inter-integrated circuit (I3C) signal.

14. The data storage device of claim 11, wherein the error notification is capable of being transmitted to the host device when the data storage device appears to be unresponsive to the host device.

15. The data storage device of claim 11, wherein the detected transmission error corresponds to receiving one or more PCIe packets that have been previously responded to.

16. The data storage device of claim 11, wherein the controller further comprises a host interface module (HIM), and wherein the error detection module is disposed in the HIM.

17. The data storage device of claim 16, wherein the error reporting module is external to the HIM.

18. A data storage device, the data storage device comprising: means for detecting the quality of a peripheral component interconnect express (PCIe) link between the data storage device and a host device coupled to the data storage device; and Means for transmitting an error notification to the host device via a sideband distinct from the PCIe link.

19. The data storage device of claim 18, wherein the means for transmitting the error notification comprises: Device for issuing an alarm signal; and means for sending an error code corresponding to the error notification.

20. The data storage device of claim 18, wherein the means for transmitting the error notification comprises: means for pulsing the sideband signal in a predefined sequence corresponding to said error notification.

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