Array substrate and display device

Abstract

An array substrate is provided. The array substrate comprises one or more barrier walls and a plurality of signal lines which are located in the peripheral area and located on the sides, away from the substrate, of the one or more barrier walls. The perimeter region includes an inner region, an outer region, and one or more inter-barrier regions. The inner region is located between the display region and the barrier wall closest to the display region. Each inter-barrier region of the one or more inter-barrier regions is located between two adjacent barrier walls. The outer region is located on a side of the barrier wall farthest from the display region away from the display region. The plurality of signal lines includes one or more first signal lines extending in at least one of the one or more inter-barrier regions in a direction substantially parallel to the at least one barrier wall.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display devices are self-luminous devices and do not require a backlight. OLED display devices also provide brighter colors and a larger color gamut than traditional liquid crystal display (LCD) devices. In addition, OLED display devices can be more flexible, thinner, and lighter than typical LCD devices. OLED display devices generally include an anode, a cathode, and an organic layer including a light emitting layer. OLEDs can be bottom-emitting OLEDs or top-emitting OLEDs. Summary of the invention

[0003] On the one hand, the present disclosure provides an array substrate, comprising one or more barrier walls, and a plurality of signal lines located in a peripheral area and on a side of the one or more barrier walls away from a base substrate; wherein the peripheral area comprises an inner area, an outer area and one or more inter-barrier areas; the inner area is located between a display area and a barrier wall closest to the display area; each of the one or more inter-barrier areas is located between two adjacent barrier walls; the outer area is located on a side of the barrier wall farthest from the display area away from the display area; and the plurality of signal lines comprises one or more first signal lines, and the one or more first signal lines extend in a direction substantially parallel to at least one barrier wall in at least one of the one or more inter-barrier areas.

[0004] Optionally, each of the one or more first signal lines includes a first portion and a second portion connected to each other; the first portion extends in a direction substantially parallel to at least one barrier wall in at least one of the one or more barrier inter-regions; and the second portion intersects at least one barrier wall.

[0005] Optionally, a length of the first portion extending in said at least one of said one or more inter-barrier regions is at least 1.5 times a corresponding inter-barrier distance of a corresponding inter-barrier region of said one or more inter-barrier regions.

[0006] Optionally, the orthographic projection of the first portion on the substrate substantially does not overlap with the orthographic projection of any barrier wall on the substrate; and the orthographic projection of the second portion on the substrate at least partially overlaps with the orthographic projection of at least one barrier wall on the substrate.

[0007] Optionally, the plurality of signal lines further include a plurality of second signal lines, the plurality of second signal lines at least partially extending in the internal area and at least partially crossing the one or more inter-barrier areas; and a portion of each of the plurality of second signal lines located in a corresponding inter-barrier area of ​​the one or more inter-barrier areas extends in a direction that is not parallel to the one or more barrier walls.

[0008] Optionally, a total length of the portion of each of the plurality of second signal lines located in the corresponding inter-barrier region is in a range from 1.0 times to 1.5 times a corresponding inter-barrier distance of a corresponding inter-barrier region among the one or more inter-barrier regions.

[0009] Optionally, each of the plurality of second signal lines includes a third portion and a fourth portion connected to each other; the third portion extends in the inner region in a direction substantially parallel to at least one barrier wall; and the fourth portion intersects at least one barrier wall.

[0010] Optionally, the plurality of signal lines further include a plurality of third signal lines, which extend in the external area; each of the plurality of third signal lines includes a fifth portion and a sixth portion connected to each other; the fifth portion extends in a direction substantially parallel to at least one barrier wall; and the sixth portion extends in a direction not parallel to the one or more barrier walls.

[0011] Optionally, in an area in the lower frame that transitions from a side area of ​​the peripheral area to a corner area, the multiple signal lines have a stepped pattern; and each signal line includes a first line segment and a second line segment alternately connected together, the first line segment and the second line segment extend in different directions, and the second line segment extends toward the display area.

[0012] Optionally, the first line segments have a first average line width, the second line segments have a second average line width, the second average line width is greater than the first average line width; and the first line segments are spaced apart from each other by a first inter-segment distance, the second line segments are spaced apart from each other by a second inter-segment distance, the second inter-segment distance is greater than the first inter-segment distance.

[0013] Optionally, the array substrate further comprises a pixel defining layer in the display area; wherein the pixel defining layer is at least partially absent in the peripheral area; and the plurality of signal lines are spaced apart from an edge of the pixel defining layer by a distance not greater than 100 μm.

[0014] Optionally, the peripheral area includes a corner area; the corner area includes a first sub-area and a second sub-area, in which a pixel defining layer exists, and in which a layer including an organic material is removed; the array substrate includes a plurality of openings arranged in a grid pattern and extending through the pixel defining layer in the first sub-area; the first sub-area is separated from the barrier wall by the second sub-area; and the second sub-area substantially does not have the plurality of signal lines.

[0015] Optionally, the one or more barrier walls include two adjacent barrier walls; the array substrate also includes a groove separating the two adjacent barrier walls; and there are one or more signal lines in the barrier inter-wall region corresponding to the following groove: in the groove, the width of the groove located between the two adjacent barrier walls is greater than the sum of the wall widths of the two barrier walls adjacent to the groove.

[0016] Optionally, the array substrate further includes an organic material layer adjacent to the barrier wall, and a groove separating the organic material layer from the barrier wall; wherein one or more signal lines exist in an area corresponding to the following groove: in the groove, the width between the barrier wall and the organic material layer is greater than twice the wall width of the barrier wall.

[0017] Optionally, the one or more barrier walls include a first adjacent barrier wall and a second adjacent barrier wall; wherein the array substrate further includes: a corresponding groove located in an inter-barrier area between the first adjacent barrier wall and the second adjacent barrier wall; and a plurality of adjacent signal lines located in the inter-barrier area corresponding to the corresponding groove; wherein the plurality of adjacent signal lines located in the inter-barrier area corresponding to the corresponding groove are alternately located in two different layers.

[0018] Optionally, a portion of each adjacent signal line among the multiple adjacent signal lines located on a side of the adjacent barrier wall away from the corresponding groove includes a double-layer portion, the double-layer portion having a first segment located in the first conductive layer and a second segment located in the second conductive layer; and the double-layer portion is connected to a portion of the corresponding adjacent signal line located in the barrier inter-region corresponding to the corresponding groove.

[0019] Optionally, each of the multiple adjacent signal lines includes at least a first single segment located in the first conductive layer but not in the second conductive layer, and a second single segment located in the second conductive layer but not in the first conductive layer; and in the barrier inter-area corresponding to each groove, one or more first single segments and one or more second single segments respectively from the adjacent signal lines are alternately arranged.

[0020] Optionally, the total length of the first single segment and the total length of the second single segment in each of the adjacent signal lines are substantially the same; and the plurality of signal lines have substantially the same total length of the single segment.

[0021] Optionally, the first single segment and the second single segment of the same corresponding signal line are located in different areas of the peripheral area, and the different areas are respectively located on different sides of the display area.

[0022] On the other hand, the present disclosure provides a display device, which includes the array substrate described herein, and one or more integrated circuits connected to the array substrate; wherein the display device includes: a plurality of light-emitting elements, which are located on the base substrate; a packaging layer, which is located on a side of the plurality of light-emitting elements away from the base substrate; a first touch metal layer, which is located on a side of the packaging layer away from the base substrate; a touch insulating layer, which is located on a side of the first touch metal layer away from the base substrate; and a second touch metal layer, which is located on a side of the touch insulating layer away from the base substrate; wherein the plurality of signal lines are a plurality of touch signal lines located in at least one of the first touch metal layer or the second touch metal layer.

[0023] On the other hand, the present disclosure provides an array substrate, comprising a display area and a peripheral area; wherein the array substrate comprises a first organic structure, one or more barrier walls and a second organic structure arranged in sequence in the peripheral area along a direction away from the display area; wherein each of the one or more barrier walls comprises one or more organic insulating layers; wherein each barrier wall separates two adjacent grooves extending at least partially into the one or more organic insulating layers; and the two adjacent grooves are located on both sides of the corresponding barrier wall along the direction in which the first organic structure, the one or more barrier walls and the second organic structure are arranged in sequence; wherein the array substrate also comprises a plurality of signal lines located in the peripheral area and on a side of the one or more barrier walls away from the base substrate; and at least one of the plurality of signal lines extends in a direction substantially parallel to the one or more barrier walls in a region having a groove adjacent to the barrier wall.

[0024] Optionally, the one or more barrier walls include two adjacent barrier walls; the array substrate also includes a groove separating the two adjacent barrier walls; and there are one or more signal lines in the barrier inter-wall region corresponding to the following groove: in the groove, the width of the groove located between the two adjacent barrier walls is greater than the sum of the wall widths of the two barrier walls adjacent to the groove.

[0025] Optionally, the array substrate also includes an organic structure adjacent to the barrier wall, and a groove separating the organic structure from the barrier wall; wherein one or more signal lines exist in an area corresponding to the following groove: in the groove, the width between the barrier wall and the organic structure is greater than twice the wall width of the barrier wall.

[0026] Optionally, the groove is adjacent to a barrier wall or an organic structure having an inclination angle in the range of 5 degrees to 30 degrees; when the groove is located between two adjacent barrier walls, the width of the groove is less than or equal to the sum of the wall widths of the two adjacent barrier walls, or when the groove is located between a barrier wall and an organic structure, the width of the groove is less than or equal to twice the wall width of the barrier wall; and at least one of the multiple signal lines extends in a direction substantially parallel to the one or more barrier walls in a region having the groove adjacent to the barrier wall or the organic structure having an inclination angle in the range of 5 degrees to 30 degrees.

[0027] Optionally, the groove is adjacent to a barrier wall or an organic structure having a thickness in the range of 1 μm to 2 μm; when the groove is located between two adjacent barrier walls, the width of the groove is less than or equal to the sum of the wall widths of the two adjacent barrier walls, or when the groove is located between a barrier wall and an organic structure, the width of the groove is less than or equal to twice the wall width of the barrier wall; and at least one of the multiple signal lines extends in a direction substantially parallel to the one or more barrier walls in a region having the groove adjacent to the barrier wall or the organic structure having a thickness in the range of 1 μm to 2 μm.

[0028] Optionally, the groove is adjacent to a barrier wall or an organic structure having an inclination angle greater than 30 degrees or a thickness greater than 2 μm; when the groove is located between two adjacent barrier walls, the width of the groove is less than or equal to the sum of the wall widths of the two adjacent barrier walls, or when the groove is located between a barrier wall and an organic structure, the width of the groove is less than or equal to twice the wall width of the barrier wall; and none of the multiple signal lines extends in a direction substantially parallel to the one or more barrier walls in an area having the groove adjacent to the barrier wall or the organic structure having an inclination angle greater than 30 degrees or a thickness greater than 2 μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0030] Figure 1 Detailed structures in a display area of ​​a display device according to some embodiments of the present disclosure are shown.

[0031] Figure 2 Detailed structures in a display area of ​​a display device according to some embodiments of the present disclosure are shown.

[0032] Figure 3 is a schematic diagram showing the layout of certain signal lines in an array substrate according to some embodiments of the present disclosure.

[0033] Figure 4 The layout of signal lines in an array substrate according to some embodiments of the present disclosure is shown.

[0034] Figure 5A The layout of signal lines in a portion of an array substrate in some embodiments of the present disclosure is shown.

[0035] Figure 5B Show Figure 5A Layout of multiple first data lines in a portion of an array substrate depicted in FIG.

[0036] Figure 5C Show Figure 5A Layout of multiple second data lines, multiple first fan-out connection lines, and multiple second fan-out connection lines in a portion of an array substrate depicted in FIG.

[0037] Figure 5D Show Figure 5A Layout of signal lines not involved in data signal transmission in a portion of an array substrate depicted in FIG.

[0038] Figure 6 Show Figure 4 The layout of signal lines not involved in data signal transmission in the array substrate depicted in FIG.

[0039] Figure 7 is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure.

[0040] Figure 8 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0041] Fig. 9 is a schematic diagram showing a display area and a peripheral area in an array substrate according to some embodiments of the present disclosure.

[0042] Fig.10 is a schematic diagram showing the layout of signal lines in a peripheral area in a related array substrate.

[0043] Fig.11 is a schematic diagram showing the layout of signal lines in a peripheral area in a related array substrate.

[0044] Fig.12is a schematic diagram showing the layout of signal lines in a peripheral area of ​​an array substrate according to some embodiments of the present disclosure.

[0045] Fig.13A is a schematic diagram showing the layout of signal lines in a peripheral area of ​​an array substrate according to some embodiments of the present disclosure.

[0046] Fig. 13B is a schematic diagram showing the layout of first line segments and second line segments according to some embodiments of the present disclosure.

[0047] Fig. 13C is along Fig.13A Cross-sectional view along line A-A'.

[0048] Fig.14 is a schematic diagram showing the layout of signal lines in a peripheral area of ​​an array substrate according to some embodiments of the present disclosure.

[0049] Fig.15 is a cross-sectional view of a portion of an array substrate in some embodiments of the present disclosure.

[0050] Fig.16 is a cross-sectional view of a portion of an array substrate in some embodiments of the present disclosure.

[0051] Fig.17 is a cross-sectional view of a portion of an array substrate in some embodiments of the present disclosure.

[0052] Fig.18A is a schematic diagram showing the layout of signal lines in the inter-barrier region in an array substrate according to some embodiments of the present disclosure.

[0053] Fig.18B is along Fig.18A Cross-sectional view along line BB'.

[0054] Fig.19 is a schematic diagram showing the layout of signal lines in the inter-barrier region in an array substrate according to some embodiments of the present disclosure.

[0055] Fig. 20 is a schematic diagram showing the layout of signal lines in the inter-barrier region in an array substrate according to some embodiments of the present disclosure.

[0056] Fig.21 is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0057] Fig. 22 It is shown Fig.21 Schematic diagram of the layout of signal lines in the first amplification area in the array substrate depicted in FIG.

[0058] Fig.23 It is shown Fig.21 Schematic diagram of the layout of signal lines in the second amplification area in the array substrate depicted in FIG. DETAILED DESCRIPTION

[0059] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0060] Figure 1 Detailed structures in the display area of ​​the display device in some embodiments of the present disclosure are shown. Figure 1In some embodiments, the display device includes, in the display area: a substrate BS (for example, a flexible substrate); an active layer ACT of each thin film transistor in a plurality of thin film transistors TFT, which is located on the substrate BS; a gate insulating layer GI, which is located on a side of the active layer ACT away from the substrate BS; a gate G and a first capacitor electrode Ce1 (both are part of the first gate metal layer), which are located on a side of the gate insulating layer GI away from the substrate BS; an insulating layer IN, which is located on a side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 ( A portion of the second gate metal layer) is located on the side of the insulating layer IN away from the gate insulating layer GI; an interlayer dielectric layer ILD is located on the side of the second capacitor electrode Ce2 away from the gate insulating layer GI; a source S and a drain D (part of the first SD metal layer) are located on the side of the interlayer dielectric layer ILD away from the gate insulating layer GI; a planarization layer PLN is located on the side of the source S and the drain D away from the interlayer dielectric layer ILD; a pixel defining layer PDL defines a sub-pixel opening and is located on the side of the planarization layer PLN away from the base substrate BS; and a light emitting element LE is located in the sub-pixel opening. The light emitting element LE includes: an anode AD, which is located on the side of the planarization layer PLN away from the interlayer dielectric layer ILD; a light emitting layer EL, which is located on the side of the anode AD away from the planarization layer PLN; and a cathode layer CD, which is located on the side of the light emitting layer EL away from the anode AD. The display device also includes an encapsulation layer EN in the display area, which encapsulates the dummy light emitting element DLE and is located on the side of the cathode layer CD away from the base substrate BS. In some embodiments, the encapsulation layer EN includes: a first inorganic encapsulation sublayer CVD1, which is located on the side of the cathode layer CD away from the base substrate BS; an organic encapsulation sublayer IJP, which is located on the side of the first inorganic encapsulation sublayer CVD1 away from the base substrate BS; and a second inorganic encapsulation sublayer CVD2, which is located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1. The display device further includes in the display area: a buffer layer BUF, which is located on the side of the encapsulation layer EN away from the base substrate BS; a plurality of second electrode bridges BR2, which are located on the side of the buffer layer BUF away from the encapsulation layer EN; a touch insulating layer TI, which is located on the side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1, which are located on the side of the touch insulating layer TI away from the buffer layer BUF; and an overcoat layer OC, which is located on the side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI.

[0061] Figure 2 Detailed structures in the display area of ​​the display device in some embodiments of the present disclosure are shown. Figure 2In some embodiments, the display device includes in the display area: a substrate BS (for example, a flexible substrate); an active layer ACT of each thin film transistor in a plurality of thin film transistors TFT, which is located on the substrate substrate BS; a gate insulating layer GI, which is located on a side of the active layer ACT away from the substrate substrate BS; a gate G and a first capacitor electrode Ce1 (both are part of the first gate metal layer), which are located on a side of the gate insulating layer GI away from the substrate substrate BS; an insulating layer IN, which is located on a side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (a part of the second gate metal layer), which is located on a side of the insulating layer IN away from the gate insulating layer GI; an interlayer dielectric layer ILD, which is located on a side of the second capacitor electrode Ce2 away from the gate insulating layer Insulation layer GI; source S and drain D (part of the first SD metal layer), which are located on the side of the interlayer dielectric layer ILD away from the gate insulating layer GI; passivation layer PVX, which is located on the side of the source S and drain D away from the interlayer dielectric layer ILD; first planarization layer PLN1, which is located on the side of the passivation layer PVX away from the interlayer dielectric layer ILD; relay electrode RE (part of the second SD metal layer), which is located on the side of the first planarization layer PLN1 away from the passivation layer PVX; second planarization layer PLN2, which is located on the side of the relay electrode RE away from the first planarization layer PLN1; pixel defining layer PDL, which defines the sub-pixel opening and is located on the side of the second planarization layer PLN2 away from the substrate BS; and light emitting element LE, which is located in the sub-pixel opening. The light emitting element LE includes: an anode AD, which is located on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light emitting layer EL, which is located on the side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD, which is located on the side of the light emitting layer EL away from the anode AD. The display device also includes an encapsulation layer EN in the display area, which encapsulates the dummy light emitting element DLE and is located on the side of the cathode layer CD away from the base substrate BS. In some embodiments, the encapsulation layer EN includes: a first inorganic encapsulation sublayer CVD1, which is located on the side of the cathode layer CD away from the base substrate BS; an organic encapsulation sublayer IJP, which is located on the side of the first inorganic encapsulation sublayer CVD1 away from the base substrate BS; and a second inorganic encapsulation sublayer CVD2, which is located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1. The display device also includes in the display area: a buffer layer BUF, which is located on the side of the encapsulation layer EN away from the base substrate BS; a plurality of second electrode bridges BR2, which are located on the side of the buffer layer BUF away from the encapsulation layer EN; a touch insulation layer TI, which is located on the side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1, which are located on the side of the touch insulation layer TI away from the buffer layer BUF; and a covering layer OC, which is located on the side of the plurality of first touch electrodes TE1 away from the touch insulation layer TI.Optionally, the display device does not include the passivation layer PVX in the display area, for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1.

[0062] Reference Figure 1 and Figure 2 , the display device includes a semiconductor material layer SML, a first gate metal layer Gate1, a second gate metal layer Gate2, a first signal line layer SLL1 and a second signal line layer SLL2. The display device also includes: an insulating layer IN, which is located between the first gate metal layer Gate1 and the second gate metal layer Gate2; an interlayer dielectric layer ILD, which is located between the second gate metal layer Gate2 and the first signal line layer SLL1; and at least a passivation layer PVX or a planarization layer PLN, which is located between the first signal line layer SLL1 and the second signal line layer SLL2. Optionally, a plurality of second electrode bridges BR2 are located on the first touch metal layer ML1, and a plurality of first touch electrodes TE1 are located on the second touch metal layer ML2.

[0063] Figure 3 Schematic diagram showing the layout of certain signal lines in an array substrate according to some embodiments of the present disclosure. Figure 3 In some embodiments, the array substrate includes a plurality of data lines DL, a plurality of first fan-out connection lines FIPh, and a plurality of second fan-out connection lines FIPv. In some embodiments, each of the plurality of data lines DL is connected to a corresponding first fan-out connection line in the plurality of first fan-out connection lines FIPh, for example, by a first connection via cv1 extending through the second planarization layer. A corresponding second fan-out connection line in the plurality of second fan-out connection lines FIPv is connected to a corresponding first fan-out connection line in the plurality of first fan-out connection lines FIPh, for example, by a second connection via cv2 extending through the second planarization layer. Each first fan-out connection line connects the corresponding data line DL to the corresponding second fan-out connection line. The plurality of second fan-out connection lines are connected to the data driving circuit DDC. Optionally, each of the plurality of first fan-out connection lines FIPh is connected to only one data line in the plurality of data lines DL, and each of the plurality of data lines DL is connected to only one first fan-out connection line in the plurality of first fan-out connection lines FIPh. Optionally, each of the plurality of second fan-out connection lines FIPv is connected to only one first fan-out connection line among the plurality of first fan-out connection lines FIPh, and each of the plurality of first fan-out connection lines FIPh is connected to only one second fan-out connection line among the plurality of second fan-out connection lines FIPv.

[0064] Figure 4 The layout of signal lines in an array substrate according to some embodiments of the present disclosure is shown. Figure 5AFIG. 2 shows the layout of signal lines in a portion of an array substrate according to some embodiments of the present disclosure. Figure 4 and Figure 5A In some embodiments, the array substrate includes a plurality of data lines, a plurality of first fan-out connection lines FIPh, and a plurality of second fan-out connection lines FIPv.

[0065] The array substrate includes a first region R1 and a second region R2 outside the first region R1. The first region R1 includes a plurality of first column sub-pixels, and the second region R2 includes a plurality of second column sub-pixels. The plurality of first column sub-pixels are different from the plurality of second column sub-pixels. In some embodiments, the first region R1 and the second region R2 are located in the display region of the array substrate. As used herein, the term "display region" refers to the region in the array substrate of the display panel where the image is actually displayed. Optionally, the display region may include a sub-pixel region and an inter-sub-pixel region. The sub-pixel region refers to the light-emitting region of the sub-pixel, for example, the region corresponding to the pixel electrode in the liquid crystal display or the region corresponding to the light-emitting layer in the organic light-emitting diode display panel. The inter-sub-pixel region refers to the region between adjacent sub-pixel regions, for example, the region corresponding to the black matrix in the liquid crystal display or the region corresponding to the pixel defining layer in the organic light-emitting diode display panel. Optionally, the inter-sub-pixel region is the region between adjacent sub-pixel regions in the same pixel. Optionally, the inter-sub-pixel region is the region between two adjacent sub-pixel regions in two adjacent pixels.

[0066] Figure 5B Show Figure 5A Layout of multiple first data lines in a portion of an array substrate depicted in FIG. Figure 5C Show Figure 5A Layout of a plurality of second data lines, a plurality of first fan-out connection lines, and a plurality of second fan-out connection lines in a portion of an array substrate depicted in FIG. Figure 4 , FIG. 5A to FIG. 5C The plurality of data lines include a plurality of first data lines DL1 configured to provide data signals to a plurality of first column sub-pixels located in the first region R1, and a plurality of second data lines DL2 configured to provide data signals to a plurality of second column sub-pixels located in the second region R2.

[0067] In some embodiments, a plurality of first data lines DL1 are connected to a data driving circuit DDC; a plurality of second data lines DL2 are connected to the data driving circuit DDC through a plurality of first fan-out connection lines FIPh and a plurality of second fan-out connection lines FIPv. Optionally, each of the plurality of second data lines DL2 is connected to the data driving circuit DDC through a corresponding first fan-out connection line in a plurality of first fan-out connection lines FIPh and a corresponding second fan-out connection line in a plurality of second fan-out connection lines FIPv. Each of the plurality of first fan-out connection lines FIPh and a corresponding second fan-out connection line in a plurality of second fan-out connection lines FIPv are connected to each other. The plurality of first fan-out connection lines FIPh and the plurality of second fan-out connection lines FIPv are substantially (for example, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 95%, at least 98%, at least 99% or 100%) located in the display area of ​​the array substrate.

[0068] Figure 4 , Figure 5A and Figure 5C The circle marks in denoted connections between corresponding first fan-out link lines among the plurality of first fan-out link lines FIPh and corresponding second data lines among the plurality of second data lines DL2. Figure 4 , Figure 5A and Figure 5C The square marks in represent the connection between the corresponding first fan-out connection lines of the plurality of first fan-out connection lines FIPh and the corresponding second fan-out connection lines of the plurality of second fan-out connection lines FIPv. Optionally, each of the plurality of second data lines DL2 is connected to the corresponding first fan-out connection lines of the plurality of first fan-out connection lines FIPh through a via extending through the second planarization layer. Optionally, each of the plurality of second fan-out connection lines FIPv is connected to the corresponding first fan-out connection lines of the plurality of first fan-out connection lines FIPh through a via extending through the second planarization layer.

[0069] Figure 5D Show Figure 5A Layout of signal lines not involved in data signal transmission in a portion of an array substrate depicted in FIG. Figure 6 Show Figure 4 The layout of the signal lines not involved in the data signal transmission in the array substrate depicted in FIG. Figure 4 , Figure 5A , Figure 5D and Figure 6 In some embodiments, the array substrate further includes a plurality of second voltage supply lines Vssv and a plurality of third voltage supply lines Vssh. The plurality of second voltage supply lines Vssv extend in a direction substantially parallel to the second direction DR2. The plurality of third voltage supply lines Vssh extend in a direction substantially parallel to the first direction DR1.

[0070] In some embodiments, the plurality of first voltage supply lines are configured to provide a first reference voltage signal (e.g., a high reference voltage signal). The plurality of second voltage supply lines Vssv and the plurality of third voltage supply lines Vssh are configured to provide a second reference voltage signal (e.g., a low reference voltage signal). Optionally, the first reference voltage signal is a constant voltage signal, the second reference voltage signal is a constant voltage signal, and the voltage level of the first reference voltage signal is higher than the voltage level of the second reference voltage signal.

[0071] In some embodiments, a plurality of third voltage supply lines Vssh and a plurality of first fan-out connection lines FIPh are located in the same layer; and a plurality of second voltage supply lines Vssv and a plurality of second fan-out connection lines FIPv are located in the same layer. Optionally, a plurality of third voltage supply lines Vssh and a plurality of first fan-out connection lines FIPh are located in the second signal line layer. Optionally, a plurality of second voltage supply lines Vssv and a plurality of second fan-out connection lines FIPv are located in the third signal line layer.

[0072] In some embodiments, the plurality of second voltage supply lines Vssv and the plurality of third voltage supply lines Vssh form an interconnected voltage supply network. In some embodiments, each of the plurality of second voltage supply lines Vssv is connected to one or more third voltage supply lines Vssh through one or more vias (e.g., one or more vias extending through the second planarization layer PLN2). Figure 4 and Figure 6 The triangle marks in denoted connections between corresponding second voltage supply lines among the plurality of second voltage supply lines Vssv and corresponding third voltage supply lines among the plurality of third voltage supply lines Vssh.

[0073] In some embodiments, the array substrate includes a first partition Z1 and a second partition Z2 outside the first partition Z1. The first partition Z1 includes a plurality of first sub-pixel rows, and the second partition Z2 includes a plurality of second sub-pixel rows. The plurality of first sub-pixel rows are different from the plurality of second sub-pixel rows. In some embodiments, the first partition Z1 and the second partition Z2 are located in the display area of ​​the array substrate.

[0074] In some embodiments, the connections (circle marks) between the plurality of first fan-out connection lines FIPh and the plurality of second data lines DL2 and the connections (square marks) between the plurality of first fan-out connection lines FIPh and the plurality of second fan-out connection lines FIPv are located in the first zone Z1. In some embodiments, the connections (triangle marks) between the plurality of second voltage supply lines Vssv and the plurality of third voltage supply lines Vssh are located in the second zone Z2.

[0075] In some embodiments, the connections (circle marks) between the plurality of first fan-out connection lines FIPh and the plurality of second data lines DL2 located in the first partition Z1 and the connections (square marks) between the plurality of first fan-out connection lines FIPh and the plurality of second fan-out connection lines FIPv constitute a first group of connections. In some embodiments, the connections between the plurality of second voltage supply lines Vssv and the plurality of third voltage supply lines Vssh located in the second partition Z2 include one or more second groups of connections between the plurality of second voltage supply lines Vssv and the plurality of third voltage supply lines Vssh. In some embodiments, each of the one or more second groups of connections located in the second partition Z2 has the same pattern as the first group of connections located in the first partition Z1. In some embodiments, the first group of connections and the one or more second groups of connections are substantially uniformly distributed in the array substrate, for example, along the second direction DR2.

[0076] The inventors of the present disclosure have discovered that enhanced display uniformity can be achieved by having one or more second sets of connections have the same pattern as the first set of connections and by having the first set of connections and the one or more second sets of connections substantially uniformly distributed in the array substrate.

[0077] In some embodiments, an interconnected voltage supply network including a plurality of second voltage supply lines Vssv and a plurality of third voltage supply lines Vssh is electrically connected to the peripheral voltage supply line to receive a second reference voltage signal. Optionally, the interconnected voltage supply network is electrically connected to the cathode of the light emitting element in the array substrate and serves as an auxiliary cathode.

[0078] In the field of AMOLED smartphones, a prominent trend in recent developments is the pursuit of narrow borders, especially achieving border sizes of 1.0 mm or less on the left, right and top edges of the screen. However, it is still relatively difficult to reduce the size of the lower border, thereby limiting the screen-to-body ratio. To solve this problem, a new design method called "fanout connecting lines in display area" has emerged, which significantly reduces the size of the lower border. Figures 3 to 6 The fan-out connection lines depicted in exemplify the fan-out connection line technique in the display area.

[0079] In the related array substrate, the fan-out line is only arranged in the lower frame, and the fan-out line and the touch signal line in the lower frame occupy a large amount of space. The inventor of the present disclosure found that by making the fan-out connection line at least partially located in the display area, the frame size of the array substrate can be significantly reduced.

[0080] Figure 7 is a schematic diagram showing the structure of a portion of an array substrate in some embodiments of the present disclosure. Figure 8 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 7 and Figure 8 In some embodiments, the array substrate has a display area DA and a peripheral area PA. In some embodiments, the array substrate includes: a base substrate BS; a plurality of light emitting elements LE, which are located on the base substrate BS and in the display area DA; an encapsulation layer EN, which is located on a side of the plurality of light emitting elements LE away from the base substrate BS to encapsulate the plurality of light emitting elements LE; an insulating layer IN, which is located on the base substrate BS; a first barrier wall BW1, which is located in the peripheral area PA and on a side of the insulating layer IN away from the base substrate BS, the first barrier wall BW1 forming a first enclosure substantially surrounding the first area EA1; and a second barrier wall BW2, which is located in the peripheral area PA and on a side of the insulating layer IN away from the base substrate BS. The second barrier wall BW2 forms a second enclosure substantially surrounding the second area EA2. Optionally, the second area EA2 surrounds the first area EA1.

[0081] As used herein, the term "peripheral region" refers to a region of an array substrate in a display panel where various circuits and wires are disposed to transmit signals to the display substrate. In order to increase the transparency of the display device, opaque or light-proof components of the display device (e.g., a battery, a printed circuit board, a metal frame) may be arranged in the peripheral region rather than in the display region.

[0082] In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer SUB1, an organic encapsulation sublayer SUB2, and a second inorganic encapsulation sublayer SUB3. In some embodiments, at least one inorganic sublayer of the encapsulation layer EN extends from the display area DA to the peripheral area PA. In one example, the first inorganic encapsulation sublayer SUB1 and the second inorganic encapsulation sublayer SUB3 extend from the display area DA to the peripheral area PA. Optionally, the first inorganic encapsulation sublayer SUB1, the organic encapsulation sublayer SUB2, and the second inorganic encapsulation sublayer SUB3 all extend from the display area DA to the peripheral area PA. Optionally, at least one inorganic sublayer of the encapsulation layer EN is located on the side of the organic encapsulation sublayer SUB2 away from the base substrate BS. Optionally, at least one inorganic sublayer of the encapsulation layer EN is located on the side of the first barrier wall BW1 away from the base substrate BS.

[0083] Each of the plurality of light emitting elements LE includes an anode AD, a light emitting layer EL on the anode AD, an organic material layer OL on a side of the light emitting layer EL away from the substrate BS, and a cathode layer CD on a side of the organic material layer OL away from the substrate BS. Optionally, the organic material layer OL and the cathode layer CD may be formed in an open mask process.

[0084] In some embodiments, the array substrate further comprises a planarization layer PLN located on a side of the plurality of thin film transistors away from the base substrate BS. The anode AD is electrically connected to the drain D of a corresponding one of the plurality of thin film transistors through a via extending through the planarization layer PLN.

[0085] In some embodiments, the array substrate further includes a pixel defining layer PDL located on a side of the planarization layer PLN away from the base substrate BS. The pixel defining layer PDL defines a plurality of sub-pixel openings for accommodating the light emitting layer EL.

[0086] Various suitable materials can be used to manufacture the first barrier wall BW1 and the second barrier wall BW2. In one example, the first barrier wall BW1 and the second barrier wall BW2 are made of an organic material. In another example, the first barrier wall BW1 and the second barrier wall BW2 are made of the same organic material as the organic encapsulation sublayer SUB2 of the encapsulation layer EN. In another example, the first barrier wall BW1, the second barrier wall BW2, and the organic encapsulation sublayer SUB2 are located in the same layer. As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the first barrier wall BW1 and the organic encapsulation sublayer SUB2 are formed due to one or more steps of the same patterning process performed in the material deposited in the same deposition process, the first barrier wall BW1 and the organic encapsulation sublayer SUB2 are located in the same layer. In another example, by simultaneously performing the steps of forming the first barrier wall BW1 and the steps of forming the organic encapsulation sublayer SUB2, the first barrier wall BW1 and the organic encapsulation sublayer SUB2 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in a cross-sectional view is the same.

[0087] Fig. 9 Schematic diagram showing a display area and a peripheral area in an array substrate according to some embodiments of the present disclosure. Fig. 9 In some embodiments, the peripheral area PA includes a first sub-area PA1 located at the first side S1 of the display area DA, a second sub-area PA2 located at the second side S2 of the display area DA, a third sub-area PA3 located at the third side S3 of the display area DA, and a fourth sub-area PA4 located at the fourth side S4 of the display area DA. Optionally, the first side S1 and the fourth side S4 are opposite to each other. Optionally, the second side S2 and the third side S3 are opposite to each other. Optionally, the first sub-area PA1 is a sub-area where a plurality of signal lines are connected to an integrated circuit (e.g., an integrated touch circuit).

[0088] In some embodiments, the first sub-region PA1 includes a side region SR and one or more corner regions (e.g., a first corner region CR1 and a second corner region CR2). The one or more corner regions are respectively located at the corners of the array substrate. The one or more corner regions respectively connect the side region SR to one or more adjacent sub-regions of the peripheral region PA. For example, the first corner region CR1 connects the side region SR to the second sub-region PA2, and the second corner region CR2 connects the side region SR to the third sub-region PA3.

[0089] Fig.10 is a schematic diagram showing the layout of signal lines in the peripheral area of ​​a related array substrate. Fig.10 , the relevant array substrate includes a plurality of signal lines SL (eg, a plurality of touch signal lines) located in a peripheral area PA of the relevant array substrate. Fig.10 Can depict Fig. 9 Layout of multiple signal lines SL in the side region SR (located in the lower frame region) depicted in FIG.

[0090] In the relevant array substrate, the plurality of signal lines SL at least partially cross the barrier walls (including the first barrier wall BW1 and the second barrier wall BW2). In the relevant array substrate, the fan-out lines are usually arranged in the same area. However, in the array substrate having the fan-out connection lines in the display area DA, Fig.10 The signal line layout depicted in FIG. 1 is not suitable because in the array substrate with fan-out connection lines in the display area DA, the lower frame area is significantly reduced, and thus there is not enough space for the plurality of signal lines SL.

[0091] Fig.11 is a schematic diagram showing the layout of signal lines in a peripheral area in a related array substrate. Fig.11 A plurality of signal lines SL may be depicted in Fig. 9 The layout of the corner area (e.g., the first corner area CR1) depicted in FIG. In this area, the layout of the plurality of signal lines SL is used to ensure the integrity of the signal lines. The plurality of signal lines SL are arranged as close as possible to the barrier wall (e.g., the first barrier wall BW1). Fig.11 As shown, in this area, a plurality of signal lines SL are located between the first barrier rib BW1 and the display area DA, wherein the first barrier rib BW1 is the barrier rib closest to the display area DA. For example, the first barrier rib BW1 separates the display area DA from all other barrier ribs (including the second barrier rib BW2).

[0092] In some embodiments, the corner region includes a first sub-region RA, in which a pixel defining layer exists, and the array substrate includes a plurality of openings AP extending through the pixel defining layer in the first sub-region RA. The plurality of openings AP are arranged in a grid pattern. In some embodiments, the corner region also includes a second sub-region RB, in which a layer including an organic material (e.g., a polymer material) is removed. For example, in the second sub-region RB, the planarization layer and the pixel defining layer are completely removed.

[0093] Reference Fig.11 , the first sub-region RA is separated from the barrier wall by the second sub-region RB, so the first sub-region RA is farther from the barrier wall. Although the grid pattern of the pixel defining layer exists in the first sub-region RA, the organic encapsulation sublayer of the encapsulation layer can flatten the first sub-region RA. Therefore, a plurality of signal lines can be disposed in the first sub-region RA.

[0094] The second sub-region RB is closer to the barrier wall. In one example, the second sub-region RB substantially does not have a plurality of signal lines SL. For example, a plurality of signal lines SL other than a ground line are disposed in the first sub-region RA, and the ground line is disposed in the second sub-region RB. In one example, the signal line in the first sub-region RA extends in a direction substantially parallel to a boundary between the first sub-region RA and the second sub-region RB.

[0095] In the related array substrate, one or more inter-barrier regions IBR have substantially no signal lines. Fig.11 In the corner regions depicted in FIG, one or more inter-barrier regions IBR do not have any signal lines at all. Fig.10 In the side regions depicted in FIG. 1 , one or more signal lines partially or completely cross one or more barrier ribs. However, no signal line extends at least partially in the inter-barrier region in a direction substantially parallel to one or more barrier ribs.

[0096] As described above, the fan-out connection line technology in the display area greatly reduces the size of the lower frame (e.g., including the side area and the corner area). The layout of the signal line (e.g., the touch signal line) in the related array substrate is no longer applicable to the array substrate using the fan-out connection line technology in the display area. The inventors of the present disclosure have discovered a novel and unique structure of an array substrate that effectively arranges the signal line in a more limited space with a more sophisticated layout in the narrow frame area.

[0097] Therefore, the present disclosure provides, in particular, an array substrate and a display device, which substantially eliminate one or more problems caused by the limitations and disadvantages of the prior art. On the one hand, the present disclosure provides an array substrate. In some embodiments, the array substrate includes one or more barrier walls and a plurality of signal lines located in a peripheral area. Optionally, the peripheral area includes an inner area, an outer area, and one or more barrier inter-areas. Optionally, the inner area is located between the display area and the barrier wall closest to the display area. Optionally, each barrier inter-area in the one or more barrier inter-areas is located between two adjacent barrier walls. Optionally, the outer area is located on the side of the barrier wall farthest from the display area away from the display area. Optionally, the plurality of signal lines include one or more first signal lines, which extend in a direction substantially parallel to at least one barrier wall in at least one of the one or more barrier inter-areas.

[0098] Fig.12 is a schematic diagram showing the layout of signal lines in a peripheral area of ​​an array substrate according to some embodiments of the present disclosure. Fig.12 A plurality of signal lines SL may be depicted in Fig. 9 The layout of the side region SR (located in the lower frame area) depicted in FIG. Fig.12 In some embodiments, the array substrate includes one or more barrier walls (e.g., a first barrier wall BW1, a second barrier wall BW2, and a third barrier wall BW3). In some embodiments, the peripheral region of the array substrate includes an inner region IR, an outer region OR, and one or more inter-barrier regions IBR. The inner region IR is located between the display area DA and the barrier wall (e.g., the first barrier wall BW1) closest to the display area DA. Each of the one or more inter-barrier regions IBR may be connected to the display area DA. Figure 8 The outer region OR is located on the side of the barrier wall farthest from the display area DA away from the display area DA. In one example, the outer region OR is located between the barrier wall farthest from the display area DA and the integrated circuit connected to the signal line in the peripheral area.

[0099] In some embodiments, the array substrate includes one or more first signal lines SL1, multiple second signal lines SL2, and multiple third signal lines SL3 in the peripheral area. In some embodiments, the one or more first signal lines SL1, multiple second signal lines SL2, and multiple third signal lines SL3 include touch signal lines connected to the touch integrated circuit.

[0100] In some embodiments, one or more first signal lines SL1 extend in a direction substantially parallel to at least one barrier wall in at least one of the one or more inter-barrier regions IBR. In some embodiments, each of the one or more first signal lines SL1 includes a first portion and a second portion connected to each other. The first portion extends in a direction substantially parallel to at least one barrier wall in at least one of the one or more inter-barrier regions IBR. Fig.12 In one example depicted in FIG, the first portion extends within the barrier inter-barrier region between the first barrier rib BW1 and the second barrier rib BW2. The first portion extends in a direction substantially parallel to the first barrier rib BW1, the second barrier rib BW2, and the third barrier rib BW3. The second portion intersects at least one barrier rib. In one example, the second portion intersects the second barrier rib BW2 and the third barrier rib BW3. As used herein, the term "substantially parallel" refers to an angle in the range of 0 degrees to about 45 degrees, such as 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, 0 degrees to about 30 degrees.

[0101] In some embodiments, the length L1 of the first portion extending in at least one of the one or more inter-barrier regions IBR is at least 1.5 times (e.g., at least 2.0 times, at least 2.5 times, at least 3.0 times, at least 3.5 times, at least 4.0 times, at least 4.5 times, at least 5.0 times, at least 5.5 times, at least 6.0 times, at least 6.5 times, at least 7.0 times, at least 7.5 times, at least 8.0 times, at least 8.5 times, at least 9.0 times, at least 9.5 times, at least 10.0 times) of the corresponding inter-barrier distance ibd of the corresponding inter-barrier region in the one or more inter-barrier regions IBR. As used herein, the term "inter-barrier distance" refers to the shortest distance between two adjacent barrier walls. In one example, the inter-barrier distance is the distance along the second direction DR2. In one example, the first direction DR1 and the second direction DR2 intersect each other. In another example, the second direction DR2 is the direction from the display area DA to the peripheral area. In another example, the first direction DR1 is substantially parallel to a boundary between the display area DA and the peripheral area.

[0102] In some embodiments, the orthographic projection of the first portion on the substrate substrate does not substantially overlap with the orthographic projection of any barrier wall on the substrate substrate (e.g., does not overlap with at least 80% of the orthographic projection of any barrier wall on the substrate substrate, does not overlap with at least 85% of the orthographic projection of any barrier wall on the substrate substrate, does not overlap with at least 90% of the orthographic projection of any barrier wall on the substrate substrate, does not overlap with at least 95% of the orthographic projection of any barrier wall on the substrate substrate, does not overlap with at least 98% of the orthographic projection of any barrier wall on the substrate substrate, does not overlap with at least 99% of the orthographic projection of any barrier wall on the substrate substrate, or does not overlap with the orthographic projection of any barrier wall on the substrate substrate at all). In some embodiments, the orthographic projection of the second portion on the substrate substrate at least partially overlaps with the orthographic projection of at least one barrier wall on the substrate substrate.

[0103] In some embodiments, the one or more first signal lines SL1 do not exist in the inner region IR.

[0104] In some embodiments, the plurality of second signal lines SL2 extend at least partially in the inner region IR and at least partially cross the one or more inter-barrier regions IBR. Optionally, the plurality of second signal lines SL2 at least partially cross the outer region OR. In some embodiments, the total length L2 of the portion of each of the plurality of second signal lines SL2 located in the corresponding inter-barrier region of the one or more inter-barrier regions IBR is in the range of 1.0 to 1.5 times (e.g., 1.0 to 1.1 times, 1.1 to 1.2 times, 1.2 to 1.3 times, 1.3 to 1.4 times, or 1.4 to 1.5 times) of the corresponding inter-barrier distance ibd of the corresponding inter-barrier region of the one or more inter-barrier regions IBR.

[0105] In some embodiments, a portion of each of the plurality of second signal lines SL2 located in a corresponding barrier inter-region in one or more barrier inter-regions IBR extends in a direction that is not parallel to the one or more barrier walls. Optionally, a portion of each of the plurality of second signal lines SL2 located in a corresponding barrier inter-region in one or more barrier inter-regions IBR extends in the second direction DR2.

[0106] In some embodiments, each of the plurality of second signal lines SL2 includes a third portion and a fourth portion connected to each other. The third portion extends in a direction substantially parallel to at least one barrier rib in the inner region IR. Fig.12In one example depicted in FIG, the third portion extends in a direction substantially parallel to the first barrier rib BW1, the second barrier rib BW2, and the third barrier rib BW3. The fourth portion intersects at least one barrier rib. In one example, the fourth portion intersects the first barrier rib BW1, the second barrier rib BW2, and the third barrier rib BW3.

[0107] In some embodiments, the orthographic projection of the third portion on the substrate substrate does not substantially overlap with the orthographic projection of any barrier wall on the substrate substrate (e.g., at least 80% does not overlap with the orthographic projection of any barrier wall on the substrate substrate, at least 85% does not overlap with the orthographic projection of any barrier wall on the substrate substrate, at least 95% does not overlap with at least 90% of the orthographic projection of any barrier wall on the substrate substrate, at least 98% does not overlap with the orthographic projection of any barrier wall on the substrate substrate, at least 99% does not overlap with the orthographic projection of any barrier wall on the substrate substrate, or does not overlap at all with the orthographic projection of any barrier wall on the substrate substrate). In some embodiments, the orthographic projection of the fourth portion on the substrate substrate at least partially overlaps with the orthographic projection of at least one barrier wall on the substrate substrate.

[0108] In some embodiments, each of the plurality of third signal lines SL3 includes a fifth portion and a sixth portion connected to each other. The fifth portion and the sixth portion extend in the outer region OR. The fifth portion extends in a direction substantially parallel to at least one barrier rib. Fig.12 In one example depicted in FIG. 5 , the fifth portion extends in a direction substantially parallel to the first barrier rib BW1 , the second barrier rib BW2 , and the third barrier rib BW3 . The sixth portion extends in a direction substantially parallel to the second direction DR2 .

[0109] Fig.13A is a schematic diagram showing the layout of signal lines in a peripheral area of ​​an array substrate according to some embodiments of the present disclosure. Fig.13A Can be depicted from Fig. 9 Layout of multiple signal lines from the side area SR depicted in the figure to the corner area (e.g., the first corner area CR1). In order to be consistent with the shape of the edge of the display area DA in this area, the multiple signal lines SL have a stepped pattern. As used herein, the term "stepped pattern" means that each signal line includes a first line segment FLS1 and a second line segment FLS2 alternately connected together, the first line segment FLS1 and the second line segment FLS2 extend in different directions, and the second line segment FLS2 extends toward the display area DA. Optionally, the first line segment FLS1 extends in a direction substantially parallel to the first direction DR1. The inventors of the present disclosure have found that by having a stepped pattern, an array substrate using a fan-out connection line technology in the display area can fully adapt to the layout of the signal lines in the lower frame.

[0110] In one example, the second line segment FLS2 extends in a consistent direction toward the display area DA.

[0111] In an alternative example, the second line segment FLS2 extends toward the display area DA in at least two different directions, but all extend toward the display area DA. For example, one or more second line segments extend along the second direction DR2, and another one or more second line segments extend in a direction at an angle of 15 degrees relative to the second direction DR2.

[0112] In some embodiments, the stair-shaped pattern includes at least three steps. In one example, each of the plurality of signal lines SL includes at least three second line segments.

[0113] Fig. 13B is a schematic diagram showing the layout of the first line segment and the second line segment according to some embodiments of the present disclosure. Fig. 13B In some embodiments, the first line segment FLS1 has a first average line width alw1, and the second line segment FLS2 has a second average line width alw2. The second average line width alw2 is greater than the first average line width alw1. Optionally, the first average line width alw1 is in a range of 1 μm to 5 μm (e.g., 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, or 4 μm to 5 μm), and the second average line width alw2 is in a range of 5 μm to 25 μm (e.g., 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, or 20 μm to 25 μm). In one example, the first average line width alw1 is about 3.2 μm, and the second average line width alw2 is about 14 μm.

[0114] In some embodiments, the first line segments FLS1 are spaced apart from each other by a first inter-segment distance isd1, and the second line segments FLS2 are spaced apart from each other by a second inter-segment distance isd2. The second inter-segment distance isd2 is greater than the first inter-segment distance isd1. Optionally, the first inter-segment distance isd1 is in a range of 2 μm to 6 μm (e.g., 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, or 5 μm to 6 μm), and the second inter-segment distance isd2 is in a range of 10 μm to 26 μm (e.g., 10 μm to 15 μm, 15 μm to 20 μm, or 20 μm to 26 μm). In one example, the first inter-segment distance isd1 is about 4 μm, and the second inter-segment distance isd2 is about 18 μm.

[0115] In some embodiments, the array substrate includes a pixel defining layer located in the display area DA, and the pixel defining layer is at least partially absent from the peripheral area. In some embodiments, the plurality of signal lines SL are spaced apart from the edge of the pixel defining layer by a distance of no more than 100 μm, for example, no more than 90 μm, no more than 80 μm, no more than 70 μm, no more than 60 μm, no more than 50 μm, no more than 40 μm, no more than 30 μm, or no more than 20 μm. In one example, referring to Fig.13A , the plurality of signal lines SL are spaced apart from the edge EG of the pixel defining layer by a distance of 20 μm.

[0116] Fig. 13C is along Fig.13A A cross-sectional view of the line A-A' in FIG. Fig. 13C In some embodiments, the array substrate includes: a base substrate BS; a first barrier wall BW1, a second barrier wall BW2, and a third barrier wall BW3, which are located on the base substrate BS; at least one sublayer of the encapsulation layer EN, which is located on the side of the first barrier wall BW1, the second barrier wall BW2, and the third barrier wall BW3 away from the base substrate BS; and one or more first signal lines SL1, multiple second signal lines SL2, and multiple third signal lines SL3, which are located on the side of the encapsulation layer EN away from the base substrate BS. Optionally, a first adjacent signal line among the one or more first signal lines includes in the barrier inter-region IBR: a first single segment, which is located in the first conductive layer CL1 but not in the second conductive layer CL2; and a second single segment, which is located in the second conductive layer CL2 but not in the first conductive layer CL1. Optionally, the array substrate includes a first inorganic encapsulation sublayer and a second inorganic encapsulation sublayer (for example, Figure 1 or Figure 2 CVD1 and CVD2 are indicated in the figure, which are located on the side of the first barrier wall BW1, the second barrier wall BW2 and the third barrier wall BW3 away from the substrate BS. Optionally, the first inorganic encapsulation sublayer and the second inorganic encapsulation sublayer are consistent with the shape of each barrier wall. For example, the inclination angle of each barrier wall is substantially the same as or similar to the inclination angle of the first inorganic encapsulation sublayer and the inclination angle of the second inorganic encapsulation sublayer on the corresponding barrier wall.

[0117] In some embodiments, each of the plurality of second signal lines SL2 includes two segments respectively located in the first conductive layer CL1 and the second conductive layer CL2. Optionally, each of the plurality of third signal lines SL3 includes two segments respectively located in the first conductive layer CL1 and the second conductive layer CL2. In one example, the first conductive layer CL1 is Figure 1 or Figure 2 In another example, the second conductive layer CL2 is Figure 1 or Figure 2The second touch metal layer ML2 is depicted in FIG.

[0118] Fig.14 is a schematic diagram showing the layout of signal lines in a peripheral area of ​​an array substrate according to some embodiments of the present disclosure. Fig.14 The layout of the signal lines in the first region R1 and the second region R2 is shown. Fig.12 The area depicted in corresponds to, for example, Fig. 9 The side region SR depicted in FIG. 1 transitions to the corner region (e.g., the first corner region CR1). The second region R2 and Fig. 9 Corresponding to the corner area (e.g., the first corner area CR1) depicted in .

[0119] In some embodiments, the corner region includes a first sub-region RA, in which a pixel defining layer exists, and the array substrate includes a plurality of openings AP extending through the pixel defining layer in the first sub-region RA. The plurality of openings AP are arranged in a grid pattern. In some embodiments, the corner region also includes a second sub-region RB, in which a layer including an organic material (e.g., a polymer material) is removed. For example, in the second sub-region RB, the planarization layer and the pixel defining layer are completely removed.

[0120] Reference Fig.14 , the first sub-region RA is separated from the barrier wall by the second sub-region RB, so the first sub-region RA is farther from the barrier wall. Although the grid pattern of the pixel defining layer exists in the first sub-region RA, the organic encapsulation sublayer of the encapsulation layer can flatten the first sub-region RA. Therefore, a plurality of signal lines can be disposed in the first sub-region RA.

[0121] The second sub-region RB is closer to the barrier wall. In one example, the second sub-region RB substantially does not have a plurality of signal lines SL. For example, a plurality of signal lines SL other than a ground line are disposed in the first sub-region RA, and the ground line is disposed in the second sub-region RB. In one example, the signal line in the first sub-region RA extends in a direction substantially parallel to a boundary between the first sub-region RA and the second sub-region RB.

[0122] Fig.15 is a cross-sectional view of a portion of an array substrate in some embodiments of the present disclosure. Fig.15In some embodiments, the array substrate includes a first barrier wall BW1 and a second barrier wall BW2 spaced apart from each other. The array substrate also includes a first groove GV1, which separates the first barrier wall BW1 from the second barrier wall BW2. Optionally, the array substrate also includes an organic material layer OG and a second groove GV2 that separates the second barrier wall BW2 from the organic material layer OG. The inventors of the present disclosure have found that when the first barrier wall BW1, the second barrier wall BW2, or the organic material layer OG has a relatively large step difference relative to the base substrate BS, the array substrate is prone to depositing residual material at the corner area of ​​the groove (for example, the area indicated by the dotted line), especially when the groove is relatively narrow. When the residual material is a metal or a conductive material, the array substrate is prone to short circuits between adjacent signal lines.

[0123] The inventors of the present disclosure have found that if the width of the groove between two adjacent barrier walls is greater than the sum of the wall widths of the two barrier walls adjacent to the groove, especially when the barrier wall has a relatively large step difference relative to the substrate BS, residual material deposition can be eliminated. For example, the first groove width S1 is greater than the sum of the first wall width W1 of the first barrier wall BW1 and the second wall width W2 of the second barrier wall BW2. As used herein, the term "wall width" refers to the width of the barrier wall along a plane that intersects the barrier wall, the groove, and the organic material layer OG and is perpendicular to the surface of the substrate BS; the term "groove width" refers to the width of the groove along a plane that intersects the barrier wall, the groove, and the organic material layer OG and is perpendicular to the surface of the substrate BS.

[0124] The inventors of the present disclosure have also found that if the width between the barrier wall and the organic material layer is greater than twice the wall width of the barrier wall, residual material deposition can be eliminated, especially when the width of the organic material layer OG is much greater than the wall width of the barrier wall. For example, the second groove width S2 is greater than twice the second wall width W2 of the second barrier wall BW2.

[0125] Fig.16 is a cross-sectional view of a portion of an array substrate in some embodiments of the present disclosure. Fig.16 In some embodiments, the array substrate includes an inner organic material layer IOG, a first groove GV1, a first barrier wall BW1, a second groove GV2, a second barrier wall BW2, a third groove GV3, and an outer organic material layer OOG arranged in sequence in the peripheral area of ​​the array substrate. Optionally, the inner organic material layer IOG includes one or more insulating material layers from the display area DA. In one example, the inner organic material layer IOG includes a first planarization layer PLN1, a second planarization layer PLN2, and a pixel defining layer PDL. Optionally, the groove corresponds to the barrier inter-area as described above.

[0126] In some embodiments, the first groove GV1 has a first groove width S1, the second groove GV2 has a second groove width S2, the third groove GV3 has a third groove width S3, the first barrier wall BW1 has a first wall width W1, and the second barrier wall BW2 has a second wall width W2. The first groove GV1 is located between the inner organic material layer IOG and the first barrier wall BW1, the second groove GV2 is located between the first barrier wall BW1 and the second barrier wall BW2, and the third groove GV3 is located between the second barrier wall BW2 and the outer organic material layer OOG.

[0127] The first groove width S1 is generally relatively small, for example, less than twice the first wall width W1. However, generally, the inclination angle of the internal organic material layer IOG is relatively small, and therefore the step difference of the internal organic material layer IOG relative to the base substrate BS is relatively small. The inventors of the present disclosure have found that when the area corresponding to the first groove GV1 is planarized, the signal line can be arranged in the area. Optionally, the inclination angle of the internal organic material layer IOG is in the range of 5 to 30 degrees, for example, 5 to 10 degrees, 10 to 15 degrees, 15 to 20 degrees, 20 to 25 degrees, or 25 to 30 degrees. Optionally, the step difference of the internal organic material layer IOG relative to the base substrate BS is in the range of 1 μm to 2 μm, for example, 1.0 μm to 1.5 μm, or 1.5 μm to 2.0 μm.

[0128] The second groove width S2 is usually smaller than the sum of the first wall width W1 and the second wall width W2, for example, approximately the same as the first wall width W1 or the second wall width W2. In addition, the second barrier wall BW2 usually has a relatively large step difference relative to the substrate BS. The inventors of the present disclosure have found that it is necessary to avoid setting a signal line in the area corresponding to the second groove GV2.

[0129] The third groove width S3 is generally greater than twice the second wall width W2. Therefore, the inventors of the present disclosure have found that when the region corresponding to the third groove GV3 is planarized, the signal line can be disposed in the region.

[0130] Fig.17 is a cross-sectional view of a portion of an array substrate in some embodiments of the present disclosure. Fig.17In some embodiments, the array substrate includes an inner organic material layer IOG, a first groove GV1, a first barrier wall BW1, a second groove GV2, a second barrier wall BW2, a third groove GV3, a third barrier wall BW3, a fourth groove GV4, and an outer organic material layer OOG arranged in sequence in the peripheral area of ​​the array substrate. Optionally, the inner organic material layer IOG includes one or more insulating material layers from the display area DA. In one example, the inner organic material layer IOG includes a first planarization layer PLN1, a second planarization layer PLN2, a third planarization layer PLN3, and a pixel defining layer PDL. Optionally, the groove corresponds to the barrier inter-area as described above.

[0131] In some embodiments, the first groove GV1 has a first groove width S1, the second groove GV2 has a second groove width S2, the third groove GV3 has a third groove width S3, the fourth groove GV4 has a fourth groove width S4, the first barrier wall BW1 has a first wall width W1, the second barrier wall BW2 has a second wall width W2, and the third barrier wall BW3 has a third wall width W3. The first groove GV1 is located between the inner organic material layer IOG and the first barrier wall BW1, the second groove GV2 is located between the first barrier wall BW1 and the second barrier wall BW2, the third groove GV3 is located between the second barrier wall BW2 and the third barrier wall BW3, and the fourth groove GV4 is located between the third barrier wall BW3 and the outer organic material layer OOG.

[0132] The first groove width S1 is generally relatively small, for example, less than twice the first wall width W1. However, generally, the inclination angle of the internal organic material layer IOG is relatively small, and therefore the step difference of the internal organic material layer IOG relative to the base substrate BS is relatively small. The inventors of the present disclosure have found that when the area corresponding to the first groove GV1 is planarized, the signal line can be arranged in the area. Optionally, the inclination angle of the internal organic material layer IOG is in the range of 5 to 30 degrees, for example, 5 to 10 degrees, 10 to 15 degrees, 15 to 20 degrees, 20 to 25 degrees, or 25 to 30 degrees. Optionally, the step difference of the internal organic material layer IOG relative to the base substrate BS is in the range of 1 μm to 2 μm, for example, 1.0 μm to 1.5 μm, or 1.5 μm to 2.0 μm.

[0133] The second groove width S2 is typically smaller than the sum of the first wall width W1 and the second wall width W2, for example, approximately the same as the first wall width W1 or the second wall width W2. In one example, the second groove width S2 is in the range of 35 μm to 40 μm; the first wall width W1 or the second wall width W2 is in the range of 30 μm to 40 μm. However, the first barrier rib BW1 and the second barrier rib BW2 typically have a relatively small step difference relative to the substrate BS. In one example, the step difference of the first barrier rib BW1 or the second barrier rib BW2 relative to the substrate BS is in the range of 1 μm to 2 μm, for example, 1.0 μm to 1.5 μm, or 1.5 μm to 2.0 μm. The inventors of the present disclosure have found that when the area corresponding to the second groove GV2 is planarized, a signal line can be set in this area.

[0134] The third groove width S3 is generally smaller than the sum of the second wall width W2 and the third wall width W3, for example, approximately the same as the second wall width W2 or the third wall width W3. In addition, the third barrier wall BW3 generally has a relatively large step difference relative to the substrate BS. The inventors of the present disclosure have found that it is necessary to avoid setting a signal line in the area corresponding to the third groove GV3.

[0135] The fourth groove width S4 is generally greater than twice the third wall width W3. Therefore, the inventors of the present disclosure have found that when the region corresponding to the fourth groove GV4 is planarized, the signal line can be disposed in the region.

[0136] The inventors of the present disclosure also discovered that in order to arrange signal lines in the area corresponding to the following grooves, a unique signal line layout can be used to achieve the arrangement of signal lines in the area between the barriers: the grooves do not have sufficient groove width or are adjacent to barrier walls that have a large step difference relative to the substrate.

[0137] Fig.18A is a schematic diagram showing the layout of signal lines in the inter-blocker region of an array substrate according to some embodiments of the present disclosure. Fig.18A , the corresponding groove RGV is located in the barrier inter-area between the first adjacent barrier wall ABW1 and the second adjacent barrier wall ABW2. The array substrate includes a plurality of adjacent signal lines located in the barrier inter-area corresponding to the corresponding groove RGV. In an example, the plurality of adjacent signal lines located in the barrier inter-area include a first adjacent signal line ASL1, a second adjacent signal line ASL2, and a third adjacent signal line ASL3 that are adjacent to each other and arranged in sequence.

[0138] In some embodiments, two adjacent signal lines located in the barrier inter-area corresponding to the corresponding groove RGV are respectively located in two different layers. A plurality of signal lines located in the barrier inter-area corresponding to the corresponding groove RGV are alternately located in two different layers. In one example, the first adjacent signal line ASL1, the second adjacent signal line ASL2, and the third adjacent signal line ASL3 located in the barrier inter-area corresponding to the corresponding groove RGV are three adjacent touch signal lines. In another example, the first adjacent signal line ASL1, the second adjacent signal line ASL2, and the third adjacent signal line ASL3 located in the barrier inter-area corresponding to the corresponding groove RGV are alternately located in the first touch electrode layer and the second touch electrode layer.

[0139] Two adjacent signal lines located in the barrier inter-area corresponding to the corresponding groove RGV may be respectively arranged in any two appropriate layers. For example, two adjacent signal lines located in the barrier inter-area corresponding to the corresponding groove RGV may be arranged in any two different layers selected from the first touch electrode layer, the second touch electrode layer, the first signal line layer, the second signal line layer and the third gate metal layer.

[0140] The portion of each of the plurality of signal lines located on the side of the adjacent barrier wall away from the corresponding groove RGV may be a portion having two layers, for example, a portion having a first segment located in the first touch electrode layer and a second segment located in the second touch electrode layer. Fig.18A In some embodiments, each of the plurality of signal lines includes a double-layer portion DLP having a first segment located in the first touch electrode layer and a second segment located in the second touch electrode layer. The double-layer portion DLP is connected to a portion of the corresponding signal line located in the barrier inter-area corresponding to the corresponding groove RGV through a via.

[0141] In some embodiments, in order to eliminate the RC delay problem caused by the layer difference between adjacent signal lines, each of the multiple signal lines includes at least a first single segment located in the first conductive layer but not in the second conductive layer; and a second single segment located in the second conductive layer but not in the first conductive layer.

[0142] In some embodiments, the total length of the first single segment and the total length of the second single segment in each signal line are substantially the same. As used herein, the term "substantially the same" means that the difference between the two values ​​does not exceed 10% of the base value (e.g., one of the two values), such as not more than 8%, not more than 6%, not more than 4%, not more than 2%, not more than 1%, not more than 0.5%, not more than 0.1%, not more than 0.05%, and not more than 0.01% of the base value.

[0143] Fig.18B is along Fig.18A Cross-sectional view of line BB' in FIG. Fig.18B In some embodiments, in the inter-spacer region corresponding to the corresponding groove RGV, one or more first single segments SS1 and one or more second single segments SS2 respectively from adjacent signal lines are alternately arranged.

[0144] Fig.19 is a schematic diagram showing the layout of signal lines in the inter-blocker region of an array substrate according to some embodiments of the present disclosure. Fig.19 , the first adjacent signal line ASL1 includes at least a first single segment FSS1 located in the first conductive layer but not in the second conductive layer and a second single segment FSS2 located in the second conductive layer but not in the first conductive layer. The first single segment FSS1 is at least partially located in the barrier inter-region corresponding to the corresponding groove RGV. The second single segment FSS2 is at least partially located outside the barrier inter-region corresponding to the corresponding groove RGV.

[0145] The second adjacent signal line ASL2 includes at least a first single segment FSS1 located in the first conductive layer but not in the second conductive layer and a second single segment FSS2 located in the second conductive layer but not in the first conductive layer. The first single segment FSS1 is at least partially located outside the barrier inter-region corresponding to the corresponding groove RGV. The second single segment FSS2 is at least partially located in the barrier inter-region corresponding to the corresponding groove RGV.

[0146] The third adjacent signal line ASL3 includes at least a first single segment FSS1 located in the first conductive layer but not in the second conductive layer and a second single segment FSS2 located in the second conductive layer but not in the first conductive layer. The first single segment FSS1 is at least partially located in the barrier inter-region corresponding to the corresponding groove RGV. The second single segment FSS2 is at least partially located outside the barrier inter-region corresponding to the corresponding groove RGV.

[0147] In some embodiments, in the inter-barrier region corresponding to the corresponding groove RGV, the first single segments and the second single segments are alternately arranged.

[0148] In some embodiments, in at least one region other than the inter-barrier region corresponding to the corresponding groove RGV, the first single segments and the second single segments are alternately arranged.

[0149] Regarding the first-adjacent signal line ASL1 , the total length of the first single segment and the total length of the second single segment in the first-adjacent signal line ASL1 are substantially the same.

[0150] Regarding the second-adjacent signal line ASL2, the total length of the first single segment and the total length of the second single segment in the second-adjacent signal line ASL2 are substantially the same.

[0151] Regarding the third-adjacent signal line ASL3, the total length of the first single segment and the total length of the second single segment in the third-adjacent signal line ASL3 are substantially the same.

[0152] Reference Fig.19 In some embodiments, the first single-segment FSS1 and the second single-segment FSS2 of each signal line are connected to each other through vias located in the inter-spacer region corresponding to the corresponding groove RGV.

[0153] Fig. 20 is a schematic diagram showing the layout of signal lines in the inter-blocker region of an array substrate according to some embodiments of the present disclosure. Fig. 20 , each signal line includes at least three single segments located in two different layers. For example, the first adjacent signal line ASL1 includes a first single segment FSS1 connecting two adjacent second single segments. The second adjacent signal line ASL2 includes a second single segment FSS2 connecting two adjacent first single segments. The third adjacent signal line ASL3 includes a first single segment FSS1 connecting two adjacent second single segments.

[0154] In some embodiments, the total length of the first single segment and the total length of the second single segment in each signal line are substantially the same. For example, the total length of the first single segment FSS1 of the first adjacent signal line ASL1 is substantially the same as the total length of the two adjacent second single segments of the first adjacent signal line ASL1. The total length of the second single segment FSS2 of the second adjacent signal line ASL2 is substantially the same as the total length of the two adjacent first single segments of the second adjacent signal line ASL2. The total length of the first single segment FSS1 of the third adjacent signal line ASL3 is substantially the same as the total length of the two adjacent second single segments of the third adjacent signal line ASL3. The inventors of the present disclosure have discovered that such a fine structure can eliminate RC delays in signal lines.

[0155] In some embodiments, the sum of the lengths of the single segments in the first adjacent signal lines is substantially the same as the sum of the lengths of the single segments in the second adjacent signal lines. Optionally, the plurality of signal lines have substantially the same total length of the single segments.

[0156] Fig.21 is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Fig. 22 It is shown Fig.21 Schematic diagram of the layout of signal lines in the first amplification area in the array substrate depicted in FIG. Fig.23 It is shown Fig.21 The schematic diagram of the layout of the signal lines in the second enlarged area of ​​the array substrate depicted in FIG. Figure 21 to Figure 23, the first single segment and the second single segment of the same corresponding signal line can be arranged in different areas. In one example, the first single segment and the second single segment of the same corresponding signal line can be arranged in Fig. 9 In the first sub-area PA1 and the third sub-area PA3 depicted in FIG.

[0157] For example, the first adjacent signal line ASL1 includes a first single segment FSS1 in the first sub-area PA1 and a second single segment FSS2 in the third sub-area PA3. The total length of the first single segment FSS1 in the first sub-area PA1 is substantially the same as the total length of the second single segment FSS2 in the third sub-area PA3.

[0158] The second adjacent signal line ASL2 includes a second single segment FSS2 in the first sub-area PA1 and a first single segment FSS1 in the third sub-area PA3. The total length of the second single segment FSS2 in the first sub-area PA1 is substantially the same as the total length of the first single segment FSS1 in the third sub-area PA3.

[0159] The third adjacent signal line ASL3 includes a first single segment FSS1 in the first sub-area PA1 and a second single segment FSS2 in the third sub-area PA3. The total length of the first single segment FSS1 in the first sub-area PA1 is substantially the same as the total length of the second single segment FSS2 in the third sub-area PA3.

[0160] In some embodiments, the array substrate includes a display area and a peripheral area. Optionally, the array substrate includes first organic structures (eg, Figures 15 to 17 The inner organic material layer IOG or the outer organic material layer OOG in the embodiment of the present invention), one or more barrier walls (for example, Figures 15 to 17 The first barrier wall BW1, the second barrier wall BW2 or the third barrier wall BW3) and the second organic structure (for example, Figures 15 to 17 10G or the outer organic material layer OOG in the inner organic material layer 10G or the outer organic material layer OOG in the outer organic material layer OOG). Figures 15 to 17 , each of the one or more barrier walls comprises one or more organic insulating layers. Optionally, each barrier wall separates two adjacent grooves extending at least partially into the one or more organic insulating layers. Optionally, the two adjacent grooves are located on both sides of the corresponding barrier wall along the direction in which the first organic structure, the one or more barrier walls and the second organic structure are arranged in sequence. Optionally, referring to FIG. 13A to FIG. 13C as well as Figures 15 to 17 The array substrate further comprises a plurality of signal lines SL located in the peripheral region. Optionally, at least one of the plurality of signal lines extends in a direction substantially parallel to one or more barrier walls in a region having a groove adjacent to the barrier wall.

[0161] In some embodiments, the one or more barrier ribs include two adjacent barrier ribs (e.g., Figures 15 to 17 The array substrate may further include a groove (e.g., any one of the first groove GV1, the second groove GV2, or the third groove GV3) separating two adjacent barrier walls. Optionally, one or more signal lines are present in the barrier inter-wall region corresponding to the groove, wherein the width of the groove between two adjacent barrier walls is greater than the sum of the wall widths of the two barrier walls adjacent to the groove.

[0162] In some embodiments, the array substrate further includes a barrier wall (eg, Figures 15 to 17 The organic structure (for example, Figures 15 to 17 The organic structure and the barrier wall are separated by a groove. Optionally, one or more signal lines exist in a region corresponding to the groove, wherein a width between the barrier wall and the organic structure is greater than twice a wall width of the barrier wall.

[0163] In some embodiments, the groove (e.g., any one of the first groove GV1, the second groove GV2, or the third groove GV3) is adjacent to a barrier wall or an organic structure having an inclination angle in the range of 5 to 30 degrees. Optionally, when the groove is located between two adjacent barrier walls, the width of the groove is less than or equal to the sum of the wall widths of the two adjacent barrier walls, or, when the groove is located between the barrier wall and the organic structure, the width of the groove is less than or equal to twice the wall width of the barrier wall; and at least one of the plurality of signal lines extends in a direction substantially parallel to one or more barrier walls in a region having a groove adjacent to a barrier wall or an organic structure having an inclination angle in the range of 5 to 30 degrees.

[0164] In some embodiments, the groove (for example, any one of the first groove GV1, the second groove GV2, or the third groove GV3) is adjacent to a barrier wall or an organic structure having a thickness in the range of 1 μm to 2 μm. Optionally, when the groove is located between two adjacent barrier walls, the width of the groove is less than or equal to the sum of the wall widths of the two adjacent barrier walls, or, when the groove is located between the barrier wall and the organic structure, the width of the groove is less than or equal to twice the wall width of the barrier wall; and at least one of the plurality of signal lines extends in a direction substantially parallel to one or more barrier walls in a region having a groove adjacent to a barrier wall or an organic structure having a thickness in the range of 1 μm to 2 μm.

[0165] In some embodiments, the groove (for example, any one of the first groove GV1, the second groove GV2, or the third groove GV3) is adjacent to a barrier wall or an organic structure having an inclination angle greater than 30 degrees or a thickness greater than 2 μm. Optionally, when the groove is located between two adjacent barrier walls, the width of the groove is less than or equal to the sum of the wall widths of the two adjacent barrier walls, or, when the groove is located between the barrier wall and the organic structure, the width of the groove is less than or equal to twice the wall width of the barrier wall; and none of the plurality of signal lines extends in a direction substantially parallel to one or more barrier walls in a region having a groove adjacent to a barrier wall or an organic structure having an inclination angle greater than 30 degrees or a thickness greater than 2 μm.

[0166] In another aspect, the present invention provides a display device, comprising an array substrate as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a micro light emitting diode display device. Optionally, the display device is a mini light emitting diode display device. Optionally, the display device is a quantum dot display device.

[0167] In some embodiments, the display device includes: a plurality of light-emitting elements located on a substrate; a packaging layer located on a side of the plurality of light-emitting elements away from the substrate; a first touch metal layer located on a side of the packaging layer away from the substrate; a touch insulating layer located on a side of the first touch metal layer away from the substrate; and a second touch metal layer located on a side of the touch insulating layer away from the substrate. Optionally, the plurality of signal lines are a plurality of touch signal lines.

[0168] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate, comprising one or more barrier walls, and a plurality of signal lines located in a peripheral region and located on a side of the one or more barrier walls away from a base substrate; in, The peripheral region includes an inner region, an outer region, and one or more inter-barrier regions; The inner region is located between the display region and the barrier wall closest to the display region; Each of the one or more inter-barrier regions is located between two adjacent barrier walls; The outer area is located at a side of the barrier wall farthest from the display area and away from the display area; as well as The plurality of signal lines include one or more first signal lines extending in a direction substantially parallel to at least one barrier wall in at least one of the one or more inter-barrier regions.

2. The array substrate according to claim 1, wherein: Each of the one or more first signal lines includes a first portion and a second portion connected to each other; the first portion extending in a direction substantially parallel to at least one barrier wall in at least one of the one or more inter-barrier regions; as well as The second portion intersects at least one barrier wall.

3. The array substrate according to claim 2, wherein: A length of the first portion extending in the at least one of the one or more inter-barrier regions is at least 1.5 times a corresponding inter-barrier distance of a corresponding inter-barrier region of the one or more inter-barrier regions.

4. The array substrate according to claim 2, wherein: The orthographic projection of the first portion on the substrate does not substantially overlap with the orthographic projection of any barrier wall on the substrate; as well as An orthographic projection of the second portion on the base substrate at least partially overlaps with an orthographic projection of at least one barrier rib on the base substrate.

5. The array substrate according to any one of claims 1 to 4, wherein: the plurality of signal lines further comprising a plurality of second signal lines extending at least partially within the interior region and at least partially intersecting the one or more inter-barrier regions; as well as A portion of each of the plurality of second signal lines located in a corresponding one of the one or more barrier inter-spacer regions extends in a direction that is not parallel to the one or more barrier walls.

6. The array substrate according to claim 5, wherein: A total length of the portion of each of the plurality of second signal lines located in the corresponding inter-barrier region is in a range from 1.0 times to 1.5 times a corresponding inter-barrier distance of a corresponding inter-barrier region among the one or more inter-barrier regions.

7. The array substrate according to claim 5, wherein: Each of the plurality of second signal lines includes a third portion and a fourth portion connected to each other; the third portion extending in the interior region in a direction substantially parallel to the at least one barrier wall; as well as The fourth portion intersects at least one barrier wall.

8. The array substrate according to any one of claims 1 to 7, wherein: The plurality of signal lines further include a plurality of third signal lines extending in the outer region; Each of the plurality of third signal lines includes a fifth portion and a sixth portion connected to each other; The fifth portion extends in a direction substantially parallel to the at least one barrier wall; as well as The sixth portion extends in a direction that is non-parallel to the one or more barrier walls.

9. The array substrate according to any one of claims 1 to 8, wherein: In a region of the lower frame transitioning from a side region of the peripheral region to a corner region, the plurality of signal lines have a stepped pattern; as well as Each signal line includes a first line segment and a second line segment alternately connected together, the first line segment and the second line segment extend in different directions, and the second line segment extends toward the display area.

10. The array substrate according to claim 9, wherein: The first line segment has a first average line width, the second line segment has a second average line width, and the second average line width is greater than the first average line width; as well as The first line segments are spaced apart from each other by a first inter-segment distance, and the second line segments are spaced apart from each other by a second inter-segment distance, wherein the second inter-segment distance is greater than the first inter-segment distance.

11. The array substrate according to any one of claims 1 to 10, further comprising a pixel defining layer located in the display area; in, The pixel defining layer is at least partially absent from the peripheral region; and The plurality of signal lines are spaced apart from an edge of the pixel defining layer by a distance not greater than 100 μm.

12. The array substrate according to claim 11, wherein: The peripheral region includes a corner region; The corner region includes a first sub-region and a second sub-region, in which the pixel defining layer exists, and in which the layer including the organic material is removed; The array substrate includes a plurality of openings arranged in a grid pattern and extending through the pixel defining layer in the first sub-region; The first sub-region is separated from the barrier wall by the second sub-region; as well as The second sub-region substantially does not have the plurality of signal lines.

13. The array substrate according to any one of claims 1 to 12, wherein: The one or more barrier walls include two adjacent barrier walls; The array substrate further comprises a groove separating the two adjacent barrier walls; as well as One or more signal lines exist in an inter-barrier region corresponding to a groove in which a width of the groove between the two adjacent barrier walls is greater than a sum of wall widths of two barrier walls adjacent to the groove.

14. The array substrate according to any one of claims 1 to 12, further comprising an organic material layer adjacent to the barrier rib, and a groove separating the organic material layer from the barrier rib; in, One or more signal lines exist in a region corresponding to a groove in which a width between the barrier rib and the organic material layer is greater than twice a wall width of the barrier rib.

15. The array substrate according to any one of claims 1 to 12, wherein: The one or more barrier ribs include a first adjacent barrier rib and a second adjacent barrier rib; Wherein, the array substrate further includes: a corresponding recess in the inter-barrier region between the first adjacent barrier wall and the second adjacent barrier wall; and a plurality of adjacent signal lines located in the inter-barrier regions corresponding to the respective grooves; and The plurality of adjacent signal lines located in the inter-barrier regions corresponding to the corresponding grooves are alternately located in two different layers.

16. The array substrate according to claim 15, wherein: The portion of each adjacent signal line of the plurality of adjacent signal lines located on a side of the adjacent barrier wall away from the corresponding groove comprises a double-layer portion having a first segment located in the first conductive layer and a second segment located in the second conductive layer; as well as The double-layered portion is connected to a portion of a corresponding adjacent signal line located in the inter-barrier region corresponding to the corresponding groove.

17. The array substrate according to claim 15, wherein: Each adjacent signal line of the plurality of adjacent signal lines includes at least a first single segment located in the first conductive layer but not in the second conductive layer, and a second single segment located in the second conductive layer but not in the first conductive layer; as well as In the inter-barrier regions corresponding to the respective grooves, one or more first single segments and one or more second single segments respectively from adjacent signal lines are alternately arranged.

18. The array substrate according to claim 17, wherein: The total length of the first single segment and the total length of the second single segment in each adjacent signal line are substantially the same; and The plurality of signal lines have substantially the same overall length of a single segment.

19. The array substrate according to claim 17, wherein: The first single segment and the second single segment of the same corresponding signal line are located in different areas of the peripheral area, and the different areas are respectively located on different sides of the display area.

20. A display device comprising an array substrate according to any one of claims 1 to 19 and one or more integrated circuits connected to the array substrate; in, The display device comprises: A plurality of light emitting elements are located on the substrate; An encapsulation layer, which is located on a side of the plurality of light-emitting elements away from the base substrate; A first touch metal layer, which is located on a side of the packaging layer away from the substrate; a touch insulating layer, located on a side of the first touch metal layer away from the base substrate; and A second touch metal layer, which is located on a side of the touch insulating layer away from the base substrate; The plurality of signal lines are touch signal lines located in at least one of the first touch metal layer or the second touch metal layer.

21. An array substrate comprising a display area and a peripheral area; in, The array substrate comprises, in the peripheral region, a first organic structure, one or more barrier ribs, and a second organic structure which are sequentially arranged in a direction away from the display region; Wherein, each of the one or more barrier ribs comprises one or more organic insulating layers; wherein each barrier rib separates two adjacent grooves extending at least partially into the one or more organic insulating layers; and The two adjacent grooves are located on both sides of the corresponding barrier wall along a direction in which the first organic structure, the one or more barrier walls and the second organic structure are arranged in sequence; Wherein, the array substrate further comprises a plurality of signal lines located in the peripheral region and located on a side of the one or more barrier walls away from the base substrate; and At least one of the plurality of signal lines extends in a direction substantially parallel to the one or more barrier ribs in a region having the groove adjacent to the barrier ribs.

22. The array substrate according to claim 21, wherein: The one or more barrier walls include two adjacent barrier walls; The array substrate further comprises a groove separating the two adjacent barrier walls; as well as One or more signal lines exist in an inter-barrier region corresponding to a groove in which a width of the groove between the two adjacent barrier walls is greater than a sum of wall widths of two barrier walls adjacent to the groove.

23. The array substrate according to claim 21, further comprising an organic structure adjacent to the barrier wall, and a groove separating the organic structure from the barrier wall; in, One or more signal lines exist in a region corresponding to a groove in which a width between the barrier rib and the organic structure is greater than twice a wall width of the barrier rib.

24. The array substrate according to claim 21, wherein: The groove is adjacent to a barrier wall or organic structure having an inclination angle ranging from 5 degrees to 30 degrees; When the groove is located between two adjacent barrier walls, the width of the groove is less than or equal to the sum of the wall widths of the two adjacent barrier walls, or when the groove is located between a barrier wall and an organic structure, the width of the groove is less than or equal to twice the wall width of the barrier wall; as well as At least one of the plurality of signal lines extends in a direction substantially parallel to the one or more barrier ribs in a region having the groove adjacent to the barrier rib or the organic structure having an inclination angle in a range of 5 to 30 degrees.

25. The array substrate according to claim 21, wherein: The groove is adjacent to a barrier wall or an organic structure having a thickness in the range of 1 μm to 2 μm; When the groove is located between two adjacent barrier ribs, the width of the groove is less than or equal to the sum of the wall widths of the two adjacent barrier ribs, or when the groove is located between a barrier rib and an organic structure, the width of the groove is less than or equal to twice the wall width of the barrier rib; and At least one of the plurality of signal lines extends in a direction substantially parallel to the one or more barrier ribs in a region having the groove adjacent to the barrier rib or the organic structure having a thickness in a range of 1 μm to 2 μm.

26. The array substrate according to claim 21, wherein: The groove is adjacent to a barrier wall or organic structure with an inclination angle greater than 30 degrees or a thickness greater than 2 μm; When the groove is located between two adjacent barrier ribs, the width of the groove is less than or equal to the sum of the wall widths of the two adjacent barrier ribs, or when the groove is located between a barrier rib and an organic structure, the width of the groove is less than or equal to twice the wall width of the barrier rib; and None of the plurality of signal lines extends in a direction substantially parallel to the one or more barrier ribs in a region having the groove adjacent to the barrier rib or the organic structure having the inclination angle greater than 30 degrees or the thickness greater than 2 μm.

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