Array substrate and display device

Abstract

The invention discloses an array substrate and a display device. The array substrate comprises a display area and a non-display area; the display area comprises a substrate and at least one switching structure; the switching structure comprises a first connecting part and a second connecting part which are located on different conductive layers, and the first connecting part is closer to the substrate than the second connecting part. The display area further comprises at least one insulating layer, the at least one insulating layer is provided with at least one switching hole, the switching hole exposes the part of the first connecting component, and the part of the second connecting component is located in the switching hole and is in contact with the first connecting component; the second connecting part is provided with at least one first step structure, and the at least one first step structure is located between the hole bottom and the hole top of the adapter hole. The display area further comprises an alignment film, a part of the alignment film makes contact with the first step structure, and the matching quality of the alignment film and the second connecting component can be improved through the first step structure.

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] Liquid Crystal Display (LCD) is a common type of display at present. LCD displays use two polarized materials with a liquid crystal solution between them. When an electric current passes through the liquid, the crystals are rearranged so that light cannot pass through them. Therefore, each crystal is like a shutter, which can allow light to pass through but also block light. Currently, liquid crystal displays (LCD) are developing towards the goal of being light, thin, short and small.

[0003] At present, existing LCD screens have quality defects such as partial whitening, horizontal stripes, and uneven display. Summary of the invention

[0004] The disclosed embodiments provide an array substrate and a display device. The first step structure is provided by the second connecting component to improve the matching quality between the alignment film at the transfer structure and the second connecting component, and the quality defects of the existing liquid crystal display screens such as local whitening, horizontal stripes, and uneven display can be solved.

[0005] On the one hand, an embodiment of the present disclosure provides an array substrate, comprising a display area and a non-display area located at least on one side of the display area; the display area comprises a substrate and at least one transfer structure located on the substrate; the transfer structure comprises a first connecting component and a second connecting component located on different conductive layers, and the first connecting component is closer to the substrate than the second connecting component;

[0006] The display area further comprises at least one insulating layer, the at least one insulating layer is provided with at least one transfer hole, the transfer hole exposes a portion of the first connecting component, and a portion of the second connecting component is located within the transfer hole and in contact with the first connecting component; the second connecting component has at least one first step structure, and the at least one first step structure is located between the bottom and top of the transfer hole;

[0007] The display area further includes an alignment film, and a portion of the alignment film is in contact with the first step structure.

[0008] In some exemplary embodiments, the first step structure includes a first step and a second step connected to each other, the first step extends along a plane parallel to the substrate, and the second step is located between the first step and the substrate; a portion of the alignment film is in contact with both the first step and the second step.

[0009] In some exemplary embodiments, the display area further includes at least one cushion layer, wherein the at least one cushion layer is located between the bottom and top of the transfer hole; the cushion layer includes a top and a side that are connected to each other, the top is parallel to the plane where the substrate is located, and the side is located between the top and the substrate; the transfer hole exposes a portion of the top and a portion of the side; the first step is in contact with the top, and the second step is in contact with the side.

[0010] In some exemplary embodiments, the orthographic projection of the cushion layer on the plane where the substrate is located is a ring, and the orthographic projection of the transfer hole on the plane where the substrate is located is located inside the outer contour of the ring.

[0011] In some exemplary embodiments, the two or more cushion layers are arranged around the hole center of the orthographic projection of the transfer hole on the plane where the substrate is located, with the orthographic projection of the two or more cushion layers on the plane where the substrate is located being arranged.

[0012] In some exemplary embodiments, the display area further includes at least one transistor, and the transistor includes a first electrode, a second electrode, an active layer, and a gate electrode; and the pad layer and the active layer are in the same layer structure.

[0013] In some exemplary embodiments, the display area further includes at least one transistor, and the transistor includes a first electrode, a second electrode, an active layer, and a gate electrode; the pad layer is in the same layer structure as the first electrode and the second electrode.

[0014] In some exemplary embodiments, the orthographic projection of the cushion layer on the plane where the substrate is located is a rectangle, a circle, an ellipse, a cross, a pentagon, or a hexagon.

[0015] In some exemplary embodiments, the second connecting member further has at least one second step structure, and the at least one second step structure is located at the bottom of the transfer hole; a portion of the alignment film is in contact with the second step structure.

[0016] In some exemplary embodiments, the second step structure includes a third step and a fourth step connected to each other, and the third step extends along a plane parallel to the plane where the substrate is located, and the fourth step is located between the third step and the substrate; a portion of the alignment film is in contact with both the third step and the fourth step.

[0017] In some exemplary embodiments, the first connecting member includes a top wall and a side wall connected to each other, the top wall is parallel to the plane where the substrate is located, and the side wall is located between the top wall and the substrate;

[0018] The transfer hole exposes a portion of the top wall and a portion of the side wall, the third step contacts the top wall, and the fourth step contacts the side wall.

[0019] In some exemplary embodiments, the display area further includes a first conductive layer, a second conductive layer and a third conductive layer sequentially stacked on the substrate; the first connecting component is located in the first conductive layer, and the second connecting component is located in the third conductive layer.

[0020] In some exemplary embodiments, the display area also includes a first insulating layer and a semiconductor layer stacked sequentially on the side of the first conductive layer away from the substrate, and a second insulating layer and an organic insulating layer stacked sequentially on the side of the second conductive layer away from the substrate; the pad layer is located in the semiconductor layer.

[0021] In some exemplary embodiments, the display area also includes a first insulating layer and a semiconductor layer stacked sequentially on the side of the first conductive layer away from the substrate, and a second insulating layer and an organic insulating layer stacked sequentially on the side of the second conductive layer away from the substrate; the pad layer is located in the second conductive layer.

[0022] On the other hand, an embodiment of the present disclosure provides a display device, which includes the array substrate described in any of the above embodiments.

[0023] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0025] Figure 1 is a schematic diagram of a main view of a display device;

[0026] Figure 2A for Figure 1 A schematic diagram of the arrangement of multiple pixel units located in the display area;

[0027] Figure 2B for Figure 2A A partial cross-sectional schematic diagram of the middle via D area;

[0028] Figure 2C for Figure 2A Another partial cross-sectional schematic diagram of the middle via D area;

[0029] Figure 3A is a schematic cross-sectional view of a transfer structure of an array substrate according to an embodiment of the present disclosure;

[0030] Figure 3B is a schematic top view of a pad layer and a transfer hole of an array substrate according to an embodiment of the present disclosure;

[0031] Figure 3C is a schematic top view of a pad layer and a transfer hole of an array substrate according to another embodiment of the present disclosure;

[0032] Figure 4A and Figure 4B This is a partial schematic diagram of an array substrate after a first insulating film is formed in an embodiment of the present disclosure;

[0033] Figure 5A and Figure 5B It is a partial schematic diagram of an array substrate after a semiconductor layer pattern is formed in an embodiment of the present disclosure;

[0034] Fig. 6A and Figure 6B It is a partial schematic diagram of an array substrate after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0035] Fig. 7A and Figure 7B It is a partial schematic diagram of an array substrate after a third insulating layer pattern is formed in an embodiment of the present disclosure;

[0036] Fig. 8A and Figure 8B It is a partial schematic diagram of an array substrate after forming a second insulating layer pattern according to an embodiment of the present disclosure;

[0037] Fig.9A and Fig. 9B It is a partial schematic diagram of an array substrate after a third conductive layer pattern is formed in an embodiment of the present disclosure;

[0038] Fig. 10A and Fig. 10B It is a partial schematic diagram of an array substrate after a semiconductor layer pattern is formed according to another embodiment of the present disclosure;

[0039] Fig.11A and Fig. 11B It is a partial schematic diagram of an array substrate after forming a second conductive layer pattern according to another embodiment of the present disclosure;

[0040] Fig. 12A and Fig. 12B It is a partial schematic diagram of an array substrate after a third insulating layer pattern is formed on the array substrate according to another embodiment of the present disclosure;

[0041] Fig.13A and Fig. 13BThis is a partial schematic diagram of an array substrate after a second insulating layer pattern is formed according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0043] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0044] The ordinal numbers such as "first", "second", and "third" in the present disclosure are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in the present disclosure includes two and more than two.

[0045] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0046] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0047] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0048] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0049] In the present disclosure, "electrical connection" includes the situation where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0050] In the present disclosure, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, a state where the angle is greater than -5° and less than 5° may be included. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, a state where the angle is greater than 85° and less than 95° may be included.

[0051] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0052] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0053] Figure 1 Schematic diagram of a main view of a display device. Figure 1 As shown, the array substrate may include a display area AA and a non-display area BB located at least on one side of the display area AA. The non-display area BB may include a first non-display area B1 located on one side of the display area AA and a second non-display area B2 located on the remaining sides of the display area AA. For example, the first non-display area B1 may include a lower frame of the array substrate, and the second non-display area B2 may include an upper frame, a left frame, and a right frame of the array substrate.

[0054] In an exemplary embodiment, if Figure 1 As shown, the display area AA may include: a plurality of data lines DL and a plurality of gate lines GL disposed on a substrate. The plurality of gate lines GL may extend along a first direction X and be sequentially arranged along a second direction Y different from the first direction X. The plurality of data lines DL may extend along the second direction Y and be sequentially arranged along the first direction X. The first direction X and the second direction Y may intersect, for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines DL and the plurality of gate lines GL may be located in different film layers, for example, the plurality of data lines DL may be located on a side of the plurality of gate lines GL away from the substrate.

[0055] In an exemplary embodiment, the display area AA may include a plurality of pixel units disposed on a substrate. At least one pixel unit may include three sub-pixels. Figure 1 As shown, at least one sub-pixel may include: a pixel electrode 10 and a common electrode ( Figure 1 Not shown), and the pixel electrode 10 of the sub-pixel and the common electrode may overlap in the positive projection of the substrate. The common electrode of multiple sub-pixels in the display area AA may be an integrated structure. For example, the common electrode may be located on the side of the pixel electrode 10 away from the substrate. The sub-pixel may also include a transistor 11. The transistor 11 may be adjacent to the intersection of the data line DL and the gate line GL. The transistor 11 may include a gate electrode, a first electrode, and a second electrode. The gate electrode may be electrically connected to the gate line GL, the first electrode of the transistor 11 may be electrically connected to the data line DL, and the second electrode may be electrically connected to the pixel electrode 10 of a sub-pixel. The transistor 11 may be configured to provide a data signal transmitted by the data line DL to the pixel electrode 10 of the sub-pixel under the control of the gate line GL.

[0056] In an exemplary embodiment, the second non-display area B2 may include at least a gate drive circuit (e.g., including a plurality of cascaded shift registers), and the plurality of shift registers may be electrically connected to the plurality of gate lines GL in the display area AA. The gate drive circuit may also include a transistor. The structure of the transistor located in the second non-display area B2 may be the same as or different from that of the transistor located in the display area AA.

[0057] Figure 2A for Figure 1 A schematic diagram of the arrangement of multiple pixel units located in the display area. Figure 2AAs shown, the pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. For example, the first color may be red, the second color may be green, and the third color may be blue. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 may be arranged linearly. The pixel unit P may include a light-emitting area and a non-light-emitting area F surrounding the light-emitting area. The light-emitting area may include a first light-emitting area F10, a second light-emitting area F20, and a third light-emitting area F30. As people's requirements for display products become higher and higher, the aperture ratio of display products is also increasing. Organic materials are increasingly being used in display products. In the development of actual products, it is often necessary to electrically connect two components located in different conductive film layers through a via D. Typically, the via D is arranged in the non-light-emitting area F.

[0058] like Figure 2B , Figure 2C As shown, the two components are a first component 1 located in the first conductive layer and a second component 2 located in the second conductive layer. Usually, at least one insulating layer is provided between the first component 1 and the second component 2. Due to the use of organic materials in display products, the thickness of the organic layer 3 formed by the organic materials is usually about 10,000 angstroms to 20,000 angstroms, which results in the hole depth of the via hole D being Figure 2B L1 in increases to Figure 2C L2 in the figure. Usually, an array substrate is provided with an alignment film, and the alignment film is used to arrange the liquid crystal molecules in a set order. As the hole depth of the via hole D increases, the alignment film and the second component may have poor matching quality at the hole wall of the via hole D, thereby affecting the arrangement of the liquid crystal molecules at that location, resulting in poor display quality defects in the liquid crystal display product.

[0059] An embodiment of the present disclosure provides an array substrate, comprising a display area and a non-display area located at least on one side of the display area; the display area comprises a substrate and at least one transfer structure located on the substrate; the transfer structure comprises a first connecting component and a second connecting component located on different conductive layers, and the first connecting component is closer to the substrate than the second connecting component;

[0060] The display area further comprises at least one insulating layer, the at least one insulating layer is provided with at least one transfer hole, the transfer hole exposes a portion of the first connecting component, and a portion of the second connecting component is located within the transfer hole and in contact with the first connecting component; the second connecting component has at least one first step structure, and the at least one first step structure is located between the bottom and top of the transfer hole;

[0061] The display area further includes an alignment film, and a portion of the alignment film is in contact with the first step structure.

[0062] In the embodiment of the present disclosure, a first step structure is provided by a second connecting component. During the process of preparing the alignment film, when the liquid forming the alignment film flows through the first step structure, the first step structure will change the dynamic characteristics of the liquid flow, thereby affecting the surface tension of the liquid. This can improve the matching quality between the alignment film and the second connecting component, and can solve the quality defects of existing liquid crystal display screens such as local whitening, horizontal stripes, and uneven display.

[0063] Figure 3A The figure is a cross-sectional schematic diagram of a transfer structure of an array substrate according to an embodiment of the present disclosure. Figure 3A for Figure 2A Schematic diagram of the improved cross-section at the via D in the middle. In a plane perpendicular to the plane where the substrate 20 is located, the array substrate may include a substrate 20 and a first conductive layer, a first insulating layer 21, a semiconductor layer, a second conductive layer, a second insulating layer 22, a third insulating layer 23 and a third conductive layer stacked in sequence on the substrate 20. The array substrate may also include at least one transistor 11 and at least one switching structure 30, and the transistor 11 may at least include a first pole 11-1, a second pole 11-2, a gate electrode 11-3 and an active layer 11-4. The switching structure 30 may at least include a first connecting component 31 and a second connecting component 32. The gate electrode 11-3 and the first connecting component 31 may be located in the first conductive layer. The active layer 11-4 may be located in the semiconductor layer. The first pole 11-1 and the second pole 11-2 may both be located in the second conductive layer. The pixel electrode 10 and the second connecting component 32 may both be located in the third conductive layer. For example, the switching structure 30 can be used for switching the common electrode line, that is, a grid-shaped common electrode line can be formed on the first conductive layer and the third conductive layer, which is conducive to ensuring the uniformity of the common electrode. In the embodiment of the present disclosure, the first insulating layer can be referred to as a gate insulating (GI) layer, the second insulating layer can be referred to as a passivation (PVX) layer, the third insulating layer can be referred to as an organic insulating layer, the first conductive layer can be referred to as a gate metal layer, and the second conductive layer can be referred to as a source-drain metal layer.

[0064] The array substrate may further include at least one connection hole K1 and at least one transfer hole K2, and the pixel electrode 10 may be connected to the second electrode 11-2 of the transistor 11 via the connection hole K1. The second connection component 32 may be connected to the first connection component 31 via the transfer hole K2. The orthographic projections of the connection hole K1 and the transfer hole K2 on the plane where the substrate 20 is located may be the same or different. The orthographic projections of the connection hole K1 and the transfer hole K2 on the plane where the substrate 20 is located may be circular, rectangular, elliptical, pentagonal, hexagonal or octagonal, etc.

[0065] The second connection part 32 may have at least one first step structure 33, and the first step structure 33 is located between the bottom and top of the transfer hole K2. For example, multiple first step structures 33 may be arranged circumferentially around the transfer hole K2, or multiple first step structures 33 may be arranged along the direction of the hole depth of the transfer hole K2 (third direction Z). The first step structure 33 has a first step 33-1 and a second step 33-2 connected to each other, the first step 33-1 extends along a plane parallel to the substrate 20, and the second step 33-2 is located between the first step 33-1 and the substrate 20. The array substrate also includes an alignment film, which is usually formed by a coating process. When the liquid forming the alignment film flows through the first step structure, the first step structure changes the dynamic characteristics of the liquid flow, thereby affecting the surface tension of the liquid, which can improve the matching quality of the alignment film and the second connection part in the transfer hole, and can solve the quality defects of local whitening, horizontal stripes, uneven display, etc. existing in the existing liquid crystal display screen. The first step structure is basically composed of a combination of planes, so it will not affect the function of the alignment film.

[0066] The second connecting component 32 may have at least one second step structure 34, and the second step structure 34 is located at the bottom of the transfer hole K2. The second step structure 34 may include a third step 34-3 and a fourth step 34-4 connected to each other, the third step 34-3 extends along a plane parallel to the substrate 20, and the fourth step 34-4 is located between the third step 34-3 and the substrate 20. In the process of forming the alignment film, the second step structure will change the dynamic characteristics of the liquid flow, thereby affecting the surface tension of the liquid, and can improve the matching quality of the alignment film and the second connecting component in the transfer hole. The second step structure is basically composed of a combination of planes, so it will not affect the function of the alignment film.

[0067] In an exemplary embodiment, the array substrate may further include at least one pad layer 40, and the pad layer 40 may be located between the bottom and top of the transfer hole K2. For example, the pad layer 40 may be located in the semiconductor layer, that is, the pad layer 40 and the active layer 11-4 are in the same layer structure. Alternatively, the pad layer 40 may be located in the second conductive layer, that is, the pad layer 40 and the first pole 11-1 and the second pole 11-2 are in the same layer structure. Alternatively, the pad layer 40 may be located between the second insulating layer 22 and the third insulating layer 23. The pad layer 40 may include a top 40a and a side 40b connected to each other, the top 40a is parallel to the plane where the substrate 20 is located, and the side 40b is located between the top 40a and the substrate 20. The transfer hole K2 exposes a portion of the top 40a and a portion of the side 40b. The first step 33-1 contacts the top 40a, and the second step 33-2 contacts the side 40b. In the disclosed embodiment, the cushion layer can be used to form a first step structure for the second connecting component. During the preparation process, the cushion layer and the existing film layer of the array substrate are prepared by the same patterning process, without adding preparation steps, thereby reducing the preparation cost of the array substrate.

[0068] In an exemplary embodiment, the first connecting component 31 includes a top wall 31a and a side wall 31b connected to each other, the top wall 31a is parallel to the plane where the substrate 20 is located, and the side wall 31b is located between the top wall 31a and the substrate 20. The transfer hole K2 exposes a portion of the top wall 31a and a portion of the side wall 31b of the first connecting component 31. The third step 34-3 contacts the top wall 31a, and the fourth step 34-4 contacts the side wall 31b. In the embodiment of the present disclosure, the second connecting component can be formed into a second step structure by using the first connecting component, without adding new components, and the preparation cost of the array substrate can be reduced.

[0069] In an exemplary embodiment, if Figure 3B As shown, the array substrate may include more than two pad layers 40, and the orthographic projections of the two or more pad layers 40 on the plane where the substrate is located may be arranged around the center of the orthographic projection of the transfer hole K2 on the plane where the substrate is located. For example, the array substrate may include two pad layers, or three, or four, or five, etc., and the embodiment of the present disclosure does not limit the number of pad layers. Figure 3B In the example, the array substrate includes four pad layers 40. For example, the orthographic projections of the four pad layers 40 on the plane where the substrate is located can be evenly distributed around the hole center of the orthographic projection of the transfer hole K2 on the plane where the substrate is located. In the process of forming the alignment film, the multiple pad layers enable the multiple first step structures formed by the second connecting component to change the tension of the alignment film from multiple positions, which is conducive to ensuring the consistency of the matching quality of the alignment film at the transfer structure and the second connecting component.

[0070] In an exemplary embodiment, if Figure 3CAs shown, the orthographic projection of the cushion layer 40 on the plane where the substrate 20 is located can be annular, and the orthographic projection of the adapter hole on the plane where the substrate 20 is located can be located inside the outer contour of the ring. For example, the outer contour of the ring can be circular or elliptical or rectangular or hexagonal, etc. For example, the inner contour of the ring can be circular or elliptical or rectangular or hexagonal, etc. In the embodiment of the present disclosure, the shapes of the outer contour and the inner contour of the ring are not limited. In the process of forming the alignment film, the annular cushion layer can make the first step structure formed by the second connecting component annular (orthographic projection on the plane where the substrate is located), and the first step structure can change the tension of the alignment film from the circumference of the adapter hole, which is beneficial to ensure the consistency of the matching quality of the alignment film and the second connecting component at the adapter structure.

[0071] The structure of the array substrate is described below by way of an example of the preparation process of the array substrate. The "patterning process" mentioned in the embodiment of the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. The deposition process may adopt any one or more of sputtering, evaporation, and chemical vapor deposition, the coating process may adopt any one or more of spraying, spin coating, and inkjet printing, and the etching process may adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B same-layer structure" mentioned in the present disclosure means that A and B are formed by the same patterning process.

[0072] Taking the cushion layer and the active layer as the same layer structure as an example, the preparation process of the array substrate may include:

[0073] (01) Forming a first insulating film. Forming the first insulating film may include: depositing a first conductive film on the substrate 20, patterning the first conductive film through a patterning process, so that the first conductive film forms a first conductive layer pattern on the substrate 20, and the first conductive layer pattern may include at least a gate line GL, a gate electrode 11-3, and a first connecting member 31, such as Figure 4A and Figure 4B shown. Figure 4B for Figure 4A In the embodiment of the present disclosure, the direction perpendicular to the plane where the substrate 20 is located can be referred to as the third direction and is marked as Z. Figure 4A for Figure 1 A partial schematic diagram of the area is shown in Figure 4A Only one gate line GL is shown in FIG.

[0074] Then, a first insulating film 21-1 is deposited on the substrate 20 having the aforementioned pattern formed thereon. Figure 4A and Figure 4B As shown, in Figure 4A In the embodiment, the first insulating film 21-1 is displayed semi-transparently to facilitate identification of the first conductive layer pattern. The orthographic projection of the first insulating film 21-1 on the plane where the substrate 20 is located may include the orthographic projection of the first connecting component 31 on the plane where the substrate 20 is located. The orthographic projection of the first insulating film 21-1 on the plane where the substrate 20 is located may at least partially overlap with the orthographic projection of the gate line GL on the plane where the substrate 20 is located. The orthographic projection of the first insulating film 21-1 on the plane where the substrate 20 is located may include the orthographic projection of the gate electrode 11-3 on the plane where the substrate 20 is located.

[0075] In some exemplary embodiments, the gate line GL and the gate electrode 11-3 may be an integrated structure connected to each other. The gate line GL may be set with equal width or unequal width, and the width of the gate line GL refers to the dimension perpendicular to the extension direction of the gate line GL (ie, the second direction Y).

[0076] In some exemplary embodiments, the first connecting member 31 may be located on one side of the second direction Y of the gate line GL in the opposite direction. The first connecting member 31 may be of any shape, and the shape of the first connecting member 31 may be adaptively designed according to the requirements of the actual product layout space. For example, the first connecting member 31 may include a plurality of connected sections, and the plurality of sections may include a first section 31-1, a second section 31-2, a third section 31-3, and a fourth section 31-4. The first section 31-1 includes a first end and a second end, and the second end extends along the second direction Y. The second section 31-2 includes a first end and a second end, the first end of the second section 31-2 is connected to the second end of the first section 31-1, and the second end of the second section 31-2 extends along the first direction X. The third section 31-3 includes a first end and a second end, the first end of the third section 31-3 is connected to the second end of the second section 31-2, and the second end of the third section 31-3 extends in the opposite direction of the second direction Y. The fourth section 31 - 4 includes a first end and a second end. The first end of the fourth section 31 - 4 is connected to the second end of the third section 31 - 3 , and the second end of the fourth section 31 - 4 extends in the opposite direction to the first direction X.

[0077] In some exemplary embodiments, the substrate 20 may include a single crystal silicon substrate or a semiconductor on insulator (SOI) substrate, etc. For example, the semiconductor on insulator substrate may be a silicon on sapphire (SOS) substrate or a silicon on glass (SOG) substrate, etc. The substrate 20 may be a single layer or a composite layer structure.

[0078] In some exemplary embodiments, the material of the first conductive film may include a metal material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, it may be an alloy material of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and molybdenum-nickel-titanium alloy (MoNiTi). The first conductive film may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti or Mo / Nb / Cu or MoNiTi / Cu or MoNb / Cu / MoNiTi or MoNiTi / Cu / MoNiTi, etc.

[0079] In some exemplary embodiments, the material of the first insulating film 21-1 may include an inorganic material. For example, silicon oxynitride (SiO x N y ) or silicon nitride (SiN x ) or silicon oxide (SiO x ) etc. The first insulating film 21-1 may be a single layer or a composite layer structure.

[0080] (02) Forming a semiconductor layer pattern. Forming a semiconductor layer pattern may include: depositing a semiconductor layer film on the substrate 20 having the aforementioned pattern formed thereon, patterning the semiconductor layer film through a patterning process, so that the semiconductor layer film forms a semiconductor layer pattern located on a side of the first insulating film 21-1 away from the substrate 20, and the semiconductor layer pattern may include at least an active layer 11-4 and a pad layer 40, such as Figure 5A and Figure 5B As shown, Figure 5B for Figure 5A The cross-sectional view at the position marked AA is shown in Figure 5A The first insulating film 21-1 is displayed semi-transparently to facilitate identification of the first conductive layer pattern.

[0081] The orthographic projection of the active layer 11-4 on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the gate line GL on the plane where the substrate 20 is located. For example, the orthographic projection of the active layer 11-4 on the plane where the substrate 20 is located may be located within the orthographic projection of the gate line GL on the plane where the substrate 20 is located. The gate line GL may be used as a light shielding layer for the active layer 11-4 to prevent light from irradiating the active layer 11-4 from one side of the substrate 20, thereby improving the performance of the transistor.

[0082] In some exemplary embodiments, the pad layer 40 may be located on one side of the fourth section 31 - 4 in the second direction Y, and the pad layer 40 is located on one side of the third section 31 - 3 in the opposite direction of the first direction X. The orthographic projection of the pad layer 40 on the plane where the substrate 20 is located does not overlap with the orthographic projection of the first connecting member 31 on the plane where the substrate 20 is located.

[0083] In some exemplary embodiments, the orthographic projection of the cushion layer 40 on the plane where the substrate 20 is located can be a rectangle, square, circle, ellipse, cross, pentagon, hexagon, etc. In the embodiment of the present disclosure, the shape of the orthographic projection of the cushion layer 40 on the plane where the substrate 20 is located is not limited.

[0084] In some exemplary embodiments, the material of the semiconductor layer thin film may include one or more materials selected from the group consisting of indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), and rare earth doped oxide (Ln-OS).

[0085] (03) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: depositing a second conductive film on the substrate 20 having the aforementioned pattern formed thereon, patterning the second conductive film through a patterning process, so that the second conductive film forms a second conductive layer pattern, and the second conductive layer pattern may include at least a first electrode 11-1, a second electrode 11-2, and a data line DL, such as Fig. 6A and Figure 6B As shown, Figure 6B for Fig. 6A The cross-sectional view at the position marked AA is shown in Fig. 6A The first insulating film 21-1 is displayed semi-transparently to facilitate identification of the first conductive layer pattern.

[0086] In some exemplary embodiments, the orthographic projection of the first pole 11-1 on the plane where the substrate 20 is located partially overlaps with the orthographic projection of the active layer 11-4 on the plane where the substrate 20 is located, and the first pole 11-1 is connected to the active layer 11-4. The orthographic projection of the first pole 11-1 on the plane where the substrate 20 is located can be a rectangle extending along the first direction X. However, the embodiment of the present disclosure does not limit the shape of the orthographic projection of the first pole 11-1 on the plane where the substrate 20 is located.

[0087] In some exemplary embodiments, the first electrode 11-1 and the data line DL may be an integral structure connected to each other. The data line DL may be arranged with equal width or unequal width, and the width of the data line DL refers to the dimension perpendicular to the extending direction of the data line DL (ie, the first direction X).

[0088] In some exemplary embodiments, the orthographic projection of the second pole 11-2 on the plane where the substrate 20 is located partially overlaps with the orthographic projection of the active layer 11-4 on the plane where the substrate 20 is located, and the second pole 11-2 is connected to the active layer 11-4. The orthographic projection of the second pole 11-2 on the plane where the substrate 20 is located can be a rectangle, a square, or a hexagon, etc. However, the embodiment of the present disclosure does not limit the shape of the orthographic projection of the second pole 11-2 on the plane where the substrate 20 is located.

[0089] In some exemplary embodiments, the second pole 11-2 may include a first portion 11a, a second portion 11b, and a third portion 11c connected to each other. The orthographic projection of the first portion 11a on the plane where the substrate 20 is located is located within the orthographic projection of the active layer 11-4 on the plane where the substrate 20 is located, and the orthographic projection of the first portion 11a on the plane where the substrate 20 is located may be a rectangle extending along the first direction X. The orthographic projection of the second portion 11b on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the active layer 11-4 on the plane where the substrate 20 is located, and the second portion 11b is located on the side opposite to the second direction Y of the first portion 11a. The orthographic projection of the second portion 11b on the plane where the substrate 20 is located may be a rectangle extending along the second direction Y. The third portion 11c is located on the side opposite to the second direction Y of the second portion 11b, and the orthographic projection of the third portion 11c on the plane where the substrate 20 is located does not overlap with the orthographic projection of the active layer 11-4 on the plane where the substrate 20 is located. The orthographic projection of the third portion 11c on the plane where the substrate 20 is located may be a square. The orthographic projection area of ​​the third part 11c on the plane where the substrate 20 is located is larger than the orthographic projection area of ​​the first part 11a on the plane where the substrate 20 is located, which facilitates the connection of the third part 11c with the subsequently formed pixel electrode to realize the connection between the second pole and the pixel electrode, thereby realizing the connection between the transistor and the pixel electrode.

[0090] In some exemplary embodiments, the material of the second conductive film may be the same as or different from the material of the first conductive film.

[0091] (04) Forming a third insulating layer pattern. Forming the third insulating layer pattern may include: depositing the second insulating film 22-1 and the third insulating film in sequence on the substrate 20 having the aforementioned pattern formed thereon, patterning the third insulating film by a patterning process, so that the third insulating film forms the third insulating layer pattern, such as Fig. 7A and Figure 7B As shown, Figure 7B for Fig. 7A The cross-sectional view at the position marked AA is shown in Fig. 7A The first insulating film 21-1 is displayed transparently, and the second insulating film 22-1 and the third insulating layer 23 are displayed semi-transparently, so as to facilitate identification of the second conductive layer pattern.

[0092] The third insulating layer 23 has a plurality of vias, and the plurality of vias may include at least a first via K11 and a second via K12. The third insulating film located within the first via K11 and the second via K12 is etched away, and a portion of the second insulating film 22-1 is exposed. The orthographic projection of the first via K11 on the plane where the substrate 20 is located overlaps at least partially with the orthographic projection of the third portion 11c of the second pole 11-2 on the plane where the substrate 20 is located. For example, the orthographic projection of the first via K11 on the plane where the substrate 20 is located is located within the orthographic projection of the third portion 11c on the plane where the substrate 20 is located. The first via K11 is used to form a connection hole in a subsequent process. The orthographic projection of the second via K12 on the plane where the substrate 20 is located partially overlaps with the orthographic projection of the pad layer 40 on the plane where the substrate 20 is located, and the orthographic projection of the second via K12 on the plane where the substrate 20 is located partially overlaps with the orthographic projection of the first connecting component 31 on the plane where the substrate 20 is located. The second via K12 is used to form a transfer hole in a subsequent process.

[0093] In some exemplary embodiments, the shapes of the first via hole K11 and the second via hole K12 may be the same or different. The first via hole K11 and the second via hole K12 may be circular holes, elliptical holes, rectangular holes, hexagonal holes, etc. However, the embodiments of the present disclosure do not limit the shapes of the first via hole K11 and the second via hole K12.

[0094] In some exemplary embodiments, the material of the second insulating film 22 - 1 may be the same as or different from the material of the first insulating film 21 - 1 .

[0095] In some exemplary embodiments, the material of the third insulating film may be an organic material. For example, the organic material may be any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, polyether resin, etc. The third insulating film may be a single layer or a composite layer structure.

[0096] (05) Forming a second insulating layer pattern. Forming the second insulating layer pattern may include: based on the substrate 20 formed with the aforementioned pattern, based on the first via hole K11 and the second via hole K12, patterning the second insulating film 22-1 and the first insulating film 21-1 through a patterning process, so that the second insulating film 22-1 forms a second insulating layer pattern, and the first insulating film 21-1 forms a first insulating layer pattern, such as Fig. 8A and Figure 8B As shown, Figure 8B for Fig. 8A The cross-sectional view at the position marked AA is shown in Fig. 8A The first insulating layer 21 is displayed transparently, and the second insulating layer 22 and the third insulating layer 23 are displayed semi-transparently, so as to facilitate identification of the second conductive layer pattern.

[0097] The array substrate includes at least one connection hole K1 and at least one transfer hole K2, the first via hole K11 constitutes part of the connection hole K1, and the second via hole K12 constitutes part of the transfer hole K2. The orthographic projection of the connection hole K1 on the plane where the substrate 20 is located overlaps at least partially with the orthographic projection of the third part 11c of the second pole 11-2 on the plane where the substrate 20 is located. For example, the orthographic projection of the connection hole K1 on the plane where the substrate 20 is located is located within the orthographic projection of the third part 11c on the plane where the substrate 20 is located, and the connection hole K1 exposes part of the third part 11c of the second pole 11-2. The pixel electrode formed in the subsequent process can be connected to the second pole 11-2 via the connection hole K1. The orthographic projection of the adapter hole K2 on the plane where the substrate 20 is located overlaps with the orthographic projection of the pad layer 40 on the plane where the substrate 20 is located, and the orthographic projection of the adapter hole K2 on the plane where the substrate 20 is located overlaps with the orthographic projection of the first connecting component 31 on the plane where the substrate 20 is located, and the adapter hole K2 exposes a portion of the pad layer 40 and a portion of the first connecting component 31.

[0098] In some exemplary embodiments, the pad layer 40 includes a top portion 40a and a side portion 40b connected to each other, the top portion 40a is parallel to the plane where the substrate 20 is located, and the side portion 40b is located between the top portion 40a and the substrate 20. The transfer hole K2 exposes a portion of the top portion 40a and a portion of the side portion 40b, and the top portion 40a and the side portion 40b exposed by the transfer hole K2 together form a step feature, which can enable the second connecting component formed subsequently to form a first step structure, and the first step structure is conducive to changing the tension of the alignment film.

[0099] In some exemplary embodiments, the first connecting component 31 includes a top wall 31a and a side wall 31b connected to each other, the top wall 31a is parallel to the plane where the substrate 20 is located, and the side wall 31b is located between the top wall 31a and the substrate 20. The transfer hole K2 exposes a portion of the top wall 31a and a portion of the side wall 31b of the first connecting component 31, and the top wall 31a and the side wall 31b exposed by the transfer hole K2 together form a step feature, which can enable the second connecting component formed subsequently to form a second step structure, and the second step structure is conducive to changing the tension of the alignment film.

[0100] (06) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: depositing a third conductive film on the substrate 20 having the aforementioned pattern formed thereon, patterning the third conductive film through a patterning process, so that the third conductive film forms a third conductive layer pattern, and the third conductive layer pattern may include at least the pixel electrode 10 and the second connecting member 32, such as Fig.9A and Fig. 9B As shown, Fig. 9B for Fig.9A The cross-sectional view at the position marked AA is shown in Fig.9A The first insulating layer 21 is displayed transparently, and the second insulating layer 22 and the third insulating layer 23 are displayed semi-transparently, so as to facilitate identification of the second conductive layer pattern.

[0101] The orthographic projection of the pixel electrode 10 on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the connection hole K1 on the plane where the substrate 20 is located. For example, the orthographic projection of the pixel electrode 10 on the plane where the substrate 20 is located includes the orthographic projection of the connection hole K1 on the plane where the substrate 20 is located. The pixel electrode 10 is connected to the second pole 11-2 via the connection hole K1. The orthographic projection of the second connecting component 32 on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the transfer hole K2 on the plane where the substrate 20 is located. For example, the orthographic projection of the second connecting component 32 on the plane where the substrate 20 is located includes the orthographic projection of the transfer hole K2 on the plane where the substrate 20 is located. The second connecting component 32 is connected to the pad layer 40 and the first connecting component 31 via the transfer hole K2.

[0102] In some exemplary embodiments, the orthographic projection of the pixel electrode 10 on the plane where the substrate 20 is located can be a square, a rectangle, or an irregular shape, etc. However, the embodiments of the present disclosure do not limit the shape of the orthographic projection of the pixel electrode 10 on the plane where the substrate 20 is located.

[0103] In some exemplary embodiments, the third conductive film may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0104] Taking the cushion layer, the first electrode and the second electrode as an example, the preparation process of the array substrate may include:

[0105] (11) Forming a semiconductor layer pattern. Forming a semiconductor layer pattern may include: depositing a first conductive film on the substrate 20, and patterning the first conductive film through a patterning process so that the first conductive film forms a first conductive layer pattern on the substrate 20, and the first conductive layer pattern may include at least the gate line GL, the gate electrode 11-3, and the first connection member 31.

[0106] Then, a first insulating film 21-1 is deposited on the substrate 20 having the aforementioned pattern formed thereon. Fig. 10A and Fig. 10B As shown, Fig. 10B for Fig. 10A The cross-sectional view at the position marked BB in the figure is Fig. 10A In the embodiment, the first insulating film 21-1 is displayed semi-transparently to facilitate identification of the first conductive layer pattern.

[0107] Subsequently, a semiconductor layer film is deposited on the substrate 20 having the aforementioned pattern formed thereon, and the semiconductor layer film is patterned by a patterning process, so that the semiconductor layer film forms a semiconductor layer pattern located on the side of the first insulating film 21-1 away from the substrate 20, and the semiconductor layer pattern may include at least an active layer 11-4, such as Fig. 10A and Fig. 10B For other details, please refer to the description of the above embodiments, which will not be elaborated here.

[0108] (12) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: depositing a second conductive film on the substrate 20 having the aforementioned pattern formed thereon, patterning the second conductive film through a patterning process, so that the second conductive film forms a second conductive layer pattern, and the second conductive layer pattern may include at least the first electrode 11-1, the second electrode 11-2, the data line DL, and the pad layer 40, such as Fig.11A and Fig. 11B As shown, Fig. 11B for Fig.11A The cross-sectional view at the position marked BB in the figure is Fig.11AThe first insulating film 21-1 is semi-transparently displayed so as to facilitate identification of the first conductive layer pattern. Other details can be referred to the description of the above embodiment and will not be elaborated here.

[0109] (13) Forming a third insulating layer pattern. Forming the third insulating layer pattern may include: depositing the second insulating film 22-1 and the third insulating film in sequence on the substrate 20 having the aforementioned pattern, and patterning the third insulating film through a patterning process so that the third insulating film forms the third insulating layer pattern, such as Fig. 12A and Fig. 12B As shown, Fig. 12B for Fig. 12A The cross-sectional view at the position marked BB in the figure is Fig. 12A The first insulating film 21-1 is displayed transparently, and the second insulating film 22-1 and the third insulating layer 23 are displayed semi-transparently, so as to facilitate identification of the second conductive layer pattern.

[0110] The third insulating layer 23 has a plurality of via holes, which may include at least a first via hole K11 and a second via hole K12. The third insulating film located within the first via hole K11 and the second via hole K12 is etched away, and a portion of the second insulating film 22-1 is exposed. The first via hole K11 is used to form a connection hole in a subsequent process, and the second via hole K12 is used to form a transfer hole in a subsequent process. For other details, please refer to the description of the aforementioned embodiment, which will not be elaborated here.

[0111] (14) Forming a second insulating layer pattern. Forming the second insulating layer pattern may include: based on the substrate 20 formed with the aforementioned pattern, based on the first via hole K11 and the second via hole K12, patterning the second insulating film 22-1 and the first insulating film 21-1 through a patterning process, so that the second insulating film 22-1 forms a second insulating layer pattern, and the first insulating film 21-1 forms a first insulating layer pattern, such as Fig.13A and Fig. 13B As shown, Fig. 13B for Fig.13A The cross-sectional view at the position marked BB in the figure is Fig.13A The first insulating layer 21 is displayed transparently, and the second insulating layer 22 and the third insulating layer 23 are displayed semi-transparently, so as to facilitate identification of the second conductive layer pattern.

[0112] The array substrate includes at least one connection hole K1 and at least one transfer hole K2, the first via hole K11 constitutes part of the connection hole K1, and the second via hole K12 constitutes part of the transfer hole K2. The orthographic projection of the connection hole K1 on the plane where the substrate 20 is located overlaps at least partially with the orthographic projection of the third part 11c of the second pole 11-2 on the plane where the substrate 20 is located. For example, the orthographic projection of the connection hole K1 on the plane where the substrate 20 is located is located within the orthographic projection of the third part 11c on the plane where the substrate 20 is located, and the connection hole K1 exposes part of the third part 11c of the second pole 11-2. The pixel electrode formed in the subsequent process can be connected to the second pole 11-2 via the connection hole K1. The orthographic projection of the transfer hole K2 on the plane where the substrate 20 is located overlaps with the orthographic projection of the cushion layer 40 on the plane where the substrate 20 is located, and the orthographic projection of the transfer hole K2 on the plane where the substrate 20 is located overlaps with the orthographic projection of the first connecting component 31 on the plane where the substrate 20 is located, and the transfer hole K2 exposes a portion of the cushion layer 40 and a portion of the first connecting component 31. For other details, please refer to the description of the aforementioned embodiment, which will not be elaborated here.

[0113] (15) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: depositing a third conductive film on the substrate 20 having the aforementioned pattern, patterning the third conductive film through a patterning process, so that the third conductive film forms a third conductive layer pattern, and the third conductive layer pattern may include at least a pixel electrode 10 and a second connecting component 32, wherein the orthographic projection of the pixel electrode 10 on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the connecting hole K1 on the plane where the substrate 20 is located, and in an example, the orthographic projection of the pixel electrode 10 on the plane where the substrate 20 is located includes the orthographic projection of the connecting hole K1 on the plane where the substrate 20 is located. The pixel electrode 10 is connected to the second electrode 11-2 via the connecting hole K1. The orthographic projection of the second connecting component 32 on the plane where the substrate 20 is located at least partially overlaps with the orthographic projection of the transfer hole K2 on the plane where the substrate 20 is located, and in an example, the orthographic projection of the second connecting component 32 on the plane where the substrate 20 is located includes the orthographic projection of the transfer hole K2 on the plane where the substrate 20 is located. The second connecting component 32 is connected to the pad layer 40 and the first connecting component 31 via the transfer hole K2. For other details, please refer to the description of the aforementioned embodiments, which will not be elaborated here.

[0114] The method for preparing the array substrate provided in the embodiment of the present disclosure can be implemented using existing mature preparation equipment and can be prepared without adding any additional steps. The preparation process is simple, the production cost is low, the production precision is high, and it has good application prospects.

[0115] The embodiment of the present disclosure further provides a display device, which may include the array substrate provided by any of the above embodiments. The display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function, and the embodiment of the present disclosure is not limited thereto.

[0116] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions or omissions may be made to the forms and details of implementation without departing from the scope of the present disclosure.

Claims

1. An array substrate, characterized in that: The invention comprises a display area and a non-display area located at least on one side of the display area; the display area comprises a substrate and at least one switching structure located on the substrate; the switching structure comprises a first connecting component and a second connecting component located on different conductive layers, and the first connecting component is closer to the substrate than the second connecting component; The display area further comprises at least one insulating layer, the at least one insulating layer is provided with at least one transfer hole, the transfer hole exposes a portion of the first connecting component, and a portion of the second connecting component is located within the transfer hole and contacts the first connecting component; The second connecting component has at least one first step structure, and the at least one first step structure is located between the bottom and top of the adapter hole; The display area further includes an alignment film, and a portion of the alignment film is in contact with the first step structure.

2. The array substrate according to claim 1, characterized in that: The first step structure includes a first step and a second step connected to each other, the first step extends along a plane parallel to the substrate, and the second step is located between the first step and the substrate; a portion of the alignment film contacts both the first step and the second step.

3. The array substrate according to claim 2, characterized in that: The display area further comprises at least one cushion layer, and the at least one cushion layer is located between the bottom and top of the transfer hole; the cushion layer comprises a top portion and a side portion connected to each other, the top portion is parallel to the plane where the substrate is located, and the side portion is located between the top portion and the substrate; The transfer hole exposes a portion of the top and a portion of the side; The first step is in contact with the top, and the second step is in contact with the side.

4. The array substrate according to claim 3, characterized in that: The orthographic projection of the cushion layer on the plane where the substrate is located is a ring, and the orthographic projection of the switching hole on the plane where the substrate is located is located inside the outer contour of the ring.

5. The array substrate according to claim 3, characterized in that: The orthographic projections of the two or more cushion layers on the plane where the substrate is located are arranged around the hole center of the orthographic projection of the transfer hole on the plane where the substrate is located.

6. The array substrate according to claim 3, characterized in that: The display area further includes at least one transistor, and the transistor includes a first electrode, a second electrode, an active layer and a gate electrode; the pad layer and the active layer are in the same layer structure.

7. The array substrate according to claim 3, characterized in that: The display area further includes at least one transistor, and the transistor includes a first electrode, a second electrode, an active layer and a gate electrode; the pad layer is in the same layer structure as the first electrode and the second electrode.

8. The array substrate according to claim 3, characterized in that: The orthographic projection of the cushion layer on the plane where the substrate is located is a rectangle, a circle, an ellipse, a cross, a pentagon, or a hexagon.

9. The array substrate according to any one of claims 1 to 8, characterized in that: The second connecting component further has at least one second step structure, and the at least one second step structure is located at the bottom of the transfer hole; a portion of the alignment film is in contact with the second step structure.

10. The array substrate according to claim 9, characterized in that: The second step structure includes a third step and a fourth step connected to each other, and the third step extends along a plane parallel to the substrate, and the fourth step is located between the third step and the substrate; a portion of the alignment film is in contact with both the third step and the fourth step.

11. The array substrate according to claim 10, characterized in that: The first connecting component includes a top wall and a side wall connected to each other, the top wall is parallel to the plane where the substrate is located, and the side wall is located between the top wall and the substrate; The transfer hole exposes a portion of the top wall and a portion of the side wall, the third step contacts the top wall, and the fourth step contacts the side wall.

12. The array substrate according to any one of claims 3 to 8, characterized in that: The display area further includes a first conductive layer, a second conductive layer and a third conductive layer which are sequentially stacked on the substrate; the first connecting component is located in the first conductive layer, and the second connecting component is located in the third conductive layer.

13. The array substrate according to claim 12, characterized in that: The display area also includes a first insulating layer and a semiconductor layer stacked in sequence on the side of the first conductive layer away from the substrate, and a second insulating layer and an organic insulating layer stacked in sequence on the side of the second conductive layer away from the substrate; the pad layer is located in the semiconductor layer.

14. The array substrate according to claim 12, wherein: The display area also includes a first insulating layer and a semiconductor layer stacked in sequence on the first conductive layer away from the substrate, and a second insulating layer and an organic insulating layer stacked in sequence on the second conductive layer away from the substrate; the pad layer is located in the second conductive layer.

15. A display device, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 14.

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