Method, apparatus, device, and medium for processor resource allocation

Abstract

Provided are a method, device, apparatus, and medium for processor resource allocation. The method comprises: obtaining lifespans of a plurality of storage objects in a plurality of instructions of a program to be compiled, the lifespan of a first storage object in the plurality of storage objects comprising a sequence of instructions involved between a start instruction at which the first storage object is used for the first time and an end instruction at which the first storage object is used for the last time, and in the lifespan of the first storage object, the first storage object is in a live state; and allocating storage resources to storage objects in a live state in the plurality of instructions, the allocation of storage resources to storage objects in a live state in a first instruction in the plurality of instructions being prioritized over the allocation of storage resources to storage objects in a live state in a second instruction in the plurality of instructions, and a total storage amount of storage objects in a live state in the first instruction being greater than a total storage amount of storage objects in a live state in the second instruction.

Description

TECHNICAL FIELD

[0001] At least one embodiment of the present disclosure relates to the field of artificial intelligence, and more particularly to a method for processor resource allocation in program compilation process, an apparatus for processor resource allocation in program compilation process, an electronic device, and a non-transitory computer-readable storage medium. BACKGROUND

[0002] In the field of artificial intelligence, convolutional neural networks are often used to process image and video data to extract features in images, thereby enabling effective recognition and understanding of images. Both training and inference of convolutional neural networks require the use of programs involving tensor operations. Such programs are usually run using general-purpose computing on graphics processing units (GPGPU), graphics processing units (GPU), and other graphics processors. In the field of compilation of such programs, it is necessary to map variables, arrays, matrices, tensors, and other storage objects in the program to appropriate memory locations, i.e., to assign physical addresses of storage resources to variables, arrays, matrices, tensors, and other storage objects in the program, so that these variables, arrays, matrices, tensors, and other storage objects can store data at the assigned physical addresses during program execution. There are various types of storage objects that need to be assigned physical addresses of storage resources. For example, in GPGPU, GPU, and other graphics processors, storage resources include registers, shared memory, descriptor indexes, constant memory addresses, synchronization barriers, and so on. In traditional approaches, some storage objects are manually assigned storage resources by programmers, and some storage objects are assigned storage resources by drivers or compilers. SUMMARY

[0003] According to one aspect of the present disclosure, at least one embodiment provides a method for processor resource allocation, comprising: obtaining lifetimes of a plurality of storage objects in a plurality of instructions of a program to be compiled, wherein a lifetime of a first storage object in the plurality of storage objects comprises a sequence of instructions between a start instruction at which the first storage object is used for the first time and an end instruction at which the first storage object is used for the last time, and the first storage object is in a live state in the lifetime of the first storage object; and allocating storage resources to the storage objects in the live state in the plurality of instructions, wherein allocating the storage resources to the storage objects in the live state in a first instruction in the plurality of instructions is prioritized over allocating the storage resources to the storage objects in the live state in a second instruction in the plurality of instructions, and a total storage amount of the storage objects in the live state in the first instruction is greater than a total storage amount of the storage objects in the live state in the second instruction.

[0004] According to another aspect of the present disclosure, at least one embodiment provides an apparatus for processor resource allocation, comprising: an obtaining module configured to obtain lifetimes of a plurality of storage objects in a plurality of instructions of a program to be compiled, wherein a lifetime of a first storage object in the plurality of storage objects comprises a sequence of instructions between a start instruction at which the first storage object is used for the first time and an end instruction at which the first storage object is used for the last time, and the first storage object is in a live state in the lifetime of the first storage object; and an allocating module configured to allocate storage resources to the storage objects in the live state in the plurality of instructions, wherein allocating the storage resources to the storage objects in the live state in a first instruction in the plurality of instructions is prioritized over allocating the storage resources to the storage objects in the live state in a second instruction in the plurality of instructions, and a total storage amount of the storage objects in the live state in the first instruction is greater than a total storage amount of the storage objects in the live state in the second instruction.

[0005] According to another aspect of the present disclosure, at least one embodiment provides an apparatus for processor resource allocation, comprising: a storage apparatus for storing computer instructions; and a processing apparatus for reading the computer instructions in the storage apparatus and executing a method according to at least one embodiment of the present disclosure.

[0006] According to another aspect of the present disclosure, at least one embodiment provides an electronic device comprising an apparatus for processor resource allocation according to at least one embodiment of the present disclosure.

[0007] According to another aspect of the present disclosure, at least one embodiment provides a non-transitory computer readable storage medium having computer instructions stored thereon, wherein the computer instructions, when executed by a processing apparatus, cause the processing apparatus to perform a method according to at least one embodiment of the present disclosure.

[0008] According to another aspect of the present disclosure, at least one embodiment provides a computer program product comprising computer instructions, wherein the computer instructions, when executed by a processing device, cause the processing device to perform a method according to at least one embodiment of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0010] Figure 1 A flow chart of a method of processor resource allocation according to at least one embodiment of the present disclosure is shown.

[0011] Figure 2A And Figure 2B A schematic diagram of instruction control flow of a program according to at least one embodiment of the present disclosure is shown.

[0012] Figure 3 A schematic diagram of the correspondence between each instruction in a program segment and a storage object in a live state according to at least one embodiment of the present disclosure is shown.

[0013] Figure 4 A schematic diagram of the correspondence between the lifetime of a storage object and the instructions of the storage object in the case of Figure 3 according to at least one embodiment of the present disclosure is shown.

[0014] Figure 5 A block diagram of an apparatus of processor resource allocation according to at least one embodiment of the present disclosure is shown.

[0015] Figure 6 A block diagram of an exemplary apparatus of processor resource allocation according to at least one embodiment of the present disclosure is shown.

[0016] Figure 7 A schematic diagram of a non-transitory computer-readable storage medium according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0017] Referring now to specific embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. Although this application will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit this application to the described embodiments. Rather, it is intended to cover variations, modifications, and equivalents included within the spirit and scope of this disclosure. It should be noted that the method steps described herein can be implemented by any functional block or functional arrangement, and any functional block or functional arrangement can be implemented as a physical entity or a logical entity, or a combination of both.

[0018] In this article, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0019] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0020] In artificial intelligence scenarios, a large number of tensor operations are needed to perform convolution, matrix multiplication and other operations for training and inference of artificial intelligence models, which can be applied to natural language processing, image processing and computer vision, medical fields, recommendation systems and personalized push, intelligent transportation and logistics, games and entertainment, and so on.

[0021] However, existing open-source compilers are typically designed for Central Processing Unit (CPU) architectures, and their register or memory resource allocation methods are not entirely suitable for the tensor operations used in artificial intelligence applications with General Purpose Graphics Cards (GPGPUs) or Graphics Processing Units (GPUs). Traditionally, memory allocation only begins when a memory object requires allocation, at which point only fragmented memory resources may remain. Therefore, it's difficult to allocate a complete tensor to a single address block in memory resources such as registers, potentially leading to further fragmentation. Traditional compilers describe program data flow in a complex way, making the design of customized memory allocation algorithms difficult and hard to optimize. Manual memory allocation methods place high demands on programmers and have low development efficiency.

[0022] The defects and problems existing in the above-mentioned prior art solutions are the result of careful research through practice and creative labor. The discovery process of the above problems and the solutions proposed by at least one embodiment disclosed below for the above problems are all contributions to the inventiveness.

[0023] At least one embodiment of the present disclosure proposes a processor resource allocation scheme in a program compilation process. The scheme can be applied to a scenario of executing a program including tensor operations by a GPGPU, in which, in the program compilation process, the live interval of each storage object of the program is analyzed based on the structured control flow of the instruction control flow of the program, and the storage resource of each instruction is allocated and recycled with respect to the storage object of the instruction in the order from more to less (or from more to less) of the total storage amount of the storage object having the live state of the instruction. The scheme is simple in design and more suitable for the scenario of executing a program including tensor operations by a GPGPU. The scheme only needs to traverse the instruction control flow once to perform live interval analysis, reducing the complexity of live interval analysis caused by the unstructured control flow of the program. The allocation and recycling of the storage object can be performed according to the live interval of the storage object corresponding to the instruction, which can reduce the fragmentation of the storage resource and improve the efficiency of program execution and the utilization effect of the storage resource. The scheme can uniformly perform centralized resource allocation of all storage resources, thereby improving the allocation efficiency. At the same time, the resource allocation scheme can be applied to independent resource pools of different types of resources (which need to be recycled or do not need to be recycled), and adapt to different allocation strategies. The resource allocation scheme also proposes a twice allocation scheme: the first allocation is for the non-temporary resource required by the live interval of the cross-tensor instruction (Tensor instruction) operating on a tensor as a unit (which is recycled after the end of the live interval), and the second allocation is for the temporary resource required by the machine instruction generated by the lower() method in the running process of the cross-tensor instruction (which is recycled immediately after the execution of the tensor instruction), thereby adapting different allocation strategies to different types of resources and reasonably and appropriately allocating storage resources.

[0024] Figure 1 A flowchart of a method of processor resource allocation in a program compilation process according to at least one embodiment of the present disclosure is shown.

[0025] Here, the program can include, for example, a program with a simplified control flow that takes a tensor as a processing object, which can be written in a triton language, a Tensor Virtual Machine (TVM) Tensor Expression, or the like designed for deep learning, high-performance computing, and the like. The program usually includes multiple instruction categories, such as loop instructions, instructions of conditional branching structures, instructions of sequential execution structures, and the like, which can include specific tensor matrix multiplication instructions, tensor convolution instructions, bias addition instructions, and the like.

[0026] The program needs to be compiled before it is actually executed. The compilation process of the program is the process of converting the source code written in a high-level programming language (such as CUDA, etc.) into machine code that the computer can directly execute. This process is usually divided into several stages, including preprocessing, compiling, assembling and linking. The preprocessing stage is the first stage of the compilation process, which mainly processes precompiled instructions and macro definitions in the source code. The compilation stage converts the preprocessed source code into intermediate code or assembly code. The assembly stage converts the assembly language code generated by the compiler into machine language instructions (i.e. machine code). The linking stage links the object files (containing machine code) generated by the assembler with standard libraries and other external code libraries to generate the final executable file. In the compilation process of the program, the physical addresses of the storage resources need to be allocated to the storage objects such as variables, arrays, matrices, tensors, etc. in the program to ensure that these storage objects have a determined location in the storage resources during the running process of the program, so that the processor can efficiently access them and perform specific operations.

[0027] The execution subject of the method provided by the embodiments of the present disclosure is generally a computer device with certain computing power, such as a computer device including a processing device and a storage device. In the present embodiment, the processing device can be a CPU, a GPGPU or a GPU, and the storage device can be a random access memory (RAM), a read-only memory (ROM), a flash memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a floppy disk, a solid state disk, a removable disk, a CD-ROM, a DVD-ROM, a Blu-ray disc, etc. The computer device is particularly suitable for allocating storage resources of a GPGPU or GPU processor performing tensor operations in the compilation process of a tensor operation program. Of course, the computer device can also allocate storage resources of a CPU processor in the compilation process of a program running on the CPU.

[0028] Figure 1 The method of processor resource allocation in the program compilation process shown includes steps 110, 120.

[0029] In step 110, the lifetimes of a plurality of storage objects in a plurality of instructions of a program to be compiled are obtained.

[0030] The storage objects can include variables, arrays, matrices, tensors, etc.

[0031] The lifetime of a first storage object among the plurality of storage objects includes a sequence of instructions involved between a start instruction at which the first storage object is first used and an end instruction at which the first storage object is last used. The main purpose of lifetime acquisition is to determine the live interval of each storage object (e.g. variable) in a program, i.e. in which instructions or basic blocks the variable is live (i.e. used or possibly used, but not yet redefined). Lifetime acquisition can include analyzing the lifetime of the plurality of storage objects in the plurality of instructions of the program during program compilation, or can include obtaining the lifetime of the plurality of storage objects in the plurality of instructions of the program from elsewhere, which has been analyzed.

[0032] It is noted here that lifetime in this disclosure is not a time concept in a general sense, but a concept at the instruction level, i.e. in which instructions the storage object will be live, i.e. used, and when the storage object should have corresponding storage resource to store the data corresponding to the storage object. In the program compilation process (not the actual execution process of the program), the storage resource should be allocated in advance for these storage objects, and therefore the specific time of the live of the storage object when the program is running is not concerned in the program compilation process, but it is concerned in which instruction or instructions the storage object should be live (i.e. defined or used) or not live (i.e. not used or redefined).

[0033] That is, in this document, the lifetime of a storage object includes a plurality of instructions, i.e. in these plurality of instructions, the storage object is live or alive. That is, in the lifetime (including instructions) of the first storage object, the first storage object is in the alive state. It is noted here that the "first" in the first storage object does not specifically refer to a particular storage object or the first storage object in any order, but refers to any storage object among the plurality of storage objects. That is, each storage object among the plurality of storage objects can have the same operation or definition as the first storage object.

[0034] In at least one embodiment, the step 110 of acquiring the lifetime of the plurality of storage objects in the plurality of instructions of the program to be compiled includes the following steps.

[0035] The instruction control flow of the program is traversed to determine a plurality of antecedent instructions and a plurality of consequent instructions of the instruction using the first storage object among the plurality of storage objects. A first antecedent instruction of the plurality of antecedent instructions in which the first storage object is first used and a last consequent instruction of the plurality of consequent instructions in which the first storage object is last used are determined. A lifetime of the first storage object is determined based on the first antecedent instruction of the plurality of antecedent instructions in which the first storage object is first used and the last consequent instruction of the plurality of consequent instructions in which the first storage object is last used. All instructions included during the lifetime of the first storage object are obtained as an instruction sequence corresponding to the first storage object in a live state.

[0036] The instruction control flow of the program can represent an abstract data structure of the execution order and logical dependency relationship between instructions in the program. This can be constructed by performing static analysis on the source code of the program to extract the dependency relationship and execution order between instructions. The instruction control flow can be described in a structured control flow. The structured control flow can include the structure of the execution order (also known as linear), branch selection, and loop repetition of instructions in the program. That is, the plurality of instructions of the program can include one or more of instructions of sequential execution structure, instructions of conditional branch structure, and instructions of loop structure. In the sequential execution structure, the instructions are executed in the order from top to bottom as written. The if, else, else if, and switch instructions and the corresponding branch execution instructions are provided to implement the conditional branch structure. In the conditional branch structure, different branch instructions are executed according to the condition judgment. The for, while, and do-while statements are provided to implement the loop structure. In the loop structure, some instructions are repeatedly executed until a specific termination condition is met. Because the three types of structures can be recursively called, and other arbitrary basic instruction blocks jump to irregular control flow of arbitrary basic instruction blocks (such as function calls, exception handling, etc.) can not be described, such a description method has good adaptability to artificial intelligence applications of tensor operations. Thus, the scheme according to at least one embodiment of the present disclosure is more suitable for the scenario of GPGPU or GPU executing programs including tensor operations.

[0037] Note that control flow is often represented by graphs. A graph of control flow often includes nodes and edges, where nodes represent instructions or basic blocks of a program, and edges represent control flow transitions. For two nodes A and B in a graph of control flow, A dominates B if every path from the entry node of the program to B must pass through A. In this case, A is called a pre-dominator of B, and the instruction represented by A is called a pre-dominator instruction of B. If A is a post-dominator of B, it means that every path from B to the exit node of the program must pass through A (or, under some definitions, to a certain specific node). In this case, the instruction represented by A can be called a post-dominator instruction of B.

[0038] Figure 2A and Figure 2B A schematic diagram of instruction control flow of a program is shown, in accordance with at least one embodiment of the present disclosure.

[0039] As Figure 2A shown, the instruction control flow of the program includes instructions beforeIf use a of a sequential execution structure, instructions If of a conditional branch structure, instructions IfTrue use a, IfFalse use a of the sequential execution structure, and instructions afterIf. The instructions that use the storage object a (variable a) include the beforeIf use a instruction, the IfTrue use a instruction, and the IfFalse use a instruction. The pre-dominator instruction of the beforeIf use a instruction is one instruction before it (not shown), and the post-dominator instruction is the If instruction. The pre-dominator instruction of the IfTrue use a instruction is the If, and the post-dominator instruction is the afterIf. The pre-dominator instruction of the IfFalse use a instruction is the If, and the post-dominator instruction is the afterIf instruction. It can be seen that the common post-dominator instruction of the IfTrue use a instruction and the IfFalse use a instruction is the afterIf instruction.

[0040] As Figure 2BAs shown, the instruction control flow of the program includes the instruction beforeloop usea of the sequential execution structure, the instruction loop of the loop repetition structure, the instruction loopBody usea, and the instruction afterLoop of the sequential execution structure. The instructions using the storage object a (variable a) include the instruction beforeLoop usea and the instruction loopBody usea. The preceding dominator instruction of the instruction beforeLoop usea is an instruction (not shown) before the instruction, and the succeeding dominator instructions of the instruction beforeLoop usea are the instruction loop, the instruction loopBody usea, and the instruction afterLoop. The preceding dominator instruction of the instruction loopBody usea is the instruction loop, and the succeeding dominator instruction of the instruction loopBody usea is the instruction afterLoop. It can be seen that the common succeeding dominator instruction of the instruction beforeLoop usea and the instruction loopBody usea is the instruction afterLoop.

[0041] Continuing the traversal, all the preceding dominator instructions and the succeeding dominator instructions of all the instructions using the variable a are obtained, and some of the instructions may be common. In this way, the preceding dominator instruction of the starting instruction in which the storage object a is used for the first time and the succeeding dominator instruction of the ending instruction in which the storage object a is used for the last time can be determined. Based on the preceding dominator instruction of the starting instruction in which the storage object a is used for the first time and the succeeding dominator instruction of the ending instruction in which the storage object a is used for the last time, the lifetime of the storage object a can be determined, for example, all the instructions between the preceding dominator instruction of the starting instruction in which the storage object a is used for the first time and the succeeding dominator instruction of the ending instruction in which the storage object a is used for the last time (excluding the preceding dominator instructions and the succeeding dominator instructions not using the storage object a), so as to obtain all the instructions included in the lifetime of the first storage object as the instruction sequence corresponding to the first storage object in the alive state.

[0042] In this way, the lifetime analysis can be performed only by traversing the instruction control flow once, reducing the complexity of the lifetime analysis caused by the unstructured control flow of the program.

[0043] According to the lifetimes of the plurality of storage objects, the correspondence between each of the plurality of instructions and the storage object in the alive state can be determined.

[0044] Figure 3 A schematic diagram showing the correspondence between each of the instructions in a program segment and the storage object in the alive state according to at least one embodiment of the present disclosure is shown.

[0045] As described before, the lifetime (of instructions) of each storage object is obtained, and the correspondence between the storage object and the instructions can be obtained. However, in order to better perform the method of at least one embodiment of the present disclosure, the reverse mapping can be performed, i.e., the storage object corresponding to the instructions is mapped to the instructions corresponding to the storage object.

[0046] As shown in Figure 3 , according to the lifetime of the plurality of storage objects, the correspondence between each instruction in the plurality of instructions and the storage object in the alive state can be determined.

[0047] For example, the lifetime of the storage object a includes the instruction instr1(a), the instruction Loop() (including each instruction in Loop()).

[0048] The lifetime of the storage object b includes the instruction instr3(b, c), instr4(c), instr5(b), if, instr6(d) in the if instruction, and instr7(b). Note that although instr4(c), instr5(b), and instr6(d) in the if instruction do not actually use the storage object b, the storage object b cannot be released from the storage resource during the execution of these instructions because the subsequent instr7(b) needs to use the storage object b for the last time. Therefore, the lifetime of the storage object b should include all instructions from the instruction in which the storage object b is first used to the instruction in which the storage object b is last used. In this way, the storage resource allocation scheme can be designed more simply, and sufficient storage resources can be reserved to ensure the normal execution of the program.

[0049] The lifetime of the storage object c includes the instruction instr3(b, c) and instr4(c).

[0050] The lifetime of the storage object d includes the instruction Loop() (including each instruction in Loop()) and instr8(d). Note that although the storage object d is not needed to be used in instr6(d) in the first loop of the instruction Loop(), the storage resource allocated for the storage object d is needed to be used after that and in the subsequent loops. Therefore, the lifetime of the storage object d is extended to the instruction Loop() (including each instruction in Loop()), so that the storage resource allocation scheme can be designed more simply, and sufficient storage resources can be reserved to ensure the normal execution of the program.

[0051] Thus, as shown in Figure 3 , the storage object in the alive state corresponding to each instruction can be obtained.

[0052] Figure 4 shows the method of allocating the storage resource according to at least one embodiment of the present disclosure. Figure 3Fig. 1 shows a schematic diagram of the correspondence between the lifetime of a storage object and the instructions of the storage object in the case where the storage object is alive.

[0053] As shown in Fig. 1, the lifetime of storage object a is shown as 410, the lifetime of storage object b is shown as 420, the lifetime of storage object c is shown as 430, and the lifetime of storage object d is shown as 440. The vertical dashed lines cross the storage objects that are alive at the time of the instructions. Figure 4

[0054] In the example shown in Fig. 1, it is assumed that the data format of storage objects a, b, c is INT 16, which determines a capacity of 2 bytes, and the data format of storage object d is INT 32, which determines a capacity of 4 bytes.

[0055] The total storage of the storage objects that are alive at the time of an instruction can be calculated as the sum of the capacities determined by the data formats of the storage objects that are alive at the time of the instruction.

[0056] Thus, the total storage of the storage objects that are alive at the time of each instruction can be determined. For example, the total storage of the storage objects that are alive at the time of instruction instrl(a) is 2 bytes; the total storage of the storage objects that are alive at the time of instruction Loop() is 6 bytes; the total storage of the storage objects that are alive at the time of instruction instr2(a) is 6 bytes; the total storage of the storage objects that are alive at the time of instruction instr3(b,c) is 10 bytes; the total storage of the storage objects that are alive at the time of instruction instr4(c) is 10 bytes; the total storage of the storage objects that are alive at the time of instruction instr5(b) is 8 bytes; the total storage of the storage objects that are alive at the time of instruction if() is 8 bytes; the total storage of the storage objects that are alive at the time of instruction instr6(d) is 6 bytes; the total storage of the storage objects that are alive at the time of instruction instr7(b) is 8 bytes; and the total storage of the storage objects that are alive at the time of instruction instr8(d) is 4 bytes.

[0057] Thus, the relationship between the total storage of the storage objects that are alive at the time of multiple instructions can be determined, e.g., which instruction(s) corresponds to the most or more (e.g., at least more than or equal to a first total storage threshold) total storage of the storage objects that are alive.

[0058] ​The total storage amount of the storage objects in the survival state corresponding to the instruction being the most or more means that when the instruction is run, storage resources need to be allocated for the storage objects with the most or more total storage amount. If the program execution can prioritize (for example, the earlier in time or the higher in priority) the allocation of sufficient storage resources for the storage objects with the most or more total storage amount, at this time the storage resources are not allocated too much, the whole block of storage resources can be allocated as much as possible, instead of only fragmented storage resources being available for allocation. If the storage objects that need to be allocated storage resources are encountered to start the allocation as in the traditional way, or all storage objects are allocated resources with the same priority, it will lead to that when the subsequent instructions are run, especially the instruction that needs to allocate storage resources for the storage objects with the most or more total storage amount, there may not be enough storage resources, or there may not be whole block of storage resources, only fragmented storage resources available for allocation, which may lead to more fragmentation of storage resources, reducing the program execution efficiency and storage resource utilization effect. According to at least one embodiment of the present disclosure, the generation of storage resource fragmentation can be reduced, and the program execution efficiency and storage resource utilization effect can be improved.

[0059] Return Figure 1 In step 120, storage resources are allocated to the storage objects in the survival state in the plurality of instructions.

[0060] In some embodiments, the total storage amount of the storage objects in the survival state corresponding to each instruction in the plurality of instructions is determined according to the correspondence relationship. The total storage amount of the storage objects in the survival state in the first instruction in the plurality of instructions can be more than the total storage amount of the storage objects in the survival state in the second instruction in the plurality of instructions. The storage resources are allocated to the storage objects in the survival state in the first instruction in the plurality of instructions prior to the storage resources being allocated to the storage objects in the survival state in the second instruction in the plurality of instructions.

[0061] As Figure 3 And Figure 4As shown, the total storage space of the living objects in instr3(b,c) and instr4(c) is 10 bytes. The total storage space of the living objects in instr5(b) and the if instruction is 8 bytes. The total storage space of the living objects in instr3(b,c) and instr4(c) is greater than that of the living objects in instr5(b) and the if instruction. Therefore, allocating storage resources to the living objects a, b, c, and d in instr3(b,c) and instr4(c) takes precedence over allocating storage resources to the living objects in instr5(b) and the if instruction. For example, in terms of timing, storage resource allocation should start from the living objects a, b, c, and d in instr3(b,c) and instr4(c).

[0062] In some embodiments, in the first instruction, the total storage amount of the storage objects in the living state is greater than or equal to a first total storage threshold, and in the second instruction, the total storage amount of the storage objects in the living state is less than the first total storage threshold.

[0063] Thus, allocating storage resources to a living object in the first instruction can have a higher priority than allocating storage resources to a living object in the second instruction. In other words, allocating storage resources to a living object in the first instruction takes precedence over allocating storage resources to a living object in the second instruction.

[0064] Note that the first or second instruction here can refer to any one or more instructions, without any order or size restrictions, as long as the conditions are met.

[0065] Here, the first total storage threshold can be preset. Furthermore, the case where the total storage of living objects in the first instruction is at its maximum can also be included in the case where the total storage of living objects in the first instruction is greater than or equal to the first total storage threshold, since the first total storage threshold can be a predetermined value.

[0066] like Figure 3 and Figure 4 As shown, the total storage size of the live objects in instr3(b,c) and instr4(c) is 10 bytes. The total storage size of the live objects in instr5(b) and the if instruction is 8 bytes.

[0067] For example, if the first total storage amount threshold is 9 bytes, then the priority of allocating storage resources to the storage objects in the instr3(b, c) and instr4(c) that are in the alive state and have a total storage amount greater than or equal to 9 is higher than the priority of allocating storage resources to the storage objects in other instructions (e.g., instr5(b) and if instructions and other instructions) that are in the alive state and have a total storage amount less than 9. For example, the storage resources are allocated first in time to the storage objects a, b, c, d in the instr3(b, c) and instr4(c) that are in the alive state.

[0068] In some embodiments, the storage resources are allocated preferentially to the storage objects in the first instruction that are in the alive state and have the most total storage amount.

[0069] As shown in FIGS. 1 1 and 12, it can be considered that the total storage amount of the storage objects in the instr3(b, c) and instr4(c) that are in the alive state is the most (10 bytes). Figure 3 Figure 4 As shown in FIGS. 1 1 and 12, it can be considered that the total storage amount of the storage objects in the instr3(b, c) and instr4(c) that are in the alive state is the most (10 bytes).

[0070] Thus, the storage resources can be allocated preferentially to the storage objects a, b, c, d in the instr3(b, c) or instr4(c). For example, the storage resources are allocated first in time to the storage objects a, b, c, d in the instr3(b, c) and instr4(c) that are in the alive state.

[0071] In one embodiment, the storage resources are allocated to the storage objects in the multiple instructions that are in the alive state by allocating whole blocks of storage addresses to the storage objects. The more preferentially (or the earlier in time) allocated storage objects will be allocated to whole blocks of storage addresses as much as possible. For example, the storage object a is allocated the register physical address [0, 1023], the storage object b is allocated the register physical address [1024, 2047], the storage object c is allocated the register physical address [2048, 4095], and the storage object d is allocated the register physical address [4095, 8191]. In this way, each storage object can be allocated a whole block (i.e., contiguous) of register addresses (i.e., the register addresses allocated to each storage object are contiguous), and all of the storage objects can be allocated a whole block of register addresses (i.e., the register addresses allocated to all of the storage objects are contiguous), which can further reduce fragmentation.

[0072] ​After the storage resource is allocated to the storage objects a, b, c, d of the instruction instr3(b, c) or the instruction instr4(c), the storage object to which the storage resource has been allocated is diffused to all the instructions corresponding to the storage object (i.e. for each instruction of the storage object, the allocated storage resource should be able to be used to store data), so as to ensure that the data of the storage object can be stored by using the allocated storage resource when the instruction using the storage object for the first time is executed. As shown in Figure 3 After the storage resource is allocated to the storage objects a, b, c, d of the instruction instr3(b, c) or the instruction instr4(c), the storage object to which the storage resource has been allocated is diffused to all the instructions corresponding to the storage object (i.e. for each instruction of the storage object, the allocated storage resource should be able to be used to store data), so as to ensure that the data of the storage object can be stored by using the allocated storage resource when the instruction using the storage object for the first time is executed. As shown in Figure 3 After the storage resource is allocated to the storage objects a, b, c, d of the instruction instr3(b, c) or the instruction instr4(c), the storage object to which the storage resource has been allocated is diffused to all the instructions corresponding to the storage object (i.e. for each instruction of the storage object, the allocated storage resource should be able to be used to store data), so as to ensure that the data of the storage object can be stored by using the allocated storage resource when the instruction using the storage object for the first time is executed. As shown in Figure 3 The subsequent storage resource allocation can be performed on the storage objects (e.g. the storage objects in other instructions not shown) that have not been allocated.

[0073] Note that Figure 3 and Figure 4 only the storage objects a, b, c, d are shown in the instructions, but there can be other storage objects in other instructions in the entire program. The allocation priority can be determined according to the life of all the storage objects in the entire program, so as to perform the storage resource allocation, diffusion, etc.

[0074] In the process of allocating the storage resource of the storage object other than the storage object in the first instruction, there can be multiple allocation sequences, and the following examples are only for illustration, but not limitation.

[0075] For example, after the storage resource is allocated to the storage object in the first instruction, the storage resource can be allocated to the storage objects in the instructions before the first instruction (e.g. the instructions before all the program instructions shown in Figure 3 ) according to the instruction control flow of the program, in the order from the last instruction to the first instruction; and the storage resource can be allocated to the storage objects in the instructions after the first instruction (e.g. the instructions after all the program instructions shown in Figure 3 ) according to the instruction control flow of the program, in the order from the first instruction to the last instruction. After the storage resource is allocated to a storage object, the storage object is diffused to all the instructions having the storage object according to the above diffusion manner.

[0076] For example, the storage resource of the storage object other than the already allocated storage object can be allocated to the instructions other than the first instruction according to the total storage amount of the storage object from more to less. For example, as shown in Figure 3 The total storage amount of the storage object to be allocated in the program instructions shown in Figure 3After the storage resources for the storage objects a, b, c, d that need to be allocated in the program instructions shown are allocated, the storage resources allocated for the storage objects a, b, c, d are diffused to a, b, c, d in other program instructions, and then the total storage amount of the storage objects (e.g., e, f) that need to be allocated in some program instructions not shown is 8 bytes, while the total storage amount of the storage objects (e.g., g, h) that need to be allocated in other program instructions not shown is 6 bytes, and so on. Next, the storage resources are allocated to the storage objects in some program instructions not shown that have a total storage amount of 8 bytes, and then the storage resources are allocated to the storage objects in other program instructions not shown that have a total storage amount of 6 bytes, and so on. Note that after the storage resources are allocated to a storage object, the storage resources are diffused to all instructions that have the storage object in the above-described manner, and the next allocation of storage resources does not need to be performed for the storage objects that have already been allocated storage resources. In this way, the whole storage addresses can be allocated to as many storage objects as possible, so as to reduce the generation of storage resource fragmentation.

[0077] The resource allocation scheme also proposes a twice allocation scheme.

[0078] The first allocation allocates the storage resources required for the life span of the cross-tensor instruction that operates in units of tensors. That is, in the example shown in Figure 1 , Figure 2A , Figure 2B , Figures 3-4 The multiple instructions (instr1(a) and the like) are operation instructions in units of tensors. For example, the storage objects a, b, c, d in Figure 3 are tensors. Therefore, the first allocation is the allocation of the storage resources required for the life span of the cross-tensor instruction (instr1(a) and the like). Here, once the storage resources required for the life span of the cross-tensor instruction (instr1(a) and the like) are allocated, the storage resources have been allocated for all cross-tensor instructions before the program starts to execute, and the storage resources are not recycled until the last execution of the storage object in the entire program (i.e., the end of the life span of the storage object) is completed.

[0079] The second allocation of temporary resources needed during the execution of the machine instructions generated by the lower() method inside the second allocation cross-tensor instruction (here, temporary resources refer to resources that are reclaimed immediately after the execution of the tensor instruction). Lower() is a phase of the compiler backend, which can be responsible for converting the intermediate representation (IR) obtained from the program code into a low-level representation closer to the target machine instructions (e.g., binary code). The lower() phase can involve tasks such as register allocation, instruction selection, instruction scheduling, etc. That is, temporary storage resources can also be allocated to storage objects in machine instructions generated by a third instruction in a plurality of instructions, wherein the temporary storage resources are reclaimed after the execution of the third instruction. Here, the third instruction can refer to any instruction as long as it can generate machine instructions through, for example, the lower() method. Generally, any instruction in a program can be further decomposed into machine instructions.

[0080] For example, the matrix multiplication instruction Tensor(a) * Tensor(b) instruction generates machine instructions through the lower() method, which can include a multiplication instruction between an element (or first element) a1 in tensor a and an element (or second element) b1 in tensor b, and at this time, the storage resources needed for the two storage objects, the first element a1 and the second element b1, are allocated temporary resources, so that the values of the first element a1 and the second element b1 are temporarily stored, and the temporary resources can be reclaimed immediately after the execution of the multiplication instruction between the first element a1 and the second element b1. The machine instructions can also include a multiplication instruction between another element (or third element) a2 in tensor a and another element (or fourth element) b2 in tensor b, and at this time, the storage resources needed for the two storage objects, the third element a2 and the fourth element b2, are allocated temporary resources, so that the values of the third element a2 and the fourth element b2 are temporarily stored, and the temporary resources can be reclaimed immediately after the execution of the multiplication instruction between the first element a1 and the second element b1. Similarly, this is not described one by one.

[0081] In other words, in the process of allocating storage resources, each storage object of a plurality of storage objects can be allocated at least one of temporary storage resources that need to be reclaimed immediately after the execution of an instruction during the execution of a program and storage resources that are reclaimed after the end of the lifetime according to the lifetime of the plurality of storage objects. As described earlier, there are many different types of storage resources, and resource pools can be set for each type of storage resource, so that resource allocation is performed in the corresponding resource pool.

[0082] In this way, different allocation strategies can be adapted to different types of resources that need to be recycled and do not need to be recycled, and the allocation of storage resources can be reasonable and appropriate.

[0083] In summary, the scheme can uniformly perform centralized resource allocation of all storage resources, thereby improving allocation efficiency.

[0084] Although the example of the scheme according to at least one embodiment of the disclosure is for allocating storage resources in GPGPU or GPU, the scheme can also be applied to allocating storage resources in CPU, and thus does not limit the storage resources of the processing unit.

[0085] Figure 5 A block diagram of an apparatus 500 for processor resource allocation in a program compilation process is shown according to at least one embodiment of the disclosure.

[0086] As shown in Figure 5 The apparatus 500 for processor resource allocation in a program compilation process includes an obtaining module 510 and an allocation module 520.

[0087] The obtaining module 510 can be configured to obtain lifetimes of a plurality of storage objects in a plurality of instructions of a program to be compiled, wherein the lifetime of a first storage object in the plurality of storage objects includes a sequence of instructions involved between a start instruction at which the first storage object is used for the first time and an end instruction at which the first storage object is used for the last time, and wherein the first storage object is in a live state in the lifetime of the first storage object.

[0088] The allocation module 520 can be configured to allocate storage resources to storage objects in a live state in a plurality of instructions, wherein allocating storage resources to storage objects in a live state in a first instruction in the plurality of instructions is prioritized over allocating storage resources to storage objects in a live state in a second instruction in the plurality of instructions, and wherein a total storage amount of storage objects in a live state in the first instruction is greater than a total storage amount of storage objects in a live state in the second instruction.

[0089] In one embodiment, the total storage amount of storage objects in a live state in the first instruction is greater than or equal to a first total storage amount threshold, and the total storage amount of storage objects in a live state in the second instruction is less than the first total storage amount threshold.

[0090] In an embodiment, the obtaining module 510 can be configured to traverse the instruction control flow of the program, determine a plurality of pre-dominating instructions and a plurality of post-dominating instructions of an instruction using a first storage object in the plurality of storage objects; determine a pre-dominating instruction of a start instruction in which the first storage object is used for the first time and a post-dominating instruction of an end instruction in which the first storage object is used for the last time in the plurality of post-dominating instructions; determine a lifetime of the first storage object based on the pre-dominating instruction of the start instruction in which the first storage object is used for the first time and the post-dominating instruction of the end instruction in which the first storage object is used for the last time; and include all instructions during the lifetime of the first storage object as an instruction sequence corresponding to the first storage object in the alive state.

[0091] In an embodiment, the allocating module 520 can be configured to determine a corresponding relationship between each instruction in the plurality of instructions and a storage object in the alive state according to the lifetimes of the plurality of storage objects; and determine a total storage amount of the storage object in the alive state corresponding to each instruction in the plurality of instructions according to the corresponding relationship.

[0092] In an embodiment, the total storage amount of the storage object in the alive state in the first instruction is the largest.

[0093] In an embodiment, the allocating module 520 can be configured to allocate storage resources to the storage object in the first instruction; allocate storage resources to the storage objects in the instructions before the first instruction in the order of the instructions from back to front according to the instruction control flow of the program; and allocate storage resources to the storage objects in the instructions after the first instruction in the order of the instructions from front to back according to the instruction control flow of the program.

[0094] In an embodiment, the allocating module 520 can be configured to allocate storage resources to the storage object in the first instruction; and allocate storage resources to the storage objects other than the storage object already allocated in the order of the total storage amount of the storage objects from more to less for the instructions other than the first instruction in the plurality of instructions.

[0095] In an embodiment, the operand of one or more instructions in the plurality of instructions can be a tensor.

[0096] In an embodiment, the plurality of instructions can include one or more of instructions in a sequential execution structure, instructions in a conditional branch structure, and instructions in a loop structure.

[0097] In an embodiment, the allocating module 520 can be further configured to allocate temporary storage resources to the storage objects in the machine instructions generated by a third instruction in the plurality of instructions, wherein the temporary storage resources are recycled after the execution of the third instruction.

[0098] In one embodiment, the allocation module 520 can be configured to allocate, for each of the plurality of storage objects, at least one of a temporary storage resource that needs to be reclaimed immediately after execution of a single instruction and a storage resource that needs to be reclaimed after execution of the entire program according to a lifetime of the plurality of storage objects.

[0099] In one embodiment, the allocation module 520 can be configured to allocate the storage resource for the storage object in a live state in the plurality of instructions by allocating a whole block of storage addresses for the storage object.

[0100] Thus, according to at least one embodiment of the present disclosure, for the scenario of executing a program including tensor operations by a GPGPU, in the program compilation process, the lifetimes of various storage objects of the program can be analyzed based on the structured control flow of the instruction control flow of the program, and the storage resource and the reclaimed storage resource of each instruction can be allocated to its respective storage object in order from more to less (or from more to less) of the total storage amount of the storage object in a live state of the instruction. This design is simple and more suitable for the scenario of executing a program including tensor operations by a GPGPU. This scheme only needs to traverse the instruction control flow once to perform the lifetime analysis, reducing the complexity of the lifetime analysis caused by the unstructured control flow of the program. The allocation and reclamation of the storage object can be performed according to the lifetime of the storage object corresponding to the instruction, which can reduce the fragmentation of the storage resource and improve the program execution efficiency and the storage resource utilization effect. This scheme can uniformly perform centralized resource allocation of all storage resources, thereby improving the allocation efficiency. At the same time, this resource allocation scheme can be applied to independent resource pools of different types of resources (that need to be reclaimed or do not need to be reclaimed) and adapt to different allocation strategies. This resource allocation scheme also proposes a two-time allocation scheme: the first time to allocate the non-temporary resource required by the cross-tensor instruction operating on a tensor as a unit according to the lifetime of the cross-tensor instruction, and the second time to allocate the temporary resource required by the machine instruction generated by the function method inside the cross-tensor instruction during operation (the temporary resource is reclaimed immediately after execution of this cross-tensor instruction), thereby adapting different allocation strategies to different types of resources and reasonably and appropriately allocating the storage resource.

[0101] Figure 6 A block diagram of an apparatus 600 for processor resource allocation in a program compilation process according to at least one embodiment of the present disclosure is shown.

[0102] The apparatus 600 for processor resource allocation in a program compilation process can include a processing apparatus 610 and a storage apparatus 620 coupled to the processing apparatus 610 and storing computer instructions therein for performing the steps of the various methods of at least one embodiment of the present disclosure when executed by the processing apparatus 610.

[0103] The processing device 610 can include, but is not limited to, for example, one or more CPUs or GPGPUs or GPUs or micro-processing units, but typically a CPU.

[0104] The storage device 620 can include, but is not limited to, for example, a random access memory (RAM), a read only memory (ROM), a flash memory, an EPROM memory, an EEPROM memory, a register, a computer storage medium (e.g., a hard disk, a floppy disk, a solid state disk, a removable disk, a CD-ROM, a DVD-ROM, a Blu-ray disk, etc.).

[0105] In addition, the processing device for processor resource allocation during program compilation can also include (but not limited to) other components, such as a bus, a display, and an input / output device (e.g., a keyboard, a mouse, a speaker, etc.), etc., as needed.

[0106] In one embodiment, the at least one computer instruction can also be compiled into or constitute a computer program product or software product, wherein the one or more computer instructions are executed by the processing device to perform the steps of the various functions and / or methods described in the embodiments of the present technology.

[0107] Figure 7 A schematic diagram of a non-transitory computer-readable storage medium according to at least one embodiment of the present disclosure is shown.

[0108] As Figure 7 shown, the non-transitory computer-readable storage medium 720 stores instructions, for example, computer instructions 710. When the computer instructions 710 are executed by a processing device, the various methods described above can be performed. The non-transitory computer-readable storage medium includes, but is not limited to, for example, a random access memory (RAM), a read only memory (ROM), a flash memory, an EPROM memory, an EEPROM memory, a register, a computer storage medium (e.g., a hard disk, a floppy disk, a solid state disk, a removable disk, a CD-ROM, a DVD-ROM, a Blu-ray disk, etc.). For example, the non-transitory computer-readable storage medium 720 can be connected to a computing device, such as a computer, and then when the computing device executes the computer instructions 710 stored on the non-transitory computer-readable storage medium 720, the various methods described above can be performed.

[0109] The present disclosure can also include an electronic device including the processing device for processor resource allocation during program compilation as described above. Figure 5 and 6 The present disclosure can also include an electronic device including the processing device for processor resource allocation during program compilation as described above.

[0110] The present disclosure can also include a computer program product, wherein the computer program product can perform the methods, steps and operations outlined in this disclosure. For example, such a computer program product can be a computer software package, a computer code instruction, a computer-readable tangible medium having computer instructions tangibly stored (and / or encoded) thereon, which can be executed by a processing apparatus to perform the operations described in this disclosure. The computer program product can include packaging material.

[0111] The block diagrams of the devices, apparatuses, equipment, systems referred to in the present disclosure are merely illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be as shown in the block diagrams. These devices, apparatuses, equipment, systems can be connected, arranged, configured in any manner as will be appreciated by those skilled in the art. Words such as "including," "containing," "comprising," etc. are to be construed as being open-ended terms, i.e., meaning "including, but not limited to," and should be interpreted in the same manner as "comprising" and "including" as those terms are used in the art. The phrase "consisting of" is to be construed as an open term, meaning "comprising and consisting of," and should be interpreted in the same manner as "comprising" and "including" as those terms are used in the art. The phrase "consisting essentially of" is to be construed as an open term, meaning "comprising essentially of," and should be interpreted in the same manner as "comprising" and "including" as those terms are used in the art.

[0112] The flow diagrams of the steps in the present disclosure and above method descriptions are merely illustrative examples and are not intended to require or imply that the steps of various embodiments must be performed in the order presented. As will be appreciated by one of skill in the art, the order of the steps in the above embodiments can be changed, as can other implementations of the disclosure. Words such as "thereafter," "then," "next," etc. are not intended to limit the order of the steps; these words are simply used to guide the reader through the description of the methods. Further, any reference to claim elements in the singular, for example, using the articles "one," "a" or "an," is not to be construed as limiting the claim to a single element but rather to one or more elements unless otherwise indicated by context.

[0113] In addition, the steps and apparatuses in various embodiments herein are not limited to performing only within one embodiment, in fact, relevant partial steps and partial apparatuses in various embodiments herein can be combined according to the concepts of the present disclosure to conceive new embodiments, and these new embodiments are also included in the scope of the present disclosure.

[0114] The above-described methods can be realized in hardware, software, firmware or any combination thereof.

[0115] Further, the modules for performing the methods and techniques described herein, and / or other appropriate means, can be downloaded in a wireless manner from a server when appropriate. Alternatively, various methods described herein can be provided via a storage means, so that various methods can be obtained by a device when coupled to the storage means. Further, any other suitable technique for providing the methods and techniques described herein to a device can be utilized.

[0116] The foregoing description has been presented for the purposes of illustration and description. Furthermore, the description is not intended to limit the embodiments of the disclosure to the forms disclosed herein. Although the various example aspects and embodiments have been described herein with regard to particular aspects and embodiments, those skilled in the art will recognize that certain modifications, changes, substitutions, additions and sub-combinations can be made without departing from the spirit of the disclosure.

Claims

1. A method for processor resource allocation, comprising: obtaining lifetimes of a plurality of storage objects in a plurality of instructions of a program to be compiled, wherein a lifetime of a first storage object in the plurality of storage objects comprises a sequence of instructions between a start instruction at which the first storage object is first used and an end instruction at which the first storage object is last used, and in the lifetime of the first storage object, the first storage object is in a live state; allocating storage resources to storage objects in the live state in the plurality of instructions, wherein the allocating storage resources to storage objects in the live state in the plurality of instructions comprises: determining a correspondence between each instruction in the plurality of instructions and a storage object in the live state according to the lifetimes of the plurality of storage objects; calculating a total storage amount of a storage object in the live state corresponding to each instruction in the plurality of instructions according to a sum of capacities determined by data formats of each storage object in the live state according to the correspondence, wherein allocating storage resources to storage objects in the live state in a first instruction in the plurality of instructions is prioritized over allocating storage resources to storage objects in the live state in a second instruction in the plurality of instructions, wherein a total storage amount of storage objects in the live state in the first instruction is more than a total storage amount of storage objects in the live state in the second instruction.

2. The method of claim 1, wherein, the total storage amount of storage objects in the live state in the first instruction is more than or equal to a first total storage amount threshold, and the total storage amount of storage objects in the live state in the second instruction is less than the first total storage amount threshold.

3. The method of any one of claims 1-2, wherein, the total storage amount of storage objects in the live state in the first instruction is the most.

4. The method of any one of claims 1-2, wherein, the allocating storage resources to storage objects in the live state in the plurality of instructions comprises: allocating storage resources to storage objects in the first instruction; allocating storage resources to storage objects in instructions before the first instruction in the order of instructions from back to front according to an instruction control flow of the program; allocating storage resources to storage objects in instructions after the first instruction in the order of instructions from front to back according to the instruction control flow of the program.

5. The method of any one of claims 1-2, wherein, the allocating storage resources to storage objects in the live state in the plurality of instructions comprises: allocating storage resources to storage objects in the first instruction; allocating storage resources to storage objects other than the storage objects in the first instruction in the plurality of instructions in the order of total storage amounts of storage objects from more to less.

6. The method of any one of claims 1-2, wherein, operands of one or more instructions in the plurality of instructions are tensors.

7. The method of any one of claims 1-2, wherein, the plurality of instructions comprise one or more of instructions in a sequential execution structure, instructions in a conditional branch structure, and instructions in a loop structure. 8.The method of any one of claims 1-2, further comprising: allocating temporary storage resources to storage objects in machine instructions generated by a third instruction in the plurality of instructions, wherein the temporary storage resources are recycled after the third instruction is executed.

9. The method of any one of claims 1-2, wherein, The allocating the storage resource to the storage object in the alive state in the plurality of instructions is performed by allocating a whole block storage address to the storage object. 10.An apparatus for processor resource allocation, comprising: an obtaining module configured to obtain lifetimes of a plurality of storage objects in a plurality of instructions of a program to be compiled, wherein a lifetime of a first storage object in the plurality of storage objects comprises a sequence of instructions between a start instruction at which the first storage object is used for the first time and an end instruction at which the first storage object is used for the last time, and in the lifetime of the first storage object, the first storage object is in an alive state; an allocating module configured to allocate a storage resource to a storage object in an alive state in the plurality of instructions, wherein the allocating module is configured to: determine a correspondence between each instruction in the plurality of instructions and a storage object in an alive state according to the lifetimes of the plurality of storage objects; calculate a total storage amount of a storage object in an alive state corresponding to each instruction in the plurality of instructions according to the correspondence, by a sum of capacities determined by data formats of each storage object in an alive state, wherein allocating the storage resource to the storage object in the alive state in a first instruction in the plurality of instructions is prior to allocating the storage resource to the storage object in the alive state in a second instruction in the plurality of instructions, and wherein the total storage amount of the storage object in the alive state in the first instruction is more than the total storage amount of the storage object in the alive state in the second instruction. 11.An apparatus for processor resource allocation, comprising: a storage device storing computer instructions; at least one processing device configured to execute the computer instructions in the storage device to perform the method according to any one of claims 1-9. 12.An electronic device comprising the apparatus for processor resource allocation according to claim 10 or 11. 13.A non-transitory computer readable storage medium having stored thereon computer instructions, wherein which when executed by a processing device, cause the processing device to perform the method according to any one of claims 1-9.

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