Shared cache management method and device and storage medium

Abstract

The invention discloses a shared cache management method and device and a storage medium, and relates to the technical field of computers. The method comprises the following steps: determining an access characteristic of an IO request for accessing the shared cache of each category in K categories for accessing the shared cache; and according to the determined access characteristics and the hit rate of the shared cache, determining the partition size and the elimination algorithm of the IO requests of each category in the shared cache. The cache size of the IO requests of each category in the shared cache is configured to be the determined partition size, and the elimination algorithm of the IO requests of each category in the shared cache is configured to be the determined elimination algorithm. According to the method, the cache performance in the shared cache can be improved.

Description

[0001] This application is a divisional application of the Chinese application with application date of July 29, 2022 and application number 202210908210.5. This application and the Chinese application with application number 202210908210.5 both claim the priority of the Chinese patent application with application number 202210197738.6 filed on March 2, 2022 and invention name “A shared cache management method and device”, all contents of which are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to a shared cache management method, device and storage medium. Background Art

[0003] Shared cache refers to sharing cache resources between multiple entities in the cache architecture (such as multiple applications, multiple clients, or multiple processing cores of a computing device, etc.) to meet different cache requirements. For example, for a central processing unit (CPU) including multiple cores in a computing device, multiple cores share the CPU's last level cache (LLC). For another example, in a distributed cache system, the data of a single client is cached in different cache nodes. Conversely, in a scenario with multiple clients, multiple clients share cache resources in a single cache node.

[0004] When multiple entities share a cache, in order to avoid cache contention, the cache shared by the multiple entities may be partitioned so that different partitions are used to cache data to be cached of different entities.

[0005] However, currently when dividing cache partitions in a shared cache, the partition size is usually specified manually, or a simple priority strategy is used to determine the size of the cache partition. In addition, the entire shared cache uses the same elimination algorithm, which leads to poor performance of the shared cache. Summary of the invention

[0006] The present application provides a shared cache management method, device and storage medium for improving cache performance in a shared cache.

[0007] To achieve the above objectives, this application provides the following technical solutions:

[0008] In a first aspect, the present application provides a shared cache management method, which is used to manage the shared cache. The shared cache is used to cache data requested by multiple IO requests, the multiple IO requests correspond to K categories, and the shared cache corresponds to N elimination algorithms. The method includes: determining the access characteristics of the IO requests of each category in the K categories to access the shared cache. According to the access characteristics of the IO requests of the K categories and the hit rate of the shared cache, determine the partition size and elimination algorithm of the IO requests of each category in the shared cache. Configure the cache size of the IO requests of each category in the shared cache to the determined partition size of the IO requests of each category in the shared cache, and configure the elimination algorithm of the IO requests of each category in the shared cache to the determined elimination algorithm of the IO requests of each category in the shared cache. The access characteristics of the IO requests of each category in the K categories to access the shared cache are: the relationship between the hit rate and cache size of the IO requests of each category in the K categories under the N elimination algorithms.

[0009] Through the shared cache management method provided by the present application, by obtaining the access characteristics of each category of input / output (IO) requests, the partition size and cache elimination algorithm are determined in the shared cache for each category of IO requests, so as to improve the appropriate cache performance for each category of IO requests, thereby improving the cache performance in the entire shared cache. Specifically, in the data reading scenario, the hit rate of the shared cache can be improved, thereby improving the efficiency of data reading, and in the data writing scenario, by improving the write hit rate, the number of times the shared cache flushes to the back-end storage unit is saved.

[0010] In a possible design, the above-mentioned determination of the access characteristics of the IO requests of each category in the K categories accessing the shared cache includes: for a first elimination algorithm among the above-mentioned N elimination algorithms, simulating in the shared cache the hit rate of the IO requests of each category in the K categories applying the first elimination algorithm in caches of different sizes to obtain the relationship between the hit rate and the cache size. The first elimination algorithm is any elimination algorithm among the N elimination algorithms.

[0011] In another possible design, the above-mentioned determination of the access characteristics of the IO requests of each category in the K categories to the shared cache includes: for the first elimination algorithm among the above-mentioned N elimination algorithms, according to the reuse distance of each IO request in the first category of IO requests and different cache sizes, determining the hit rate of the first category of IO requests applying the first elimination algorithm in caches of different sizes, so as to obtain the relationship between the hit rate and the cache size. The first elimination algorithm is any elimination algorithm among the N elimination algorithms, and the first category of IO requests is any category of IO requests among the K categories.

[0012] The above two possible designs provide two methods for determining the access characteristics of the IO requests of each category in the K categories accessing the shared cache.

[0013] In another possible design, the above-mentioned method of determining the partition size and elimination algorithm of each category of IO requests in the shared cache according to the access characteristics of K categories of IO requests and the hit rate of the shared cache includes: determining the hit rate of K categories of IO requests in the shared cache under each combination according to the X hit rates corresponding to the X cache sizes determined under each elimination algorithm based on each category of IO requests. Determine the cache size corresponding to each category of IO requests when the hit rate of K categories of IO requests in the shared cache is the maximum as the partition size of each category of IO requests in the shared cache, and determine the elimination algorithm corresponding to each category of IO requests when the hit rate of K categories of IO requests in the shared cache is the maximum as the elimination algorithm of each category of IO requests in the shared cache. Wherein, for any category of the K categories of IO requests, the X cache sizes and the N elimination algorithms constitute X*N combinations, each combination includes a cache size and an elimination algorithm, and the X cache sizes are the X cache sizes preset for the cache corresponding to each category of IO requests.

[0014] Through this possible design, the partition size and elimination algorithm corresponding to each category of IO requests can be determined when the hit rate of K categories of IO requests in the shared cache is the largest. Then, based on the determined partition size and elimination algorithm, the cache size and elimination algorithm of each category of IO requests in the K categories in the shared cache are configured, which can achieve the purpose of optimizing the cache size and elimination algorithm of each category of IO requests in the K categories in the shared cache by jointly solving the two factors that affect the cache performance, the elimination algorithm and the cache size. Therefore, the optimized cache size and elimination algorithm of each category of IO requests in the K categories in the shared cache can improve the overall cache performance of the shared cache.

[0015] In another possible design, before determining the access characteristics of the IO requests of each category in the K categories to access the shared cache, the method further includes: obtaining multiple IO requests, and classifying the IO requests into the K categories according to the characteristics of the addresses of the data accessed by the multiple IO requests or according to the category tags carried in the multiple IO requests.

[0016] When IO requests are divided into K categories according to the characteristics of the addresses of the data accessed by multiple IO requests, the entity initiating the IO request does not need to mark the IO request with a category tag for classification, so that the entity initiating the IO request does not incur additional resource overhead. In addition, since the method provided by the present application does not invade the upper layer of the cache (i.e., the entity initiating the IO request), the method provided by the present application can be applied to a general cache system for diverse customers without the need for ecological support.

[0017] In another possible design, the shared cache is an LLC of a CPU in a computing device, and the multiple IO requests are IO requests initiated by multiple processing cores in the CPU.

[0018] In another possible design, the shared cache is a cache in a cache node, and the multiple IO requests are IO requests initiated by multiple computing nodes that access the cache node.

[0019] In another possible design, the shared cache is a cache pool formed by caches in multiple nodes, and the multiple IO requests are IO requests initiated by multiple computing nodes that access the cache pool.

[0020] Through the above three possible designs, the method provided in this application can be applied to a variety of scenarios.

[0021] In another possible design, the access characteristic is characterized by a hit rate curve (HRC) or a miss rate curve (MRC) of the IO request.

[0022] In another possible design, the above-mentioned determination of the access characteristics of IO requests of each category in the K categories accessing the shared cache includes: periodically determining the access characteristics of IO requests of each category in the K categories accessing the shared cache. For the access characteristics of IO requests of each category in the K categories accessing the shared cache determined in the first cycle, the above-mentioned determination of the partition size and elimination algorithm of IO requests of each category in the shared cache based on the access characteristics of IO requests of the K categories and the hit rate of the shared cache includes: determining the partition size and elimination algorithm of IO requests of each category in the shared cache in the first cycle based on the access characteristics of IO requests of the K categories determined in the first cycle and the hit rate of the shared cache. Among them, the first cycle is any cycle for determining the access characteristics of IO requests of each category in the K categories accessing the shared cache.

[0023] Through the above possible design, the shared cache can periodically adjust the cache size and elimination algorithm of each category of IO requests in the shared cache according to the cache size and elimination algorithm of IO requests in each category of K categories periodically determined by the computing device, thereby improving the hit rate of IO requests in the shared cache in the time domain, thereby improving the overall cache performance of the shared cache in the time domain.

[0024] In a second aspect, the present application provides a shared cache management device. The shared cache management device is used to execute any one of the methods provided in the first aspect above. The present application may divide the shared cache management device into functional modules according to any one of the methods provided in the first aspect above. For example, each functional module may be divided according to each function, or two or more functions may be integrated into one processing module. Exemplarily, the present application may divide the shared cache management device into a determination unit and a configuration unit, etc. according to the function. The description of the possible technical solutions and beneficial effects executed by the above-mentioned divided functional modules can refer to the technical solutions provided by the above-mentioned first aspect or its corresponding possible design, and will not be repeated here.

[0025] In a third aspect, the present application provides a computing device for managing a shared cache, the computing device comprising: a memory, one or more processors, the one or more processors being configured to read program instructions stored in the memory to execute any method provided in the first aspect and any possible design thereof.

[0026] In a fourth aspect, the present application provides a computer-readable storage medium, which includes program instructions. When the program instructions are executed on a computer or a processor, the computer or the processor executes any method provided by any possible implementation of the first aspect.

[0027] In a fifth aspect, the present application provides a computer program product, which, when executed on a computing device, enables any method provided by any possible implementation of the first aspect to be executed.

[0028] It can be understood that any of the above-mentioned devices, computer storage media or computer program products can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here.

[0029] In this application, the name of the shared cache management device does not limit the device or functional module itself. In actual implementation, these devices or functional modules may appear with other names. As long as the functions of each device or functional module are similar to those of this application, they fall within the scope of the claims of this application and their equivalent technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of a shared cache scenario;

[0031] Figure 2 This is another scenario diagram of shared cache;

[0032] Figure 3 This is another scenario diagram of shared cache;

[0033] Figure 4 A schematic diagram of the hardware structure of a computing device provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of a flow chart of a shared cache management method provided in an embodiment of the present application;

[0035] Figure 6 A schematic diagram of an IO request initiated by an entity to access a shared cache provided in an embodiment of the present application;

[0036] Figure 7 A schematic diagram of a flow chart of a method for generating a classifier provided in an embodiment of the present application;

[0037] Figure 8 A schematic diagram of the classification of IO requests provided in an embodiment of the present application;

[0038] Fig. 9 A flowchart of another shared cache management method provided in an embodiment of the present application;

[0039] Fig.10 A flowchart of another shared cache management method provided in an embodiment of the present application;

[0040] Fig.11 A schematic diagram of the structure of a shared cache management device 110 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to more clearly understand the embodiments of the present application, some terms or technologies involved in the embodiments of the present application are explained below:

[0042] 1) Cache

[0043] When the computing speed of the computing unit does not match the access speed of the computing unit to the data stored in the storage unit, the computing unit will generate a lot of idle rotation while waiting to access data in the storage unit. To solve this problem, cache technology came into being.

[0044] The cache refers to a memory that can exchange data at high speed. Generally, the cache is located between a storage unit (such as an external memory, referred to as external memory) and a computing unit (such as a CPU). The external memory can be, for example, a hard disk of a device, and the hard disk can be, for example, a solid state disk (SSD) or a hard disk drive (HDD).

[0045] On the one hand, by preloading high-value data from the storage unit to the cache, the computing unit can directly read the high-value data in the cache that can perform high-speed data exchange when accessing the high-value data. In this way, the efficiency of the computing unit in accessing data can be improved, thereby reducing the idle time of the computing unit and improving the execution speed of the application. Among them, high-value data is, for example, data that has been recently accessed by the computing unit, or data that is frequently accessed by the computing unit, or working set data, etc., and is not limited to this. Here, the working set can be understood as a data set consisting of all the data required by an application.

[0046] On the other hand, when an entity writes data to a storage unit, the data to be written can be written to a cache first, and then the cache periodically writes the cache data to an external memory (called flushing). The entity is, for example, an application, a computing node, a client device, or a CPU core, etc., but is not limited thereto. In this way, for the entity, writing data to the cache can be considered that the input / output (IO) operation for writing data has been completed, which can improve the response speed of the entity.

[0047] Optionally, the cache of the device can generally be implemented by the memory of the node and / or the SSD of the node. The memory, also known as the main memory, is a storage space that can be directly addressed by the CPU. As an example, the memory can be a dynamic random access memory (DRAM), etc., but is not limited thereto.

[0048] 2) Shared Cache

[0049] In order to adapt to different cache requirements, the cache resources shared between multiple entities in the cache architecture are called shared cache. The multiple entities may be, for example, multiple applications, multiple computing nodes, multiple client devices, or multiple processing cores in the CPU of a computing device, etc., but are not limited thereto. The application refers to an application running in a computing device, the computing node is a computing node that needs to access the shared cache, the client device may be, for example, a client device of a storage system, a client device of an application, etc., and the computing device may be, for example, a general-purpose computer, a laptop, a tablet computer, a server, or any other device including a CPU, but are not limited thereto.

[0050] The shared cache may be a level 3 cache of a CPU including multiple processing cores in a computing device. In this case, the multiple entities that initiate IO requests to the shared cache are the multiple processing cores in the CPU.

[0051] As an example, refer to Figure 1 , Figure 1 A schematic diagram of a shared cache scenario is shown. Figure 1 As shown, the CPU 10 of the computing device includes four processing cores, namely, processing core 1, processing core 2, processing core 3 and processing core 4. Each of the four processing cores of the CPU 10 is configured with an independent level 1 cache and a level 2 cache, and the four processing cores of the CPU 10 can access the level 3 cache of the CPU 10, that is, the level 3 cache of the CPU 10 is a shared cache of the four processing cores.

[0052] The shared cache may also be a cache in a cache node in a cache system. In this case, the multiple entities that initiate IO requests to the shared cache are multiple client devices accessing the cache node, or multiple computing nodes accessing the shared cache. The specific form of the client device may also be any computing node with computing processing capabilities, without limitation.

[0053] The cache system may be a distributed cache system. It is understood that in a distributed cache system, data of a computing node may be cached in caches of multiple cache nodes in the distributed cache system. Conversely, data of multiple computing nodes may be cached in the cache of a cache node in the distributed cache system. Therefore, the cache of a cache node used to cache data of multiple computing nodes in the distributed cache system is a shared cache of the multiple computing nodes.

[0054] The cache system may also be a centralized cache system. Generally, a centralized cache system includes a cache node. In this case, data of multiple computing nodes are cached in the cache of the cache node. Therefore, the cache of the cache node in the centralized cache system is the shared cache of the multiple computing nodes.

[0055] It should be understood that the above-mentioned cache node can be an independent device. In this case, the cache of the independent device is used as the cache of the cache node. Alternatively, the functions implemented by the above-mentioned cache node are implemented by the functional modules in the independent device, that is, the independent device can realize other functional purposes in addition to realizing the functions of the cache node. In this case, part of the cache of the independent device is used as the cache of the cache node. As an example, the functions implemented by the cache node in the distributed cache system are integrated in the computing device that serves as the storage node in the distributed storage system. That is to say, in addition to realizing the functions of the storage node, the computing device also realizes the functions of the cache node. In this case, part of the cache in the independent device is used as the cache of the cache node.

[0056] As an example, refer to Figure 2 , Figure 2 FIG. 1 shows another scenario diagram of shared cache. Figure 2 As shown, Figure 2 The j computing nodes accessing the cache system 20 of the distributed cache system 20 are shown, which are computing node 1, computing node 2, computing node 3, ..., and computing node j, where j is a positive integer. The cache system 20 includes three cache nodes, which are cache node 1, cache node 2, and cache node 3. Among them, the high-value data of any of the j computing nodes are cached in a dispersed manner in the caches of multiple cache nodes in the cache system 20. In contrast, the cache of a single cache node in the cache system 20 is the shared cache of the j computing nodes.

[0057] The shared cache can also be a cache pool composed of caches of multiple nodes. The cache pool is a cache pool composed of the caches of each of the multiple nodes. In this case, the multiple entities that initiate IO requests to the shared cache are the multiple computing nodes that access the cache pool. That is, the cache pool is used to cache the data of the multiple computing nodes.

[0058] The node providing cache for the cache pool can be a node in any network system, without limitation. For example, the node providing cache for the cache pool is a storage node in a storage system, and the multiple computing nodes accessing the cache pool are multiple client devices of the storage system. For another example, the node providing cache for the cache pool is a plurality of servers in a server cluster, and the multiple computing nodes accessing the cache pool are multiple client devices of the server cluster, or the multiple computing nodes accessing the cache pool run multiple applications accessing the server cluster, without limitation.

[0059] As an example, refer to Figure 3 , Figure 3 FIG. 4 shows another schematic diagram of a shared cache scenario. Figure 3As shown, node 1, node 2, and node 3 are storage nodes in the storage system, the cache of node 1 is cache 1, the cache of node 2 is cache 2, and the cache of node 3 is cache 3. Then a portion of cache 1, a portion of cache 2, and a portion of cache 3 can constitute a cache pool 30. Furthermore, data of computing node 1, computing node 2, computing node 3, ..., computing node j of the storage system can be cached in the cache pool 30, and the cache pool 30 is the shared cache of the j computing nodes.

[0060] 3) Read hits and write hits

[0061] Since the size of the cache is generally limited and much smaller than the size of the external memory, the data that can be stored in the cache is very limited.

[0062] In the scenario of reading data, the IO request for reading data initiated by the entity carries the logical address of the data to be read. That is, the logical address carried in the IO request for reading data is the logical address to be accessed by the IO request.

[0063] When data corresponding to the logical address carried by the IO request exists in the cache, the IO request is read hit in the cache.

[0064] When there is no data corresponding to the logical address carried by the IO request in the cache, it means that the IO request for reading data does not hit the data to be read in the cache, that is, a cache miss occurs. Furthermore, the cache miss can trigger the backend (such as external memory) of the cache to read the data to be read requested by the IO request, and cache the data to be read from the backend in the cache.

[0065] It can be seen that when an IO request hits the read in the cache, there is no need to read the data to be read from the backend, thereby improving the response speed of the entity.

[0066] In the scenario of writing data, the IO request for writing data initiated by the entity carries the data to be written and the logical address for storing the data to be written. That is, the logical address carried in the IO request for writing data is the logical address to be accessed by the IO request.

[0067] When there is a physical address in the cache that corresponds to the logical address carried by the IO request, it means that the logical address has been written to data before this IO request and is cached in the cache, but has not yet been flushed from the cache to the external memory. In this case, the IO request for writing data is said to hit the logical address storing the data to be written in the cache, which is referred to as the IO request write hit in the cache. Furthermore, the cache can update the data written to the logical address in the cache based on the data to be written carried by this IO request, and subsequently flush the updated data to the external memory.

[0068] When there is no physical address corresponding to the logical address carried by the IO request in the cache, it means that the logical address has not been written to before this IO request, or the logical address has been written to before this IO request, and the written data has been flushed from the cache to the external memory. In this case, the IO request for writing data is said to miss the logical address storing the data to be written in the cache, which is referred to as the IO request not writing in the cache. Furthermore, the cache assigns the corresponding physical address to the logical address carried in the IO request received this time, and writes the data to be written carried by this IO request to the physical address, thereby realizing the caching of the data to be written.

[0069] It can be seen that when an IO request writes a hit in the cache, the data written in the logical address can be updated in the cache, thereby reducing the number of times the cache flushes data to the external memory, thereby saving bandwidth between the cache and the external memory.

[0070] 4) Elimination algorithm

[0071] In the data reading scenario, when an IO request does not hit the data to be read in the cache, it is necessary to read the data from the back end of the cache (such as external memory) to the cache. For example, for the third-level cache in the CPU, when a cache miss occurs in the third-level cache in the CPU, it is necessary to read the data from the memory of the computing device where the CPU is located to the third-level cache of the CPU. For another example, for the memory, when a cache miss occurs in the memory, it is necessary to read the data from the external memory of the device where the memory is located to the memory.

[0072] If the free space in the cache is insufficient to store the data read from the backend, the existing data in the cache needs to be eliminated (for example, deleting some or all of the data, or marking some or all of the data as invalid, etc.) to provide storage space for the new data read from the backend. The algorithm used to determine the data that needs to be eliminated from the existing data in the cache is called the elimination algorithm.

[0073] Generally, the elimination algorithm is designed based on the access pattern (such as the frequency of accessing data) when IO requests access data. Therefore, by applying the elimination algorithm in the cache, high-value data can be retained in the cache as long as possible, while low-value data can be eliminated. This can increase the hit rate of IO requests for reading data in the cache, thereby improving cache performance.

[0074] In the data writing scenario, the data cached in the cache will be periodically flushed to the external memory, or when the data cached in the cache exceeds a certain amount, the currently cached data will be flushed to the external memory. In this case, some data that may be updated less frequently in the future can be flushed to the external memory, while data that may be updated more frequently in the future can be retained in the cache. In this way, the hit rate of subsequent IO requests in the cache can be improved, thereby reducing the number of times the cache flushes data to the external memory. Here, the algorithm used to determine which data in the cache needs to be flushed to the external memory is the elimination algorithm.

[0075] 5) Cache performance

[0076] Cache performance can generally be evaluated by hit rate or miss rate.

[0077] In the scenario where the read and write caches are separated (i.e., the read cache and the write cache are isolated from each other by physical or software means), the hit rate of read hits is: the ratio of the number of read hits of IO requests in the cache over a period of time to the total number of IO read requests during that period. The miss rate in the read data scenario is: the ratio of the number of cache misses of IO requests in the cache over a period of time to the total number of IO read requests during that period. The hit rate of write hits is: the ratio of the number of write hits of IO requests in the cache over a period of time to the total number of IO write requests during that period. The miss rate in the write data scenario is: the ratio of the number of write misses of IO requests in the cache over a period of time to the total number of IO write requests during that period.

[0078] In the scenario of read-write cache fusion (i.e., read data and write data share the same cache space), the hit rate is: the ratio of the sum of the number of IO request read hits in the cache and the number of IO request write hits in the cache during a period of time to the total number of IO requests during that period. The miss rate is: the ratio of the sum of the number of IO request cache misses in the cache and the number of IO request write misses in the cache during that period of time to the total number of IO requests during that period.

[0079] It can be understood that cache performance is not only related to the elimination algorithm applied in the cache, but also to the size of the cache itself. Therefore, in practice, cache performance is generally characterized by the cache miss rate curve (miss rate curve, MRC) or the cache hit rate curve (hit rate curve, HRC). Among them, MRC is the corresponding relationship curve between cache size and miss rate, which is used to describe the miss rate of IO requests in the cache when the cache is of different sizes under an elimination algorithm. HRC is the corresponding relationship curve between cache size and hit rate, which is used to describe the hit rate of IO requests in the cache when the cache is of different sizes under an elimination algorithm.

[0080] 6) Reuse distance

[0081] For an IO request initiated by an entity, the reuse distance of the IO request is used to indicate the number of different logical addresses accessed by other IO requests during an interval between two consecutive accesses to the logical address carried by the IO request.

[0082] The reuse distance of an IO request can be characterized by the number of different logical addresses. Specifically, for any one of the multiple IO requests initiated by an entity within a period of time (e.g., the first IO request), the reuse distance of the first IO request is: the number of different logical addresses accessed by the IO request that is located between the first IO request and another IO request in terms of timing among the multiple IO requests initiated by the entity. The other IO request is the previous IO request that accesses the logical address carried by the first IO request in terms of timing.

[0083] As an example, assume that the IO requests initiated by an entity within a period of time include 10 IO requests, and the logical addresses accessed by these 10 IO requests in sequence are (a, b, c, d, a, d, a, c, b, a), where each letter represents a logical address.

[0084] For the first IO request among the above 10 IO requests, the logical address carried by the IO request is a. Since there is no IO request that accesses the logical address a before the first IO request among the above 10 IO requests. Therefore, the reuse distance of the first IO request usually defaults to infinity (symbol is ∞). Similarly, for the second IO request, the third IO request and the fourth IO request among the above 10 IO requests, the reuse distances of the second IO request, the third IO request and the fourth IO request are all infinite.

[0085] For the fifth IO request among the above 10 IO requests, the logical address carried by the IO request is a. Since there is an IO request accessing the logical address a before the fifth IO request among the above 10 IO requests, and the previous IO request accessing the logical address a is the first IO request among the above 10 IO requests, and the number of different logical addresses accessed by the IO requests located between the fifth IO request and the first IO request in timing is 3 (including the logical address b accessed by the second IO request, the logical address c accessed by the third IO request, and the logical address d accessed by the fourth IO request). Therefore, the reuse distance of the fifth IO request is 3. Similarly, for the sixth IO request among the above 10 IO requests, the reuse distance of the sixth IO request is 1. And, for the seventh IO request among the above 10 IO requests, the reuse distance of the seventh IO request is 1.

[0086] For the 8th IO request among the above 10 IO requests, the logical address carried by the IO request is c. Since there is an IO request accessing logical address c before the 8th IO request among the above 10 IO requests, and the previous IO request accessing logical address c is the 3rd IO request among the above 10 IO requests, and the number of different logical addresses accessed by the IO requests located between the 8th IO request and the 3rd IO request in timing is 2 (including the logical address d accessed by the 4th IO request and the 6th IO request, and the logical address a accessed by the 5th IO request and the 7th IO request). Therefore, the reuse distance of the 8th IO request is 2. Similarly, for the 9th IO request among the above 10 IO requests, the reuse distance of the 9th IO request is 3. And, for the 10th IO request among the above 10 IO requests, the reuse distance accessed by the 10th IO request is 2.

[0087] 7) Reuse time

[0088] The reuse time is used to indicate the time interval between two consecutive accesses to the same logical address. Therefore, the reuse time can be called the reuse time of the logical address.

[0089] Generally, the reuse time of a logical address can be characterized by the number of IO requests. Specifically, for any one IO request (e.g., the first IO request) among multiple IO requests initiated by an entity within a period of time, the reuse time of the logical address carried by the first IO request is: the number of IO requests that are located between the first IO request and another IO request in terms of timing among the multiple IO requests initiated by the entity. The other IO request is the previous IO request that accesses the logical address carried by the first IO request in terms of timing.

[0090] As an example, assume that the IO requests initiated by an entity within a period of time include 10 IO requests, and the logical addresses accessed by these 10 IO requests in sequence are (a, b, d, c, b, d, a, a, c, d), where each letter represents a logical address.

[0091] For the first IO request among the above 10 IO requests, the logical address accessed by the IO request is a, and there is no IO request accessing the logical address a before the first IO request among the above 10 IO requests. Therefore, the reuse time of the logical address a accessed by the first IO request is usually infinite by default. Similarly, for the second IO request, the third IO request, and the fourth IO request among the above 10 IO requests, the reuse time of the logical address b accessed by the second IO request, the logical address d accessed by the third IO request, and the logical address c accessed by the fourth IO request are all infinite.

[0092] For the fifth IO request among the above 10 IO requests, the logical address accessed by the IO request is b. Since there is an IO request accessing the logical address b before the fifth IO request among the above 10 IO requests, and the previous IO request accessing the logical address b is the second IO request among the above 10 IO requests, and there are two IO requests (including the third IO request and the fourth IO request) between the fifth IO request and the second IO request in terms of timing. Therefore, the reuse time of the logical address b accessed by the fifth IO request is 2. Similarly, for the sixth IO request among the above 10 requests, the reuse time of the logical address d accessed by the sixth IO request is 2. For the seventh IO request among the above 10 requests, the reuse time of the logical address a accessed by the seventh IO request is 5. For the eighth IO request among the above 10 requests, the reuse time of the logical address a accessed by the eighth IO request is 0. For the 9th IO request among the above 10 requests, the reuse time of the logical address c accessed by the 9th IO request is 4. For the 10th IO request among the above 10 requests, the reuse time of the logical address d accessed by the 10th IO request is 3.

[0093] 8) Other terms

[0094] In the embodiments of the present application, the terms "first" and "second" do not indicate an order relationship, but are used to distinguish different objects. The first, second, etc. mentioned in the following documents are also used to distinguish different messages, etc., and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

[0095] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0096] In order to avoid cache contention, the shared cache can usually be partitioned so that the data requested to be read by different categories of IO requests are cached in different partitions of the cache. Among them, different categories of IO requests are, for example, IO requests initiated by different entities, which is not limited to this. However, when the cache partitions are currently divided in the shared cache, the partition size is usually manually specified based on the memory access rules (such as the frequency of accessing data, etc.) when IO requests access data within a period of time, or a simple heuristic strategy (such as the priority of different categories of IO requests) is used to determine the partition size of the cache, and the cache partitions divided in this way can generally only guarantee cache performance within a period of time, but cannot guarantee long-term cache performance. In addition, the entire shared cache uses the same elimination algorithm, which leads to poor performance of the shared cache.

[0097] Based on this, an embodiment of the present application provides a method for managing a shared cache, which first determines the access characteristics of IO requests of each category in a plurality of categories accessing the shared cache, and determines the partition size and elimination algorithm of each category of IO requests in the shared cache based on the determined access characteristics of IO requests of each category in the plurality of categories and the hit rate of the shared cache. Then, the determined partition size and elimination algorithm of each category of IO requests in the shared cache are applied to the shared cache. Among them, the access characteristics of each category of IO requests are the relationship between the hit rate and cache size of each category of IO requests in the plurality of categories under a plurality of elimination algorithms. Through this method, the cache size and elimination algorithm can be set for each category of IO requests according to the access characteristics of each category of IO requests, thereby improving the performance of the shared cache.

[0098] In addition, when the above method is executed periodically, the access characteristics of the I / O requests of each category in the multiple categories that are periodically determined to access the shared cache can be timely adjusted, and the partition size and elimination algorithm of each category of IO requests in the shared cache can be regularly adjusted, thereby continuously ensuring the cache performance of the shared cache in the time dimension.

[0099] The embodiment of the present application also provides a shared cache management device, which is applied to a computing device, and the computing device can manage the shared cache by executing the method provided in the embodiment of the present application. The detailed description of the shared cache can refer to the description in the above terminology, which will not be repeated here. As an example, the computing device can be any computing device such as a general-purpose computer, a laptop, a tablet computer, a mobile phone, a vehicle-mounted terminal, etc.

[0100] Optionally, the computing device may be any computing device including a shared cache. Figure 1 In another exemplary embodiment, the computing device may be a server or cache node (e.g., Figure 2 ). In another exemplary embodiment, the computing device may be as follows Figure 3 The example shown includes any node of a shared cache, etc., but is not limited thereto. It is understood that when the computing device can be such as Figure 3 Any node including a shared cache as shown in the figure can be connected to the Figure 3 The method described below in the embodiment of the present application is executed based on the acquired data by interacting with other nodes including the shared cache to obtain the data required for executing the method provided in the embodiment of the present application (such as IO request), and executing the method described below in the embodiment of the present application based on the acquired data.

[0101] Optionally, the computing device may also be a computing device connected to and communicating with a node including a shared cache. Figure 3The node that provides cache for the cache pool is shown, and the computing device can be an independent node independent of the node that provides cache for the cache pool, such as a management node, which is not limited to this. In this case, the computing device can obtain the data (such as IO request) required to execute the method provided in the embodiment of the present application by interacting with the node that provides cache for the cache pool, and execute the method described below in the embodiment of the present application based on the obtained data.

[0102] refer to Figure 4 , Figure 4 FIG. 1 is a schematic diagram showing a hardware structure of a computing device provided in an embodiment of the present application. Figure 4 As shown, the computing device 40 includes a processor 401, a memory 402, a communication interface 403, and a bus 404. The processor 401, the memory 402, and the communication interface 403 are connected via the bus 404.

[0103] Processor 401 is the control center of computing device 40 and may be a general-purpose CPU. Processor 401 may also be other general-purpose processors, digital signal processors (digital signal processing, DSP), application-specific integrated circuits (application-specific integrated circuits, ASIC), field-programmable gate arrays (field-programmable gate arrays, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, graphics processing units (graphics processing units, GPU), neural processing units (neural processing units, NPU), tensor processing units (tensor processing units, TPU) or artificial intelligence (artificial intelligent) chips, data processors (data processing units, DPU), etc.

[0104] As an example, the processor 401 includes one or more CPUs, such as Figure 4 In addition, the present application does not limit the number of processor cores in each processor.

[0105] The memory 402 is used to store program instructions or data to be accessed by the application process. The processor 401 can implement the shared cache management method provided in the embodiment of the present application by executing the program instructions in the memory 402.

[0106] The memory 402 includes a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Among them, the volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), DRAM, synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous connection dynamic random access memory (SLDRAM) and direct rambus RAM (DR RAM). The non-volatile memory may be a storage class memory (SCM), a solid state drive (SSD), a hard disk drive (HDD), etc. Among them, the storage class memory may be, for example, a non-volatile memory (NVM), a phase-change memory (PCM), a persistent memory, etc.

[0107] In one possible implementation, the memory 402 exists independently of the processor 401. The memory 402 is connected to the processor 401 via a bus 404 and is used to store data, instructions or program codes. When the processor 401 calls and executes the instructions or program codes stored in the memory 402, the shared cache management method provided in the embodiment of the present application can be implemented.

[0108] In another possible implementation, the memory 402 and the processor 401 are integrated together.

[0109] Communication interface 403, used for computing device 40 and other devices (such as Figure 2 or Figure 3The computing nodes shown in FIG. 4 and the like) are connected through a communication network, and the communication network may be Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc. The communication interface 403 includes a receiving unit for receiving data / messages, and a sending unit for sending data / messages.

[0110] The bus 404 may be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, a high-speed serial computer expansion bus (PCIe), a compute express link (CXL) or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0111] It should be pointed out that Figure 4 The structure shown in the figure does not constitute a limitation on the computing device 40, except Figure 4 In addition to the components shown, the computing device 40 includes Figure 4 More or fewer components may be shown, or certain components may be combined, or the components may be arranged differently.

[0112] The following is a detailed description of the shared cache management method provided in the embodiment of the present application in conjunction with the accompanying drawings.

[0113] In an embodiment of the present application, a shared cache is used to cache data for operations (such as reading or writing) requested by IO requests initiated by multiple entities. In the following, an example is given in which the IO requests initiated by the multiple entities correspond to K categories and the shared cache corresponds to N elimination algorithms. That is, the IO requests initiated by the multiple entities include K categories of IO requests, and the shared cache is pre-equipped with N elimination algorithms. Wherein, K and N are integers greater than 1, respectively.

[0114] It should also be understood that each IO request carries a logical address, which is the logical address that the IO request wants to access. For example, an IO request reads the to-be-read data stored in the logical address it carries, or an IO request writes the to-be-written data to the logical address it carries. Therefore, in the following embodiments of the present application, the logical address carried by the IO request and the logical address accessed by the IO request can be used interchangeably.

[0115] Embodiment 1

[0116] In the scenario where the read and write caches of a shared cache are separated, the shared cache management method provided in the embodiment of the present application can be used to manage the read cache in the shared cache, or to manage the write cache in the shared cache. Among them, the read and write cache separation of the shared cache refers to the isolation of the read cache and the write cache in the shared cache by physical or software means. The read cache is used to cache the data requested to be read by the IO request initiated by the cache entity. The write cache is used to cache the data written by the IO request initiated by the cache entity.

[0117] refer to Figure 5 , Figure 5 The following is a flow chart of a method for managing a shared cache provided by an embodiment of the present application. Optionally, the method can be applied to Figure 1 The CPU shown, or applied to Figure 2 In the cache node shown, or applied to Figure 3 The method can be implemented by Figure 4 The method is executed by a computing device with the hardware structure shown, and includes the following steps.

[0118] S101, obtaining IO requests initiated by multiple entities, and determining the category of each IO request, wherein the IO requests initiated by multiple entities include K categories of IO requests.

[0119] Among them, since the computing device executes the process of the shared memory management method provided in the embodiment of the present application, it is carried out in parallel with the process of the IO request initiated by the entity to access the shared cache. Therefore, in the process of IO requests initiated by multiple entities to access the shared cache, the computing device obtains copies of the IO requests initiated by the multiple entities for accessing the shared cache. Thus, the computing device obtains IO requests initiated by multiple entities, and these IO requests are IO requests including K categories.

[0120] As an example, combining Figure 2 ,refer to Figure 6 , Figure 6 FIG. 1 shows a schematic diagram of an IO request initiated by an entity to access a shared cache. Figure 6As shown, cache node 2 includes a shared cache, and j computing nodes (including computing node 1, computing node 2, computing node 3, ..., and computing node j) can access the shared cache of cache node 2. In addition, the shared cache in cache node 2 also communicates with the back-end storage of cache node 2 (the back-end storage can be located inside cache node 2 or outside cache node 2). In this case, in the scenario of writing data, the shared cache can regularly flush the data written to the shared cache by j computing nodes through IO requests into the back-end storage. In the scenario of reading data, the shared cache can pre-load the data of the back-end storage into its own storage space so that j computing nodes can read these data through IO requests later. And, when j computing nodes access the shared cache through IO requests for reading data, the shared cache has a cache miss, then the shared cache can load the data to be read from the back-end storage so that j computing nodes can read the data to be read. In an embodiment of the present application, the computing device obtains a copy of the IO request for accessing the shared cache initiated by j computing nodes during the process of j computing nodes accessing the shared cache through IO requests, so as to execute the method provided in an embodiment of the present application.

[0121] It should be noted that when the method provided in the embodiment of the present application is used to manage the read cache in the shared cache, the IO request obtained by the computing device in S101 is an IO read request for reading data. When the method provided in the embodiment of the present application is used to manage the write cache in the shared cache, the IO request obtained by the computing device in S101 is an IO write request for writing data.

[0122] Further, the computing device determines a category of each acquired IO request.

[0123] In a possible implementation, the IO request initiated by the entity carries a category tag identifying the category to which the IO request belongs. In this way, the computing device determines the category of each IO request according to the category tag carried by each IO request in the acquired IO requests.

[0124] Optionally, the category tag carried in the IO request may be a category tag added to the IO request when the entity initiates the IO request. In this case, the category tag carried in the IO request may be used to indicate the entity that initiates the IO request. In other words, the category of the IO request is divided according to the entity that initiates the IO request. In this case, K categories of IO requests correspond to K entities, and the IO requests initiated by the same entity have the same category tag, that is, the IO requests initiated by the same entity belong to the same category. Among them, entities may be different applications, different processing cores, or different computing nodes, client devices, etc. that access a shared cache, without limitation.

[0125] In another possible implementation, the computing device may determine the category of each acquired IO request through a classifier, and the classifier is used to classify the IO requests into K categories of IO requests, and specifically to classify IO requests carrying logical addresses with high similarity into one category. The classifier is pre-generated based on the features of a certain number of IO requests accessing the logical addresses. The computing device pre-generates the classifier based on the features of a certain number of IO requests accessing the logical addresses. Please refer to the following description for a detailed description, which will not be repeated here.

[0126] Specifically, the computing device sequentially inputs the acquired logical address carried by each IO request into the classifier, and the classifier can output a category identifier indicating the category of each IO request.

[0127] Optionally, after determining the category of the IO request through a classifier, the computing device adds a category identifier indicating the category of the IO request to the IO request.

[0128] S102: Determine access characteristics of IO requests of each category in the K categories accessing the shared cache, where the access characteristics are the relationship between the hit rate of IO requests of each category in the K categories under N elimination algorithms and the cache size.

[0129] Among them, the N elimination algorithms are elimination algorithms pre-configured for the shared cache, that is, the shared cache corresponds to N elimination algorithms.

[0130] The computing device presets X cache sizes for each category of IO requests. For a category of IO requests (such as the first category of IO requests), the X cache sizes are the X cache sizes preset for the cache corresponding to the first category of IO requests. The cache corresponding to the first category of IO requests is the partition in the shared cache used to cache the read data requested by the first category of IO requests, and the cache size of the cache corresponding to the first category of IO requests is the partition size in the shared cache used to cache the read data requested by the first category of IO requests. It can be understood that the cache size preset by the computing device for each category of IO requests is smaller than the size of the shared cache.

[0131] It should be understood that the embodiment of the present application does not specifically limit the rule that the computing device presets X cache sizes for each category of IO requests, and the size interval between the X cache sizes.

[0132] As an example, the computing device presets three cache sizes for the first type of IO requests. Assuming that the size of the shared cache is 4M, the three cache sizes preset by the computing device for the first type of IO requests may be 1M, 2M, and 3M.

[0133] Optionally, the number of cache sizes preset by the computing device for each category of IO requests in the K categories may be X, that is, the number of cache sizes preset by the computing device for each category of IO requests in the K categories is the same. Of course, the number of cache sizes preset by the computing device for each category of IO requests in the K categories may also be different. For example, the number of cache sizes preset by the computing device for the first category of IO requests in the K categories is 3, the number of cache sizes preset by the computing device for the second category of IO requests in the K categories is 4, and so on. The second category of IO requests is any category of IO requests in the K categories except the first category.

[0134] For the sake of simplicity, the embodiments of the present application are described below by taking the example that the number of cache sizes preset by the computing device for IO requests of each category in K categories is X.

[0135] Optionally, the relationship between the hit rate and cache size of IO requests of each category in the K categories represented by the above access characteristics under N elimination algorithms can be characterized by the HRC of IO requests of each category in the K categories in the shared cache under N elimination algorithms. Alternatively, the relationship between the hit rate and cache size of IO requests of each category in the K categories represented by the above access characteristics under N elimination algorithms can be characterized by the MRC of IO requests of each category in the K categories in the shared cache under N elimination algorithms, which is not limited in the embodiments of the present application.

[0136] Specifically, the computing device determines the hit rate of IO requests of each category in caches of different sizes under N elimination algorithms based on the IO requests of each category in the K categories obtained, and then obtains the relationship between the hit rate and cache size of IO requests of each category in the K categories under the N elimination algorithms, that is, the access characteristics of IO requests of each category in the K categories accessing the shared cache.

[0137] Among them, the process of the computing device determining the access characteristics of the IO requests of each category in the K categories accessing the shared cache based on the IO requests of each category in the K categories obtained can be implemented by the following possible implementation methods.

[0138] In a first possible implementation, the computing device obtains the hit rate of each category of IO requests under N elimination algorithms in caches of different sizes by simulating in a shared cache, thereby obtaining the relationship between the hit rate and cache size of each category of IO requests under the N elimination algorithms, for example, obtaining the HRC or MRC of each category of IO requests under the N elimination algorithms.

[0139] Specifically, the computing device can obtain the relationship between the hit rate and cache size of each category of sample IO under N elimination algorithms by simulating the hit rate of each category of sample IO in different sizes of caches at a reduced scale in the shared cache, for example, obtaining the HRC or MRC of each category of sample IO under N elimination algorithms. Then, the computing device determines the relationship between the hit rate and cache size of each category of sample IO under N elimination algorithms as the relationship between the hit rate and cache size of each category of IO request under N elimination algorithms. For example, the computing device determines the HRC of each category of sample IO under N elimination algorithms as the HRC of each category of IO request under N elimination algorithms. Alternatively, the computing device determines the MRC of each category of sample IO under N elimination algorithms as the MRC of each category of IO request under N elimination algorithms.

[0140] The sample IO of each category is an IO request sampled by the computing device from the IO requests of each category in the K categories obtained in S101. The specific sampling process is described below and will not be repeated here.

[0141] Among them, the computing device simulates the hit rate of sample IO of each category in caches of different sizes under N elimination algorithms at a reduced scale in the shared cache, so as to obtain a detailed description of the relationship between the hit rate of sample IO of each category under N elimination algorithms and the cache size. Please refer to the description below and will not be repeated here.

[0142] In a second possible implementation, the computing device determines the hit rate of each category of IO requests in caches of different sizes under N elimination algorithms based on the reuse distance of each IO request in each category of IO requests and different cache sizes, thereby obtaining the relationship between the hit rate and cache size of each category of IO requests under the N elimination algorithms.

[0143] For example, for a first type of IO request among K types of IO requests and a first elimination algorithm among N elimination algorithms, the computing device may determine the hit rate of the first type of IO request when the first elimination algorithm is applied in caches of different sizes according to the reuse distance of each IO request in the first type of IO request and different cache sizes, thereby obtaining the relationship between the hit rate and cache size of the first type of IO request under the first elimination algorithm. The first elimination algorithm is any elimination algorithm among the N elimination algorithms.

[0144] Optionally, in order to save computing resources and efficiency of the computing device, the computing device can determine the hit rate of sample IO of each category in caches of different sizes under N elimination algorithms based on the reuse distance of each sample IO in each category of sample IO and different cache sizes, thereby obtaining the relationship between the hit rate and cache size of sample IO of each category under N elimination algorithms. Furthermore, the computing device determines the relationship between the hit rate and cache size of sample IO of each category under N elimination algorithms as the relationship between the hit rate and cache size of IO requests of each category under N elimination algorithms. Among them, the sample IO of each category is the IO request sampled by the computing device based on the IO request of each category in the K categories obtained in S101.

[0145] For example, for the first type of sample IO and the first elimination algorithm, the computing device can determine the hit rate of the first type of sample IO when the first elimination algorithm is applied in caches of different sizes based on the reuse distance of each sample IO in the first type of sample IO and different cache sizes, thereby obtaining the relationship between the hit rate and cache size of the first type of sample IO under the first elimination algorithm. Then, the computing device approximately determines the relationship between the hit rate and cache size of the first type of sample IO under the first elimination algorithm as the relationship between the hit rate and cache size of the first type of IO request under the first elimination algorithm. Among them, the detailed description of the reuse distance of the sample IO can refer to the detailed description of the reuse distance in the term above, which will not be repeated here.

[0146] Among them, the computing device determines the hit rate of the first type of sample IO when the first elimination algorithm is applied in caches of different sizes according to the reuse distance of each sample IO in the first type of sample IO and different cache sizes, thereby obtaining a detailed description of the relationship between the hit rate and cache size of the first type of sample IO under the first elimination algorithm. Please refer to the description below and will not be repeated here.

[0147] It can be seen that for a category of IO requests, under one elimination algorithm, the computing device can determine a set of relationships between different cache sizes and hit rates, that is, one HRC or MRC. Furthermore, for a category of IO requests, under N elimination algorithms, the computing device can determine N sets of relationships between cache sizes and hit rates, that is, N HRCs or MRCs. Furthermore, for K categories of IO requests, under N elimination algorithms, the computing device can determine N×K sets of relationships between cache sizes and hit rates, that is, N×K HRCs or MRCs.

[0148] It should be noted that when the computing device determines the HRC or MRC of each category of sample IO under N elimination algorithms, it can be obtained by using the first possible implementation method mentioned above, or by using the second possible implementation method. Of course, for the HRC or MRC of sample IO of a part of categories under a part of the elimination algorithms, the computing device can obtain it by using the first possible implementation method mentioned above, and for the HRC or MRC of sample IO of another part of categories under another part of the elimination algorithms, the computing device can determine it by using the second possible implementation method mentioned above, and the embodiments of the present application do not limit this.

[0149] The following briefly describes the process of obtaining sample IOs of each category by the computing device sampling the IO requests of each category in the K categories obtained in S101.

[0150] Specifically, the computing device samples the IO requests of each category in the acquired K categories based on the preset sampling condition to obtain sample IOs of each category, wherein the logical addresses carried by the sample IOs meet the preset sampling condition.

[0151] The preset sampling condition is a sampling condition designed based on a preset sampling rate. The preset sampling rate is preset by the computing device. For example, the preset sampling rate is 0.01, that is, one sample IO is sampled in 100 IO requests. It should be noted that when the computing device samples in each category of IO requests with the preset sampling condition designed according to the preset sampling rate, the sampling rate sampled in each category of IO requests can be the preset sampling rate.

[0152] As an example, if the preset sampling rate is L, the sample IO that meets the preset sampling condition satisfies: the remainder of the hash value of the logical address carried by the sample IO divided by the coefficient A is less than or equal to the product of the preset sampling rate L and the coefficient A. The hash value of the logical address can be obtained by hashing the logical address based on any hash algorithm, and the embodiment of the present application does not limit this. The coefficient A is a preset coefficient, and the embodiment of the present application does not limit the value of A.

[0153] It should be noted that in a category of IO requests, the preset sampling conditions can ensure that: when the computing device samples a sample IO that meets the preset sampling conditions in this category of IO requests, then the IO requests in this category of IO requests that have the same logical address as that carried by the sample IO can all be sampled by the computing device as sample IO. In other words, the preset sampling conditions can ensure that: when the computing device samples a sample IO that meets the preset sampling conditions in this category of IO requests, then the IO requests in this category of IO requests that have the same access logical address as that accessed by the sample IO can all be sampled by the computing device as sample IO. Therefore, any sampling conditions that can guarantee the above-mentioned sampling purpose should be within the protection scope of the embodiments of the present application.

[0154] Specifically, for any one of the K categories of IO requests (such as the first category of IO requests), the computing device determines whether each IO request in the first category of IO requests meets the preset sampling condition. If so, the computing device determines the IO request that meets the preset sampling condition as a sample IO. In this way, the computing device can sample multiple sample IOs at a preset sampling rate from the acquired first category of IO requests.

[0155] As an example, for any IO request in the first category of IO requests (such as the first IO request), the computing device first determines the hash value of the logical address carried in the first IO request, and further determines whether the remainder Y of the hash value divided by the coefficient A is less than or equal to the product P of the preset sampling rate L and the coefficient A. When Y is less than or equal to P, the computing device samples the first IO request, that is, the first IO request is determined as a sample IO of the first category of IO requests.

[0156] It can be understood that, in practice, since the IO requests initiated by the entity to access the shared cache are performed in real time, during this process, the computing device, after obtaining and determining the category of an IO request, determines whether the IO request meets the preset sampling conditions to determine whether to sample it.

[0157] S103: Determine the partition size and elimination algorithm of each category of IO requests in the shared cache according to the access characteristics of the IO requests of each category in the K categories and the hit rate of the shared cache.

[0158] Specifically, based on the relationship between the hit rate and cache size of the IO request of each category in the K categories determined by the computing device in S102 under the N elimination algorithms (i.e., the access characteristics of the IO request of each category in the K categories), the computing device can determine the X hit rates corresponding to the X cache sizes of the IO request of each category under each elimination algorithm. In this way, the computing device can determine the hit rates of the IO requests of K categories in the shared cache under different combinations according to the X hit rates corresponding to the X cache sizes of the IO request of each category under each elimination algorithm. Here, the detailed description of the X cache sizes can be referred to above and will not be repeated here.

[0159] The different combinations refer to the combinations of different cache sizes and different elimination algorithms corresponding to each category of IO requests. For example, if the cache sizes preset by the computing device include X, and the elimination algorithms pre-configured for the shared cache include N, then the combinations corresponding to one category of IO requests include X×N combinations.

[0160] It should be understood that based on the relationship between the hit rate of IO requests of each category in the K categories determined by the computing device in S102 under the N elimination algorithms and the cache size (i.e., the access characteristics of IO requests of each category in the K categories), it can be known that an IO request of one category under one combination corresponds to a hit rate of the IO request of the category under this combination. Therefore, the computing device can obtain a hit rate of IO requests of the K categories in the shared cache according to the hit rate of IO requests of each category under any combination.

[0161] Specifically, for the first category of IO requests among the K categories of IO requests, the computing device can determine the hit rate of the first category of IO requests in the shared cache under the first combination according to the hit rate of the first category of IO requests in any combination (such as the first combination) and the proportion of the first category of IO requests in the K categories of IO requests. Exemplarily, the computing device multiplies the hit rate of the first category of IO requests in the first combination and the proportion of the first category of IO requests in the K categories of IO requests to obtain the hit rate of the first category of IO requests in the shared cache under the first combination. For example, assuming that the hit rate of the first category of IO requests in the first combination is Z1, and the proportion of the first category of IO requests in the K categories of IO requests is R1, then the hit rate of the first category of IO requests in the shared cache under the first combination is K1=Z1×R1.

[0162] The proportion of the first category of IO requests in the K categories of IO requests is determined by the computing device based on the number of IO requests in the first category of IO requests and the total number of IO requests in the K categories. Optionally, after acquiring the K categories of IO requests initiated by the entity and determining the category of each IO request, the computing device can determine the proportion of each category of IO requests in the K categories of IO requests based on the total number of IO requests acquired and the number of IO requests in each category.

[0163] Similarly, the computing device can determine the hit rate of each category of IO requests in the shared cache under any combination. Furthermore, the computing device sums up the K hit rates of K categories of IO requests in the shared cache to obtain the hit rates of K categories of IO requests in the shared cache. Among them, the K hit rates used for summing are the hit rates of K categories of IO requests in the shared cache under any combination. For example, taking the value of K as 2, assuming that the hit rate of the first category of IO requests in the shared cache under the first combination is K1, and the hit rate of the second category of IO requests in the shared cache under the second combination is K2, then the hit rate of K categories of IO requests in the shared cache is: K1+K2.

[0164] It should be noted that when the computing device sums up the K hit rates of K categories of IO requests in the shared cache to obtain the hit rates of the K categories of IO requests in the shared cache, the sum of the cache sizes of the K categories of IO requests is less than or equal to the size of the shared cache.

[0165] Furthermore, for K categories of IO requests, the computing device can obtain the (X×N) hit rates of K categories of IO requests in the shared cache according to the X×N hit rates of each category of IO requests under X×N combinations. K A hit rate.

[0166] As an example, taking the value of K as 2, the value of N as 2, and the value of X as 2, in this case, the IO requests obtained by the computing device include the first category IO requests and the second category IO requests, and the proportion of the first category IO requests in the two categories of IO requests is R1, and the proportion of the second category IO requests in the two categories of IO requests is R2. The elimination algorithms pre-configured for the shared cache include the first elimination algorithm and the second elimination algorithm. The cache sizes preset by the computing device for each category of IO requests include cache size 1 and cache size 2. In addition, there are 4 combinations corresponding to each category of IO requests, and these 4 combinations include: combination 1 consisting of the first elimination algorithm and cache size 1, combination 2 consisting of the second elimination algorithm and cache size 1, combination 3 consisting of the first elimination algorithm and cache size 2, and combination 4 consisting of the second elimination algorithm and cache size 2. In this case, under the premise that the sum of the cache sizes of the first type of IO requests and the second type of IO requests is less than or equal to the shared cache, the computing device can calculate the (X×N) hit rates of the two types of IO requests in the shared cache based on the hit rates of each type of IO requests in X×N (i.e., 2×2=4) combinations. K (ie 4 2 =16) hit rates, respectively:

[0167] The hit rate 1 of the 2 categories of IO requests in the shared cache is: the product of the hit rate of the 1st category IO request under combination 1 and R1 (i.e., the hit rate of the 1st category IO request in the shared cache under combination 1) + the product of the hit rate of the 2nd category IO request under combination 1 and R2 (i.e., the hit rate of the 2nd category IO request in the shared cache under combination 1);

[0168] The hit rate 2 of the two categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 1 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 1) + the product of the hit rate of the second category IO request under combination 2 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 2);

[0169] The hit rate 3 of the 2 categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 1 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 1) + the product of the hit rate of the second category IO request under combination 3 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 3);

[0170] The hit rate 4 of the 2 categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 1 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 1) + the product of the hit rate of the second category IO request under combination 4 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 4);

[0171] The hit rate 5 of the two categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 2 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 2) + the product of the hit rate of the second category IO request under combination 1 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 1);

[0172] The hit rate 6 of the two categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 2 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 2) + the product of the hit rate of the second category IO request under combination 2 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 2);

[0173] The hit rate 7 of the two categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 2 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 2) + the product of the hit rate of the second category IO request under combination 3 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 3);

[0174] The hit rate 8 of the two categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 2 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 2) + the product of the hit rate of the second category IO request under combination 4 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 4);

[0175] The hit rate 9 of the two categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 3 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 3) + the product of the hit rate of the second category IO request under combination 1 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 1);

[0176] The hit rate 10 of the two categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 3 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 3) + the product of the hit rate of the second category IO request under combination 2 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 2);

[0177] The hit rate 11 of the two categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 3 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 3) + the product of the hit rate of the second category IO request under combination 3 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 3);

[0178] The hit rate 12 of the two categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 3 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 3) + the product of the hit rate of the second category IO request under combination 4 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 4);

[0179] The hit rate 13 of the two categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 4 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 4) + the product of the hit rate of the second category IO request under combination 1 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 1);

[0180] The hit rate 14 of the two categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 4 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 4) + the product of the hit rate of the second category IO request under combination 2 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 2);

[0181] The hit rate 15 of the two categories of IO requests in the shared cache is: the product of the hit rate of the first category IO request under combination 4 and R1 (i.e., the hit rate of the first category IO request in the shared cache under combination 4) + the product of the hit rate of the second category IO request under combination 3 and R2 (i.e., the hit rate of the second category IO request in the shared cache under combination 3);

[0182] The hit rate 16 of the two categories of IO requests in the shared cache is: the product of the hit rate of the first category IO requests under combination 4 and R1 (that is, the hit rate of the first category IO requests in the shared cache under combination 4) + the product of the hit rate of the second category IO requests under combination 4 and R2 (that is, the hit rate of the second category IO requests in the shared cache under combination 4).

[0183] Further, the computing device determines the maximum hit rate of K categories of IO requests in the shared cache, and determines the cache size indicated by the combination corresponding to each category when the maximum hit rate is obtained as the partition size for each category of IO requests in the shared cache, and determines the elimination algorithm indicated by the combination corresponding to each category when the maximum hit rate is obtained as the elimination algorithm for each category of IO requests in the shared cache.

[0184] For example, assuming that the hit rate of 15 of the above two categories of IO requests in the shared cache is the maximum hit rate of the above two categories of IO requests in the shared cache, the computing device will determine the cache size 2 indicated by the combination 4 corresponding to the first category IO request when the maximum hit rate is obtained as the partition size of the first category IO request in the shared cache, and will determine the second elimination algorithm indicated by the combination 4 corresponding to the first category IO request when the maximum hit rate is obtained as the elimination algorithm of the first category IO request in the shared cache. In addition, the computing device will determine the cache size 2 indicated by the combination 3 corresponding to the second category IO request when the maximum hit rate is obtained as the partition size of the second category IO request in the shared cache, and will determine the first elimination algorithm indicated by the combination 3 corresponding to the second category IO request when the maximum hit rate is obtained as the elimination algorithm of the second category IO request in the shared cache.

[0185] Optionally, in a possible implementation, the computing device may determine the maximum hit rates of K categories of IO requests in the shared cache under different combinations by solving the following formula (2) under the constraint of formula (1) based on X hit rates corresponding to X cache sizes determined under each elimination algorithm based on each category of IO requests.

[0186]

[0187] Wherein, m represents the preset cache size, the number of m is X preset by the computing device, and M represents the size of the shared cache, so the value of m satisfies m∈[0,M]. K represents the number of categories of IO requests, or it can be understood that K represents the number of partitions in the shared cache. It should be understood that one category of IO requests corresponds to one partition of the shared cache, that is, one partition of the shared cache is used to cache data of one category of IO requests. i represents the i-th partition among the K partitions, or it can be understood that i represents the i-th category of IO requests among the K categories of IO requests. m i represents the cache size corresponding to the i-th partition in the shared cache. p represents the elimination algorithm, {P1,P2,…,P N} represents N elimination algorithms, p i represents the elimination algorithm for the i-th partition configuration, p i Take {P1,P2,…,P N}. Ri represents the proportion of the IO requests of the i-th category in all IO requests.

[0188] Furthermore, formula (1) indicates that the sum of K cache sizes of K categories of IO requests in the shared cache is less than or equal to the size of the shared cache.

[0189] In formula (2) Indicates that in the elimination algorithm p i Under this condition, the IO request of the i-th category is i The hit rate when m i and p i This is a combination of the above. Indicates that in m i and p i The hit rate of the IO request of the i-th category in the shared cache under the combination of represents the hit rate of K categories of IO requests in the shared cache under different combinations. The argmax in formula (2) represents the The maximum value of , that is, argmax represents the maximum hit rate of K categories of IO requests in the shared cache under different combinations.

[0190] Thus, by solving formula (2) under the constraint of formula (1), the computing device can determine the maximum hit rate of K categories of IO requests in the shared cache under different combinations, and determine the cache size indicated by the combination corresponding to each category of IO requests when the maximum hit rate is obtained as the partition size of each category of IO requests in the shared cache, and determine the elimination algorithm indicated by the combination corresponding to each category of IO requests when the maximum hit rate is obtained as the elimination algorithm of each category of IO requests in the shared cache.

[0191] In another possible implementation, the computing device may determine the maximum hit rates of K categories of IO requests in the shared cache under different combinations by solving the following formula (3) under the constraint of formula (1) based on X hit rates corresponding to X cache sizes determined under each elimination algorithm based on each category of IO requests.

[0192]

[0193] Among them, m, M, K, i, m i , p, {P1,P2,…,P N}、p i For detailed descriptions of , and Ri, please refer to the description in the previous possible implementation method, which will not be repeated here.

[0194] In formula (3) Indicates that in the elimination algorithm p i Under this condition, the IO request of the i-th category is i The missing rate when m i and p i This is a combination of the above. Shown in m i and p iThe miss rate of the IO request of the i-th category in the shared cache under the combination of It can represent the miss rate of K categories of IO requests in the shared cache under different combinations. The argmin in formula (3) represents the miss rate of K categories of IO requests in the shared cache. The minimum value of , that is, argmin represents the minimum miss rate of K categories of IO requests in the shared cache under different combinations.

[0195] Thus, by solving formula (3) under the constraint of formula (1), the computing device can determine the minimum miss rate of K categories of IO requests in the shared cache under different combinations. Accordingly, the computing device determines the maximum hit rate of K categories of IO requests in the shared cache under different combinations. In this way, the computing device can determine the cache size indicated by the combination corresponding to each category of IO requests when the minimum miss rate is obtained as the partition size of each category of IO requests in the shared cache, and determine the elimination algorithm indicated by the combination corresponding to each category of IO requests when the minimum miss rate is obtained as the elimination algorithm of each category of IO requests in the shared cache.

[0196] S104. Configure the cache size of each category of IO requests in the shared cache as the partition size of each category of IO requests in the shared cache determined above, and configure the elimination algorithm of each category of IO requests in the shared cache as the elimination algorithm of each category of IO requests in the shared cache determined above.

[0197] Specifically, after determining the partition size and elimination algorithm for each category of IO requests in the shared cache, the computing device configures the cache size of each category of IO requests in the shared cache to the partition size of each category of IO requests in the shared cache determined above, and configures the elimination algorithm of each category of IO requests in the shared cache to the elimination algorithm of each category of IO requests in the shared cache determined above.

[0198] Furthermore, after configuring the cache size and elimination algorithm of each category of IO requests in the shared cache, different categories of IO requests initiated by the entity can access the shared cache under the configuration.

[0199] Specifically, in a data reading scenario, for any category of IO requests initiated by an entity (such as a first category of IO requests), during the process of the first category of IO requests accessing the shared cache under this configuration, when the shared cache monitors that the size of data cached by the first category of IO requests in the shared cache exceeds the eviction threshold, the data cached by the first category of IO requests in the shared cache is eliminated according to the eviction algorithm configured in the shared cache for the first category of IO requests.

[0200] In a data write scenario, for any type of IO request (such as the first type of IO request) initiated by an entity, during the process of the first type of IO request accessing the shared cache under this configuration, one possible implementation method is that when the shared cache monitors that the size of the data cached in the shared cache by the first type of IO request exceeds the elimination threshold, the data cached in the shared cache by the first type of IO request is eliminated according to the elimination algorithm configured in the shared cache for the first type of IO request. Another possible implementation method is that the shared cache periodically eliminates the data cached in the shared cache by the first type of IO request according to the elimination algorithm.

[0201] In summary, through the shared cache management method described in S101-S104, it is possible to determine the corresponding partition size and cache elimination algorithm in the shared cache for each category of IO requests based on the access characteristics of each category of IO requests, so as to improve the cache performance of each category of IO requests, and further improve the cache performance in the entire shared cache.

[0202] When the method described in S101-S104 is used to manage the read cache in the shared cache, the partition size and elimination algorithm determined for each category of IO request based on the method provided in the embodiment of the present application can improve the read hit rate of IO read requests in the shared cache, thereby improving data reading efficiency. When the method described in S101-S104 is used to manage the write cache in the shared cache, the partition size and elimination algorithm determined for each category of IO request based on the method provided in the embodiment of the present application can improve the write hit rate of IO write requests in the shared cache, thereby saving the number of times the shared cache flushes the disk to the back-end storage unit, that is, saving the data transmission bandwidth between the shared cache and the back-end storage unit.

[0203] In some embodiments, the methods described in S101-S104 above can be executed periodically. In this case, the IO request obtained by the computing device in S101 is the IO request initiated by the entity and obtained by the computing device within a cycle (e.g., the current cycle). Furthermore, the computing device executes S102-S103 based on the IO requests obtained within a cycle, thereby determining the partition size and elimination algorithm of each category of IO requests in the shared cache. Then in S104, the computing device can determine the partition size of each category of IO requests in the shared cache and the elimination algorithm based on each cycle to periodically configure the shared cache. In other words, the computing device can determine the partition size of each category of IO requests in the shared cache and the elimination algorithm based on each cycle to periodically adjust the size of each partition of the shared cache and its corresponding elimination algorithm.

[0204] It should be noted that when the method described in S101-S104 is executed for the first time, the shared cache can be configured according to the partition size and elimination algorithm specified by the user, or the shared cache is a pooled cache, which is not limited in this embodiment of the present application.

[0205] It can be seen that when the method described in S101-S104 is executed periodically, the shared cache can periodically adjust the cache size and elimination algorithm of each category of IO requests in the shared cache according to the cache size and elimination algorithm of each category of IO requests in the K categories periodically determined by the computing device, thereby achieving a hit rate of IO requests in the shared cache that is guaranteed in the time domain, that is, ensuring the cache performance of the shared cache in the time domain.

[0206] Below, for the first type of sample IO sampled in the first type of IO request, and taking the first elimination algorithm among N elimination algorithms as an example, the process of "calculating the hit rate of each category of sample IO in the shared cache under N elimination algorithms with a reduced scale in the computing device, thereby obtaining the relationship between the hit rate and cache size of each category of sample IO under the N elimination algorithms" in S102 is explained by example.

[0207] Among them, the description of the first type of IO request, the first type of sample IO, and the first elimination algorithm can refer to the relevant description above, which will not be repeated here.

[0208] As an example, assuming that the number of cache sizes preset by the computing device for the first type of IO requests is 3 (i.e., X is 3), which are 1M, 2M, and 3M respectively, and the preset sampling rate L of the computing device in the first type of IO requests is 0.01, then when the computing device determines the hit rate of applying the first elimination algorithm in caches of different sizes for simulating the first type of sample IO, the corresponding cache sizes are 0.01M (i.e., 1M×0.01), 0.02M (2M×0.01), and 0.03M (3M×0.01). In this way, the computing device applies for caches of sizes 0.01M, 0.02M and 0.03M (hereinafter referred to as simulated caches) in the shared cache for the first type of sample IO, so as to simulate the hit rates of the first type of sample IO when the first elimination algorithm is applied in these three cache spaces, so as to obtain the hit rate of the first type of sample IO when the first elimination algorithm is applied in the cache with a cache size of 0.01, the hit rate of the first elimination algorithm when the first elimination algorithm is applied in the cache with a cache size of 0.02M, and the hit rate of the first elimination algorithm when the first elimination algorithm is applied in the cache with a cache size of 0.03M, and then the relationship between the hit rate and cache size of the first type of sample IO under the first elimination algorithm can be obtained, that is, the HRC of the first type of sample IO under the first elimination algorithm is obtained.

[0209] Taking the example that the computing device applies for a simulated cache 1 with a cache size of 0.01M in the shared cache for the first type of sample IO, the computing device can instruct each sample IO in the first type of sample IO to access the simulated cache 1 in turn, and count the number of hit sample IOs.

[0210] Specifically, when the simulation starts, the computing device may first instruct the first sample IO in the first type of sample IO to access the simulation cache 1. Since the simulation cache 1 is empty at this time, the computing device caches the logical address of the first sample IO in the simulation cache 1. Next, the computing device instructs the second sample IO in the first type of sample IO to access the simulation cache 1. If the logical address of the second sample IO is the same as the logical address of the first sample IO, it means that the second sample IO hits in the simulation cache 1. If the logical address of the second sample IO is different from the logical address of the first sample IO, it means that the second sample IO does not hit in the simulation cache 1. At this time, the computing device caches the logical address of the second IO sample in the simulation cache 1. Similarly, the computing device instructs each sample IO in the first type of sample IO to access the simulation cache 1 in turn, and counts the number of sample IOs that hit. It should be noted that the computing device also monitors the size of the logical addresses stored in the simulation cache 1 during the simulation process. When the size of the logical addresses stored in the simulation cache 1 exceeds a certain threshold, a part of the logical addresses in the simulation cache 1 is eliminated (for example, a part is deleted, or a part is invalidated) through the first elimination algorithm.

[0211] Furthermore, the computing device calculates the hit rate of the first-category sample IO in the simulated cache 1 based on the total number of IOs of the first-category sample IO and the number of hit sample IOs. Similarly, the computing device simulates and counts the number of sample IOs that hit the first-category sample IO in the simulated cache 2 with a cache size of 0.02M, and calculates the hit rate of the first-category sample IO in the simulated cache 2 based on the total number of IOs of the first-category sample IO and the number of hit sample IOs. And, the computing device simulates and counts the number of sample IOs that hit the first-category sample IO in the simulated cache 3 with a cache size of 0.03M, and calculates the hit rate of the first-category sample IO in the simulated cache 3 based on the total number of IOs of the first-category sample IO and the number of hit sample IOs.

[0212] In this way, if the computing device presets X cache sizes for the first type of IO request, the computing device can determine the X hit rates corresponding to the X cache sizes when the first type of sample IO is applied with the first elimination algorithm. Thus, the computing device obtains the relationship between the hit rate and cache size of the first type of sample IO under the first elimination algorithm, that is, obtains the HRC of the first type of sample IO under the first elimination algorithm.

[0213] Optionally, the computing device may also first determine the number of sample IOs that are missed based on the total number of IOs of the first type of sample IOs and the number of sample IOs that are hit, and then calculate the miss rate of the first type of sample IOs in the simulated cache 1 based on the total number of IOs of the first type of sample IOs and the number of sample IOs that are missed. Similarly, the computing device simulates and counts the number of sample IOs that are hit by the first type of sample IOs in the simulated cache 2, and first determines the number of sample IOs that are missed based on the total number of IOs of the first type of sample IOs and the number of sample IOs that are hit, and then calculates the miss rate of the first type of sample IOs in the simulated cache 2 based on the total number of IOs of the first type of sample IOs and the number of sample IOs that are missed. And, the computing device simulates and counts the number of sample IOs that are hit by the first type of sample IOs in the simulated cache 3, and first determines the number of sample IOs that are missed based on the total number of IOs of the first type of sample IOs and the number of sample IOs that are hit, and then calculates the miss rate of the first type of sample IOs in the simulated cache 3 based on the total number of IOs of the first type of sample IOs and the number of sample IOs that are missed.

[0214] In this way, if the computing device presets X cache sizes for the first type of IO request, the computing device can determine the X miss rates corresponding to the X cache sizes when the first elimination algorithm is applied to the first type of sample IO. Thus, the computing device obtains the relationship between the miss rate and cache size of the first type of sample IO under the first elimination algorithm, that is, obtains the MRC of the first type of sample IO under the first elimination algorithm.

[0215] It should be noted that, since the simulated cache requested by the computing device for the sample IO is empty at the beginning of each simulation, it is equivalent to the state after the cache is restarted after power failure (i.e., cache cold start). Therefore, after determining the HRC of each category of sample IO, the computing device can appropriately increase the hit rate in the HRC curve, or, after determining the MRC of each category of sample IO, appropriately reduce the miss rate in the large MRC curve to compensate for the cache miss caused by the cache cold start. It should be understood that what is actually intended to be simulated in the embodiments of the present application is the hit rate of IO requests when there is data cached in the cache, and the hit rate simulated when the cache is empty at the beginning is usually lower than the hit rate when there is data cached in the cache. Therefore, the embodiments of the present application compensate for the hit rate in the simulated HRC or the miss rate in the MRC.

[0216] Among them, the specific compensation value for cold start compensation of the hit rate in the simulated HRC or the miss rate in the MRC in the embodiment of the present application can be determined by the sample IO of each category used to simulate the HRC or MRC. For example, the embodiment of the present application can use the number of sample IOs that miss within a preset time length when the first type of sample IO starts to be simulated in the applied simulation cache as the specific compensation value for the hit rate compensation in the simulated HRC or the miss rate in the MRC. Here, the embodiment of the present application does not specifically limit the preset time length, and does not limit the specific method for determining the compensation value.

[0217] It should also be noted that when an IO request initiated by an entity accesses a shared cache, a data prefetching mechanism can be used. That is, the entity will preload data that may be accessed in the future into the shared cache. Therefore, when a subsequent IO request initiated by the entity accesses the prefetched data, it will definitely hit. Therefore, the hit rate of IO requests under the prefetching mechanism is higher than the hit rate of IO requests when the prefetching mechanism is not adopted. Therefore, after determining the HRC of the sample IO of each category, the computing device can appropriately reduce the hit rate in the HRC curve, or, after determining the MRC of the sample IO of each category, appropriately increase the miss rate in the MRC curve, so as to reduce the impact of the prefetching mechanism on the hit rate of IO requests.

[0218] Among them, the specific value of reducing the hit rate in the HRC simulated by the embodiment of the present application (or increasing the specific value of the miss rate in the MRC simulated by the embodiment of the present application) can be the number of sample IOs that access pre-fetched data in the sample IO of each category used to simulate the HRC or MRC. It should be understood that when an IO request initiated by an entity accesses pre-fetched data, the entity will mark the pre-fetch identifier in the IO request to indicate that the data accessed by the IO request is pre-fetched. Therefore, the computing device only needs to count the number of sample IOs that access pre-fetched data in the sample IO of each category to determine the specific value of reducing the hit rate in the simulated HRC (or increasing the specific value of the miss rate in the MRC simulated by the embodiment of the present application).

[0219] Similarly, the computing device can simulate the relationship between the hit rate and cache size of the first category of sample IO under N elimination algorithms, and simulate the relationship between the hit rate and cache size of each category of sample IO under N elimination algorithms.

[0220] Further, the computing device determines the relationship between the hit rate and cache size of each category of sample IO under the N elimination algorithms as the relationship between the hit rate and cache size of each category of IO requests under the N elimination algorithms. For example, the computing device determines the HRC of each category of sample IO under the N elimination algorithms as the HRC of each category of IO requests under the N elimination algorithms. Alternatively, the computing device determines the MRC of each category of sample IO under the N elimination algorithms as the MRC of each category of IO requests under the N elimination algorithms.

[0221] The following is a detailed description of the process in S102 in which "the computing device determines the hit rate of the first type of sample IO when the first elimination algorithm is applied in caches of different sizes according to the reuse distance of each sample IO in the first type of sample IO and different cache sizes, thereby obtaining the relationship between the hit rate and cache size of the first type of sample IO under the first elimination algorithm."

[0222] Specifically, the computing device may determine the reuse distance of each sample IO in the first category of sample IOs based on the logical address accessed by each sample IO in the first category of sample IOs. Then, in the first category of sample IOs, the computing device counts the number of the same reuse distances in the reuse distances of each sample IO, that is, counts the frequency of each reuse distance.

[0223] As an example, assume that the first type of sample IO includes 10 sample IOs, and the logical addresses accessed in sequence in these 10 sample IOs are (a, b, c, d, a, d, a, c, b, a), and the computing device obtains the reuse distance of each sample IO in these 10 sample IOs by statistics (∞, ∞, ∞, ∞, 3, 1, 1, 2, 3, 2). Then, the computing device counts the number of the same reuse distance based on the reuse distance of each sample IO in these 10 sample IOs. Among them, the number of reuse distances of ∞ (i.e., frequency) is 4, the number of reuse distances of 1 (i.e., frequency) is 2, the number of reuse distances of 2 (i.e., frequency) is 2, and the number of reuse records of 3 is (i.e., frequency) 2.

[0224] Further, the computing device determines the hit rate of the first type of sample IO at different cache sizes based on the preset rules and the number of the first type of sample IO with the same reuse distance counted, thereby obtaining the relationship between the hit rate and cache size of the first type of sample IO under the first elimination algorithm. Among them, the preset rules are designed based on the elimination algorithm, one elimination algorithm corresponds to one preset rule, and N elimination algorithms correspond to N preset rules. The embodiment of the present application does not limit the specific design of the preset rules corresponding to the elimination algorithm.

[0225] Taking the first elimination algorithm as the least recently used algorithm (LRU) as an example, for the first type of sample IO, the preset rule corresponding to LRU can be: the number of reuse distances less than the preset value is determined as the number of hits of the first type of sample IO when the cache size is the preset value of the data size requested to access the sample IO. Here, the computing device can pre-determine the value of the preset value corresponding to each cache size based on the value of each cache size in the preset X cache sizes and the size of the data accessed by a single sample IO. For example, one of the cache sizes in the X cache sizes is 1M, and the size of a single sample IO is 4K, then the value of the preset value = 1M / 4K = 256. In this way, the computing device can determine the X number of hits corresponding to the X cache sizes when the first elimination algorithm is applied to the first type of sample IO. Among them, the description of the X cache sizes is referred to the above description and will not be repeated here.

[0226] Among them, optionally, the embodiment of the present application can assume that the size of the data accessed by each sample IO is the same, for example, all are 4K, and there is no limitation on this. In this case, the size of the data requested to be accessed by a single sample IO is preset in the computing device. Optionally, the computing device can also determine the average size of the data requested to be accessed by each sample IO based on the number of sample IOs included in the first category of sample IOs and the total size of the data requested to be accessed by the first category of sample IOs, and use the average size as the size of the data requested to be accessed by a single sample IO, and the embodiment of the present application does not limit this.

[0227] As an example, assume that the first category of sample IO includes 10 sample IOs, and based on the statistics of these 10 sample IOs, the number of samples with a reuse distance of ∞ is 4, the number of samples with a reuse distance of 1 is 2, the number of samples with a reuse distance of 2 is 2, and the number of samples with a reuse distance of 3 is 2.

[0228] If the preset value is 1, the computing device determines that there is no reuse distance less than 1, so the computing device determines that when the cache size is the size of the access data requested by 1 sample IO, the number of hits of the first type of sample IO is 0.

[0229] If the preset value is 2, the computing device can determine the number of reuse distances less than 2 (i.e., the number of reuse distances of 1) as the number of hits of the first type of sample IO when the cache size is the size of the data requested to be accessed by 2 sample IOs.

[0230] If the preset value is 3, the computing device can determine the number of reuse distances 4 less than 3 (i.e., the sum of the number of reuse distances 2 of 1 and the number of reuse distances 2 of 2 (i.e., 2+2)) as the number of hits of the first type of sample IO when the cache size is the size of the data requested to be accessed by 3 sample IOs.

[0231] If the preset value is 4, the computing device can determine the number of reuse distances less than 4, 6 (i.e., the sum of the number of reuse distances of 1, 2, and 2 of the reuse distance of 3 (i.e., 2+2+2)) as the number of hits of the first type of sample IO when the cache size is the size of the data requested to be accessed by 4 sample IOs.

[0232] Furthermore, based on the values ​​of different preset numerical values, the preset rules corresponding to the LRU algorithm, and the number of first-category sample IOs with the same reuse distance counted, the computing device can determine the number of hits of the first-category sample IO at different cache sizes under the LRU algorithm. Further, based on the determined number of hits and the number of first-category sample IOs, the computing device can calculate the hit rate of the first-category sample IO at different cache sizes under the LRU algorithm. In this way, for the X cache sizes preset by the computing device for the first-category IO request, the computing device determines the X hit rates corresponding to the X cache sizes of the first-category sample IO when the LRU algorithm is applied. Thus, the computing device obtains the relationship between the hit rate and cache size of the first-category sample IO under the LRU algorithm, that is, the HRC of the first-category sample IO under the LRU algorithm.

[0233] Optionally, after determining the number of hits of the first type of sample IO under the LRU algorithm at different cache sizes, the computing device can determine the number of misses of the first type of sample IO under the LRU algorithm at different cache sizes based on the total number of the first type of sample IO and the number of hits of the first type of sample IO under the LRU algorithm at different cache sizes. Furthermore, the computing device calculates the miss rate of the first type of sample IO under the LRU algorithm at different cache sizes based on the total number of the first type of sample IO and the number of misses of the first type of sample IO under the LRU algorithm. In this way, for the X cache sizes preset by the computing device for the first type of IO request, the computing device determines the X hit rates corresponding to the X cache sizes of the first type of sample IO when the LRU algorithm is applied. Thus, the computing device obtains the relationship between the miss rate and cache size of the first type of sample IO under the LRU algorithm, that is, the MRC of the first type of sample IO under the LRU algorithm.

[0234] Similarly, based on the values ​​of different preset numerical values, N preset rules corresponding to N elimination algorithms, and the number of sample IOs of each category with the same reuse distance, the computing device can determine the number of hits (or misses) of sample IOs of each category under the N elimination algorithms at different cache sizes. Further, based on the determined number of hits (or misses) and the number of sample IOs of each category, the computing device can calculate the hit rate (or miss rate) of sample IOs of each category under the N elimination algorithms at different cache sizes. In this way, the computing device obtains the relationship between the hit rate and cache size (or the relationship between the miss rate and cache size) of sample IOs of each category under the N elimination algorithms, that is, the HRC (MRC) of sample IOs of each category under the N elimination algorithms.

[0235] The following is an explanation of the process of "the computing device pre-generates a classifier based on the features of a certain number of IO requests accessing the logical address" in S101.

[0236] Specifically, before S101, the method provided in the embodiment of the present application further includes: Figure 7 A method for generating a classifier is shown in FIG. Figure 7 As shown, before S101, the method provided in the embodiment of the present application also includes S101a-S101d.

[0237] S101a. Acquire multiple IO requests initiated by multiple entities.

[0238] The description of the computing device acquiring the multiple IO requests may refer to the description of acquiring the IO requests initiated by the entity in S101, which will not be repeated here.

[0239] Optionally, when the methods described in S101-S104 above are executed periodically, taking the first cycle as an example, in a possible implementation, the multiple IO requests obtained by the computing device in S101a are the multiple IO requests obtained by the computing device in the first time period of the first cycle. In this case, the K categories of IO requests obtained by the computing device in S101 are the K categories of IO requests obtained by the computing device in the second time period of the first cycle. Among them, the first time period is a time period in the first cycle that starts from the start time of the first cycle and has a preset time period. The second time period is the remaining time period in the first cycle except the first time period. Here, the embodiment of the present application does not limit the specific values ​​of the duration of the first cycle and the preset duration.

[0240] As an example, assuming that the first cycle is 1 hour, the start time of the first cycle is 10:00, and the preset duration is 10 minutes, the first time period is the time period from 10:00 to 10:10, and the second time period is the time period from 10:11 to 11:00. In this case, the multiple IO requests obtained by the computing device in S101a are the multiple IO requests obtained by the computing device within 10:00 to 10:10, and the K categories of IO requests obtained by the computing device in S101 are the K categories of IO requests obtained by the computing device within 10:11 to 11:00.

[0241] In another possible implementation, the multiple IO requests obtained by the computing device in S101a are the first preset number of IO requests in the timing sequence of all IO requests obtained by the computing device in the first cycle. In this case, the K categories of IO requests obtained by the computing device in S101 are the IO requests other than the preset number of IO requests in all IO requests obtained by the computing device in the first cycle. The specific value of the preset number is not limited in the embodiment of the present application.

[0242] As an example, assuming that the preset number is 1000, and all IO requests obtained by the computing device in the first cycle include 10,000 IO requests, the multiple IO requests obtained by the computing device in S101a are the first 1000 IO requests in the 10,000 IO requests in terms of timing, that is, the 1st to 1000th IO requests in the 10,000 IO requests in terms of timing. In this case, the K categories of IO requests obtained by the computing device in S101 are the 9,000 IO requests in the 10,000 IO requests except the 1st to 1000th IO requests, that is, the 1001st to 10,000th IO requests in the 10,000 IO requests in terms of timing.

[0243] S101b, extracting features of the multiple IO requests accessing logical addresses.

[0244] The characteristics of the multiple IO requests accessing the logical address include the access frequency of the multiple IO requests accessing the same logical address, and / or, include the reuse time of the logical address accessed by the multiple IO requests.

[0245] Optionally, after obtaining the above-mentioned multiple IO requests, for the logical address (such as the first logical address) accessed by any one of the multiple IO requests, the computing device counts the number of IO requests (such as the first number) that access the first logical address in the multiple IO requests. It can be understood that the first number is the access frequency of the above-mentioned multiple IO requests accessing the first logical address. Furthermore, the computing device determines the determined first number as the frequency characteristic of each IO request that accesses the first logical address in the above-mentioned multiple IO requests.

[0246] Similarly, the computing device may determine the frequency characteristics of each IO request among the multiple IO requests.

[0247] Optionally, in the process of obtaining the above-mentioned multiple IO requests, the computing device may determine the reuse time of the logical address accessed by each IO request for each IO request. Alternatively, after obtaining the above-mentioned multiple IO requests, the computing device may determine the reuse time of the logical address accessed by each IO request in the multiple IO requests. The detailed description of the reuse time can be referred to the description in the above terminology, which will not be repeated here.

[0248] It can be understood that, for the above-mentioned multiple IO requests, there may be at least two IO requests accessing the same logical address (such as the first logical address) among the multiple IO requests, and for the at least two IO requests, the reuse time of the first logical address determined by the computing device is different. In other words, for one logical address, the computing device can determine multiple different reuse times. Exemplarily, for 10 IO requests that access logical addresses (a, b, d, c, b, d, a, a, c, d) in sequence, the reuse time of the logical address d accessed by the 3rd IO request among the 10 requests is infinite, the reuse time of the logical address d accessed by the 6th IO request is 2, and the reuse time of the logical address d accessed by the 10th IO request is 3.

[0249] In this case, after determining the reuse time of the logical address accessed by each IO request, the computing device can select a reuse time from different reuse times of the same logical address, and use the selected reuse time as the reuse time feature of each IO request accessing the logical address.

[0250] Optionally, the computing device can arbitrarily select a reuse time from different reuse times of the same logical address, and use the selected reuse time as the reuse time feature of each IO request accessing the logical address. The reuse time arbitrarily selected by the computing device is a non-infinite reuse time. Alternatively, the computing device can average the multiple different reuse times of the same logical address determined (or round up / down after averaging), and use the average (or the rounded value after averaging) as the reuse time feature of each IO request accessing the logical address. This application is not limited to this. The multiple different reuse times used for averaging are multiple different reuse times other than the reuse time with an infinite value.

[0251] As an example, for 10 IO requests that sequentially access logical addresses (a, b, d, c, b, d, a, a, c, d), since the reuse time of the logical address d accessed by the 3rd IO request among the 10 requests is infinite, the reuse time of the logical address d accessed by the 6th IO request is 2, and the reuse time of the logical address d accessed by the 10th IO request is 3. Then the computing device can use 2 or 3 as the reuse time feature of each IO request accessing the logical address d. Alternatively, the computing device averages the reuse time of 2 for the logical address d accessed by the 6th IO request and the reuse time of 3 for the logical address d accessed by the 10th IO request, and rounds up (i.e., [(2+3) / 2] rounds up), and uses the averaged and rounded value 3 as the reuse time feature of each IO request accessing the logical address d.

[0252] S101c: According to the characteristics of the multiple IO requests accessing the logical addresses, the multiple IO requests are divided into K categories of IO requests.

[0253] Specifically, the computing device divides the plurality of IO requests into K categories of IO requests according to the characteristics of the plurality of IO requests accessing the logical addresses and at least one characteristic threshold, wherein the characteristic threshold includes a frequency threshold and / or a reuse time threshold.

[0254] In one possible case, when the characteristics of the multiple IO requests accessing the logical addresses include the access frequency of the multiple IO requests accessing the same logical address, the computing device divides the multiple IO requests into K categories of IO requests according to the frequency characteristics of each IO request in the multiple IO requests and K-1 frequency thresholds. It should be noted that the logical addresses accessed by the IO requests belonging to the same category have a high degree of similarity.

[0255] Optionally, the K-1 frequency thresholds may be frequency thresholds preset by a user. Alternatively, the K-1 frequency thresholds are the computing device dividing the multiple frequencies determined by S101b into K frequency ranges according to a first preset algorithm, and the K-1 critical frequencies between the K frequency ranges are the K-1 frequency thresholds. The first preset algorithm may be any classification algorithm, and the embodiment of the present application is not limited thereto. The logical addresses accessed by IO requests whose frequency characteristics belong to a frequency range have a high degree of similarity.

[0256] In another possible case, when the characteristics of the logical addresses accessed by the multiple IO requests include the reuse time of the logical addresses accessed by the multiple IO requests, the computing device divides the multiple IO requests into K categories of IO requests according to the reuse time characteristics of each IO request in the multiple IO requests and K-1 reuse time thresholds. It should be noted that the logical addresses accessed by the IO requests belonging to the same category have a high similarity.

[0257] Optionally, the K-1 reuse time thresholds may be user preset reuse time thresholds. Alternatively, the K-1 reuse time thresholds are obtained by dividing the multiple reuse times determined by S101b into K reuse time ranges according to a second preset algorithm, and the K-1 critical reuse times between the K reuse time ranges are the K-1 reuse time thresholds. The second preset algorithm may be any classification algorithm, which is not limited in comparison with the embodiments of the present application. The logical addresses accessed by IO requests whose reuse time characteristics belong to a reuse time range have a high degree of similarity.

[0258] In another possible scenario, when the characteristics of the multiple IO requests accessing the logical address include the access frequency of the multiple IO requests accessing the same logical address, and the reuse time of the logical address accessed by the multiple IO requests, the computing device divides the multiple IO requests into K categories of IO requests according to the frequency characteristics of each IO request in the multiple IO requests, p frequency thresholds, the reuse time characteristics of each IO request in the multiple IO requests, and q reuse time thresholds. Wherein, p and q are both positive integers, and p+q≤K-1. Wherein, the detailed description of the frequency threshold and the reuse time threshold can be referred to the above description and will not be repeated here.

[0259] Optionally, for multiple IO requests obtained by the computing device in S101a, the computing device may first divide the multiple IO requests into q+1 categories based on the reuse time characteristics of each IO request in the multiple IO requests and q reuse time thresholds. Furthermore, for at least one category of IO requests in the aforementioned q+1 categories, the computing device divides each category of IO requests in the at least one category into p+1 categories of IO requests based on the frequency characteristics of each IO request in the at least one category and p frequency thresholds, thereby achieving the division of the multiple IO requests into K categories of IO requests. It should be noted that the logical addresses accessed by IO requests belonging to the same category have a high degree of similarity.

[0260] As an example, take the values ​​of p and q as 1 and the value of K as 3. Figure 8For multiple IO requests obtained by the computing device in S101a, the computing device may first divide the multiple IO requests into a first category of IO requests and a second category of IO requests according to the reuse time characteristics of each IO request in the multiple IO requests and a reuse time threshold (such as threshold 1). The first category of IO requests are IO requests with a reuse time characteristic less than threshold 1, and the second category of IO requests are IO requests with a reuse time characteristic greater than threshold 1. The embodiment of the present application does not limit the case where the reuse time characteristic is equal to threshold 1. For example, the IO request with a reuse time characteristic equal to threshold 1 may be an IO request of the first category, or an IO request of the second category.

[0261] Furthermore, for any one of the IO requests of the first category or the IO requests of the second category, such as the IO requests of the second category, the computing device divides the IO requests of the second category into IO requests of the third category and IO requests of the fourth category according to the frequency characteristics of each IO request in the IO requests of the second category and a frequency threshold (such as threshold 2). The IO requests of the third category are IO requests with a frequency characteristic less than threshold 2, and the IO requests of the fourth category are IO requests with a frequency characteristic greater than threshold 2. The embodiment of the present application does not limit the case where the frequency characteristic is equal to threshold 2. For example, the IO request with a frequency characteristic equal to threshold 2 can be an IO request of the third category, or an IO request of the fourth category.

[0262] In this way, the multiple IO requests acquired by the computing device in S101a are divided into IO requests of the first category, IO requests of the third category, and IO requests of the fourth category.

[0263] Optionally, for multiple IO requests obtained by the computing device in S101a, the computing device may first divide the multiple IO requests into p+1 categories based on the frequency characteristics of each IO request in the multiple IO requests and p frequency thresholds. Furthermore, for at least one category of IO requests in the aforementioned p+1 categories, the computing device divides the IO requests in each category in the at least one category into q+1 categories based on the reuse time characteristics of each IO request in the multiple IO requests and q reuse time thresholds, thereby achieving the division of the multiple IO requests into K categories of IO requests. It should be noted that the logical addresses accessed by IO requests belonging to the same category have a high degree of similarity.

[0264] S101d. Generate a classifier according to the multiple IO requests divided into K categories.

[0265] After dividing the multiple IO requests obtained above into K categories of IO requests, the computing device marks a category identifier for each IO request, where the category identifier is used to indicate the category to which the IO request belongs.

[0266] For example, the computing device divides the multiple IO requests obtained above into two categories of IO requests (including IO requests of category 1 and IO requests of category 2). In this way, the computing device marks each IO request in category 1 with an identifier 1 indicating category 1, and marks each IO request in category 2 with an identifier 2 indicating category 2.

[0267] Furthermore, the computing device generates a classifier according to the sample parameters of each IO request in the above-mentioned multiple IO requests and the third preset algorithm. The sample parameters of an IO request include the category identifier of the IO request and the logical address carried by the IO request. The third preset algorithm can be any supervised learning classification algorithm, which is not limited in the embodiment of the present application.

[0268] Optionally, the third preset algorithm may be a k-Nearest-Neighbor (KNN) algorithm, or a KNN+prototype algorithm. Among them, the KNN+prototype algorithm is simpler than the KNN algorithm. Furthermore, the computing device may input the sample parameters of each IO request in the above-mentioned multiple IO requests into KNN (or KNN+prototype) to obtain a classifier. In this way, when the classifier receives the logical address of the IO request to be classified, it may first determine the sample parameters of the logical address with the greatest similarity to the logical address, and output the category identifier in the sample parameter to indicate the category of the IO request to be classified.

[0269] For example, in S101, the computing device may input the acquired logical address 1 of the IO request 1 into the classifier generated above. In this way, the classifier determines that the logical address with the greatest similarity to the logical address 1 is the logical address 2. Furthermore, the classifier outputs the category identifier 1 of the sample parameter 1 where the logical address 2 is located, so as to indicate the category of the IO request 1.

[0270] In this way, based on the method described in S101a-S101d, the computing device can generate a classifier for classifying IO requests. When the method described in S101-S104 is executed periodically, the classifier generated by the computing device based on a part of IO requests in the current cycle can be used to classify another part of IO requests in the current cycle (for example, into K categories), thereby determining the partition size and elimination algorithm of each category of IO requests in the shared cache according to the access characteristics of the K categories of IO requests accessing the shared cache.

[0271] In addition, the classifier generated by the computing device in the current cycle can be used to classify the IO requests initiated by the entity in the next cycle of the current cycle, so that the classified IO requests access the cache corresponding to it. Therefore, based on the method described in S101a~S101d, the entity that initiates the IO request does not need to mark the IO request with a category tag for classification, so that the entity that initiates the IO request does not incur additional resource overhead. Moreover, since the method provided in the embodiment of the present application does not invade the upper layer of the cache (i.e., the entity that initiates the IO request), the method provided in the embodiment of the present application can be applied to a general cache system for diversified customers without the need for ecological support.

[0272] Embodiment 2

[0273] The shared cache management method provided in the embodiment of the present application can also be applied to the scenario of read-write cache fusion in the shared cache. The read-write cache fusion of the shared cache means that the shared cache does not distinguish between the read cache and the write cache, and the IO request for reading data and the IO request for writing data share the shared cache.

[0274] In the scenario of read-write cache fusion in shared cache, refer to Fig. 9 , Fig. 9 A schematic diagram of another shared cache management method provided in an embodiment of the present application is shown. Optionally, the method can be applied to Figure 1 The CPU shown, or applied to Figure 2 In the cache node shown, or applied to Figure 3 The method can be implemented by Figure 4 The method is executed by a computing device with the hardware structure shown, and includes the following steps.

[0275] S201, obtaining IO requests initiated by multiple entities, and determining the category of each IO request, wherein the IO requests initiated by multiple entities include K categories of IO requests, and each category of IO requests in the K categories includes an IO read request and an IO write request.

[0276] The detailed description of the computing device obtaining IO requests initiated by multiple entities and determining the category of each IO request can be referred to the description of S101 and will not be repeated here.

[0277] It should be noted that in S101, the IO request obtained by the computing device is an IO read request for reading data or an IO write request for writing data. In S201, the IO request obtained by the computing device includes an IO read request for reading data and an IO write request for writing data.

[0278] S202: Determine a read access characteristic of an IO read request of each of the K categories accessing a shared cache, and determine a write access characteristic of an IO write request of each of the K categories accessing a shared cache.

[0279] The read access characteristic is the relationship between the read hit rate and cache size of the IO read requests of each category in the K categories under N elimination algorithms, and the write access characteristic is the relationship between the write hit rate and cache size of the IO write requests of each category in the K categories under N elimination algorithms. Here, the read hit rate refers to the hit rate of IO read requests in the cache. The write hit rate refers to the hit rate of IO write requests in the cache.

[0280] Specifically, the computing device determines the read access characteristics of the IO read requests of each category in the K categories accessing the shared cache according to the IO read requests of each category in the K categories obtained. Also, the computing device determines the write access characteristics of the IO write requests of each category in the K categories accessing the shared cache according to the IO write requests of each category in the K categories obtained.

[0281] Among them, the computing device determines the detailed description of the read access characteristics of the IO read requests of each category in the K categories to access the shared cache according to the IO read requests of each category in the K categories, and determines the detailed description of the write access characteristics of the IO write requests of each category in the K categories to access the shared cache according to the IO write requests of each category in the K categories. Both of them can refer to the relevant description in S102 "The computing device determines the access characteristics of the IO requests of each category in the K categories to access the shared cache based on the IO requests of each category in the K categories obtained", and no further details are given.

[0282] S203. Determine the partition size and elimination algorithm of each category of IO requests in the shared cache according to the read access characteristics of the IO read requests of each category in the K categories, the write access characteristics of the IO write requests of each category in the K categories, and the hit rate of the shared cache.

[0283] Specifically, the computing device determines the partition size of each category of IO requests in the shared cache and the detailed description of the elimination algorithm based on the read access characteristics of the IO read requests of each category in the K categories, the write access characteristics of the IO write requests of each category in the K categories and the hit rate of the shared cache. Please refer to the description of S103.

[0284] It should be noted that, with respect to "the computing device can obtain a hit rate of K categories of IO requests in the shared cache according to the hit rate of each category of IO requests in any combination" in S103, in S203, the computing device can obtain the comprehensive hit rate of K categories of IO requests in the shared cache according to the read hit rate of each category of IO read requests in any combination, the read hit weight coefficient, the write hit rate of each category of IO write requests in any combination, and the write hit weight coefficient.

[0285] Among them, the read hit weight coefficient is used to characterize the degree of influence of the read hit rate of each category of IO read requests in the shared cache on the comprehensive hit rate of the shared cache, and the write hit weight coefficient is used to characterize the degree of influence of the write hit rate of each category of IO write requests in the shared cache on the comprehensive hit rate of the shared cache. Among them, the comprehensive hit rate of the shared cache is the hit rate of K categories of IO requests in the shared cache. Among them, the embodiments of the present application do not limit the specific values ​​of the read hit weight coefficient and the write hit weight coefficient. For example, the read hit weight coefficient and the write hit weight coefficient are both preset weight coefficients. For another example, the read hit weight coefficient and / or the write hit weight coefficient can be determined based on the access pattern of the entity to the shared cache in a recent period of time, or the read hit weight coefficient and / or the write hit weight coefficient can be determined based on the estimated access pattern of the entity to the shared cache in the future period of time.

[0286] Specifically, for any one of the K categories of IO requests (such as the first category of IO requests), the computing device may determine the hit rate of the first category of IO read requests in the shared cache in the first combination according to the hit rate of the IO read requests in the first category of IO requests (the first category of IO read requests) in any combination (such as the first combination) and the proportion of the first category of IO read requests in the K categories of IO requests. For example, the computing device performs a product operation on the hit rate of the first category of IO read requests in the first combination and the proportion of the first category of IO read requests in the K categories of IO requests, thereby obtaining the hit rate of the first category of IO read requests in the shared cache in the first combination.

[0287] Similarly, for IO write requests in the first category of IO requests (hereinafter referred to as first category IO write requests), the computing device may determine the hit rate of the first category IO write requests in the shared cache under the first combination according to the hit rate of the first category IO write requests in any combination (such as the first combination) and the proportion of the first category IO write requests in the K categories of IO requests. For example, the computing device performs a product operation on the hit rate of the first category IO write requests in the first combination and the proportion of the first category IO write requests in the K categories of IO requests, thereby obtaining the hit rate of the first category IO write requests in the shared cache under the first combination.

[0288] Among them, for detailed descriptions of the proportion of the first type of IO read requests in the K types of IO requests and the proportion of the first type of IO write requests in the K types of IO requests, please refer to the relevant description in S103 and will not be repeated here.

[0289] Furthermore, the computing device determines the hit rate of the first type of IO requests in the shared cache under the first combination according to the hit rate of the first type of IO read requests in the shared cache under the first combination (such as the first hit rate), the read hit weight coefficient, the hit rate of the first type of IO write requests in the shared cache under the first combination (such as the second hit rate), and the write hit weight coefficient. For example, the computing device performs a sum operation on the product of the first hit rate and the read hit weight coefficient, and the product of the second hit rate and the write hit weight coefficient, thereby obtaining the hit rate of the first type of IO requests in the shared cache under the first combination. As an example, assuming that the read hit weight coefficient is W1 and the write hit weight coefficient is W2, the hit rate of the first type of IO requests in the shared cache under the first combination is: first hit rate × W1 + second hit rate × W2.

[0290] Similarly, the computing device can determine the hit rate of each category of IO requests in the shared cache under any combination. Then, the computing device sums up the K hit rates of K categories of IO requests in the shared cache to obtain the hit rates of K categories of IO requests in the shared cache. Furthermore, for K categories of IO requests, the computing device can obtain the (X×N) hit rates of K categories of IO requests in the shared cache based on the X×N hit rates of each category of IO requests in X×N combinations. K hit rate. Further, the computing device determines the maximum hit rate of K categories of IO requests in the shared cache, and determines the cache size indicated by the combination corresponding to each category when the maximum hit rate is obtained as the partition size of each category of IO requests in the shared cache, and determines the elimination algorithm indicated by the combination corresponding to each category when the maximum hit rate is obtained as the elimination algorithm of each category of IO requests in the shared cache. For specific instructions, please refer to the description in S103, which will not be repeated here.

[0291] It should be noted that when the computing device sums up the K hit rates of K categories of IO requests in the shared cache to obtain the hit rates of the K categories of IO requests in the shared cache, the sum of the cache sizes of the K categories of IO requests is less than or equal to the size of the shared cache.

[0292] Then, the computing device executes S104.

[0293] In this way, through the shared cache management method described in S201-S104, in the scenario of read-write cache fusion in the shared cache, it is possible to determine and configure a suitable cache size and elimination algorithm for each category of IO requests, thereby improving the hit rate of IO requests in the shared cache, and further improving the overall cache performance of the shared cache.

[0294] In some embodiments, the methods described in S201-S104 above can be executed periodically, and the relevant descriptions can refer to the relevant descriptions in the first embodiment, which will not be repeated here. By periodically executing S201-S104, the shared cache can periodically adjust the cache size and elimination algorithm of each category of IO requests in the shared cache according to the cache size and elimination algorithm of each category of IO requests in the K categories periodically determined by the computing device, thereby achieving the hit rate of IO requests in the shared cache in the time domain, that is, ensuring the cache performance of the shared cache in the time domain.

[0295] Embodiment 3

[0296] In the scenario of read-write cache fusion in shared cache, refer to Fig.10 , Fig.10 A schematic diagram of a flow chart of another shared cache management method provided in an embodiment of the present application is shown. Optionally, the method can be applied to Figure 1 The CPU shown, or applied to Figure 2 In the cache node shown, or applied to Figure 3 The node shown in . And can be composed of Figure 4 The computing device of the hardware structure shown in the figure executes: The computing device first executes S201, and then the computing device executes S302.

[0297] S302: Determine access characteristics of IO requests of each category in the K categories accessing the shared cache according to IO read requests of each category in the K categories, read hit weight coefficients, IO write requests of each category in the K categories, and write hit weight coefficients.

[0298] Among them, the detailed description of the read hit weight coefficient and the write hit weight coefficient can be referred to above and will not be repeated here.

[0299] Specifically, the computing device first determines the read hit rate of each category of IO read requests in caches of different sizes under N elimination algorithms based on the IO read requests of each category in the K categories obtained, and the computing device determines the write hit rate of each category of IO write requests in caches of different sizes under N elimination algorithms based on the IO write requests of each category in the K categories obtained. For example, taking the first category of IO requests among the K categories of IO requests as an example, the computing device can determine the read hit rate of the first category of IO read requests in caches of different sizes under N elimination algorithms based on the first category of IO read requests obtained. And, the computing device determines the write hit rate of the first category of IO write requests in caches of different sizes under N elimination algorithms based on the first category of IO write requests obtained.

[0300] Among them, the description of IO read request, read hit rate, IO write request, write hit rate, first type IO read request, and first type IO write request can all refer to the above related description and will not be repeated here.

[0301] Among them, the computing device determines the detailed description of the read hit rate of IO read requests of each category in caches of different sizes under N elimination algorithms based on the IO read requests of each category in the K categories obtained, and the computing device determines the detailed description of the write hit rate of IO write requests of each category in caches of different sizes under N elimination algorithms based on the IO write requests of each category in the K categories obtained. Both of these can refer to the relevant description of determining the hit rate of IO requests of each category in caches of different sizes under N elimination algorithms in S102, and will not be repeated here.

[0302] Furthermore, for the first category of IO requests among the K categories of IO requests, under the same elimination algorithm and the same cache size, the computing device adds the product of the read hit rate and the read hit weight coefficient of the first category IO read requests, and the product of the write hit rate and the write hit weight coefficient of the first category IO write requests, thereby obtaining the hit rate of the first category IO requests under the elimination algorithm and cache size.

[0303] Similarly, the computing device can determine the hit rate of each category of IO requests in caches of different sizes under the N elimination algorithms. In this way, the relationship between the hit rate and cache size of each category of IO requests in the K categories under the N elimination algorithms is obtained, that is, the access characteristics of each category of IO requests in the K categories accessing the shared cache are obtained.

[0304] Then, the computing device executes S103 - S104 .

[0305] In this way, through Fig.10The shared cache management method can determine and configure a suitable cache size and elimination algorithm for each category of IO request in the scenario of read-write cache fusion in the shared cache, thereby improving the hit rate of IO requests in the shared cache and further improving the overall cache performance of the shared cache.

[0306] In some embodiments, the above Fig.10 The method described above can be executed periodically. For related descriptions, please refer to the related descriptions in the first embodiment, which will not be repeated here. Fig.10 According to the method described, the shared cache can periodically adjust the cache size and elimination algorithm of each category of IO requests in the shared cache according to the cache size and elimination algorithm of each category of IO requests in K categories periodically determined by the computing device, thereby ensuring the hit rate of IO requests in the shared cache in the time domain, that is, ensuring the cache performance of the shared cache in the time domain.

[0307] The above mainly introduces the solution provided in the embodiment of the present application from the perspective of method.

[0308] In order to achieve the above functions, Fig.11 As shown, Fig.11 FIG. 1 is a schematic diagram showing the structure of a shared cache management device 110 provided in an embodiment of the present application. The management device 110 is used to execute the above-mentioned shared cache management method, for example, to execute Figure 5 , Figure 7 , Fig. 9 or Fig.10 The management device 110 may include a determining unit 111 and a configuring unit 112.

[0309] The determination unit 111 is used to determine the access characteristics of IO requests of each category in the K categories accessing the shared cache, and to determine the partition size and elimination algorithm of each category of IO requests in the shared cache according to the access characteristics of the K categories of IO requests and the hit rate of the shared cache. The access characteristics are the relationship between the hit rate and cache size of IO requests of each category in the K categories under N elimination algorithms. The configuration unit 112 is used to configure the cache size of each category of IO requests in the shared cache to the determined partition size of each category of IO requests in the shared cache, and to configure the elimination algorithm of each category of IO requests in the shared cache to the determined elimination algorithm of each category of IO requests in the shared cache.

[0310] As an example, combining Figure 5 , the determining unit 111 may be used to execute S102 and S103, and the configuring unit 112 may be used to execute S104. Fig. 9, the determining unit 111 can be used to execute S202 and S203, and the configuring unit 112 can be used to execute S104. Fig.10 , the determining unit 111 can be used to execute S302 and S103, and the configuring unit 112 can be used to execute S104.

[0311] Optionally, the management device 110 further includes: a simulation unit 113, configured to simulate, in a shared cache, the hit rate of applying the first elimination algorithm to IO requests of each category in the K categories in caches of different sizes for a first elimination algorithm among the N elimination algorithms, so as to obtain a relationship between the hit rate and the cache size. The first elimination algorithm is any one of the N elimination algorithms.

[0312] Optionally, the determination unit 111 is specifically used to: for a first elimination algorithm among the N elimination algorithms, determine the hit rate of applying the first elimination algorithm to the first type of IO requests in caches of different sizes according to the reuse distance of each IO request in the first type of IO requests and different cache sizes, so as to obtain the relationship between the hit rate and the cache size. The first elimination algorithm is any one of the N elimination algorithms, and the first type of IO request is any one of the K categories of IO requests.

[0313] Optionally, the determination unit 111 is further specifically used to: determine the hit rates of K categories of IO requests in the shared cache under each combination according to the X hit rates corresponding to the X cache sizes determined under each elimination algorithm based on each category of IO requests, and determine the cache size corresponding to each category of IO requests when the hit rate of the K categories of IO requests in the shared cache is the maximum as the partition size of each category of IO requests in the shared cache, and determine the elimination algorithm corresponding to each category of IO requests when the hit rate of the K categories of IO requests in the shared cache is the maximum as the elimination algorithm of each category of IO requests in the shared cache. For any one category of the K categories of IO requests, the X cache sizes and the N elimination algorithms constitute X*N combinations, each of which includes a cache size and an elimination algorithm; the X cache sizes are the X cache sizes preset for the cache corresponding to each category of IO requests.

[0314] As an example, combining Figure 5 , the determining unit 111 may be used to execute S103. Fig. 9 , the determining unit 111 can be used to execute S203.

[0315] Optionally, the management device 110 further includes: an acquisition unit 114, configured to acquire multiple IO requests before determining the access characteristics of the IO requests of each category in the K categories to access the shared cache. A classification unit 115, configured to classify the IO requests into K categories according to the characteristics of the addresses of the data accessed by the multiple IO requests or according to the category tags carried in the multiple IO requests.

[0316] As an example, combining Figure 5 , the acquisition unit 114 and the classification unit 115 can be used to execute S101.

[0317] Optionally, the shared cache is an LLC of a CPU in a computing device, and the multiple IO requests are IO requests initiated by multiple processing cores in the CPU.

[0318] Optionally, the shared cache is a cache in a cache node, and the multiple IO requests are IO requests initiated by multiple computing nodes that access the cache node.

[0319] Optionally, the shared cache is a cache pool formed by caches in multiple nodes, and the multiple IO requests are IO requests initiated by multiple computing nodes that access the cache pool.

[0320] Optionally, the above access characteristics are represented by HRC or MRC of the IO request.

[0321] Optionally, the determination unit 111 is also used to periodically determine the access characteristics of IO requests of each category in the K categories accessing the shared cache. For the access characteristics of IO requests of each category in the K categories determined in the first cycle accessing the shared cache, the determination unit 111 is specifically used to determine the partition size and elimination algorithm of IO requests of each category in the shared cache in the first cycle according to the access characteristics of IO requests of the K categories determined in the first cycle and the hit rate of the shared cache, wherein the first cycle is any cycle for determining the access characteristics of IO requests of each category in the K categories accessing the shared cache.

[0322] For the detailed description of the above optional methods, please refer to the above method embodiments, which will not be repeated here. In addition, the explanation of any management device 110 provided above and the description of the beneficial effects can refer to the above corresponding method embodiments, which will not be repeated here.

[0323] As an example, combining Figure 4 The functions implemented by the determination unit 111, the configuration unit 112, the simulation unit 113 and the classification unit 115 in the management device 110 can be realized by Figure 4 Processor 401 in the execution Figure 4 The functions implemented by the acquisition unit 114 can be implemented by the program code in the memory 402 in the memory 402. Figure 4 The communication interface 403 in is implemented.

[0324] Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0325] It should be noted that Fig.11 The division of modules in the example is schematic and is only a logical function division. There may be other division methods in actual implementation. For example, two or more functions may be integrated into one processing module. The above integrated modules may be implemented in the form of hardware or software function modules.

[0326] The present application also provides a computer program product and a computer-readable storage medium for storing the computer program product. The computer program product may include one or more program instructions, which, when executed by one or more processors, can provide the above Figure 5 , Figure 7 , Fig. 9 or Fig.10 Thus, for example, reference to Figure 5 One or more features of S101 to S104 may be undertaken by one or more instructions in the computer program product.

[0327] In some examples, such as for executing Figure 5 , Figure 7 , Fig. 9 or Fig.10 The shared cache management device of the method may be configured to provide various operations, functions, or actions in response to one or more program instructions stored in a computer-readable storage medium.

[0328] The present application also provides a computing device, which can be used to execute the above Figure 5 , Figure 7 , Fig. 9 or Fig.10 The method described is used to implement the management of the shared cache.

[0329] Optionally, the computing device may be the same device as the device including the shared cache, or the computing device may be a device connected to and communicating with the device including the shared cache. For detailed description, please refer to Figure 4 The relevant description of the computing device in will not be repeated here.

[0330] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When executing instructions on a computer and executing a computer, a process or function according to an embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, data center, etc. that contains one or more servers that can be integrated with a medium. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0331] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for managing a shared cache, characterized in that: The shared cache is used to cache data requested by multiple input and output (IO) requests, the multiple IO requests include K categories of IO requests, and the shared cache includes N elimination algorithms; the method includes: Determine an access characteristic of IO requests of each category in the K categories accessing the shared cache, wherein the access characteristic is a relationship between a hit rate and a cache size of the IO requests of each category under the N elimination algorithms; Determine, according to the access characteristics of the K categories of IO requests and the hit rate of the shared cache, a partition size of each category of IO requests in the shared cache and an elimination algorithm of each category of IO requests in the shared cache; The determined partition size of each category of IO requests in the shared cache is the cache size of each category of IO requests in the shared cache, and the determined elimination algorithm of each category of IO requests in the shared cache is the elimination algorithm of each category of IO requests in the shared cache.

2. The method according to claim 1, characterized in that Determining the access characteristics of the IO request of each category in the K categories accessing the shared cache includes: For a first elimination algorithm among the N elimination algorithms, the hit rate of applying the first elimination algorithm in caches of different sizes to IO requests of each category in the K categories is simulated in the shared cache to obtain a relationship between the hit rate and the cache size; wherein the first elimination algorithm is any one of the N elimination algorithms.

3. The method according to claim 1, characterized in that Determining the access characteristics of the IO request of each category in the K categories accessing the shared cache includes: For a first elimination algorithm among the N elimination algorithms, a hit rate of applying the first elimination algorithm to the first category of IO requests in caches of different sizes is determined according to a reuse distance of each IO request in the first category of IO requests and different cache sizes, so as to obtain a relationship between the hit rate and the cache size; wherein the first elimination algorithm is any one of the N elimination algorithms, and the first category of IO requests is IO requests of any one category among the K categories.

4. The method according to any one of claims 1 to 3, characterized in that The method of determining the partition size of each category of IO requests in the shared cache and the elimination algorithm of each category of IO requests in the shared cache according to the access characteristics of the K categories of IO requests and the hit rate of the shared cache includes: According to the X hit rates corresponding to the X cache sizes determined under each elimination algorithm based on each category of IO requests, the hit rates of the K categories of IO requests in the shared cache under each combination are determined; wherein, for any one category of the K categories of IO requests, the X cache sizes and the N elimination algorithms constitute X*N combinations, each combination including a cache size and an elimination algorithm; the X cache sizes are X cache sizes preset for the cache corresponding to each category of IO requests; The cache size corresponding to each category of IO requests when the hit rate of the K categories of IO requests in the shared cache is maximized is determined as the partition size of each category of IO requests in the shared cache, and the elimination algorithm corresponding to each category of IO requests when the hit rate of the K categories of IO requests in the shared cache is maximized is determined as the elimination algorithm of each category of IO requests in the shared cache.

5. The method according to any one of claims 1 to 4, characterized in that Before determining the access characteristics of the IO requests of each category in the K categories accessing the shared cache, the method further includes: Obtain the multiple IO requests; The IO requests are divided into the K categories according to the characteristics of addresses of data accessed by the multiple IO requests or according to category tags carried in the multiple IO requests.

6. The method according to any one of claims 1 to 5, characterized in that The shared cache is a level 3 cache LLC of a central processing unit CPU in a computing device, and the multiple IO requests are IO requests initiated by multiple processing cores in the CPU.

7. The method according to any one of claims 1 to 5, characterized in that The shared cache is a cache in a cache node, and the multiple IO requests are IO requests initiated by multiple computing nodes that access the cache node.

8. The method according to any one of claims 1 to 5, characterized in that The shared cache is a cache pool composed of caches in multiple nodes, and the multiple IO requests are IO requests initiated by multiple computing nodes accessing the cache pool.

9. The method according to any one of claims 1 to 8, characterized in that The access characteristic is characterized by a hit rate curve HRC or a miss rate curve MRC of the IO request.

10. The method according to any one of claims 1 to 9, characterized in that Determining the access characteristics of the IO request of each category in the K categories accessing the shared cache includes: Periodically determining access characteristics of IO requests of each category in the K categories accessing the shared cache; For the access characteristics of the IO requests of each category in the K categories determined in the first cycle accessing the shared cache, determining the partition size and elimination algorithm of the IO requests of each category in the shared cache according to the access characteristics of the IO requests of the K categories and the hit rate of the shared cache includes: Based on the access characteristics of the K categories of IO requests and the hit rate of the shared cache determined in the first cycle, the partition size and elimination algorithm of each category of IO requests in the shared cache are determined in the first cycle; the first cycle is any cycle for determining the access characteristics of IO requests of each category in the K categories accessing the shared cache.

11. A shared cache management device, characterized in that: The shared cache is used to cache data requested by multiple input and output (IO) requests, the multiple IO requests include K categories of IO requests, and the shared cache includes N elimination algorithms; the device includes: a determining unit, configured to determine an access characteristic of IO requests of each category in the K categories accessing the shared cache, wherein the access characteristic is a relationship between a hit rate and a cache size of the IO requests of each category in the K categories under the N elimination algorithms; and to determine a partition size of the IO requests of each category in the shared cache and an elimination algorithm of the IO requests of each category in the shared cache according to the access characteristics of the IO requests of the K categories and the hit rate of the shared cache; The determined partition size of each category of IO requests in the shared cache is the cache size of each category of IO requests in the shared cache, and the determined elimination algorithm of each category of IO requests in the shared cache is the elimination algorithm of each category of IO requests in the shared cache.

12. The device according to claim 11, characterized in that The device also includes: A simulation unit is used to simulate, in the shared cache, a hit rate of applying the first elimination algorithm to IO requests of each category in the K categories in caches of different sizes for a first elimination algorithm among the N elimination algorithms, so as to obtain a relationship between the hit rate and the cache size; wherein the first elimination algorithm is any one of the N elimination algorithms.

13. The device according to claim 11, characterized in that The determining unit is specifically used for: For a first elimination algorithm among the N elimination algorithms, a hit rate of applying the first elimination algorithm to the first category of IO requests in caches of different sizes is determined according to a reuse distance of each IO request in the first category of IO requests and different cache sizes, so as to obtain a relationship between the hit rate and the cache size; wherein the first elimination algorithm is any one of the N elimination algorithms, and the first category of IO requests is IO requests of any one category among the K categories.

14. The device according to any one of claims 11 to 13, characterized in that The determining unit is further specifically configured to: According to the X hit rates corresponding to the X cache sizes determined under each elimination algorithm based on each category of IO requests, the hit rates of the K categories of IO requests in the shared cache under each combination are determined; wherein, for any one category of the K categories of IO requests, the X cache sizes and the N elimination algorithms constitute X*N combinations, each combination including a cache size and an elimination algorithm; the X cache sizes are X cache sizes preset for the cache corresponding to each category of IO requests; The cache size corresponding to each category of IO requests when the hit rate of the K categories of IO requests in the shared cache is maximized is determined as the partition size of each category of IO requests in the shared cache, and the elimination algorithm corresponding to each category of IO requests when the hit rate of the K categories of IO requests in the shared cache is maximized is determined as the elimination algorithm of each category of IO requests in the shared cache.

15. The device according to any one of claims 11 to 14, characterized in that The device also includes: an acquisition unit, configured to acquire the plurality of IO requests before determining access characteristics of the IO requests of each category in the K categories accessing the shared cache; The classification unit is used to classify the IO requests into the K categories according to the characteristics of the addresses of the data accessed by the multiple IO requests or according to the category tags carried in the multiple IO requests.

16. The device according to any one of claims 11 to 15, characterized in that The shared cache is a level 3 cache LLC of a central processing unit CPU in a computing device, and the multiple IO requests are IO requests initiated by multiple processing cores in the CPU.

17. The device according to any one of claims 11 to 15, characterized in that The shared cache is a cache in a cache node, and the multiple IO requests are IO requests initiated by multiple computing nodes that access the cache node.

18. The device according to any one of claims 11 to 15, characterized in that The shared cache is a cache pool composed of caches in multiple nodes, and the multiple IO requests are IO requests initiated by multiple computing nodes accessing the cache pool.

19. The device according to any one of claims 11 to 18, characterized in that The access characteristic is characterized by a hit rate curve HRC or a miss rate curve MRC of the IO request.

20. The device according to any one of claims 11 to 19, characterized in that The determining unit is further used to periodically determine the access characteristics of the IO requests of each category in the K categories accessing the shared cache; For the access characteristics of the IO requests of each category in the K categories determined in the first cycle accessing the shared cache, the determining unit is specifically used to determine the partition size and elimination algorithm of the IO requests of each category in the shared cache in the first cycle according to the access characteristics of the K categories of IO requests determined in the first cycle and the hit rate of the shared cache; The first cycle is any cycle for determining access characteristics of IO requests of each category in the K categories accessing the shared cache.

21. A computing device, characterized in that The computing device is used to manage a shared cache, and the computing device includes: a memory, and one or more processors, wherein the one or more processors are configured to read program instructions stored in the memory to execute the method according to any one of claims 1 to 10.

22. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes program instructions. When the program instructions are executed on a computer or a processor, the computer or the processor executes the method according to any one of claims 1 to 10.

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