Visual chip security implementation module, device and method
By superimposing the PUF SEL timing signal in the CMOS image sensor, unpredictable PUF sequences are generated, and the problems of large computing volume and high cost in the prior art are solved, and high security guarantees of the vision chip are achieved.
Patent Information
- Application Number
- CN202411334598.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2025-01-10
AI Technical Summary
The existing CMOS time domain image sensor PUF generation method has a large amount of calculation, high cost and difficult to implement, making it difficult to ensure chip security and image encryption of vision chips.
Two CMOS image sensor pixel units are used to superimpose the PUF SEL timing signals through the exact same control timing, and output 0 or 1 signals using the comparator to generate an unpredictable and repeatable PUF sequence for chip security.
It realizes the security of vision chips with small computing volume, low cost and easy to achieve. It uses the image sensor's own characteristics to generate a unique sequence for authentication or encryption, and improves the confidentiality of the chip.
Smart Images
Figure CN119299879A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of vision chip security, and in particular to a vision chip security implementation module, device and method. Background Art
[0002] In recent years, there have been many cyber security incidents in the power system. As the foundation of the construction of important national facilities, the power system has always been one of the important targets of cyber attacks. Security protection of the power system is of great significance to ensure the safe and stable operation of the power grid. The commonly used encryption method in general security is key encryption, and the commonly used encryption methods are AES, DES, RSA, etc., but these encryption methods also have the risk of being cracked.
[0003] PUFs rely on random physical factors that are unpredictable and uncontrollable, are natively present and / or accidentally introduced during the manufacturing process, and unlike traditional cryptographic methods that use a single stored key, PUFs work by implementing challenge-response authentication. For a given PUF, a specific input, called a "challenge," will produce an output response that is unique to that specific PUF and is therefore unclonable.
[0004] There are many technical means to implement PUF. SRAM-based PUF has the advantages of high reliability, scalability and ease of use. It is the current mainstream PUF application solution, but it requires an additional security chip.
[0005] A vision chip is a semiconductor integrated system-on-chip chip consisting of an image sensor array and an array-type parallel information processor. It overcomes the bottleneck of serial data transmission and serial information processing speed in existing visual image systems, and can achieve high-speed image acquisition and intelligent visual information processing at a maximum speed of more than one thousand frames per second on the chip. It has broad application prospects in the fields of real-time tracking of high-speed moving targets, machine vision, virtual reality, fast image recognition, energy and electricity, intelligent transportation, and various intelligent toys. Commonly used image sensors include charge-coupled devices (CCDs), which are Coupled Charge Devices, and complementary metal oxide semiconductor (CMOS) image sensors.
[0006] See attached Figure 1 , which is a traditional CMOS image sensor pixel unit, includes a transfer transistor MOS1, a reset transistor MOS2, a source follower transistor MOS3, a row selection transistor MOS4, a clock control line TG, a clock control line RST, a clock control line SEL and a photodiode PD.
[0007] The input end of MOS1 is connected to the photodiode PD, the output end is connected to the output end of MOS2 and the control end of MOS3, and the control end is connected to the clock control line TG.
[0008] The input end of MOS2 is connected to Vcc, the output end is connected to the output end of MOS1 and the control end of MOS3, and the control end is connected to the clock control line RST.
[0009] The input end of MOS3 is connected to Vcc, and the output end is connected to the input end of MOS4.
[0010] The output end of MOS4 is connected to the column output bus, and the control end is connected to the clock control line SEL.
[0011] See attached Figure 2 , is the timing within one cycle of the pixel circuit of the traditional CMOS image sensor. The t1 time period is the reset stage, which resets the circuit to the initial state for signal acquisition in this cycle; in the t2 time period, the photodiode PD is exposed, and PD collects the electron-hole pairs generated by the incident light to accumulate signals; the t3 time period is for resetting the floating diffusion layer FD of the photodiode, and after resetting, the FD node voltage returns to Vcc; the t4 time period is used for signal acquisition, and the acquired signal is output from the column output bus.
[0012] Due to process changes caused by semiconductor process fluctuations in the silicon-based chip manufacturing process, different inherent properties such as path delay and transistor threshold voltage will occur, resulting in each physical chip being unique after tape-out. These changes, including path delay, are randomly distributed between different chips, but are deterministic and reusable for a given chip. The Physical Unclonable Function (PUF) uses this inherent difference that naturally occurs in the semiconductor manufacturing process to generate a unique identification for each chip as the chip's unique identity, namely the "digital fingerprint". PUF technology provides digital fingerprints for physical chips and is an important solution for achieving hardware security on resource-constrained electronic devices, with the advantages of being lightweight and unique.
[0013] The existing PUF generation method of CMOS time-domain image sensors usually achieves PUF output by adding a Vref reference voltage. Because the pixel output fluctuates in a very small range, it is difficult to find a reference voltage source, which makes the PUF generation method difficult to implement, making it difficult to ensure the chip security of the vision chip, as well as image encryption and identity authentication.
[0014] CN114826622A discloses an optical reconfigurable PUF device based on a CMOS image sensor, including a bias adjustment circuit, an image sensor, a dual-mode row decoder, a column selector, a readout circuit and a comparator. The image sensor is a pixel array composed of multiple pixel units. The bias adjustment circuit is connected to each column of pixel units, the dual-mode row decoder is connected to each pixel unit respectively, the column selector is connected to each pixel unit respectively through the readout circuit, and the comparator is connected to the readout circuit. The above-mentioned PUF device is based on the mainstream APS architecture of CMOS image sensors and is combined with traditional circuits for multiplexing. It can not only meet the imaging requirements but also generate keys using physical unclonable functions. It uses the process errors of the pixel units in the image sensor during the manufacturing process to obtain a nonlinear random sequence signal containing a large number of CRPs, thereby obtaining an unclonable function device. In this patent, each unclonable function is generated by a combination of multiple pixel outputs, which is not convenient for analysis and requires a large amount of calculation, so the cost is high. Summary of the invention
[0015] In order to solve the shortcomings of the prior art, such as large amount of calculation, high cost and difficulty in implementation, the present invention provides a visual chip security implementation module, device and method.
[0016] The present invention adopts the following technical solution.
[0017] On one hand, the present invention discloses a visual chip security implementation module, comprising two CMOS image sensor pixel units, a first control transistor E1, a second control transistor E2, a first clock control line PUF SEL1, a second clock control line PUF SEL2 and a comparator, characterized in that:
[0018] The input end of the first control transistor E1 is connected to the first CMOS image sensor pixel unit, the output end is connected to the positive input end V+ or the negative input end V- of the comparator, and the control end is connected to the first clock control line PUF SEL1;
[0019] The input end of the second control transistor E2 is connected to the second CMOS image sensor pixel unit, the output end is connected to the inverting input end V- or the non-inverting input end V+ of the comparator, and the control end is connected to the second clock control line PUF SEL2;
[0020] The two CMOS image sensor pixel units have exactly the same control timing;
[0021] On the basis of the control timing of each CMOS image sensor pixel unit, the same PUF SEL timing signal is superimposed on the first clock control line PUFSEL1 and the second clock control line PUF SEL2, and based on the two CMOS image sensor pixel units fixedly arranged in pairs, each time the control timing is superimposed on the PUF SEL timing signal, the comparator can repeatedly and determine the output of a 0 or 1 signal;
[0022] The 0 or 1 signal output by each security implementation module is unpredictable, and the unpredictable 0 or 1 signal that can be repeated and determined is used as the identity of the security implementation module.
[0023] More preferably,
[0024] The first control transistor E1 and the second control transistor E2 are connected in parallel to the row selection transistors in the pixel units of the CMOS image sensor to which they are connected.
[0025] More preferably,
[0026] The CMOS image sensor pixel unit control timing sequence includes a t1 time period, a t2 time period, a t3 time period and a t4 time period;
[0027] The t1 time period is used to reset the circuit to an initial state;
[0028] During the t2 period, the photodiodes in the two CMOS image sensor pixel units are exposed to perform signal accumulation;
[0029] The t3 time period is used to reset the floating diffusion layers of the two photodiodes;
[0030] The t4 time period is used to collect signals from the two CMOS image sensor pixel units respectively and output the collected signals from the column output buses of the corresponding pixel units.
[0031] More preferably,
[0032] By superimposing the same PUF SEL timing signal on the first clock control line PUF SEL1 and the second clock control line PUF SEL2, a tpuf time period is increased, wherein the tpuf time period is within the t2 time period, and its end edge is the same as the t3 time period;
[0033] During the tpuf period, the comparator outputs a 0 or 1 signal while accumulating the signal.
[0034] The present application also claims protection for a vision chip security implementation device using the aforementioned vision chip security implementation module, including multiple vision chip security implementation modules, characterized in that:
[0035] Number each vision chip security implementation module;
[0036] Each vision chip security implementation module is based on its two CMOS image sensor pixel units that are fixed in pairs. It can unpredictably output 0 or 1 signals repeatedly and deterministically each time the control timing is superimposed on the PUF SEL timing signal, and read the output of each vision chip security implementation module in turn to generate a set of multi-bit PUF sequences for authentication or encryption.
[0037] This application also claims protection for a method for implementing visual chip security using the aforementioned visual chip security implementation device, which is characterized by:
[0038] Set up multiple vision chip security implementation modules;
[0039] The two CMOS image sensor pixel units in each vision chip security implementation module have exactly the same control timing;
[0040] On the basis of the control timing of each CMOS image sensor pixel unit, the same PUF SEL timing signal is superimposed on the first clock control line PUFSEL1 and the second clock control line PUF SEL2, and based on the two CMOS image sensor pixel units fixedly arranged in pairs, each time the control timing is superimposed on the PUF SEL timing signal, the comparator can repeatedly and determine the output of a 0 or 1 signal;
[0041] The 0 or 1 signal output by each security implementation module is unpredictable, and the unpredictable but repeatable and deterministic 0 or 1 signal is used as the identity of the security implementation module;
[0042] Each vision chip security implementation module output is read in turn to generate a set of multi-bit PUF sequences.
[0043] More preferably,
[0044] The CMOS image sensor pixel unit control timing sequence includes a t1 time period, a t2 time period, a t3 time period and a t4 time period;
[0045] The t1 time period is used to reset the circuit to an initial state;
[0046] During the t2 period, the photodiodes in the two CMOS image sensor pixel units are exposed to perform signal accumulation;
[0047] The t3 time period is used to reset the floating diffusion layers of the two photodiodes;
[0048] The t4 time period is used to collect signals from the two CMOS image sensor pixel units respectively and output the collected signals from the column output buses of the corresponding pixel units.
[0049] More preferably,
[0050] By superimposing the same PUF SEL timing signal on the first clock control line PUF SEL1 and the second clock control line PUF SEL2, a tpuf time period is increased, wherein the tpuf time period is within the t2 time period, and its end edge is the same as the t3 time period;
[0051] During the tpuf period, the comparator outputs a 0 or 1 signal while accumulating the signal.
[0052] On the other hand, the present application discloses an electronic device, including a processor and a storage medium; the characteristics are:
[0053] The storage medium is used to store instructions;
[0054] The processor is used to operate according to the instructions to execute the aforementioned vision chip security implementation method.
[0055] The present application also discloses a computer-readable storage medium having a computer program stored thereon, wherein the program implements the visual chip security implementation method when executed by a processor.
[0056] Compared with the prior art, the present invention has the following beneficial effects:
[0057] (1) A first control transistor, a first clock control line connected to the control end of the first control transistor, a second control transistor, a second clock control line connected to the control end of the second control transistor, and a comparator are added. The existing two CMOS image sensor pixel units have exactly the same control timing. By superimposing the same timing signal on the first clock control line and the second clock control line based on the control timing of each CMOS image sensor pixel unit, the outputs of the two pixels are compared to obtain a fixed 0 or 1 signal. Multiple pixels can generate a PUF sequence.
[0058] (2) The image sensor, which is indispensable in the vision chip, is used to achieve its own security, without the need for an additional security chip.
[0059] (3) Without introducing an external PUF chip, the PUF sequence is generated by utilizing the characteristics of the device itself.
[0060] By taking advantage of the heterogeneity of device performance in semiconductor processes and modifying the acquisition circuit, a unique sequence for the vision chip is generated, which can be used for authentication or encryption to achieve chip security.
[0061] The present invention also has outstanding advantages such as small amount of calculation, low cost and easy implementation.
[0062] In summary, the present invention utilizes the deviation caused by the semiconductor process of the CMOS image sensor to cause the threshold voltage of each transistor to be different, and generates a PUF sequence. Each CMOS image sensor has its own PUF sequence, and the PUF sequence is unique, achieving the characteristics of good confidentiality, and does not require the addition of additional PUF chips, which will not increase additional costs. The technical means of pixel output comparison is adopted to overcome the technical problems of chip security and achieve a high security technical effect for visual content. BRIEF DESCRIPTION OF THE DRAWINGS
[0063] Figure 1 It is a traditional CMOS image sensor pixel unit;
[0064] Figure 2 It is the timing within one cycle of the pixel circuit of a traditional CMOS image sensor;
[0065] Figure 3 It is an improved CMOS image sensor pixel unit;
[0066] Figure 4 It is the timing within one cycle of the improved CMOS image sensor pixel circuit. DETAILED DESCRIPTION
[0067] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. The embodiments described in this application are only part of the embodiments of the present invention, not all of them. Based on the spirit of the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.
[0068] A visual chip security implementation module, see attached Figure 3 , including two CMOS image sensor pixel units, a first control transistor E1, a second control transistor E2, a first clock control line PUF SEL1, a second clock control line PUF SEL2 and a comparator.
[0069] The input end of the first control transistor E1 is connected to the first CMOS image sensor pixel unit, the output end is connected to the positive input end V+ or the negative input end V- of the comparator, and the control end is connected to the first clock control line PUF SEL1;
[0070] The input end of the second control transistor E2 is connected to the second CMOS image sensor pixel unit, the output end is connected to the inverting input end V- or the non-inverting input end V+ of the comparator, and the control end is connected to the second clock control line PUF SEL2;
[0071] The first control transistor E1 and the second control transistor E2 are connected in parallel to the row selection transistors in the pixel units of the CMOS image sensor to which they are connected.
[0072] The two CMOS image sensor pixel units have exactly the same control timing;
[0073] On the basis of the control timing of each CMOS image sensor pixel unit, the same PUF SEL timing signal is superimposed on the first clock control line PUFSEL1 and the second clock control line PUF SEL2, and based on the two CMOS image sensor pixel units fixedly arranged in pairs, each time the control timing is superimposed on the PUF SEL timing signal, the comparator can repeatedly and determine the output of a 0 or 1 signal;
[0074] See attached Figure 2 The CMOS image sensor pixel unit control timing includes a t1 time period, a t2 time period, a t3 time period and a t4 time period; in the t1 time period, the t2 time period, the t3 time period and the t4 time period, the SEL1 clock control line and the SEL2 clock control line are superimposed with the same SEL timing signal, the TG1 clock control line and the TG2 clock control line are superimposed with the same TG timing signal, the PUF SEL1 clock control line and the PUF SEL2 clock control line are superimposed with the same PUF SEL timing signal, and the RST1 clock control line and the RST2 clock control line are superimposed with the same RST timing signal.
[0075] The t1 time period is used to reset the circuit to an initial state;
[0076] During the t2 period, the photodiodes in the two CMOS image sensor pixel units are exposed to perform signal accumulation;
[0077] See attached Figure 4 ,exist Figure 2 On the basis of the timing within one cycle of the pixel circuit of the traditional CMOS image sensor, the same PUF SEL timing signal is superimposed on the first clock control line PUF SEL1 and the second clock control line PUF SEL2 to increase the tpuf time period, whose end edge is the same as the t3 time period; during the tpuf time period, the signal is accumulated while the comparator outputs a 0 or 1 signal.
[0078] In the tpuf time period, the SEL timing signal and the TG timing signal are both at low level, and the PUF SEL timing signal and the RST timing signal are both at high potential, thereby turning on the first reset transistor B1, the second reset transistor B2 and the first control transistor E1, and the second control transistor E2. Due to the difference in the process, the threshold voltage Vth of each transistor is different, so for Figure 3 The thresholds of the driving transistors C1 and C2 are also different, denoted as Vth1 and Vth2 respectively. At the tpuf moment, the voltages output by the two pixel units are Vcc-Vth1 and Vcc-Vth2 respectively. Since the Vths of different transistors are different, when Vcc-Vth1 and Vcc-Vth2 enter the comparator, the output 0 or 1 signal is unpredictable and fixed.
[0079] The t3 time period is used to reset the floating diffusion layers of the two photodiodes;
[0080] The t4 time period is used to collect signals from the two CMOS image sensor pixel units respectively and output the collected signals from the column output buses of the corresponding pixel units.
[0081] The 0 or 1 signal output by each security implementation module is unpredictable, and the unpredictable 0 or 1 signal that can be repeated and determined is used as the identity of the security implementation module.
[0082] The present application also claims protection for a vision chip security implementation device using the aforementioned vision chip security implementation module, including multiple vision chip security implementation modules, characterized in that:
[0083] Number each vision chip security implementation module;
[0084] Each vision chip security implementation module is based on its two CMOS image sensor pixel units that are fixed in pairs. It can unpredictably output an unpredictable 0 or 1 signal repeatedly and deterministically each time the control timing is superimposed on the PUF SEL timing signal. The output of each vision chip security implementation module is read in turn to generate a set of multi-bit PUF sequences. The PUF sequence can be used for authentication or encryption to achieve chip security. The higher the number of bits, the better the confidentiality performance.
[0085] The present invention also discloses a visual chip security implementation method based on the aforementioned visual chip security implementation device, comprising:
[0086] Set up multiple vision chip security implementation modules;
[0087] The two CMOS image sensor pixel units in each vision chip security implementation module have exactly the same control timing;
[0088] On the basis of the control timing of each CMOS image sensor pixel unit, the same PUF SEL timing signal is superimposed on the first clock control line PUFSEL1 and the second clock control line PUF SEL2, and based on the two CMOS image sensor pixel units fixedly arranged in pairs, each time the control timing is superimposed on the PUF SEL timing signal, the comparator can repeatedly and determine the output of a 0 or 1 signal;
[0089] The CMOS image sensor pixel unit control timing sequence includes a t1 time period, a t2 time period, a t3 time period and a t4 time period;
[0090] The t1 time period is used to reset the circuit to an initial state;
[0091] During the t2 period, the photodiodes in the two CMOS image sensor pixel units are exposed to perform signal accumulation;
[0092] In the t2 time period, the same PUF SEL timing signal is superimposed on the first clock control line PUF SEL1 and the second clock control line PUF SEL2 to increase the tpuf time period, whose end edge is the same as the t3 time period; in the tpuf time period, the comparator outputs a 0 or 1 signal while accumulating signals.
[0093] The t3 time period is used to reset the floating diffusion layers of the two photodiodes;
[0094] The t4 time period is used to collect signals from the two CMOS image sensor pixel units respectively and output the collected signals from the column output buses of the corresponding pixel units.
[0095] The 0 or 1 signal output by each security implementation module is unpredictable, and the unpredictable but repeatable and deterministic 0 or 1 signal is used as the identity of the security implementation module;
[0096] Each vision chip security implementation module output is read in turn to generate a set of multi-bit PUF sequences.
[0097] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.
[0098] The purpose of the present invention is to achieve chip security of visual chips, image encryption and identity authentication, etc. By utilizing the instability and unpredictability of the semiconductor process of the CMOS image sensor itself, two pixel units are used for comparison calculation to form a series of unpredictable random number sequences, thereby proposing a method for achieving chip security.
[0099] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.
[0100] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.
[0101] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.
[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents, and any modifications or equivalent replacements that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A visual chip security implementation module, comprising two CMOS image sensor pixel units, a first control transistor (E1), a second control transistor (E2), a first clock control line (PUF SEL1), a second clock control line (PUF SEL2) and a comparator, characterized in that: The input end of the first control transistor (E1) is connected to the first CMOS image sensor pixel unit, the output end is connected to the positive input end V+ or the negative input end V- of the comparator, and the control end is connected to the first clock control line (PUF SEL1); The input end of the second control transistor (E2) is connected to the second CMOS image sensor pixel unit, the output end is connected to the inverting input end V- or the non-inverting input end V+ of the comparator, and the control end is connected to the second clock control line (PUF SEL2); The two CMOS image sensor pixel units have exactly the same control timing; On the basis of the control timing of each CMOS image sensor pixel unit, the same PUF SEL timing signal is superimposed on the first clock control line (PUF SEL1) and the second clock control line (PUF SEL2), and based on the two CMOS image sensor pixel units fixedly arranged in pairs, each time the control timing is superimposed with the PUF SEL timing signal, the comparator can repeatedly and determine the output of a 0 or 1 signal; The 0 or 1 signal output by each security implementation module is unpredictable, and the unpredictable 0 or 1 signal that can be repeated and determined is used as the identity of the security implementation module.
2. The visual chip security implementation module according to claim 1, characterized in that: The first control transistor (E1) and the second control transistor (E2) are connected in parallel to the row selection transistors in the pixel units of the CMOS image sensor to which they are connected.
3. The visual chip security implementation module according to claim 1, characterized in that: The CMOS image sensor pixel unit control timing sequence includes a t1 time period, a t2 time period, a t3 time period and a t4 time period; The t1 time period is used to reset the circuit to an initial state; During the t2 period, the photodiodes in the two CMOS image sensor pixel units are exposed to perform signal accumulation; The t3 time period is used to reset the floating diffusion layers of the two photodiodes; The t4 time period is used to collect signals from the two CMOS image sensor pixel units respectively and output the collected signals from the column output buses of the corresponding pixel units.
4. The visual chip security implementation module according to claim 3, characterized in that: By superimposing the same PUF SEL timing signal on the first clock control line (PUF SEL1) and the second clock control line (PUF SEL2), a tpuf time period is increased, wherein the tpuf time period is within the t2 time period, and its end edge is the same as the t3 time period; During the tpuf period, the comparator outputs a 0 or 1 signal while accumulating the signal.
5. A visual chip security implementation device using the visual chip security implementation module according to any one of claims 1 to 4, comprising a plurality of visual chip security implementation modules, characterized in that: Number each vision chip security implementation module; Each vision chip security implementation module is based on its two CMOS image sensor pixel units that are fixed in pairs. It can unpredictably output 0 or 1 signals repeatedly and deterministically each time the control timing is superimposed on the PUF SEL timing signal, and read the output of each vision chip security implementation module in turn to generate a set of multi-bit PUF sequences for authentication or encryption.
6. A method for implementing visual chip security using the visual chip security implementation device of claim 5, characterized in that: Set up multiple vision chip security implementation modules; The two CMOS image sensor pixel units in each vision chip security implementation module have exactly the same control timing; On the basis of the control timing of each CMOS image sensor pixel unit, the same PUF SEL timing signal is superimposed on the first clock control line (PUF SEL1) and the second clock control line (PUF SEL2), and based on the two CMOS image sensor pixel units fixedly arranged in pairs, each time the control timing is superimposed with the PUF SEL timing signal, the comparator can repeatedly and determine the output of a 0 or 1 signal; The 0 or 1 signal output by each security implementation module is unpredictable, and the unpredictable but repeatable and deterministic 0 or 1 signal is used as the identity of the security implementation module; Each vision chip security implementation module output is read in turn to generate a set of multi-bit PUF sequences.
7. The method for implementing visual chip security according to claim 6, characterized in that: The CMOS image sensor pixel unit control timing sequence includes a t1 time period, a t2 time period, a t3 time period and a t4 time period; The t1 time period is used to reset the circuit to an initial state; During the t2 period, the photodiodes in the two CMOS image sensor pixel units are exposed to perform signal accumulation; The t3 time period is used to reset the floating diffusion layers of the two photodiodes; The t4 time period is used to collect signals from the two CMOS image sensor pixel units respectively and output the collected signals from the column output buses of the corresponding pixel units.
8. The method for implementing visual chip security according to claim 6, characterized in that: By superimposing the same PUF SEL timing signal on the first clock control line (PUF SEL1) and the second clock control line (PUF SEL2), a tpuf time period is increased, wherein the tpuf time period is within the t2 time period, and its end edge is the same as the t3 time period; During the tpuf period, the comparator outputs a 0 or 1 signal while accumulating the signal.
9. An electronic device, comprising a processor and a storage medium; characterized in that: The storage medium is used to store instructions; The processor is used to operate according to the instructions to execute the visual chip security implementation method according to claims 6-8.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the visual chip security implementation method described in claims 6-8 is implemented.