Display device

Abstract

The display device includes: a substrate; a plurality of first pixels and second pixels disposed on the substrate, the first pixels representing a first color, and the second pixels representing a second color different from the first color; a plurality of light emitting elements disposed on each of the plurality of first pixels and the second pixels; a plurality of signal lines that supply signals to the first pixels and the second pixels, respectively; and a plurality of anode power supply lines that supply power supply potentials to the first pixels and the second pixels, respectively, the width of the anode power supply lines of the first pixels being larger than the width of the anode power supply lines of the second pixels.

Description

[0001] This application is a divisional application based on a patent application with an application date of 2020.03.26, application number 202080025581.8, and invention name “Display Device”. Technical Field

[0002] The present invention relates to a display device. Background Art

[0003] In recent years, displays using tiny light-emitting diodes (micro LEDs) as display elements have attracted much attention (see, for example, Patent Document 1). Multiple light-emitting diodes are connected to an array substrate (a driver backplane in Patent Document 1), and the array substrate has a pixel circuit (an electronic control circuit in Patent Document 1) for driving the light-emitting diodes.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application No. 2017-529557 Summary of the invention

[0007] Technical problem to be solved by the invention

[0008] Red LEDs have lower luminous efficiency than blue LEDs and green LEDs. This trend is particularly pronounced in the case of GaN LEDs. Therefore, it is necessary to increase the driving current of the red LEDs, which may increase power consumption. On the other hand, if the luminous intensity of the red LEDs is increased, the red light may be reflected by the wiring on the array substrate and mixed with the light from other pixels. Therefore, it is sometimes difficult to display images well.

[0009] An object of the present invention is to provide a display device capable of suppressing degradation of display quality.

[0010] Technical solutions for solving technical problems

[0011] A display device according to one embodiment of the present invention comprises: a substrate; a plurality of first pixels and a second pixel, which are arranged on the substrate; a plurality of inorganic light-emitting elements, which are arranged in each of the plurality of first pixels and the second pixels; a plurality of signal lines, which supply signals to the first pixels and the second pixels, respectively; and a plurality of power lines, which supply power supply potentials to the first pixels and the second pixels, respectively; in the first pixel, at least one of the plurality of signal lines is arranged in a layer different from the power line; and in the second pixel, the plurality of signal lines and the power line are arranged in the same layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a plan view schematically showing the display device according to the first embodiment.

[0013] Figure 2 is a top view showing a plurality of pixels.

[0014] Figure 3 is a circuit diagram showing a pixel circuit.

[0015] Figure 4 It is a top view schematically showing two adjacent pixels.

[0016] Figure 5 yes Figure 4 V-V' cross-sectional view.

[0017] Figure 6 This is a graph schematically showing the wavelength dependence of the light transmittance of a circularly polarizing plate.

[0018] Figure 7 yes Figure 4 VII-VII' cross-sectional view.

[0019] Figure 8 yes Figure 4 VIII-VIII' cross-sectional view.

[0020] Fig. 9 It is a plan view schematically showing two adjacent pixels in the display device according to the second embodiment.

[0021] Fig.10 yes Fig. 9 X-X' section view. DETAILED DESCRIPTION

[0022] With reference to the accompanying drawings, the mode (implementation method) for implementing the present invention is described in detail. The present invention is not limited to the contents described in the following embodiments. In addition, the constituent elements described below include elements that can be easily thought of by a person skilled in the art, and substantially the same elements. Moreover, the constituent elements described below can be appropriately combined. It should be noted that the disclosure is only an example, and for a person skilled in the art, the contents that can be easily thought of by appropriate changes that maintain the main idea of ​​the invention are certainly included in the scope of the present invention. In addition, in order to explain more clearly, the accompanying drawings schematically show the width, thickness, shape, etc. of each part compared to the actual state, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, for the elements that are the same as the elements already described in the figures that have already appeared, the same figure mark is sometimes marked, and the detailed description is appropriately omitted.

[0023] (First Embodiment)

[0024] Figure 1 FIG. 2 is a schematic top view of a display device according to the first embodiment. Figure 1 As shown, the display device 1 includes an array substrate 2, a pixel Pix, a driving circuit 12, a driving IC (Integrated Circuit) 210, and a cathode wiring 60. The array substrate 2 is a driving circuit substrate for driving each pixel Pix, also known as a backplane or an active matrix substrate. The array substrate 2 has a substrate 21, a plurality of transistors, a plurality of capacitors, and various wirings.

[0025] like Figure 1 As shown, the display device 1 has a display area AA and a peripheral area GA. The display area AA is an area that overlaps with a plurality of pixels Pix and displays an image. The peripheral area GA is an area that does not overlap with a plurality of pixels Pix and is arranged outside the display area AA.

[0026] A plurality of pixels Pix are arranged along a first direction Dx and a second direction Dy in a display area AA of the substrate 21. In this specification, the first direction Dx and the second direction Dy are directions parallel to the surface of the substrate 21. The first direction Dx is orthogonal to the second direction Dy. However, the first direction Dx may not intersect the second direction Dy orthogonally. The third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy. The third direction Dz corresponds to, for example, the normal direction of the substrate 21. In addition, the following "top view" represents the positional relationship when viewed from the third direction Dz.

[0027] The driving circuit 12 drives a plurality of gate lines (for example, a light emission control scanning line BG, a reset control scanning line RG, an initialization control scanning line IG, and a writing control scanning line SG (see FIG. Figure 3 The driving circuit 12 selects a plurality of gate lines sequentially or simultaneously and supplies a gate driving signal to the selected gate lines. Thus, the driving circuit 12 selects a plurality of pixels Pix connected to the gate lines.

[0028] The driver IC 210 is a circuit for controlling the display of the display device 1. The driver IC 210 is mounted in the peripheral area GA of the substrate 21 in the form of COG (Chip On Glass). Not limited to this, the driver IC 210 may also be mounted in the form of COF (Chip On Film) on a wiring substrate connected to the peripheral area GA of the substrate 21. In addition, the wiring substrate connected to the substrate 21 is, for example, a flexible printed substrate or a rigid substrate.

[0029] The cathode wiring 60 is provided in the peripheral area GA of the substrate 21. The cathode wiring 60 is provided to surround the plurality of pixels Pix in the display area AA and the drive circuit 12 in the peripheral area GA. The cathodes of the plurality of light emitting elements 3 are electrically connected to the common cathode wiring 60 and are supplied with a fixed potential (for example, a ground potential). More specifically, the cathode terminal 33 (see Figure 5 ) is connected to the cathode wiring 60 via the cathode electrode 22. In addition, the cathode wiring 60 may have a slit in a part and be formed by two different wirings on the substrate 21.

[0030] Figure 2 is a top view of a pixel including multiple pixels. Figure 2 As shown, a pixel Pix includes a plurality of pixels 11. For example, the pixel Pix includes a first pixel 11R, a second pixel 11G, and a third pixel 11B. The first pixel 11R displays red as a primary color of the first color. The second pixel 11G displays green as a primary color of the second color. The third pixel 11B displays blue as a primary color of the third color. Hereinafter, when it is not necessary to distinguish the first pixel 11R, the second pixel 11G, and the third pixel 11B, they are referred to as pixels 11.

[0031] The pixel 11 includes light emitting elements 3R, 3G, 3B and an anode electrode 23. In the following description, when it is not necessary to distinguish the light emitting elements 3R, 3G, 3B, they are simply referred to as light emitting elements 3. The display device 1 displays an image by emitting different light (for example, red, green, blue light) from each of the light emitting elements 3R, 3G, 3B in the first pixel 11R, the second pixel 11G, and the third pixel 11B.

[0032] The light emitting element 3 is provided in each of the plurality of pixels Pix. The light emitting element 3 is an inorganic light emitting diode (LED: Light Emitting Diode) chip having a size of about several μm or more and about 300 μm or less when viewed from above. Generally speaking, a chip having a size of 100 μm or more is a mini LED, and a chip having a size of several μm or more and less than 100 μm is a micro LED. In the present invention, LEDs of any size can be used as long as they are used separately according to the screen size of the display device 1 (the size of one pixel). The display device 1 having a micro LED in each pixel is also referred to as a micro LED display device. In addition, the micro size of the micro LED does not limit the size of the light emitting element 3.

[0033] like Figure 2As shown, in a pixel Pix, the first pixel 11R and the second pixel 11G are arranged along the first direction Dx. In addition, the second pixel 11G and the third pixel 11B are arranged along the second direction Dy. In addition, the first color, the second color, and the third color are not limited to red, green, and blue, respectively, and any color such as complementary colors can be selected. In addition, the plurality of light emitting elements 3R, 3G, and 3B can also emit four or more different colors of light. In addition, the configuration of the plurality of pixels 11 is not limited to Figure 2 For example, the first pixel 11R may be adjacent to the third pixel 11B in the first direction Dx. In addition, the first pixel 11R, the second pixel 11G, and the third pixel 11B may be repeatedly arranged in sequence in the first direction Dx.

[0034] Figure 3 is a circuit diagram showing a pixel circuit. Figure 3 The pixel circuit PICA shown is provided in each of the first pixel 11R, the second pixel 11G, and the third pixel 11B. The pixel circuit PICA is provided in the substrate 21 and is a circuit that supplies a driving signal (current) to the light emitting elements 3R, 3G, and 3B. Figure 3 In the description of the pixel circuit PICA, the description can be applied to the pixel circuit PICA included in each of the first pixel 11R, the second pixel 11G, and the third pixel 11B.

[0035] like Figure 3 As shown, the pixel circuit PICA includes a light emitting element 3 (light emitting elements 3R, 3G, 3B), five transistors and two capacitors. Specifically, the pixel circuit PICA includes a light emitting control transistor BCT, an initialization transistor IST, a write transistor SST (a second transistor), a reset transistor RST and a drive transistor DRT (a first transistor). A portion of the transistors may also be shared by multiple adjacent pixels 11.

[0036] The plurality of transistors included in the pixel circuit PICA are each formed of an n-type TFT (Thin Film Transistor), but the present invention is not limited thereto, and each transistor may be formed of a p-type TFT.

[0037] The light emission control scanning line BG is connected to the gate of the light emission control transistor BCT. The initialization control scanning line IG is connected to the gate of the initialization transistor IST. The writing control scanning line SG is connected to the gate of the writing transistor SST. The reset control scanning line RG is connected to the gate of the reset transistor RST.

[0038] The light emission control scanning line BG, the initialization control scanning line IG, the writing control scanning line SG, and the reset control scanning line RG are respectively connected to the driving circuit 12 (see FIG. Figure 1 The driving circuit 12 supplies a light emission control signal Vbg, an initialization control signal Vig, a write control signal Vsg, and a reset control signal Vrg to the light emission control scanning line BG, the initialization control scanning line IG, the write control scanning line SG, and the reset control scanning line RG, respectively.

[0039] Driver IC210 (refer to Figure 1 ) supplies the image signal Vsig to the pixel circuit PICA of each of the first pixel 11R, the second pixel 11G and the third pixel 11B in a time-division manner. A switching circuit such as a multiplexer is provided between each column of the first pixel 11R, the second pixel 11G and the third pixel 11B and the driver IC210. ​​The image signal Vsig is supplied to the write transistor SST via the image signal line L2. In addition, the driver IC210 supplies the reset power supply potential Vrst to the reset transistor RST via the reset signal line L3. The driver IC210 supplies the initialization potential Vini to the initialization transistor IST via the initialization signal line L4.

[0040] The light emission control transistor BCT, the initialization transistor IST, the write transistor SST and the reset transistor RST function as switch elements for selecting conduction and non-conduction between two nodes. The drive transistor DRT functions as a current control element for controlling the current flowing in the light emitting element 3 according to the voltage between the gate and the drain.

[0041] The cathode (cathode terminal 33) of the light emitting element 3 is connected to the cathode power supply line L10. In addition, the anode (anode terminal 32) of the light emitting element 3 is connected to the anode power supply line L1 (power supply line) through the driving transistor DRT and the light emission control transistor BCT. The anode power supply line L1 is supplied with the anode power supply potential PVDD. The cathode power supply line L10 is supplied with the cathode power supply potential PVSS. The anode power supply potential PVDD is a potential higher than the cathode power supply potential PVSS. The cathode power supply line L10 includes a cathode wiring 60.

[0042] In addition, the pixel circuit PICA includes a capacitor Cs1 and a capacitor Cs2. The capacitor Cs1 is a holding capacitor formed between the gate and source of the driving transistor DRT. The capacitor Cs2 is an additional capacitor formed between the source of the driving transistor DRT and the anode and cathode power supply line L10 of the light emitting element 3.

[0043] During the reset period, the light emission control transistor BCT is turned off (non-conducting state) and the reset transistor RST is turned on (conducting state) according to the potential of the light emission control scanning line BG and the reset control scanning line RG. As a result, the source of the driving transistor DRT is fixed to the reset power supply potential Vrst. The reset power supply potential Vrst is a potential where the potential difference between the reset power supply potential Vrst and the cathode power supply potential PVSS is smaller than the potential difference at which the light emitting element 3 starts to emit light.

[0044] Next, according to the potential of the initialization control scan line IG, the initialization transistor IST is turned on. The gate of the driving transistor DRT is fixed to the initialization potential Vini by the initialization transistor IST. In addition, the driving circuit 12 turns on the light emitting control transistor BCT and turns off the reset transistor RST. The driving transistor DRT is turned off when the source potential reaches (Vini-Vth), and the inconsistency of the threshold voltage Vth of the driving transistor DRT of each pixel 11 is offset.

[0045] Next, during the video signal writing operation period, the light emission control transistor BCT is turned off, the initialization transistor IST is turned off, and the writing transistor SST is turned on. The video signal Vsig is input to the gate of the driving transistor DRT.

[0046] Next, during the light emitting operation, the light emitting control transistor BCT is turned on and the write transistor SST is turned off. The anode power supply potential PVDD is supplied from the anode power supply line L1 to the drive transistor DRT via the light emitting control transistor BCT. The drive transistor DRT supplies a current corresponding to the gate-source voltage to the light emitting element 3. The light emitting element 3 emits light at a brightness corresponding to the current.

[0047] In addition, the above Figure 3 The configuration of the pixel circuit PICA shown is only an example and can be modified as appropriate. For example, the number of wirings and the number of transistors in one pixel 11 may be different.

[0048] Next, refer to Figures 4 to 8 , a specific configuration example of each transistor and each wiring is described. Figure 4 It is a top view schematically showing two adjacent pixels. Figure 4 1 and 11B illustrate the first pixel 11R and the second pixel 11G as two pixels 11 adjacent to each other in the first direction Dx. However, the third pixel 11B has the same configuration as the second pixel 11G, and the description of the second pixel 11G can also be applied to the third pixel 11B.

[0049] like Figure 4As shown, the anode power line L1, the image signal line L2, the reset signal line L3 and the initialization signal line L4 extend along the second direction Dy. The reset control scan line RG, the light emission control scan line BG, the write control scan line SG and the initialization control scan line IG extend along the first direction Dx, and intersect the anode power line L1, the image signal line L2, the reset signal line L3 and the initialization signal line L4 respectively when viewed from above. In addition, a connection wiring L9 is provided between two adjacent anode power lines L1 in the first direction Dx. The connection wiring L9 connects the drive transistor DRT, the write transistor SST and the initialization transistor IST.

[0050] The first pixel 11R has an image signal line L2 and a reset signal line L3 as signal lines for supplying signals. The second pixel 11G has an image signal line L2 and an initialization signal line L4 as signal lines for supplying signals. In the present embodiment, the reset signal line L3 and the initialization signal line L4 are shared by two adjacent pixels 11. In other words, in the first pixel 11R, the initialization signal line L4 is not provided, but the reset signal line L3 is provided along the image signal line L2. In the second pixel 11G, the reset signal line L3 is not provided, but the initialization signal line L4 is provided along the image signal line L2. In addition, the reset signal line L3 may be arranged in the second pixel 11G, and the initialization signal line L4 may be arranged in the first pixel 11R. For example, the reset signal line L3 may not be provided in the first pixel 11R, but the initialization signal line L4 may be provided along the image signal line L2. In addition, the reset signal line L3 may not be provided in the second pixel 11G, but the initialization signal line L4 may be provided along the image signal line L2.

[0051] A reset signal line L3 supplies a reset power supply potential Vrst to the first pixel 11R and the second pixel 11G. In addition, an initialization signal line L4 supplies an initialization potential Vini to the first pixel 11R and the second pixel 11G. However, this is not limited to this, and the first pixel 11R and the second pixel 11G may each have three: an image signal line L2, a reset signal line L3, and an initialization signal line L4.

[0052] In this embodiment, the display device 1 (array substrate 2) has a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3 arranged in different layers in the third direction Dz. The first metal layer ML1, the second metal layer ML2, and the third metal layer ML3 are arranged in a layer different from the semiconductor layers 61, 65, 71, 75, and 79 of each transistor. Figure 4 In the figure, in order to distinguish the first metal layer ML1, the second metal layer ML2 and the third metal layer ML3, the second metal layer ML2 and the third metal layer ML3 are marked with oblique lines.

[0053] The reset control scan line RG, the light emission control scan line BG, the write control scan line SG, and the initialization control scan line IG are formed by the first metal layer ML1. In the first pixel 11R, the anode power line L1 is formed by the second metal layer ML2. The image signal line L2 and the reset signal line L3 are formed by the third metal layer ML3. That is, the image signal line L2 and the reset signal line L3 are provided in a layer different from the anode power line L1. The image signal line L2 is provided so as to overlap with the anode power line L1 when viewed from above. In addition, the reset signal line L3 is provided adjacent to the image signal line L2 in the first direction Dx.

[0054] In the second pixel 11G, the anode power line L1, the image signal line L2, and the initialization signal line L4 are formed by the second metal layer ML2. That is, the image signal line L2 and the initialization signal line L4 are provided in the same layer as the anode power line L1. The image signal line L2 and the initialization signal line L4 are provided in a region that does not overlap with the anode power line L1 when viewed from above, and are provided adjacent to the anode power line L1 in the first direction Dx.

[0055] At least one of the plurality of signal lines of the first pixel 11R is provided in a layer different from the anode power line L1. Thus, wiring can be efficiently arranged in the first pixel 11R. As a result, the display device 1 can make the metal wiring occupancy rate of the first pixel 11R smaller than the metal wiring occupancy rate of the second pixel 11G. Here, the metal wiring occupancy rate refers to the ratio of the total area of ​​various metal wirings including the plurality of signal lines, scanning lines, and the anode power line L1 to the area of ​​the first pixel 11R or the second pixel 11G when viewed from above.

[0056] In addition, the area of ​​each pixel 11 is given by Figure 4 The area of ​​the region divided by the virtual line Lx and the virtual line Ly shown in FIG. The virtual line Lx is a virtual line that overlaps with the connection wirings L3a and L3b connected to the reset signal line L3 and extends in the first direction Dx. The virtual line Lx passes through the midpoint position of the second direction Dy of the connection wirings L3a and L3b. The virtual line Ly is a virtual line that overlaps with the anode power supply line L1 and extends in the second direction Dy. The virtual line Ly passes through the midpoint position of the first direction Dx of the anode power supply line L1.

[0057] The metal wiring occupancy rate of the first pixel 11R is about 64% or more and about 80% or less, for example, about 72%. The metal wiring occupancy rate of the second pixel 11G is about 72% or more and about 80% or less, for example, about 80%. The metal wiring occupancy rates of the first pixel 11R and the second pixel 11G are only examples, and can be appropriately set to different values ​​according to the pixel density and resolution.

[0058] According to such a configuration, in the first pixel 11R, compared with a case where the image signal line L2 and the reset signal line L3 are provided on the same layer as the anode power line L1, it is possible to suppress the red light emitted from the light emitting element 3R of the first pixel 11R from being reflected in the side or oblique direction by the metal wirings of the array substrate 2. Thus, the display device 1 can suppress the useless reflected light in the first pixel 11R, thereby suppressing the color mixing with the light of other pixels 11.

[0059] As the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3, titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), niobium, indium tin oxide (ITO), aluminum (Al), silver (Ag), Ag alloy, copper (Cu), carbon nanotubes, graphite, graphene, or carbon nanobelts are used. Here, the sheet resistance value of the anode power line L1 formed by the second metal layer ML2 is less than the sheet resistance value of each signal line (third metal layer ML3) formed in a layer different from the anode power line L1 among the multiple signal lines. In addition, the sheet resistance value of each signal line formed by the third metal layer ML3 is less than the sheet resistance value of each gate line formed by the first metal layer ML1.

[0060] For example, the sheet resistance value of the anode power line L1 (second metal layer ML2) is greater than or equal to 30 mΩ / □ and less than or equal to 120 mΩ / □. In addition, the sheet resistance value of each signal line formed by the third metal layer ML3 among the plurality of signal lines is greater than or equal to 120 mΩ / □ and less than or equal to 300 mΩ / □. The sheet resistance value of each gate line (first metal layer ML1) is greater than or equal to 300 mΩ / □ and less than or equal to 3000 mΩ / □. Thus, the display device 1 can suppress the drop in the driving voltage applied to the anode power line L1, thereby suppressing the reduction in display performance.

[0061] In addition, the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3 are not limited to single layers, and may be composed of laminated films. For example, the second metal layer ML2 may be a laminated film of Ti / Al / Ti or Mo / Al / Mo, and the third metal layer ML3 may be a single layer film of Al. In addition, Ti, Al, and Mo may also be alloys.

[0062] The semiconductor layers 61, 65, 71, 75 are made of, for example, amorphous silicon, microcrystalline oxide semiconductor, amorphous oxide semiconductor, polycrystalline silicon, low temperature polycrystalline silicon (LTPS) or gallium nitride (GaN). Examples of oxide semiconductors include IGZO, zinc oxide (ZnO) and ITZO. IGZO is indium gallium zinc oxide. ITZO is indium tin zinc oxide.

[0063] The driving transistor DRT has a semiconductor layer 61, a source electrode 62, and a gate electrode 64. The semiconductor layer 61, the source electrode 62, and the gate electrode 64 are arranged to overlap at least partially when viewed from above, and are arranged in a region surrounded by two anode power lines L1, a light emission control scanning line BG, and a writing control scanning line SG adjacent to each other in the first direction Dx. The driving transistor DRT has a single gate structure that overlaps the semiconductor layer 61 and is provided with a gate electrode 64. The source electrode 62 is provided to cover the semiconductor layer 61. The semiconductor layer 61 is connected to the source electrode 62 at a portion 61a.

[0064] The light emission control transistor BCT includes a semiconductor layer 65. The semiconductor layer 65 is connected to the semiconductor layer 61 and intersects with the light emission control scanning line BG in a plan view. A channel region is formed in a region of the semiconductor layer 65 that overlaps with the light emission control scanning line BG. The portion of the light emission control scanning line BG that overlaps with the semiconductor layer 65 functions as a gate electrode 66 of the light emission control transistor BCT. One end side of the semiconductor layer 65 is electrically connected to the anode power supply line connection portion L1a. The anode power supply line connection portion L1a is a portion that branches from the anode power supply line L1 in the first direction Dx. Thus, the anode power supply potential PVDD is supplied from the anode power supply line L1 to the drive transistor DRT and the light emission control transistor BCT.

[0065] In the second pixel 11G, the initialization transistor IST has a semiconductor layer 71. In the first pixel 11R, the initialization transistor IST has a semiconductor layer 71A. The semiconductor layers 71 and 71A intersect with the initialization control scan line IG and the branch scan line IGa when viewed from above. A channel region is formed in the semiconductor layers 71 and 71A in the region overlapping with the initialization control scan line IG and the branch scan line IGa. The branch scan line IGa branches from the initialization control scan line IG and extends in the first direction Dx. The portions of the initialization control scan line IG and the branch scan line IGa that overlap with the semiconductor layers 71 and 71A function as gate electrodes 74 of the initialization transistor IST, respectively. In other words, the initialization transistor IST has a dual-gate structure that overlaps with the semiconductor layers 71 and 71A, respectively, and is provided with two gate electrodes. However, the initialization transistor IST may also have a single-gate structure without providing the branch scan line IGa.

[0066] In the second pixel 11G, the semiconductor layer 71 extends along the second direction Dy, one end of which is electrically connected to the connection wiring L9, and the other end of which is connected to the connection wiring L4a. The connection wiring L4a is a portion branching from the initialization signal line L4 to the first direction Dx. In addition, in the first pixel 11R, the semiconductor layer 71A has a portion extending along the second direction Dy and a portion extending along the first direction Dx. One end of the portion of the semiconductor layer 71A extending along the second direction Dy is electrically connected to the connection wiring L9. The portion of the semiconductor layer 71A extending along the first direction Dx intersects with the anode power line L1 and the image signal line L2 when viewed from above and extends to the second pixel 11G, and is electrically connected to the connection wiring L4a. According to the above-described configuration, one initialization signal line L4 is electrically connected to two initialization transistors IST, and is shared by two pixels 11 adjacent to each other in the first direction Dx.

[0067] The write transistor SST has a semiconductor layer 75. The semiconductor layer 75 extends along the first direction Dx and intersects with the two branch scan lines SGa when viewed from above. A channel region is formed in the region of the semiconductor layer 75 that overlaps with the two branch scan lines SGa. The two branch scan lines SGa are portions that branch out from the write control scan line SG in the second direction Dy. The portions of the two branch scan lines SGa that overlap with the semiconductor layer 75 function as gate electrodes 78 of the write transistor SST, respectively. In other words, the write transistor SST has a dual-gate structure that overlaps with the semiconductor layer 75 and is provided with two gate electrodes 78. However, the write transistor SST may also have a single-gate structure that is provided with one branch scan line SGa.

[0068] One end of the semiconductor layer 75 is connected to the video signal line L2, and the other end is connected to the connection wiring L9. In the first pixel 11R, one end of the semiconductor layer 75 is connected to the video signal line L2 formed by the third metal layer ML3. On the other hand, in the second pixel 11G, one end of the semiconductor layer 75 is connected to the video signal line L2 formed by the second metal layer ML2.

[0069] The reset transistor RST has a semiconductor layer 79. The semiconductor layer 79 extends along the second direction Dy and intersects the reset control scan line RG and the branch scan line RGa when viewed from above. A channel region is formed in the semiconductor layer 79 in the region overlapping the reset control scan line RG and the branch scan line RGa. The branch scan line RGa branches from the reset control scan line RG and extends in the first direction Dx. The portions of the reset control scan line RG and the branch scan line RGa that overlap with the semiconductor layer 79 function as gate electrodes of the reset transistor RST, respectively. In other words, the reset transistor RST has a dual-gate structure. However, the reset transistor RST may also have a single-gate structure without providing the branch scan line RGa.

[0070] The reset signal line L3 is connected to connection wirings L3a and L3b extending in the first direction Dx and a bridge L3c. The connection wiring L3a is provided in the first pixel 11R and is formed by the third metal layer ML3. The bridge L3c intersects the anode power line L1, the image signal line L2, and the initialization signal line L4 in a plan view, and connects the connection wiring L3a to the connection wiring L3b. The bridge L3c is formed by a layer different from the anode power line L1 (the second metal layer ML2), for example, the first metal layer ML1. The connection wiring L3b is provided in the second pixel 11G and is formed by the second metal layer ML2.

[0071] In the first pixel 11R, one end of the semiconductor layer 79 is connected to the connection wiring L3a. In addition, in the second pixel 11G, one end of the semiconductor layer 79 is connected to the connection wiring L3b. In addition, the other end of the semiconductor layer 79 is connected to the semiconductor layer 61. That is, the other end of the semiconductor layer 79 of the reset transistor RST is electrically connected to the source of the drive transistor DRT and the anode terminal 32 of the light emitting element 3. According to the above-mentioned structure, one reset signal line L3 is electrically connected to two reset transistors RST, and is shared by two pixels 11 adjacent to each other in the first direction Dx.

[0072] In addition, in this embodiment, the driving transistor DRT and the light-emitting control transistor BCT for supplying the driving current to the light-emitting element 3 have a single-gate structure. The initialization transistor IST, the write transistor SST, and the reset transistor RST have a double-gate structure. Thus, the leakage current of the initialization transistor IST, the write transistor SST, and the reset transistor RST can be suppressed.

[0073] Next, the cross-sectional structure of the display device 1 will be described. Figure 5 yes Figure 4 V-V' section view. Figure 5 As shown, in the display device 1, the light emitting element 3 is provided on the array substrate 2. The array substrate 2 has a substrate 21, an anode electrode 23, an opposing electrode 26, a connecting electrode 24, various transistors, various wirings, and various insulating films.

[0074] The substrate 21 is an insulating substrate, and for example, a glass substrate such as quartz or alkali-free glass, or a resin substrate such as polyimide is used.

[0075] In addition, in this specification, in the direction perpendicular to the surface of the substrate 21, the direction from the substrate 21 toward the light-emitting element 3 is referred to as the "upper side" or simply "upper". In addition, the direction from the light-emitting element 3 toward the substrate 21 is referred to as the "lower side" or simply "lower". In addition, when describing a form in which another structure is arranged on a certain structure, if it is simply expressed as "on", unless otherwise specified, the following two cases are included: a case in which another structure is directly arranged on a certain structure in a manner of contacting with the certain structure and a case in which another structure is arranged on the top of the certain structure with another structure interposed therebetween.

[0076] The driving transistor DRT, the emission control transistor BCT, the initialization transistor IST, the writing transistor SST and the reset transistor RST are provided on one side of the substrate 21. The reset transistor RST has the same layer structure as the initialization transistor IST and the writing transistor SST, so the detailed description is omitted.

[0077] An undercoat film 90 is provided on the substrate 21. The undercoat film 90, the insulating films 91, 92, 93, and the insulating films 95, 96 are inorganic insulating films, such as silicon dioxide (SiO2) or silicon nitride (SiN).

[0078] The gate electrodes 64, 66, 74, 78 formed of the first metal layer ML1 are provided on the primer film 90. The insulating film 91 covers the gate electrodes 64, 66, 74, 78 and is provided on the primer film 90. The semiconductor layers 61, 65, 71A, 75 are provided on the insulating film 91. The insulating film 92 covers the semiconductor layers 61, 65, 71A, 75 and is provided on the insulating film 91.

[0079] The source electrode 62 and the drain electrodes 67, 73, 77 formed of the second metal layer ML2 are electrically connected to the semiconductor layers through contact holes provided in the insulating film 92. The drain of the write transistor SST is electrically connected to the drain of the initialization transistor IST through the connection wiring L9.

[0080] The capacitor Cs1 is formed by the gate electrode 64 and the source electrode 62 which are opposed to each other via the insulating films 91 and 92. The capacitor Cs1 also includes a capacitor formed by the gate electrode 64 and the connection electrode 24 which are opposed to each other via the insulating films 93 and 94.

[0081] The insulating film 93 covers the source electrode 62 and the drain electrodes 67, 73, and 77 and is provided on the insulating film 92. The insulating film 94 covers each transistor and is provided on the insulating film 93. An organic material such as photosensitive acrylic is used for the insulating film 94. The insulating film 94 is a planarizing film that can planarize the unevenness formed by the driving transistor DRT and various wirings.

[0082] The connection electrode 24 and the counter electrode 26 are provided on the insulating film 94. The connection electrode 24 is connected to the source electrode 62 through contact holes provided in the insulating film 93 and the insulating film 94. The connection electrode 24 and the counter electrode 26 are made of a light-transmitting conductive material such as ITO (Indium Tin Oxide).

[0083] The anode electrode 23 is electrically connected to the connection electrode 24 and the source electrode 62 through a contact hole provided in the insulating film 95. Thus, the anode electrode 23 is electrically connected to the drive transistor DRT. The anode electrode 23 has a laminated structure of, for example, molybdenum (Mo) and aluminum (Al).

[0084] A capacitor Cs2 is formed between the anode electrode 23 and the counter electrode 26 which face each other via the insulating film 95. The insulating film 96 is provided to cover the anode electrode 23. The insulating film 96 covers the peripheral edge of the anode electrode 23 and insulates the anode electrodes 23 of the adjacent pixels 11.

[0085] The insulating film 96 has an opening for mounting the light emitting element 3 at a position overlapping with the anode electrode 23. The size of the opening of the insulating film 96 is set to be larger than the area of ​​the light emitting element 3 in consideration of the mounting offset amount in the mounting process of the light emitting element 3. That is, when viewed from above in a direction perpendicular to the substrate 21, the area of ​​the anode electrode 23 is larger than the area of ​​the light emitting element 3.

[0086] The light emitting element 3 includes a semiconductor layer 31, an anode terminal 32, and a cathode terminal 33. Each light emitting element 3 is mounted in such a manner that the anode terminal 32 is in contact with the anode electrode 23. Thus, the semiconductor layer 61 of the driving transistor DRT is electrically connected to the light emitting element 3 via the source electrode 62 formed by the second metal layer ML2. The anode electrode 23 supplies the anode power supply potential PVDD to the anode terminal 32. The semiconductor layer 31 may be a structure in which an n-type cladding layer, an active layer, and a p-type cladding layer are stacked.

[0087] The semiconductor layer 31 uses a compound semiconductor such as gallium nitride (GaN), aluminum indium gallium phosphide (AlInGaP), aluminum gallium arsenide (AlGaAs), or gallium arsenic phosphide (GaAsP). The semiconductor layer 31 may use a different material for each light emitting element 3R, 3G, 3B. In addition, in order to achieve high efficiency, the active layer may also adopt a multi-quantum well structure (MQW structure) in which well layers and barrier layers composed of multiple atomic layers are periodically stacked.

[0088] An element insulating film 27 is provided between the plurality of light emitting elements 3. The element insulating film 27 is formed of a resin material. The element insulating film 27 covers at least the side surfaces of the light emitting elements 3, and the element insulating film 27 is not provided on the cathode terminal 33 of the light emitting element 3. The element insulating film 27 is formed flatly so that the upper surface of the element insulating film 27 and the upper surface of the cathode terminal 33 form the same surface. However, the position of the upper surface of the element insulating film 27 may be different from the position of the upper surface of the cathode terminal 33.

[0089] The cathode electrode 22 covers the plurality of light emitting elements 3 and the element insulating film 27, and is electrically connected to the plurality of light emitting elements 3. More specifically, the cathode electrode 22 is arranged across the upper surface of the element insulating film 27 and the upper surface of the cathode terminal 33. The cathode electrode 22 supplies the cathode power supply potential PVSS to the cathode terminal 33. The cathode electrode 22 uses a light-transmitting conductive material such as ITO. Thus, the light emitted from the light emitting element 3 can be efficiently emitted to the outside.

[0090] A circular polarizing plate 5 is provided on the cathode electrode 22 via an adhesive layer 98. In other words, the circular polarizing plate 5 is provided on the plurality of light emitting elements 3. The circular polarizing plate 5 includes, for example, a linear polarizing plate and a 1 / 4 phase difference plate (also referred to as a 1 / 4 wavelength plate) provided on one side of the linear polarizing plate. Compared with the linear polarizing plate, the 1 / 4 phase difference plate is provided at a position closer to the substrate 21.

[0091] For example, external light (incident light) passes through a linear polarizer and is changed into linear polarized light. Linear polarized light passes through a 1 / 4 phase difference plate and is changed into circular polarized light. The circularly polarized light is reflected by the metal wiring of the array substrate 2 and becomes circularly polarized light (reflected light) in the opposite direction to the incident light. The reflected light passes through the 1 / 4 phase difference plate again and becomes linear polarized light orthogonal to the incident light, and is absorbed by the linear polarizer. Thus, in the display device 1, the reflection of external light is suppressed.

[0092] Figure 6 This is a graph schematically showing the wavelength dependence of the light transmittance of a circularly polarizing plate. Figure 6 The vertical axis represents the transmittance of light passing through the circular polarizer 5, and the horizontal axis represents the wavelength of the light. Figure 6 As shown, the circular polarizer 5 has a tendency that the transmittance of light increases as the wavelength becomes longer. In the wavelength region of blue light (e.g., wavelength 450nm), the transmittance is 38% or more, in the wavelength region of green light (e.g., 550nm), the transmittance is 41% or more, and in the wavelength region of red light (e.g., 620nm), the transmittance is 44% or more.

[0093] The circular polarizing plate 5 may be obtained by, for example, adsorbing a dichromatic substance such as iodine or a dichromatic dye on a polyvinyl alcohol film and then uniaxially stretching the film. The circular polarizing plate 5 is formed by a polyiodine complex (I3 － 、I5 － ) is obtained by the absorption characteristics of Figure 6 The wavelength dependence is shown.

[0094] The transmittance of red light through the circular polarizer 5 is higher than that of blue or green light, so the display device 1 can improve the efficiency of extracting light emitted from the light emitting element 3R. Therefore, even when the light emitting efficiency of the light emitting element 3R is lower than that of the light emitting elements 3G and 3B, the display device 1 can suppress the decrease in the intensity of red light when passing through the circular polarizer 5. Therefore, the display device 1 can suppress the decrease in the quality of the displayed image. In addition, Figure 4 As shown, in the first pixel 11R, the image signal line L2 and the anode power line L1 are arranged to overlap, so even when the transmittance of red light of the circular polarizer 5 is high, the reflected light in the first pixel 11R can be suppressed, thereby suppressing color mixing with light from other pixels 11.

[0095] Figure 7 yes Figure 4 VII-VII' section view. In addition, Figure 7 Schematically shows the cathode wiring 60 and the transistor Tr provided in the peripheral area GA.

[0096] like Figure 7 As shown, in the peripheral area GA of the substrate 21, a driving circuit 12 (see Figure 1 ) includes a transistor Tr and a cathode wiring 60. The cathode wiring 60 is formed by the second metal layer ML2 and is provided on the insulating film 92 in the peripheral area GA. The cathode electrode 22 is provided from the display area AA to the peripheral area GA and is electrically connected to the cathode wiring 60 through a contact hole H11 provided in the insulating films 93, 94 and the element insulating film 27. In addition, the cathode wiring 60 can also be formed by the third metal layer ML3 and provided on the insulating film 93.

[0097] The transistor Tr includes a semiconductor layer 81, a source electrode 82, a drain electrode 83, and a gate electrode 84. The transistor Tr has the same layer structure as each transistor included in the pixel circuit PICA, so a detailed description is omitted. The source electrode 82 and the drain electrode 83 of the transistor Tr may also be connected to a wiring formed by the third metal layer ML3. Thus, the wiring of the peripheral area GA including the driving circuit 12 can be efficiently configured.

[0098] like Figure 7As shown in FIG. 1 , in the first pixel 11R, the anode power line L1 is disposed on the insulating film 92, and the image signal line L2 and the reset signal line L3 are disposed on the insulating film 93. The image signal line L2 is disposed on the upper side of the anode power line L1. In addition, the reset signal line L3 is disposed at a position that does not overlap with the anode power line L1. In the second pixel 11G, the anode power line L1, the image signal line L2, and the initialization signal line L4 are disposed on the insulating film 92 in the same layer.

[0099] In the first pixel 11R, the width of the anode power supply line L1 is larger than the width of the video signal line L2 and the reset signal line L3. In addition, the thickness t2 of the anode power supply line L1 formed by the second metal layer ML2 is larger than the thickness t1 of the gate electrode 64 formed by the first metal layer ML1 (refer to Figure 5 ) thicker. In addition, the thickness t2 of the anode power line L1 formed by the second metal layer ML2 is thicker than the thickness t3 of the image signal line L2 and the reset signal line L3 formed by the third metal layer ML3. The thickness of the anode power line L1 of the first pixel 11R is formed to be thicker than the thickness of the anode power line L1 of the second pixel 11G. Thus, the resistance value of the anode power line L1 in the first pixel 11R can be reduced. However, this is not limited to this, and the thickness of the anode power line L1 of the first pixel 11R can also be the same as the thickness of the anode power line L1 of the second pixel 11G.

[0100] The layer structure of each wiring can be changed appropriately. In the first pixel 11R, at least one of the image signal line L2 and the reset signal line L3 can be provided in a layer different from the anode power line L1. For example, in the first pixel 11R, any one of the image signal line L2 and the reset signal line L3 can also be provided in the same layer as the anode power line L1. In addition, the reset signal line L3 can also be provided on the upper side of the anode power line L1, and the image signal line L2 can be provided at a position that does not overlap with the anode power line L1.

[0101] Figure 8 yes Figure 4 VIII-VIII' cross-sectional view. Figure 8 , a cross-sectional view of a write transistor SST is shown as an example of a connection structure of a plurality of transistors included in the pixel circuit PICA of the first pixel 11R. The semiconductor layer 75 of the write transistor SST is electrically connected to the image signal line L2 formed by the third metal layer ML3. Specifically, the write transistor SST has a source electrode 76 formed by the second metal layer ML2. The source electrode 76 is connected to the semiconductor layer 75 via a contact hole provided in the insulating film 92. The image signal line L2 is connected to the source electrode 76 via a contact hole provided in the insulating film 93. In addition, in the second pixel 11G, as shown in FIG. Figure 4As shown, the video signal line L2 is formed of the second metal layer ML2 and is connected to the semiconductor layer 75 through a contact hole provided in the insulating film 92 .

[0102] The connection wiring L9 (drain electrode 77) is connected to the semiconductor layer 75 through a contact hole provided in the insulating film 92. In addition, the connection wiring L9 is connected to the gate electrode 64 of the drive transistor DRT through contact holes provided in the insulating films 91 and 92. According to such a configuration, the gate electrode 64 of the drive transistor DRT is electrically connected to the write transistor SST through the connection wiring L9 formed by the second metal layer ML2. In addition, the connection wiring L9 can also be provided in the third metal layer ML3.

[0103] also, Figure 4 , 5 The configuration of each pixel 11 shown in , 7, and 8 is only an example and can be changed appropriately. For example, the top view configuration of each transistor in a pixel circuit PICA is not limited to Figure 4 In addition, the thickness and width of each wiring can be appropriately changed as needed.

[0104] (Second Embodiment)

[0105] Fig. 9 2 is a plan view schematically showing two adjacent pixels in a display device according to Embodiment 2. In the following description, components identical to those described in the above embodiment are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0106] like Fig. 9 As shown, the display device 1A of the second embodiment is different from the first embodiment in that the reset signal line L3 and the image signal line L2 are overlapped in the first pixel 11R. More specifically, the image signal line L2 is formed by the second metal layer ML2 and is arranged adjacent to the anode power line L1 in the first direction Dx. The reset signal line L3 is formed by the third metal layer ML3 and is arranged at a position that does not overlap with the anode power line L1 when viewed from above.

[0107] Furthermore, the first pixel 11R has an overlapping wiring L11. The overlapping wiring L11 extends along the second direction Dy and is provided to overlap with the anode power supply line L1 in a plan view. The overlapping wiring L11 is formed of the third metal layer ML3 and is provided in the same layer as the reset signal line L3. The overlapping wiring L11 is electrically connected to the anode power supply line L1.

[0108] Fig.10 yes Fig. 9 X-X' section view. Fig.10As shown, in the first pixel 11R, the anode power line L1 and the image signal line L2 are provided on the insulating film 92. The overlapping wiring L11 and the reset signal line L3 are provided on the insulating film 93. The overlapping wiring L11 is provided on the upper side of the anode power line L1 and is electrically connected to the anode power line L1 through a contact hole H12 provided in the insulating film 93. The reset signal line L3 is provided on the upper side of the image signal line L2 and is insulated from the image signal line L2 by the insulating film 93.

[0109] In addition, the overlap wiring L11 only needs to be electrically connected to the anode power supply line L1 at any position. That is, the contact hole H12 can be provided inside the first pixel 11R or outside the first pixel 11R, such as in the peripheral area GA.

[0110] In the second pixel 11G, the anode power line L1, the image signal line L2, and the initialization signal line L4 are provided in the same layer on the insulating film 92 and are arranged adjacent to each other in the first direction Dx. That is, in the second pixel 11G, the anode power line L1, the image signal line L2, and the initialization signal line L4 are provided in the same layer as the anode power line L1 and the image signal line L2 of the first pixel 11R.

[0111] According to such a configuration, when the display device 1A of the second embodiment is viewed from above, in the first pixel 11R, at least one reset signal line L3 among the plurality of signal lines is provided to overlap with the other video signal lines L2. Thus, the display device 1A can make the metal wiring occupancy rate of the first pixel 11R smaller than the metal wiring occupancy rate of the second pixel 11G. The metal wiring occupancy rate of the first pixel 11R is about 67% or more and about 83% or less, for example, about 75%. The metal wiring occupancy rate of the second pixel 11G is about 72% or more and about 88% or less, for example, about 80%, similarly to the first embodiment.

[0112] In addition, since the overlapping wiring L11 is provided, the total resistance value of the anode power line L1 and the overlapping wiring L11 is reduced compared to when the anode power line L1 is a single layer. This can suppress the voltage drop of the signal supplied to the anode terminal 32 of the light emitting element 3R, thereby improving the light emission intensity of the light emitting element 3R.

[0113] In addition, in the second embodiment, the stacking order of the video signal line L2 and the reset signal line L3 may be reversed. That is, the reset signal line L3 may be disposed on the insulating film 92 formed by the second metal layer ML2, and the video signal line L2 may be disposed on the insulating film 93 formed by the third metal layer ML3.

[0114] In the above description, the anode terminal 32 and the cathode terminal 33 are described as different from each other depending on the connection direction of the light emitting element 3 and the direction of voltage application. They are not limited to the description in the specification and may be opposite. Figure 5 and Figure 8 , a configuration is shown in which one electrode of the light emitting element 3 is located at the lower side and the other electrode is located at the upper side, but both electrodes may be located at the lower side, that is, both electrodes may be located at the side opposite to the array substrate 2. That is, in the display device 1, it is not limited to a face-up configuration in which the upper part of the light emitting element 3 is connected to the cathode electrode 22, and a so-called face-down configuration in which the lower part of the light emitting element 3 is connected to the anode electrode 23 and the cathode electrode 22 may be used.

[0115] The preferred embodiments of the present invention have been described above, but the present invention is not limited to such embodiments. The contents disclosed in the embodiments are only examples, and various changes can be made without departing from the scope of the present invention. Appropriate changes made within the scope of the present invention certainly also fall within the technical scope of the present invention. Without departing from the scope of the above-mentioned embodiments and the scope of the various modifications, at least one of the various omissions, replacements and changes of the constituent elements can be made.

[0116] Description of Reference Numerals

[0117] 1. 1A…display device; 2…array substrate; 3. 3R, 3G, 3B…light-emitting element; 5…circular polarizer; 11. Pix…pixel; 11R…first pixel; 11G…second pixel; 11B…third pixel; 12…driving circuit; 21…substrate; 22…cathode electrode; 23…anode electrode; 24…connecting electrode; 26…opposing electrode; 27…element insulating film; 32…anode terminal; 33…cathode terminal; 60…cathode wiring; 61, 65, 71, 75, 79…semiconductor layer; 90…primer film; 210…driving circuit IC; SST…write transistor; IST…initialization transistor; DRT…drive transistor; BG…light emission control scan line; IG…initialization control scan line; SG…write control scan line; RG…reset control scan line; PVDD…anode power supply potential; PVSS…cathode power supply potential; L1…anode power supply line; L2…image signal line; L3…reset signal line; L4…initialization signal line; L10…cathode power supply line; L11…overlapping wiring; ML1…first metal layer; ML2…second metal layer; ML3…third metal layer.

Claims

1. A display device comprising: substrate; A plurality of first pixels and second pixels are disposed on the substrate, the first pixels represent a first color, and the second pixels represent a second color different from the first color; A plurality of light emitting elements, disposed at each of the plurality of the first pixels and the second pixels; A plurality of signal lines for supplying signals to the first pixel and the second pixel respectively; as well as A plurality of anode power supply lines supply power supply potentials to the first pixel and the second pixel respectively. The width of the anode power line of the first pixel is greater than the width of the anode power line of the second pixel.

2. The display device according to claim 1, wherein: The first pixel has an image signal line and a reset signal line as the plurality of signal lines. The second pixel has another image signal line and an initialization signal line as the plurality of signal lines, In the first pixel, at least one of the plurality of signal lines is provided in a layer different from that of the anode power supply line, In the second pixel, a plurality of the signal lines and the anode power supply lines are arranged in the same layer, In the first pixel, when viewed from above in a direction perpendicular to the substrate, one of the image signal line and the reset signal line is arranged to overlap with the anode power supply line. In the second pixel, the signal line is disposed adjacent to the anode power line in the plan view.

3. The display device according to claim 1, wherein: The thickness of the anode power supply line of the first pixel is thicker than the thickness of the anode power supply line of the second pixel.

4. The display device according to claim 2, wherein: The display device has a first metal layer, a second metal layer, and a third metal layer arranged in different layers in a direction perpendicular to the substrate, The first pixel includes: a driving transistor electrically connected to the light emitting element, a writing transistor connected to the driving transistor, and a plurality of scanning lines formed by the first metal layer. The semiconductor layer of the driving transistor is electrically connected to the light emitting element via an electrode formed by the second metal layer. The semiconductor layer of the write transistor is electrically connected to the image signal line formed by the third metal layer.

5. The display device according to any one of claims 1 to 3, wherein: The sheet resistance value of the anode power supply line is equal to or less than the sheet resistance value of the signal line provided in a layer different from the anode power supply line among the plurality of signal lines.

6. The display device according to any one of claims 1 to 3, wherein: When viewed from above in a direction perpendicular to the substrate, the ratio of the total area of ​​the metal wiring including the plurality of signal lines and the anode power lines to the area of ​​the first pixel is smaller than the ratio of the total area of ​​the metal wiring including the plurality of signal lines and the anode power lines to the area of ​​the second pixel.

7. The display device according to any one of claims 1 to 3, wherein: The display device includes a circular polarizing plate, which is opposite to the substrate and is disposed on the plurality of light emitting elements. The circular polarizing plate has a higher transmittance of light having a red wavelength than a transmittance of light having a blue wavelength or a green wavelength.

8. The display device according to any one of claims 1 to 3, wherein: The first pixel displays red, The second pixel displays blue or green.

9. A display device comprising: substrate; A plurality of first pixels and second pixels are disposed on the substrate, the first pixels represent a first color, and the second pixels represent a second color different from the first color; A plurality of light emitting elements, disposed at each of the plurality of the first pixels and the second pixels; A plurality of signal lines for supplying signals to the first pixel and the second pixel respectively; as well as A plurality of anode power supply lines supply power supply potentials to the first pixel and the second pixel respectively. When viewed from above in a direction perpendicular to the substrate, in the first pixel, at least one of the plurality of signal lines is arranged to overlap with other signal lines, and in the second pixel, the plurality of signal lines are arranged adjacent to each other. The first pixel includes an overlapping wiring, which is provided to overlap with the anode power supply line and is electrically connected to the anode power supply line.

10. The display device according to claim 9, wherein: The first pixel has an image signal line and a reset signal line as the plurality of signal lines. The second pixel has another image signal line and an initialization signal line as the plurality of signal lines, In the first pixel, at least one of the plurality of signal lines is provided in a layer different from that of the anode power supply line, In the second pixel, a plurality of the signal lines and the anode power supply lines are arranged in the same layer, In the second pixel, the signal line is disposed adjacent to the anode power line in the plan view.

11. The display device according to claim 9 or 10, wherein: The overlapping wiring is provided in the same layer as at least one of the plurality of signal lines.

Images