Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a display area, at least one first signal line and at least one connecting wire. The display area comprises a first display area and a second display area; the second display area at least partially surrounds the first display area; the first display area comprises at least one first light-emitting element, and the second display area comprises at least one first pixel circuit; the at least one first signal line comprises a first main body part and a first winding part; the first main body part extends along a first direction, and at least part of the first winding part extends along a direction crossed with the first direction; the at least one first signal line is electrically connected with the at least one first pixel circuit so as to provide a first driving signal for the at least one first pixel circuit; the at least one first pixel circuit is electrically connected with the at least one first light-emitting element through the corresponding connecting wire; and the at least one first pixel circuit is configured to respectively drive the at least one first light emitting element.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application is a divisional application of 202080000311.1, which claims priority to PCT patent applications PCT / CN2020 / 073993, PCT / CN2020 / 073995, PCT / CN2020 / 073996 and PCT / CN2020 / 074001 filed on January 23, 2020. For all purposes, the contents of the above-mentioned PCT patent applications are hereby cited in their entirety as part of this application. Technical Field

[0003] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0004] Organic light emitting diode (OLED) display devices have the characteristics of wide viewing angle, high contrast, fast response speed, wide color gamut, high screen-to-body ratio, self-luminescence, and thinness. In addition, compared with inorganic light-emitting display devices, organic light-emitting diode display devices have advantages such as higher luminous brightness and lower driving voltage. Due to the above characteristics and advantages, organic light-emitting diode (OLED) display devices have gradually attracted widespread attention and can be applied to mobile phones, monitors, laptops, smart watches, digital cameras, instruments, flexible wearable devices and other devices with display functions. With the further development of display technology, display devices with high screen-to-body ratio can no longer meet people's needs, and display devices with full screens have become the development trend of future display technology. Summary of the invention

[0005] At least one embodiment of the present disclosure provides a display substrate, which includes a display area, at least one first signal line and at least one connecting wire. The display area includes a first display area and a second display area; the second display area at least partially surrounds the first display area; the first display area includes at least one first light-emitting element, and the second display area includes at least one first pixel circuit; the at least one first signal line includes a first main body and a first winding part; the first main body extends along a first direction, and the first winding part deviates from the virtual extension line of the first main body along the first direction and is routed; the at least one first signal line is electrically connected to the at least one first pixel circuit to provide a first driving signal to the at least one first pixel circuit; the at least one first pixel circuit is electrically connected to the at least one first light-emitting element via corresponding connecting wires respectively; and the at least one first pixel circuit is configured to drive the at least one first light-emitting element respectively.

[0006] For example, in at least one example of the display substrate, the display area also includes a third display area; the third display area at least partially surrounds the second display area; the at least one first light-emitting element includes a plurality of first light-emitting elements; the second display area includes a plurality of second light-emitting elements; the third display area includes a plurality of third light-emitting elements; and the at least one first signal line is configured to drive the first light-emitting elements and the third light-emitting elements arranged in parallel along the first direction.

[0007] For example, in at least one example of the display substrate, the display substrate further includes at least one second signal line. The at least one second signal line includes a second main body portion, the second main body portion extends along a second direction intersecting the first direction; a virtual extension line of the first main body portion extending along the first direction and a virtual extension line of the second main body portion extending along the second direction intersect within the first display area; the second main body portion of the at least one second signal line is electrically connected to the at least one first pixel circuit to provide the at least one first pixel circuit with a second drive signal different from the first drive signal.

[0008] For example, in at least one example of the display substrate, the at least one connecting wire extends from the first display area to the second display area along the second direction.

[0009] For example, in at least one example of the display substrate, the first main body portion includes a first sub-portion and a second sub-portion separated by the first display area; the first sub-portion and the second sub-portion are electrically connected via the first winding portion; and at least a portion of the first winding portion intersects with a virtual line extending along the first direction between the first sub-portion and the second sub-portion.

[0010] For example, in at least one example of the display substrate, the first winding portion is an arc, a first end of the arc is connected to an end of the first sub-portion close to the second sub-portion, and a second end of the arc is connected to an end of the second sub-portion close to the first sub-portion; or the first winding portion includes a first line segment, a second line segment, and a third line segment connected in sequence, an end of the first line segment not connected to the second line segment is connected to an end of the first sub-portion close to the second sub-portion, an end of the third line segment not connected to the second line segment is connected to an end of the second sub-portion close to the first sub-portion, the second line segment extends along the first direction, and the first line segment and the third line segment extend along a second direction intersecting the first direction.

[0011] For example, in at least one example of the display substrate, the second display area has an inner edge and an outer edge, and the inner edge of the second display area surrounds the first winding portion.

[0012] For example, in at least one example of the display substrate, the at least one first signal line further includes a second winding portion. The first end of the second winding portion is electrically connected to the second sub-portion, and the second end of the second winding portion is electrically connected to the corresponding first pixel circuit; the second winding portion includes a first line portion and a second line portion connected in sequence; an end of the first line portion that is not connected to the second line portion serves as the first end of the second winding portion; an end of the second line portion that is not connected to the first line portion serves as the second end of the second winding portion; the first line portion extends along a second direction intersecting the first direction; the second line portion extends along the first direction and is arranged in parallel with the second sub-portion in the second direction; and during operation, the current direction in the second line portion is opposite to the current direction in the main body portion.

[0013] For example, in at least one example of the display substrate, the display substrate further includes a peripheral region surrounding the display region. The first line portion is entirely located in the peripheral region and is arranged in parallel with the second display region in the first direction.

[0014] For example, in at least one example of the display substrate, the first line portion is entirely located in the second display region, and at least a portion of the first line portion is arranged in parallel with the first display region in the first direction.

[0015] For example, in at least one example of the display substrate, the display substrate further includes a peripheral area surrounding the display area. The first line portion includes a first part, a second part, and a third part connected in sequence; the first part of the first line portion is electrically connected to the second sub-portion, and the third part of the first line portion is electrically connected to the second line portion; the first part of the first line portion is located in the peripheral area and is arranged in parallel with the second display area in the first direction; the second part of the first line portion extends from the peripheral area to the second display area along the first direction; and the third part of the first line portion is located in the second display area, and a virtual extension line of the third part of the first line portion extending along the second direction is arranged in parallel with the first display area in the first direction.

[0016] For example, in at least one example of the display substrate, the at least one first signal line further includes a third winding portion. A first end of the third winding portion is electrically connected to the first sub-portion, a second end of the third winding portion is electrically connected to a corresponding first pixel circuit, and the first pixel circuit connected to the second winding portion is different from the first pixel circuit connected to the third winding portion.

[0017] For example, in at least one example of the display substrate, the third winding portion includes a third wire portion and a fourth wire portion connected in sequence; an end of the third wire portion that is not connected to the fourth wire portion serves as a first end of the third winding portion, and an end of the fourth wire portion that is not connected to the third wire portion serves as a second end of the third winding portion; the third wire portion extends along the second direction and is arranged parallel to the first wire portion in the first direction; the fourth wire portion extends along the first direction and is arranged parallel to the first sub-portion in the second direction; and during operation, a current direction in the fourth wire portion is the same as a current direction in the main body portion.

[0018] For example, in at least one example of the display substrate, the first main body portion, the first winding portion and the second line portion are located on a first electrode layer of the display substrate; the first line portion is located on a second electrode layer of the display substrate; the first electrode layer and the second electrode layer are overlapped in a normal direction of a display surface of the display substrate; and the first line portion is electrically connected to the second sub-portion and the second line portion via a first via hole and a second via hole of an insulating layer located between the first electrode layer and the second electrode layer, respectively.

[0019] For example, in at least one example of the display substrate, each of the at least one first pixel circuit includes a thin film transistor; the thin film transistor includes a gate and a source and a drain; and the source and the drain are located in the first electrode layer, and the gate is located in the second electrode layer.

[0020] For example, in at least one example of the display substrate, the first winding portion surrounds the first display area and is located as a whole in the second display area; the first winding portion includes a fifth line portion, a sixth line portion and a seventh line portion connected in sequence; the fifth line portion is electrically connected to the first sub-portion, and the seventh line portion is electrically connected to the second sub-portion; the sixth line portion extends along the first direction, and the fifth line portion and the seventh line portion extend along a second direction intersecting the first direction; the sixth line portion and a virtual line extending along the first direction between the first sub-portion and the second sub-portion are arranged side by side in the first direction; the sixth line portion and a first pixel circuit electrically connected to the sixth line portion at least partially overlap; and during operation, the current direction in the sixth line portion is the same as the current direction in the main body portion.

[0021] For example, in at least one example of the display substrate, the first winding portion surrounds the first display area and is located as a whole in the second display area; the first winding portion includes an eighth line portion and a ninth line portion connected in sequence; the eighth line portion is electrically connected to the first main body portion and extends along the second direction; the ninth line portion extends along the first direction and is arranged in parallel with a virtual extension line of the first main body portion in the first direction; during operation, the current direction in the ninth line portion is the same as the current direction in the main body portion; and the ninth line portion is electrically connected to a first pixel circuit configured to drive the first number of first light-emitting elements arranged in parallel along the first direction in the first display area.

[0022] For example, in at least one example of the display substrate, the second signal line also includes a fourth winding portion, and the fourth winding portion is routed away from a virtual extension line of the second main body portion along the second direction; the second main body portion includes a third sub-portion and a fourth sub-portion separated by the first display area, and the third sub-portion and the fourth sub-portion are electrically connected via the fourth winding portion; and the fourth winding portion is routed away from a virtual connection line extending along the second direction between the third sub-portion and the fourth sub-portion.

[0023] For example, in at least one example of the display substrate, each of the at least one first pixel circuit includes a thin film transistor, which includes a gate and a source and drain; and the source and drain, the first winding portion and the second signal line are all located in the first electrode layer, and the first main body and the gate are located in the second electrode layer.

[0024] For example, in at least one example of the display substrate, a portion of the at least one connecting wire located in the first display area is a transparent wire.

[0025] At least one embodiment of the present disclosure further provides a display device, which includes any display substrate provided by at least one embodiment of the present disclosure.

[0026] For example, in at least one example of the display substrate, the display device further includes a sensor. The sensor is disposed on a non-display side of the display substrate, overlapped with the first display area in a normal direction of a display surface of the display substrate, and configured to receive and process an optical signal passing through the first display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0028] Figure 1A is a schematic cross-sectional view of a display substrate;

[0029] Figure 1B yes Figure 1A A schematic plan view of a display substrate is shown;

[0030] Figure 1C yes Figure 1B A schematic diagram of a partial area of ​​a display substrate is shown;

[0031] Figure 1D yes Figure 1B A schematic diagram of a portion of a first display area and a portion of a second display area of ​​a display substrate shown;

[0032] Figure 2A is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure;

[0033] Figure 2B yes Figure 2A A schematic plan view of a first display area and a second display area of ​​a display substrate shown;

[0034] Figure 2C yes Figure 2B An example of a first display area and a second display area of ​​a display substrate shown;

[0035] Figure 2D yes Figure 2C A magnified view of a portion of the area;

[0036] Figure 2E yes Figure 2D An enlarged view of a portion of the first display area shown;

[0037] Figure 2F yes Figure 2A An enlarged view of a partial area of ​​a third display area of ​​the display substrate shown;

[0038] Figure 3 is a cross-sectional schematic diagram of a display device provided by at least one embodiment of the present disclosure;

[0039] Figure 4 yes Figure 2A A first example of a display substrate is shown;

[0040] Figure 5A It is used to show Figure 4 A first schematic diagram of a first display area, a second display area and a portion of a peripheral area of ​​a display substrate shown;

[0041] Figure 5B It is used to show Figure 4A second schematic diagram of the first display area, the second display area and a portion of the peripheral area of ​​the display substrate shown;

[0042] Figure 5C It is used to show Figure 4 A third schematic diagram of the first display area, the second display area and part of the peripheral area of ​​the display substrate shown;

[0043] Figure 5D A schematic diagram of a stacked structure of a first light-emitting element and a first pixel circuit driving the first light-emitting element provided by at least one embodiment of the present disclosure is shown;

[0044] Figure 5E A schematic diagram of a stacked structure of a second pixel unit provided by at least one embodiment of the present disclosure is shown;

[0045] Fig. 5F A schematic diagram of a stacked structure of a third pixel unit provided by at least one embodiment of the present disclosure is shown;

[0046] Figure 5G is a schematic diagram of a stacked structure of a second pixel unit, a first wire portion of a second winding portion, and a second sub-portion of a first main body portion provided by at least one embodiment of the present disclosure;

[0047] Figure 5H Another schematic diagram of a stacked structure of a second pixel unit provided by at least one embodiment of the present disclosure is shown;

[0048] Fig.5I is along Figure 5A A schematic cross-sectional view of line HH' is shown;

[0049] Figure 6 yes Figure 2A A second example of a display substrate is shown;

[0050] Fig. 7A It is used to show Figure 6 A first schematic diagram of a first display area, a second display area and a portion of a peripheral area of ​​a display substrate shown;

[0051] Figure 7B It is used to show Figure 6 A second schematic diagram of the first display area, the second display area and a portion of the peripheral area of ​​the display substrate shown;

[0052] Figure 8 yes Figure 2A A third example of a display substrate is shown;

[0053] Fig. 9A It is used to show Figure 8A first schematic diagram of a first display area, a second display area and a portion of a peripheral area of ​​a display substrate shown;

[0054] Fig. 9B It is used to show Figure 8 A second schematic diagram of the first display area, the second display area and a portion of the peripheral area of ​​the display substrate shown;

[0055] Fig.10 yes Figure 2A A fourth example of a display substrate is shown;

[0056] Fig.11 yes Figure 2A A fifth example of a display substrate is shown;

[0057] Fig. 12A It is used to show Fig.11 A first schematic diagram of a first display area, a second display area and a portion of a peripheral area of ​​a display substrate shown;

[0058] Fig. 12B It is used to show Fig.11 A second schematic diagram of the first display area, the second display area and a portion of the peripheral area of ​​the display substrate shown;

[0059] Fig. 12C is corresponding to Fig. 12B A schematic diagram of a part of the area;

[0060] Fig.13A yes Figure 2A A schematic plan view of a sixth example of the display substrate 01 shown;

[0061] Fig. 13B yes Figure 2A Another schematic plan view of a sixth example of the display substrate shown;

[0062] Fig. 13C yes Figure 2A Still another schematic plan view of a sixth example of the display substrate shown;

[0063] Fig.13D is corresponding to Fig. 13C A schematic plan view of a partial region REG_B is shown;

[0064] Fig.14 yes Figure 2A A schematic plan view of a seventh example of the display substrate shown;

[0065] Fig.15 yes Figure 2A A schematic plan view of an eighth example of the display substrate shown;

[0066] Fig.16 yes Figure 2A Another schematic plan view of an eighth example of the display substrate shown;

[0067] Fig.17 A pixel circuit provided by at least one embodiment of the present disclosure and a light-emitting element driven by the pixel electrode;

[0068] Fig.18 yes Fig.17 The structural schematic diagram of the 7T1C pixel circuit shown;

[0069] Fig.19 is a schematic diagram showing the structure of a sub-pixel according to an embodiment of the present disclosure;

[0070] Figure 20-23 are schematic diagrams respectively showing the layout of a certain layer in a sub-pixel according to some embodiments of the present disclosure;

[0071] Fig.24 FIG. 1 is a diagram showing a sub-pixel according to an embodiment of the present disclosure. Figure 20-23 A schematic diagram of the layout of the layer stack shown; and

[0072] Fig.25 FIG. 1 is a diagram showing a sub-pixel according to an embodiment of the present disclosure. Figure 20-23 Schematic diagram of the layout of the layer stackup shown. DETAILED DESCRIPTION

[0073] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0074] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0075] The inventors of the present disclosure have noticed that, for a current display substrate with an under-screen sensor (e.g., a camera), in order to improve the transmittance of the display area of ​​the display substrate corresponding to the under-screen sensor (e.g., a camera), the unit area distribution density (PPI) of the light-emitting elements corresponding to the display area of ​​the under-screen sensor (camera) is smaller than the unit area distribution of the light-emitting elements of other display areas of the display substrate. Figure 1A and Figure 1B An exemplary description is given.

[0076] Figure 1A is a schematic cross-sectional view of a display substrate 500, Figure 1B yes Figure 1A The schematic plan view of the display substrate 500 is shown in FIG. Figure 1A The display substrate 500 shown corresponds to Figure 1B The BB' line of the display substrate 10 is shown. Figure 1C yes Figure 1B FIG. 5 is a schematic diagram of a partial area 513 of a display substrate 500 .

[0077] like Figure 1A As shown, the display substrate 500 includes a display layer 510 and a sensing layer 520, and the sensing layer 520 is disposed on the non-display side (ie, the side facing away from the user) of the display substrate 500. Figure 1A-Figure 1CAs shown, the display layer 510 includes a first display area 511 and a second display area 512; the first display area 511 includes a plurality of first pixel units 531 arranged in an array, each of the plurality of first pixel units 531 includes a first light-emitting element and a first pixel circuit; the second display area 512 includes a plurality of second pixel units 532 arranged in an array, each of the plurality of second pixel units 532 includes a second light-emitting element and a second pixel circuit. For example, the plurality of first light-emitting elements and the plurality of second light-emitting elements have the same structure and performance characteristics; the plurality of first pixel circuits and the plurality of second first pixel circuits have the same structure and performance characteristics.

[0078] like Figure 1A As shown, the sensing layer 520 includes a sensor 521 , which is overlapped with the first display area 511 in the normal direction of the display surface of the display substrate 500 and is configured to receive and process an optical signal passing through the first display area 511 .

[0079] like Figure 1C As shown, in order to reduce the obstruction of the light signals incident to the first display area 511 and transmitted toward the sensor 521 by the elements in the first display area 511, the unit area distribution density of the multiple first pixel units 531 in the first display area 511 is smaller than the unit area distribution density of the multiple second pixel units 532 in the second display area 512, and the unit area distribution density of the multiple first light-emitting elements in the first display area 511 is smaller than the unit area distribution density of the multiple second light-emitting elements in the second display area 512.

[0080] The inventors of the present disclosure also noted that although the transmittance of the display area of ​​the display substrate corresponding to the under-screen sensor (camera) can be improved to a certain extent by reducing the distribution density per unit area (PPI) of the first light-emitting elements and increasing the spacing between adjacent first light-emitting elements, the transmittance-enhancing effect of this solution is still limited, and it is difficult to fully meet the user's needs for obtaining high-quality photos through the under-screen camera.

[0081] like Figure 1A-Figure 1C As shown, the data line 541 and the gate line 542 of the display substrate pass through the first display area 511 . Figure 1D yes Figure 1B A schematic diagram of a portion of the first display area and a portion of the second display area of ​​the display substrate 500 is shown. Figure 1D As shown, the data line 541 passes through the first display area 511 .

[0082] The inventors of the present disclosure also noticed that the data lines 541 and gate lines 542 passing through the first display area 511 will not only block the light incident on the first display area 511 and transmitted toward the sensor 521, but may also cause diffraction, resulting in double images or ghost images in the image output by the sensor, thereby further reducing the image quality of the image output by the sensor.

[0083] At least one embodiment of the present disclosure provides a display substrate and a display device. The display substrate includes a display area, at least one first signal line and at least one connecting wire. The display area includes a first display area and a second display area; the second display area at least partially surrounds the first display area; the first display area includes at least one first light-emitting element, and the second display area includes at least one first pixel circuit; at least one first signal line includes a first main body and a first winding part; the first main body extends along a first direction, and at least part of the first winding part extends along a direction intersecting the first direction; at least one first signal line is electrically connected to at least one first pixel circuit to provide a first drive signal to at least one first pixel circuit; at least one first pixel circuit is electrically connected to at least one first light-emitting element via corresponding connecting wires, respectively; at least one first pixel circuit is configured to drive at least one first light-emitting element, respectively.

[0084] At least one embodiment of the present disclosure further provides a display device, which includes any display substrate provided by at least one embodiment of the present disclosure. The display substrate and the display device can improve the transmittance of the first display area.

[0085] The following is a non-restrictive description of the display substrate and display device provided according to at least one embodiment of the present disclosure through several examples or embodiments. As described below, different features in these specific examples or embodiments can be combined with each other without conflicting with each other to obtain new examples or embodiments, and these new examples or embodiments also fall within the scope of protection of the present disclosure.

[0086] Figure 2A FIG. 1 is a schematic plan view of a display substrate 01 provided by at least one embodiment of the present disclosure. Figure 2A As shown, the display substrate 01 includes a display area 10 and a peripheral area 14, the display area 10 includes a first display area 11, a second display area 12 and a third display area 13, and the peripheral area 14 at least partially surrounds (for example, completely surrounds) the third display area 13. For example, Figure 2A As shown, the first display area 11, the second display area 12 and the third display area 13 do not overlap each other. Figure 2A As shown, the third display area 13 at least partially surrounds (eg, partially surrounds) the second display area 12. Figure 2AAs shown, the third display area 13 partially surrounds the second display area 12. It should be noted that, in some examples, the display substrate 01 may not have the peripheral area 14.

[0087] Figure 2B yes Figure 2A FIG. 1 is a schematic plan view of a first display area 11 and a second display area 12 of a display substrate 01. Figure 2A and Figure 2B As shown, the second display area 12 at least partially surrounds (eg, completely surrounds) the first display area 11 .

[0088] For example, Figure 2A and Figure 2B As shown, the shape of the first display area 11 can be circular, and the shape of the second display area 12 can be rectangular, but the embodiments of the present disclosure are not limited thereto. For another example, the shapes of the first display area 11 and the second display area 12 can both be rectangular or other applicable shapes.

[0089] Figure 2C yes Figure 2B An example of the first display area 11 and the second display area 12 of the display substrate 01 is shown. Figure 2D yes Figure 2C A magnified view of a partial region of REG1. Figure 2E yes Figure 2D An enlarged view of a partial region REG3 of the first display region 11 is shown.

[0090] For example, Figure 2C-Figure 2E As shown, the first display area 11 includes a plurality of first light emitting elements 411. It should be noted that, for the sake of clarity, the relevant drawings use the anode structure 4111 of the first light emitting element 411 to schematically illustrate the first light emitting element 411. For example, Figure 2C-Figure 2E As shown, the first display area 11 includes a plurality of first pixel units 41 arranged in an array, each of the plurality of first pixel units 41 includes a first number of first light emitting elements 411, and the first number of first light emitting elements 411 are configured to emit light of a second number of colors. Figure 2C-Figure 2E As shown, the anode structures 4111 of different first light-emitting elements 411 in the first number of first light-emitting elements 411 have different shapes. Correspondingly, different first light-emitting elements 411 in the first number of first light-emitting elements 411 have different shapes.

[0091] For example, Figure 2C-Figure 2EAs shown, the first number may be four, and the second number may be three, that is, each of the plurality of first pixel units 41 includes four first light-emitting elements 411, and the four first light-emitting elements 411 are configured to emit three colors of light (e.g., red, green, and blue). For example, each of the plurality of first pixel units 41 includes four first light-emitting elements 411 (e.g., GGRB, that is, two green light-emitting elements, one red light-emitting element, and one blue light-emitting element), and the four light-emitting elements (e.g., GGRB) are configured to emit green, green, red, and blue light, respectively. For another example, in the case where each of the plurality of first pixel units 41 includes four first light-emitting elements 411, the arrangement of the four first light-emitting elements 411 is not limited to GGRB, and the arrangement of the four first light-emitting elements 411 may also be RGBG or other applicable arrangements. It should be noted that in some examples, both the first number and the second number may be three; in this case, each of the plurality of first pixel units 41 includes three first light-emitting elements 411 (e.g., RGB).

[0092] For example, Figure 2C and Figure 2D As shown, the second display area 12 includes a plurality of first pixel circuits 412. For example, the plurality of first pixel circuits 412 are configured to drive a plurality of first light emitting elements 411 in a one-to-one correspondence. For example, Figure 2C and Figure 2D The white rectangular boxes shown represent first pixel driving units, and each first pixel driving unit includes a first number of pixel circuits. For example, Figure 2C and Figure 2D The ratio of the number of first pixel driving units to the number of first pixel units 41 in the second display area 12 shown is three; correspondingly, only the pixel circuit of one first pixel driving unit out of every three first pixel driving units is used to drive the first light-emitting element 411, and therefore, the pixel circuit included in the first pixel driving unit used to drive the first light-emitting element 411 is referred to as a first pixel circuit 412, and the pixel circuit included in the first pixel driving unit that is not used to drive the first light-emitting element 411 is referred to as a dummy pixel circuit. For example, the first pixel circuit 412 and the dummy pixel circuit have the same circuit structure. For example, each first pixel driving unit used to drive the first light-emitting element 411 includes a first number of first pixel circuits 412 that are configured to drive a first number of first light-emitting elements 411 of a corresponding first pixel unit 41 in a plurality of first pixel units 41 in a one-to-one correspondence. For example, as Figure 2C-Figure 2E As shown, a plurality of first light emitting elements 411 are arranged in an array, and a plurality of first pixel circuits 412 are arranged in an array. For the sake of clarity, the specific structures of the first light emitting elements 411 and the first pixel circuits 412 will be described in detail in Figure 5DThe examples shown are described above and will not be repeated here.

[0093] For example, Figure 2C and Figure 2D As shown, the second display area 12 further includes a plurality of second pixel units 42, each of the plurality of second pixel units 42 includes a second light emitting element 421 (e.g., a first number of second light emitting elements 421) and a second pixel circuit 422 (e.g., a first number of second pixel circuits 422) for driving the second light emitting element 421. Figure 2C and Figure 2D As shown, each of the plurality of second pixel units 42 includes a second light emitting element 421 and a second pixel circuit 422 (i.e., a rectangular frame at least partially overlapping the second light emitting element 421) at least partially overlapping in the normal direction of the display surface of the display substrate 01 (e.g., a direction perpendicular to the display substrate 01). Figure 2C and Figure 2D As shown, a plurality of second pixel units 42 are arranged in an array. For the sake of clarity, the specific structure of the second pixel unit 42 will be described in detail in Figure 5E The example shown is described in detail and will not be repeated here. Figure 2D The rectangular frame shown is only used to illustrate the second pixel circuit 422 , but does not represent a specific shape of the second pixel circuit 422 or a specific boundary of the second pixel circuit 422 .

[0094] For example, the first number of second light-emitting elements 421 included in the second pixel unit 42 has the same arrangement and structure as the first number of first light-emitting elements 411 included in the first pixel unit 41. For example, the first number of second pixel circuits 422 included in the second pixel unit 42 has the same arrangement and structure as the first number of first pixel circuits 412 included in the first pixel driving unit for driving the first light-emitting elements 411.

[0095] Figure 2F yes Figure 2A FIG. 1 is an enlarged view of a partial area REG2 of the third display area 13 of the display substrate 01. Figure 2F As shown, the third display area 13 includes a plurality of third pixel units 43, each of the plurality of third pixel units 43 includes a third light-emitting element 431 (e.g., a first number of third light-emitting elements 431) and a third pixel circuit 432 (e.g., a first number of third pixel circuits 432) for driving the third light-emitting element 431. Figure 2F As shown, each of the plurality of third pixel units 43 includes a third light emitting element 431 and a third pixel circuit 432 which at least partially overlap in the normal direction of the display surface of the display substrate 01. For the sake of clarity, the specific structure of the third pixel unit 43 will be described in detail in Fig. 5FThe example shown is described in detail and will not be repeated here. Figure 2F The rectangular frame shown is only used to illustrate the third pixel circuit 432 , but does not represent a specific shape of the third pixel circuit 432 and a specific boundary of the third pixel circuit 432 .

[0096] For example, the first number of third light-emitting elements 431 included in the third pixel unit 43 has the same arrangement and structure as the first number of first light-emitting elements 411 included in the first pixel unit 41. For example, the first number of third pixel circuits 432 included in the third pixel unit 43 has the same arrangement and structure as the first number of first pixel circuits 412 included in the first pixel driving unit for driving the first light-emitting element 411.

[0097] For example, Figure 2D and Figure 2F As shown, the unit area distribution density of the plurality of first light emitting elements 411 in the first display area 11 is less than the unit area distribution density of the plurality of third light emitting elements 431 in the second display area 12; the unit area distribution density of the plurality of second light emitting elements 421 in the second display area 12 is less than the unit area distribution density of the plurality of third light emitting elements 431 in the second display area 12. For example, the first display area 11 and the second display area 12 can be referred to as low-resolution areas of the display substrate 01. For example, Figure 2D As shown, the distribution density per unit area of ​​the plurality of first light-emitting elements 411 in the first display area 11 is equal to the distribution density per unit area of ​​the plurality of second light-emitting elements 421 in the second display area 12 .

[0098] Figure 3 03 is a cross-sectional schematic diagram of a display device 03 provided by at least one embodiment of the present disclosure. Figure 3 As shown, the display device 03 includes Figure 2A The display substrate 01 is shown. Figure 3 The schematic cross-sectional view of the display device 03 shown corresponds to Figure 2A The AA' line is shown. Figure 3 As shown, the display device 03 also includes a sensor 02 .

[0099] For example, the display substrate 01 includes a display side and a non-display side opposite to each other, and the display substrate 01 is configured to perform a display operation on the display side of the display substrate 01, that is, the display side of the display substrate 01 is the light emitting side of the display substrate 01, facing the user. The display side and the non-display side are opposite to each other in the normal direction of the display surface of the display substrate 01.

[0100] like Figure 3As shown, the sensor 02 is overlapped with the first display area 11 in the normal direction of the display surface of the display substrate 01 (for example, a direction perpendicular to the display substrate 01), and is configured to receive and process an optical signal passing through the first display area 11, which may be visible light, infrared light, etc. For example, the first display area 11 is not provided with a pixel circuit; in this case, the transmittance of the first display area 11 can be improved.

[0101] For example, by arranging a plurality of first pixel circuits 412 configured to drive a plurality of first light-emitting elements 411 in a one-to-one correspondence in the second display area 12, and overlapping the sensor 02 and the first display area 11 in the normal direction of the display surface of the display substrate 01, the shielding of the light signal incident to the first display area 11 and transmitted toward the sensor 02 by the elements in the first display area 11 can be reduced, thereby improving the signal-to-noise ratio of the image output by the sensor 02. For example, the first display area 11 can be referred to as a high light-transmittance area of ​​the low-resolution area of ​​the display substrate 01.

[0102] For example, the sensor 02 may be an image sensor, and may be used to collect an image of the external environment facing the light-collecting surface of the sensor 02, such as a CMOS image sensor or a CCD image sensor; the sensor 02 may also be an infrared sensor, a distance sensor, etc. For example, in the case where the display device 03 is a mobile terminal such as a mobile phone or a notebook, the sensor 02 may be used to implement a camera of a mobile terminal such as a mobile phone or a notebook, and may also include optical devices such as lenses, reflectors, or optical waveguides as needed to modulate the optical path. For example, the sensor 02 may include photosensitive pixels arranged in an array. For example, each photosensitive pixel may include a photosensitive detector (e.g., a photodiode, a phototransistor) and a switching transistor (e.g., a switching transistor). For example, a photodiode may convert a light signal irradiated thereon into an electrical signal, and a switching transistor may be electrically connected to the photodiode to control whether the photodiode is in a state of collecting light signals and the time of collecting light signals.

[0103] In some examples, only the anode of the first light-emitting element 411 in the first display area 11 is opaque, that is, the wiring for driving the first light-emitting element 411 bypasses the first display area 11 or is set as a transparent wiring; in this case, not only can the transmittance of the first display area 11 be further improved, but also the diffraction caused by each element in the first display area 11 can be reduced. Figure 4 The examples shown are for illustrative purposes only.

[0104] Figure 4 yes Figure 2A A first example of a display substrate 01 is shown. Figure 5A It is used to show Figure 4The first schematic diagram shows a first display area 11 , a second display area 12 and a portion of a peripheral area 14 of a display substrate 01 .

[0105] like Figure 4 and Figure 5A As shown, the display substrate 01 includes at least one first signal line 20, at least one second signal line 30 and at least one connecting line 60. It should be noted that, for the sake of clarity, Figure 4 The sizes of the first display area 11 and the second display area 12 are enlarged, and the size of the third display area 13 in the first direction D1 is reduced. For the convenience of description, Figure 4 The data driving circuit is also shown.

[0106] In one example, at least one first signal line includes multiple first signal lines, and at least one first pixel circuit includes multiple first pixel circuits; in another example, at least one first signal line includes one first signal line, and at least one first pixel circuit includes multiple first pixel circuits; in yet another example, at least one first signal line includes multiple first signal lines, and at least one first pixel circuit includes one first pixel circuit.

[0107] For example, Figure 4 and Figure 5A As shown, the first display area 11 includes at least one first light-emitting element 411, and the second display area 12 includes at least one first pixel circuit 412; at least one connecting wire 60 electrically connects at least one first pixel circuit 412 and at least one first light-emitting element 411 in a one-to-one correspondence; at least one first pixel circuit 412 is configured to drive at least one first light-emitting element 411 in a one-to-one correspondence.

[0108] For example, Figure 4 and Figure 5A As shown, at least one connecting wire 60 extends from the first display area 11 to the second display area 12 along the second direction D2. It should be noted that, Figure 5A The line segments shown connecting between the first number of first light-emitting elements 411 included in each first pixel unit 41 and the first number of first pixel circuits 412 included in each first pixel driving unit for driving the first light-emitting elements 411 represent a first number (eg, four) of connecting wires 60 .

[0109] For example, Figure 4 and Figure 5A As shown, at least one first pixel circuit 412 and at least one first light emitting element 411 driven by the at least one first pixel circuit 412 are arranged in parallel in a second direction D2 intersecting (eg, perpendicular to) the first direction D1.

[0110] For example, the portion of at least one connecting wire 60 located in the first display area 11 is a transparent wire; in this case, not only can the transmittance of the first display area 11 and the signal-to-noise ratio of the image output by the sensor 02 be further improved, but also the diffraction caused by the non-transparent wire can be avoided, thereby further improving the image quality of the image output by the sensor. For example, by making at least one connecting wire 60 entirely made of a transparent conductive material. For example, the transparent conductive material can be selected from transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0111] In some examples, in order to reduce the resistance of the connecting trace 60 and improve the transmission speed of the signal on the connecting trace 60, the connecting trace may include a first part located in the first display area and a second part located in the second display area that are electrically connected to each other, the first part includes a first light-transmitting trace layer made of a transparent conductive material, and the second part includes a metal trace layer made of a metal material, which will not be repeated here.

[0112] For example, Figure 4 and Figure 5A As shown, at least one connecting wire 60 includes multiple connecting wires 60 , and at least one first light-emitting element 411 includes multiple first light-emitting elements 411 ; the length of at least one of the multiple connecting wires 60 is greater than twice the distance between two adjacent first pixel units 41 .

[0113] For example, the resistances of the plurality of connection traces 60 are equal to each other, thereby improving the uniformity of the driving current (for example, when the data signals are equal to each other). Figure 4 and Figure 5A As shown, the lengths of the plurality of connection traces 60 are equal to each other, so that the resistances of the plurality of connection traces 60 can be equal to each other when the plurality of connection traces 60 are made of the same material.

[0114] For example, Figure 4 and Figure 5A As shown, at least one first signal line 20 includes a first main body portion 21 and a first winding portion 22; the first main body portion 21 extends along a first direction D1, and the first winding portion 22 deviates from a virtual extension line 213 of the first main body portion 21 along the first direction D1 and is routed. For example, at least a portion of the first winding portion 22 extends along a direction intersecting the first direction D1. For example, at least a portion of the first winding portion 22 extends along a direction perpendicular to the first direction D1.

[0115] For example, Figure 4As shown, at least one second signal line 30 includes a second main body portion 32, and the second main body portion 32 extends along the second direction D2; a virtual extension line of the first main body portion 21 along the first direction D1 and a virtual extension line of the second main body portion 32 along the second direction D2 intersect in the first display area 11. In some examples, the second signal line 30 also includes a winding portion (for example, a winding portion surrounding the first display area 11), so that the second signal line can still simultaneously drive the pixel circuits located on both sides of the first display area 11 and in the same row in the second direction D2 without passing through the first display area, which will not be repeated here.

[0116] It should be noted that, in order to indicate that the first signal line and the second signal line are used to drive the corresponding pixel circuit, the first signal line and the second signal line cross at the position of the corresponding driven pixel circuit, but the embodiments of the present disclosure are not limited thereto. For example, the first signal line and the second signal line may be closely adjacent to the pixel circuit driven by the first signal line and the second signal line but do not cross at the position of the pixel circuit, and the pixel circuit and the corresponding first signal line and the second signal line may be electrically connected using corresponding routing lines.

[0117] For example, Figure 4 As shown, at least one first signal line 20 is electrically connected to at least one first pixel circuit 412 to provide a first driving signal to at least one first pixel circuit 412; the second main body 32 of at least one second signal line 30 is electrically connected to at least one first pixel circuit 412 to provide a second driving signal different from the first driving signal to at least one first pixel circuit 412.

[0118] For example, Figure 4 As shown, at least one first signal line 20 is electrically connected to the data driving circuit 50 to receive a first driving signal from the data driving circuit 50 , that is, the first signal line 20 is a data line and the first driving signal is a data signal.

[0119] For example, Figure 4 As shown, the first direction D1 and the second direction D2 are the column direction and the row direction of the display substrate 01 respectively; the first signal line 20 and the second signal line 30 are the data line and the gate line of the display substrate 01 respectively; the first driving signal and the second driving signal are the data signal and the gate scanning signal respectively.

[0120] For example, Figure 4 and Figure 5AAs shown, at least one first signal line 20 is configured to drive the first light emitting element 411 and the third light emitting element 431 arranged in parallel along the first direction D1, that is, the first light emitting element 411 and the third light emitting element 431 driven by the same first signal line 20 are located in the same column of the display substrate 01. For example, at least one first signal line 20 is configured to drive the first light emitting element 411, the second light emitting element 421 and the third light emitting element 431 arranged in parallel along the first direction D1, that is, the first light emitting element 411, the second light emitting element 421 and the third light emitting element 431 driven by the same first signal line 20 are located in the same column of the display area of ​​the display substrate 01.

[0121] It should be noted that the display substrate also includes a third signal line (e.g., a data line) and a fourth signal line (e.g., a gate line), the third signal line extends along the first direction D1, and the fourth signal line extends along the second direction D2; the third signal line and the fourth signal line are both straight line segments and do not overlap with the first display area 11 (i.e., do not pass through the first display area 11).

[0122] For example, Figure 4 and Figure 5A As shown, the first main body 21 includes a first sub-section 211 and a second sub-section 212 separated by the first display area 11 (that is, the first sub-section 211 and the second sub-section 212 are respectively located on both sides of the first display area 11 in the first direction D1); the first sub-section 211 and the second sub-section 212 are electrically connected via the first winding section 22; the first winding section 22 deviates from the virtual line extending along the first direction D1 between the first sub-section 211 and the second sub-section 212 (that is, the virtual extension line 213 of the first main body 21 along the first direction D1) and is routed. For example, the first sub-section 211 and the second sub-section 212 are both straight line segments.

[0123] For example, Figure 4 and Figure 5A As shown, by making the first winding portion 22 deviate from the virtual extension line of the first main body portion 21 along the first direction D1, the first signal line 20 can be prevented from overlapping with the first light-emitting element 411 driven by the first signal line 20 and the area near it, thereby improving the transmittance of the display area 10 near the first light-emitting element 411 driven by the first signal line 20.

[0124] For example, Figure 4 and Figure 5A As shown, the second display area 12 has an inner edge 121 and an outer edge 122. Figure 4 and Figure 5AAs shown, the inner edge 121 of the second display area 12 is composed of a circle of pixel circuits (for example, the first pixel circuit 412 and the second pixel circuit 422) located at the innermost side of the second display area 12 and close to the boundary of the first display area 11, that is, the inner edge 121 of the second display area 12 is composed of a circle of pixel circuits located in the second display area 12 that is closest to the first display area 11 and close to the boundary of the first display area 11.

[0125] For example, Figure 4 and Figure 5A As shown, the inner edge 121 of the second display area 12 surrounds the first winding portion 22; in this case, short circuit between the first winding portion 22 and the pixel circuits (eg, the first pixel circuit 412 and the second pixel circuit 422) located in the second display area 12 can be avoided.

[0126] In the first example, the inner edge 121 of the second display area 12 surrounds the first winding portion 22 and the first winding portion 22 surrounds the first display area 11. In this case, not only can the first winding portion 22 avoid blocking the light signal incident on the first display area 11 and transmitted toward the sensor 02, but also can avoid blocking the light emitted by the first light-emitting element 411 located in the first display area 11. This can not only improve the signal-to-noise ratio of the image output by the sensor 02 and avoid the diffraction caused by the first winding portion 22, but also improve the display quality of the first display area 11.

[0127] In the second example, the inner edge 121 of the second display area 12 surrounds the first winding portion 22 and the first winding portion 22 surrounds the effective boundary of the first display area 11. In this case, the first winding portion 22 can avoid blocking the light signal incident into the effective boundary of the first display area 11 and transmitted toward the sensor 02, thereby improving the signal-to-noise ratio of the image output by the sensor 02 and the display quality of the first display area 11. For example, the effective boundary of the first display area 11 is formed by the outer boundary of the outermost circle of the first light-emitting elements 411 located in the first display area 11. In this case, the first winding portion 22 can avoid blocking the light emitted by the first light-emitting elements 411 located in the first display area 11, thereby improving the display quality of the first display area 11. For another example, the effective boundary of the first display area 11 is constituted by the outer boundary of a circle of first light-emitting elements 411 located on the second outermost side of the first display area 11 (i.e., the outermost circle of light-emitting elements among the remaining first light-emitting elements 411 after removing the outermost circle of first light-emitting elements 411 located in the first display area 11); in this case, the first winding portion 22 may at least partially overlap with the outermost circle of first light-emitting elements 411 located in the first display area 11, thereby increasing the wiring space of the first winding portion 22 while slightly reducing the effective area of ​​the first display area 11.

[0128] For example, Figure 5A As shown, the shape of the first display area 11 is a rectangle; the first winding portion 22 includes a first line segment 221, a second line segment 222, and a third line segment 223 connected in sequence; the end of the first line segment 221 not connected to the second line segment 222 is connected to the end of the first sub-portion 211 close to the second sub-portion 212; the end of the third line segment 223 not connected to the second line segment 222 is connected to the end of the second sub-portion 212 close to the first sub-portion 211; the second line segment 222 extends along the first direction D1, and the first line segment 221 and the third line segment 223 extend along the second direction D2 intersecting the first direction D1. For example, the first line segment 221, the second line segment 222, and the third line segment 223 are all straight line segments.

[0129] For example, Figure 4 and Figure 5A As shown, the second line segment 222 may be located between the innermost pixel circuit of the second display area 12 (ie, the side close to the first display area 11 ) and the outermost pixel circuit of the first display area 11 in the second direction D2 .

[0130] For example, Figure 4 and Figure 5AAs shown, the display substrate 01 may further include a second winding portion 23. For example, at least a portion of the second winding portion 23 is routed along a direction intersecting (e.g., perpendicular to) the first direction D1. For example, a first end of the second winding portion 23 is electrically connected to the second sub-portion 212, and a second end of the second winding portion 23 is electrically connected to the corresponding first pixel circuit 412. For example, Figure 4 and Figure 5A As shown, the second end of the second winding portion 23 may be electrically connected to the first pixel circuits 412 in the same column (eg, the first pixel circuits 412 in the same column directly adjacent to the second line portion 232 of the second winding portion 23 ).

[0131] For example, Figure 4 and Figure 5A As shown, the second winding portion 23 includes a first wire portion 231 and a second wire portion 232 connected in sequence; one end of the first wire portion 231 that is not connected to the second wire portion 232 serves as the first end of the second winding portion 23; one end of the second wire portion 232 that is not connected to the first wire portion 231 serves as the second end of the second winding portion 23; the first wire portion 231 extends along the second direction D2; the second wire portion 232 extends along the first direction D1 and is arranged in parallel with the second sub-portion 212 in the second direction D2. For example, the second wire portion 232 is a straight line segment. For example, the first wire portion 231 can be a straight line segment. For another example, the first wire portion 231 can have a bending structure and extend along the second direction D2 as a whole.

[0132] For example, by making the first signal line 20 include the second winding portion 23, the same first signal line 20 can be used to connect pixel circuits located in different columns for driving the first light-emitting element 411 and the third light-emitting element 431 located in the same column, respectively. In this case, the data signal provided by the data driving circuit 50 can be directly corresponding to the position of the light-emitting element, thereby eliminating the need to change the algorithm for providing the data signal and the setting of the data driving circuit 50, and eliminating the need to provide a separate data driving circuit for the data line having the winding portion, thereby reducing the amount of computation of the data driving circuit 50 or the related controller and processor. For example, by making the first signal line 20 include the second winding portion 23, there is no need to adjust the first signal line for providing a data signal to the first pixel circuit configured to drive the first light-emitting element from the first signal line located in the same column as the first light-emitting element (the first signal line located in the third display area portion is located in the same column as the first light-emitting element) to the first signal line located in the same column as the first pixel circuit (the first signal line located in the third display area portion is located in the same column as the first pixel circuit).

[0133] For example, in operation, the current in the second line portion 232 flows in the opposite direction to the current in the main body portion. For example, the current in the first main body portion 21 flows from the lower side of the display substrate 01 (the side where the data driving circuit 50 is disposed) to the upper side of the display substrate 01, and the current in the second line portion 232 flows from the upper side of the display substrate 01 to the lower side of the display substrate 01.

[0134] Figure 5B It is used to show Figure 4 The second schematic diagram of the display substrate 01 showing the first display area 11, the second display area 12 and part of the peripheral area 14, Figure 5C It is used to show Figure 4 The third schematic diagram of the display substrate 01 shows the first display area 11 , the second display area 12 and a portion of the peripheral area 14 . Figure 5B for Figure 5C The upper part of the .

[0135] Figure 5C and Figure 5A resemblance, Figure 5C and Figure 5A The difference is, Figure 5C More first light emitting elements 411, connecting wires 60, first pixel circuits 412, first signal lines 20, second light emitting elements 421 and second pixel circuits 422 are shown, and Figure 5C A fifth signal line 71 (eg, a data line) electrically connected to the second pixel circuit 422 is also shown.

[0136] For example, Figure 5B and Figure 5C As shown, the fifth signal line 71 also has a winding portion. For example, the fifth signal line 71 also has a winding portion surrounding the effective boundary of the first display area 11 , and the inner edge of the second display area 12 surrounds the winding portion of the fifth signal line 71 .

[0137] For example, Figure 5A-Figure 5C As shown, the display substrate 01 includes a plurality of first signal lines 20 , and a plurality of first line portions 231 included in the plurality of first signal lines 20 are arranged in parallel in the first direction D1 (ie, at least partially overlap in the first direction D1 ).

[0138] For example, Figure 5A-Figure 5C As shown, the first line portions 231 included in the first signal lines 20 have the same lengths in the second direction D2, thereby further improving the uniformity of the driving current on the first line portions 231 (for example, when the data signals are equal).

[0139] For example, the first main body portion 21, the first winding portion 22 and the second line portion 232 are located on the first electrode layer of the display substrate 01; the first line portion 231 is located on the second electrode layer of the display substrate 01; the first electrode layer and the second electrode layer are overlapped in the normal direction of the display surface of the display substrate 01; the first line portion 231 is electrically connected to the second sub-portion 212 and the second line portion 232 via the first via hole and the second via hole of the insulating layer located between the first electrode layer and the second electrode layer, respectively.

[0140] For example, by making the first wire portion 231 of the second winding portion 23 of each first signal line 20 connected to other portions of each first signal line 20 (for example, the second wire portion 232 and the second sub-portion 212 ), the first wire portion 231 of the second winding portion 23 of each first signal line 20 can be avoided from being short-circuited with other first signal lines 20 .

[0141] For example, the first electrode layer and the second electrode layer are both made of metal materials, such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), aluminum alloy or other suitable materials.

[0142] Combine the following Figure 5D-5G The specific structures of the first light emitting element 411 , the first pixel circuit 412 , the second pixel unit 42 and the third pixel unit 43 and the relationship between various parts of the first signal line 20 and various components of the thin film transistor of the pixel circuit are exemplarily described.

[0143] Figure 5D The schematic diagram of the stacked structure of the first light-emitting element 411 and the first pixel circuit 412 driving the first light-emitting element 411 provided by at least one embodiment of the present disclosure is shown. For example, the first pixel circuit 412 includes a thin film transistor 412T and a storage capacitor 412C. The first light-emitting element 411 includes a first anode structure 4111, a first cathode structure 4113, and a first light-emitting layer 4112 between the first anode structure 4111 and the first cathode structure 4113. The first anode structure 4111 is electrically connected to the thin film transistor 412T included in the first pixel circuit 412 through a via. For example, the first anode structure 4111 may include a plurality of anode sublayers, such as a three-layer structure of ITO / Ag / ITO (not shown in the figure), and the embodiment of the present disclosure does not limit the specific form of the first anode structure 4111. For example, the first cathode structure 4113 may be a structure formed on the entire surface of the display substrate 01, and the first cathode structure 4113 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag). For example, since the first cathode structure 4113 can be formed as a very thin layer, the first cathode structure 4113 has good light transmittance.

[0144] For example, the thin film transistor 412T includes an active layer 4121, a gate 4122, and source-drain electrodes (i.e., a source 4123 and a drain 4124), and the storage capacitor 412C includes a first capacitor plate 4125 and a second capacitor plate 4126. For example, the active layer 4121 is disposed on the substrate 74, a first gate insulating layer 741 is disposed on the side of the active layer 4121 away from the substrate 74, the gate 4122 and the first capacitor plate 4125 are disposed in the same layer and are located on the side of the first gate insulating layer 741 away from the substrate 74, a second gate insulating layer 742 is disposed on the side of the gate 4122 and the first capacitor plate 4125 away from the substrate 74, and the second capacitor plate 4126 is disposed on the second gate insulating layer 742. The side of the second capacitor plate 4126 away from the substrate 74 is provided with an interlayer insulating layer 743, the source and drain electrodes are provided on the side of the interlayer insulating layer 743 away from the substrate 74, and are electrically connected to the active layer 4121 through vias located in the first gate insulating layer 741, the second gate insulating layer 742 and the interlayer insulating layer 743, and the side of the source and drain electrodes away from the substrate 74 is provided with a planarizing layer 744 to planarize the first pixel circuit 412.

[0145] For example, the planarization layer 744 has a via hole, and the first anode structure 4111 is electrically connected to the source 4123 or the drain 4124 of the thin film transistor 412T through the via hole in the planarization layer 744 .

[0146] For example, the first display area 11 further includes a transparent supporting layer 78 located on the base substrate 74, and the first light emitting element 11 is located on a side of the transparent supporting layer 78 away from the base substrate 74. Thus, relative to the base substrate 74, the first light emitting element 411 in the first display area 11 can be at substantially the same height as the second light emitting element 421 in the second display area 12 and the third light emitting element 431 in the third display area 13, thereby improving the display effect of the display substrate.

[0147] Figure 5E FIG. 4 shows a schematic diagram of a stacked structure of a second pixel unit 42 provided by at least one embodiment of the present disclosure, such as Figure 5EAs shown, the second pixel unit 42 includes a second light-emitting element 421 and a second pixel circuit 422 that drives the second light-emitting element 421. For example, the second pixel circuit 422 includes structures such as a thin film transistor 422T and a storage capacitor 422C. The second light-emitting element 421 includes a second anode structure 4211, a second cathode structure 4213, and a second light-emitting layer 4212 between the second anode structure 4211 and the second cathode structure 4213. The second anode structure 4211 is electrically connected to the thin film transistor 422T included in the second pixel circuit 422 through a via 744A. For example, the second anode structure 4211 may include a plurality of anode sublayers, such as a three-layer structure of ITO / Ag / ITO, etc. (not shown in the figure), and the embodiments of the present disclosure do not limit the specific form of the second anode structure 4211.

[0148] For example, the thin film transistor 422T includes an active layer 4221, a gate 4222, and source-drain electrodes (i.e., a source 4223 and a drain 4224), and the storage capacitor 422C includes a first capacitor plate 4225 and a second capacitor plate 4226. For example, the active layer 4221 is disposed on the substrate 74, a first gate insulating layer 741 is disposed on the side of the active layer 4221 away from the substrate 74, the gate 4222 and the first capacitor plate 4225 are in the same layer and are disposed on the side of the first gate insulating layer 741 away from the substrate 74, a second gate insulating layer 742 is disposed on the side of the gate 4222 and the first capacitor plate 4225 away from the substrate 74, and the second capacitor plate 4226 is disposed on the second gate insulating layer 742. An interlayer insulating layer 743 is provided on the side of the second capacitor plate 4226 away from the substrate 74, and the source and drain electrodes are provided on the side of the interlayer insulating layer 743 away from the substrate 74, and are electrically connected to the active layer 4221 through vias located in the first gate insulating layer 741, the second gate insulating layer 742 and the interlayer insulating layer 743. A flattening layer 744 is provided on the side of the source and drain electrodes away from the substrate 74 to flatten the second pixel circuit 422.

[0149] For example, the planarization layer 744 has a via hole 744A, and the second anode structure 4211 is electrically connected to the source 4223 or the drain 4224 of the thin film transistor 422T through the via hole 744A in the planarization layer 744 .

[0150] It should be noted that, for the sake of clarity, Figure 5E Only one second light emitting element 421 and one second pixel circuit 422 included in the second pixel unit 42 are shown, and only one thin film transistor 422T and one storage capacitor 422C included in the second pixel circuit 422 are shown, but the embodiments of the present disclosure are not limited thereto.

[0151] For example, Fig. 5FFIG. 4 shows a schematic diagram of a stacked structure of a third pixel unit 43 provided by at least one embodiment of the present disclosure, such as Fig. 5F As shown, each third sub-pixel includes a third light-emitting element 431 and a third pixel circuit 432 electrically connected to the third light-emitting element, and the third pixel circuit 432 is configured to drive the third light-emitting element 431. The third light-emitting element 431 includes a third anode structure 4311, a third cathode structure 4313, and a third light-emitting layer 4312 between the third anode structure 4311 and the third cathode structure 4313, and the third anode structure 4311 is electrically connected to the third pixel circuit 432 through a via. For example, the third anode structure 4311 may include a plurality of anode sub-layers, such as a three-layer structure of ITO / Ag / ITO, etc. (not shown in the figure), and the embodiments of the present disclosure do not limit the specific form of the third anode structure 4311.

[0152] For example, the third pixel circuit 432 includes a thin film transistor 432T and a storage capacitor 432C. For example, the thin film transistor 432T includes an active layer 4321, a gate 4322, and a source-drain electrode (i.e., a source 4323 and a drain 4324), and the storage capacitor 432C includes a first capacitor plate 4325 and a second capacitor plate 4326. For example, the active layer 4321 is disposed on the substrate 74, a first gate insulating layer 741 is disposed on the side of the active layer 4321 away from the substrate 74, the gate 4322 and the first capacitor plate 4325 are in the same layer and are disposed on the side of the first gate insulating layer 741 away from the substrate 74, a second gate insulating layer 742 is disposed on the side of the gate 4322 and the first capacitor plate 4325 away from the substrate 74, and the second capacitor plate 4326 is disposed on the second gate insulating layer 742. An interlayer insulating layer 743 is provided on the side of the second capacitor plate 4326 away from the substrate 74, the source and drain electrodes are provided on the side of the interlayer insulating layer 743 away from the substrate 74, and are electrically connected to the active layer 4321 through the first gate insulating layer 741, the second gate insulating layer 742 and the via holes in the interlayer insulating layer 743, and a flattening layer 744 is provided on the side of the source and drain electrodes away from the substrate 74 to flatten the third pixel circuit 432.

[0153] For example, the planarization layer 744 has a via hole 744B, and the third anode structure 4311 is electrically connected to the source 4323 or the drain 4324 of the thin film transistor 432T through the via hole 744B in the insulation layer 745 .

[0154] It should be noted that, for the sake of clarity, Fig. 5FOnly one third light emitting element 431 and one third pixel circuit 432 included in the third pixel unit 43 are shown, and only one thin film transistor 432T and one storage capacitor 432C included in the third pixel circuit 432 are shown, but the embodiments of the present disclosure are not limited thereto.

[0155] For example, the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 are arranged in the same layer, so they can be formed by the same patterning process in the preparation process. For example, the first gate insulating layer 741, the second gate insulating layer 742, the interlayer insulating layer 743, and the planarization layer 744 are arranged in the same layer in the first display area 11, the second display area 12, and the third display area 13, and in some embodiments, they are integrally connected (that is, integrally formed and connected to each other), so the same reference numerals are used in the drawings.

[0156] For example, in some embodiments, the display substrate further includes structures such as a pixel defining layer 746 and an encapsulation layer 747. For example, the pixel defining layer 746 is disposed on the first anode structure and includes a plurality of openings to define different pixels or sub-pixels, and the first light-emitting layer is formed in the openings of the pixel defining layer 746. For example, the encapsulation layer 747 may include a single-layer or multi-layer encapsulation structure, and the multi-layer encapsulation structure may include, for example, a stack of an inorganic encapsulation layer and an organic encapsulation layer, thereby improving the encapsulation effect on the display substrate.

[0157] For example, the pixel defining layer 746 in the first display area 11, the second display area 12 and the third display area 13 are arranged in the same layer, and the encapsulation layer 747 in the first display area 11, the second display area 12 and the third display area 13 are arranged in the same layer, and in some embodiments, they are integrally connected, so the same labels are used in the drawings.

[0158] For example, in various embodiments of the present disclosure, the base substrate 74 may be a glass substrate, a quartz substrate, a metal substrate, a resin substrate, etc., and may be a rigid substrate or a flexible substrate. The embodiments of the present disclosure are not limited to this.

[0159] For example, the first gate insulating layer 741, the second gate insulating layer 742, the interlayer insulating layer 743, the planarizing layer 744, the insulating layer 745, the pixel defining layer 746, the encapsulation layer 747, and the insulating layer 748 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin. The embodiments of the present disclosure do not specifically limit the materials of the above-mentioned functional layers.

[0160] For example, the material of the active layer 4121 / 4221 / 4321 may include semiconductor materials such as polysilicon or oxide semiconductors (eg, indium gallium zinc oxide). For example, a portion of the active layer 4121 / 4221 / 4321 may be conductively treated by doping or the like to have higher conductivity.

[0161] For example, in each of the above examples, the material of the gate 4122 / 4222 / 4322, the first capacitor plate 4125 / 4225 / 4325 and the second capacitor plate 4126 / 4226 / 4326 may include a metal material or an alloy material, such as molybdenum, aluminum and titanium.

[0162] For example, the materials of the source 4123 / 4223 / 4323 and the drain 4124 / 4224 / 4324 may include metal materials or alloy materials, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack, such as a three-layer metal stack of titanium, aluminum and titanium (Ti / Al / T i), etc.

[0163] For example, the display substrate provided in the embodiment of the present disclosure may be an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, and the embodiment of the present disclosure does not limit the specific type of the display substrate.

[0164] For example, in the case where the display substrate is an organic light emitting diode display substrate, the light emitting layer 4111 / 4211 / 4311 may include small molecule organic materials or polymer molecule organic materials, may be fluorescent light emitting materials or phosphorescent light emitting materials, may emit red light, green light, blue light, or may emit white light, etc. Moreover, according to different actual needs, in different examples, the light emitting layer 4111 / 4211 / 4311 may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0165] For example, in the case where the display substrate is a quantum dot light-emitting diode (QLED) display substrate, the light-emitting layer 4111 / 4211 / 4311 may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc., and the particle size of the quantum dots is 2-20nm.

[0166] Figure 5G is a schematic diagram of a stacked structure of a second pixel unit 42, a first wire portion 231 of a second winding portion 23, and a second sub-portion 212 of a first main body portion 21 provided by at least one embodiment of the present disclosure. Figure 5GAs shown, the second sub-portion 212 of the first main body 21, the source 4223 and the drain 4224 are located in the first electrode layer 251 of the display substrate 01. For example, the first sub-portion 211 of the first main body 21, the first winding portion 22 and the second winding portion 232 are also located in the first electrode layer 251. Fig. 5F As shown, the first wire portion 231 of the second winding portion 23, the gate electrode 4222 and the first capacitor plate 4225 are located on the second electrode layer 252 of the display substrate 01. Figure 5G As shown, the first wire portion 231 is electrically connected to the second sub-portion 212 and the second wire portion 232 via the first via hole 254 and the second via hole 255 of the insulating layer between the first electrode layer 251 and the second electrode layer 252, that is, the first signal line 20 adopts a jumper design, for example, a design including multiple jumpers can be adopted. In some examples, the first wire portion 231 and the second capacitor plate 4226 of the second winding portion 23 are located on the second electrode layer 252 of the display substrate 01, which will not be described in detail here. For example, the second main body 32 of the second signal line 30 is also located on the second electrode layer 252 of the display substrate 01.

[0167] Figure 5H FIG. 4 shows another schematic diagram of a stacked structure of a second pixel unit 42 provided by at least one embodiment of the present disclosure, such as Figure 5H As shown, the second pixel unit 42 includes a second light-emitting element 421 and a second pixel circuit 422 that drives the second light-emitting element 421. For example, the second pixel circuit 422 includes structures such as a thin film transistor 422T and a storage capacitor 422C. The second light-emitting element 421 includes a second anode structure 4211, a second cathode structure 4213, and a second light-emitting layer 4212 between the second anode structure 4211 and the second cathode structure 4213. The second anode structure 4211 is electrically connected to the switching electrode 749 through a via 744A, and the switching electrode 749 is electrically connected to the thin film transistor 422T included in the second pixel circuit 422 via a via 744B. For example, the second anode structure 4211 may include multiple anode sublayers, such as a three-layer structure of ITO / Ag / ITO, etc. (not shown in the figure), and the embodiments of the present disclosure do not limit the specific form of the second anode structure 4211. For example, the switching electrode 749 can be made of a transparent conductive material. For example, the transparent conductive material may be selected from transparent metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0168] For example, the thin film transistor 422T includes an active layer 4221, a gate 4222, and source-drain electrodes (i.e., a source 4223 and a drain 4224), and the storage capacitor 422C includes a first capacitor plate 4225 and a second capacitor plate 4226. For example, the active layer 4221 is disposed on the substrate 74, a first gate insulating layer 741 is disposed on the side of the active layer 4221 away from the substrate 74, the gate 4222 and the first capacitor plate 4225 are in the same layer and are disposed on the side of the first gate insulating layer 741 away from the substrate 74, a second gate insulating layer 742 is disposed on the side of the gate 4222 and the first capacitor plate 4225 away from the substrate 74, the second capacitor plate 4226 is disposed on the side of the second gate insulating layer 742 away from the substrate 74, an interlayer insulating layer 743 is disposed on the side of the second capacitor plate 4226 away from the substrate 74, and the source-drain The electrode is arranged on the side of the interlayer insulating layer 743 away from the base substrate 74, and is electrically connected to the active layer 4221 through vias located in the first gate insulating layer 741, the second gate insulating layer 742 and the interlayer insulating layer 743; a passivation layer 748 is arranged on the side of the source and drain electrodes away from the base substrate 74; a first planarization layer 744 is arranged on the side of the passivation layer 748 away from the base substrate 74 to planarize the second pixel circuit 422; a transfer electrode 749 is arranged on the side of the first planarization layer 7441 away from the base substrate 74; a second planarization layer 7442 is arranged on the side of the transfer electrode 749 away from the base substrate 74.

[0169] For example, the first planarization layer 7441 has a via hole 744B, and the switching electrode 749 is electrically connected to the source 4223 or the drain 4224 of the thin film transistor 422T through the via hole 744B in the first planarization layer 7441. For example, the planarization layer 744 has a via hole 744A, and the second anode structure 4211 is electrically connected to the switching electrode 749 through the via hole 744A in the second planarization layer 7442, so that the second anode structure 4211 can be electrically connected to the source 4223 or the drain 4224 of the thin film transistor 422T.

[0170] For example, Figure 5H As shown, the display substrate further includes structures such as a pixel defining layer 746 and an encapsulation layer 747. For example, the pixel defining layer 746 is disposed on the first anode structure and includes a plurality of openings to define different pixels or sub-pixels, and the first light-emitting layer is formed in the openings of the pixel defining layer 746. For example, the encapsulation layer 747 may include a first encapsulation layer 7471, a second encapsulation layer 7472, and a third encapsulation layer 7473 sequentially disposed on the second cathode structure 4213 in a direction perpendicular to the display substrate. For example, the first encapsulation layer 7471, the second encapsulation layer 7472, and the third encapsulation layer 7473 are respectively an inorganic encapsulation layer, an organic encapsulation layer, and an inorganic encapsulation layer.

[0171] It should be noted that, for the sake of clarity, Figure 5H Only one second light emitting element 421 and one second pixel circuit 422 included in the second pixel unit 42 are shown, and only one thin film transistor 422T and one storage capacitor 422C included in the second pixel circuit 422 are shown, but the embodiments of the present disclosure are not limited thereto.

[0172] It should be noted that the second pixel unit 42 provided in at least one embodiment of the present disclosure adopts Figure 5H In the case of the structure shown in FIG. 1 , the third pixel unit 43 provided by at least one embodiment of the present disclosure, the first light-emitting element 411 provided by at least one embodiment of the present disclosure, and the first pixel circuit 412 driving the first light-emitting element 411 may also be adopted. Figure 5H The structure shown will not be described in detail here.

[0173] Fig.5I is along Figure 5A The cross-sectional view of the HH' line is shown in FIG. Fig.5I As shown, the second sub-portion 212 of the first main body 21 and the second wire portion 232 of the second winding portion 23 are located on the side of the interlayer insulating layer 743 away from the base substrate 74, that is, the second sub-portion 212 of the first main body 21 and the second wire portion 232 of the second winding portion 23 and the source and drain electrodes (e.g., source 4223 and drain 4224) of the thin film transistor are arranged in the same electrode layer (e.g., first electrode layer 251). For example, the first sub-portion 211 of the first main body 21 and the first winding portion 22 are also located in the same electrode layer (e.g., first electrode layer 251) as mentioned above.

[0174] For example, Fig.5I As shown, the first wire portion 231 of the second winding portion 23 is located between the first gate insulating layer 741 and the second gate insulating layer 742, that is, the first wire portion 231 of the second winding portion 23, the gate 4222 and the first capacitor plate 4225 are located in the same electrode layer (for example, located in the second electrode layer 252 of the display substrate 01). Fig.5I As shown, the first wire portion 231 is electrically connected to the second sub-portion 212 and the second wire portion 232 via the first via hole 254 and the second via hole 255 of the insulating layer between the first electrode layer 251 and the second electrode layer 252, respectively, that is, the first signal line 20 adopts a jumper design, for example, a design including multiple jumpers can be adopted. For example, the second main body 32 of the second signal line 30 is also located in the second electrode layer 252 of the display substrate 01. In some examples, the first wire portion 231 of the second winding portion 23 and the second capacitor plate 4226 are located in the same electrode layer (for example, the second electrode layer 252 of the display substrate 01), and the gate 4222 is not located in the same electrode layer (for example, the second electrode layer 252 of the display substrate 01).

[0175] For example, Figure 4 , Figure 5A-Figure 5C and Figure 5G As shown, the first line portion 231 is entirely located in the peripheral area 14 and arranged in parallel with the second display area 12 in the first direction D1. For example, since the peripheral area 14 does not have a pixel circuit (first pixel circuit 412 to third pixel circuit 432), the wiring difficulty of the first line portion 231 can be reduced.

[0176] For example, Figure 4 and Figure 5A-Figure 5C As shown, the first line portion 231 is entirely located on a side of the second display area 12 away from the third display area 13 in the first direction D1. Figure 4 and Figure 5A-Figure 5C As shown, the first line portion 231 is entirely located at the upper edge of the display substrate 01 .

[0177] It should be noted that although Figure 4 , Figure 5A-Figure 5C and Figure 5G The first line portion 231 shown is located entirely in the peripheral area 14, but the embodiments of the present disclosure are not limited thereto. According to actual application requirements, the first line portion 231 may also be located entirely in the second display area 12 or the first line portion 231 may be located in both the peripheral area 14 and the second display area 12. Figure 6 , Figure 7A-7B , Figure 8 and Figure 9A-9B An exemplary description is given.

[0178] Figure 6 yes Figure 2A A second example of a display substrate 01 is shown. Fig. 7A It is used to show Figure 6 The first schematic diagram of the display substrate 01 shows a first display area 11, a second display area 12 and a portion of a peripheral area 14. Figure 7B It is used to show Figure 6 The second schematic diagram shows the first display area 11 , the second display area 12 and a portion of the peripheral area 14 of the display substrate 01 .

[0179] For example, Figure 6 and Figure 7A-7B As shown, the first line portion 231 is entirely located in the second display area 12 and is arranged in parallel with the first display area 11 in the first direction D1. Figure 6 and Figure 7A-7B As shown, the first line portion 231 is located on a side of the first display area 11 away from the third display area 13 in the first direction D1.

[0180] In one example, the first line portions 231 included in the first signal lines 20 are all straight (i.e., straight line segments). In another example, at least some of the first line portions 231 included in the first signal lines 20 may have a bent structure to prevent some of the first line portions 231 from overlapping with the second light-emitting element 421 and shielding the light emitted by the second light-emitting element 421.

[0181] For example, by making the first line portion 231 entirely located in the second display area 12 , the size of the peripheral area 14 of the display substrate 01 can be reduced, thereby facilitating a narrow frame or full-screen design of the display substrate 01 .

[0182] It should be noted that Figure 6 The other structures and specific implementation methods of the display substrate 01 are similar to those of Figure 4 The other structures and specific implementation methods of the display substrate 01 are the same or similar, and the same or similar parts are not described in detail.

[0183] It should be noted that, compared with the connection wiring 60 , the first light emitting element 411 and the second light emitting element 421 are further away from the base substrate of the display substrate 01 ; Fig. 7A The plan view diagram and other related plan view diagrams are used to illustrate the arrangement and connection of the various components of the display substrate 01 in a plane parallel to the base substrate of the display substrate 01, and are not used to limit the arrangement or relative position relationship of the various components of the display substrate 01 in a direction perpendicular to the base substrate of the display substrate 01. The arrangement and relative position relationship of the various components of the display substrate 01 in a direction perpendicular to the base substrate of the display substrate 01 can be seen in Figure 5D-Figure 5H The schematic diagram of the stacked structure shown in FIG. Fig.5I The cross-sectional schematic diagram shown is not repeated here.

[0184] Figure 8 yes Figure 2A A third example of a display substrate 01 is shown. Fig. 9A It is used to show Figure 8 The first schematic diagram of the display substrate 01 shows a first display area 11, a second display area 12 and a portion of a peripheral area 14. Fig. 9B It is used to show Figure 8 The second schematic diagram shows the first display area 11 , the second display area 12 and a portion of the peripheral area 14 of the display substrate 01 .

[0185] For example, Figure 8 and Figure 9A-9BAs shown, the first line portion 231 includes a first portion 2311, a second portion 2312 and a third portion 2313 which are connected in sequence; the first portion 2311 of the first line portion 231 is electrically connected to the second sub-portion 212, and the third portion 2313 of the first line portion 231 is electrically connected to the second line portion 232; the first portion 2311 of the first line portion 231 is located in the peripheral area 14, and is arranged in parallel with the second display area 12 in the first direction D1; the second portion 2312 of the first line portion 231 extends from the peripheral area 14 to the second display area 12 along the first direction D1; the third portion 2313 of the first line portion 231 is located in the second display area 12, and a virtual extension line of the third portion 2313 of the first line portion 231 extending along the second direction D2 is arranged in parallel with the first display area 11 in the first direction D1.

[0186] In some examples, the third portion 2313 of the first line portion 231 is electrically connected to the second sub-portion 212, and the first portion 2311 of the first line portion 231 is electrically connected to the second line portion 232, that is, the electrically connected portion of the first line portion 231 and the second sub-portion 212 is located in the second display area 12, and the electrically connected portion of the first line portion 231 and the second line portion 232 is located in the peripheral area 14, which will not be repeated here.

[0187] It should be noted that Figure 8 The other structures and specific implementation methods of the display substrate 01 are similar to those of Figure 4 The other structures and specific implementation methods of the display substrate 01 are the same or similar, and the same or similar parts are not described in detail.

[0188] It should be noted that although Figure 4 , Figure 6 and Figure 8 The second winding portion 23 of the display substrate 01 shown in the figure is wound from the second sub-portion 212 of the first main body portion 21 to a position parallel to the second sub-portion 212 of the first main body portion 21 (parallel in the second direction D2) via the first display area 11 on the side far away from the third display area 13 in the first direction D1, but the embodiments of the present disclosure are not limited thereto. In some examples, the second winding portion 23 can be wound from the first sub-portion 211 of the first main body portion 21 via the side of the first display area 11 close to the third display area 13 in the first direction D1 to a position parallel to the second sub-portion 212 of the first main body portion 21 (parallel in the second direction D2), as shown below in combination with Fig.10 An exemplary description is given.

[0189] Fig.10 yes Figure 2A A fourth example of the display substrate 01 is shown. Fig.10 The display substrate 01 shown is Figure 6The display substrate 01 shown is similar, and only the differences between the two are described here, and the similarities are not repeated. Fig.10 The display substrate 01 shown is Figure 6 The difference of the display substrate 01 shown is that Fig.10 The first line portion 231 of the display substrate 01 shown is located on a side of the first display area 11 close to the third display area 13 in the first direction D1, and, in operation, Fig.10 The current flow in the second line portion 232 of the display substrate 01 is shown to be the same as the current flow in the main body portion.

[0190] In some examples, in the first direction D1, at least part (eg, all) of the first line portion 231 may be arranged in parallel with the first display area 11 and located at one end of the third display area 13 close to the first display area 11, which is not described in detail herein.

[0191] It should be noted that although Figure 4 , Figure 6 , Figure 8 and Fig.10 The first signal lines 20 of the display substrate 01 shown in the figure are all wound from one side of the first display area 11 in the first direction D1 to a position parallel to the first main body 21 (parallel to the second direction D2), however, the embodiments of the present disclosure are not limited thereto. In some examples, the first signal lines 20 of the display substrate 01 can be wound from both sides of the first display area 11 in the first direction D1 to a position parallel to the first main body 21 (parallel to the second direction D2). Fig.11 and Figure 12A-12C An exemplary description is given.

[0192] Fig.11 yes Figure 2A A fifth example of the display substrate 01 is shown. Fig. 12A It is used to show Fig.11 The first schematic diagram of the display substrate 01 shows a first display area 11, a second display area 12 and a portion of a peripheral area 14. Fig. 12B It is used to show Fig.11 A second schematic diagram of the first display area 11, the second display area 12 and a portion of the peripheral area 14 of the display substrate 01 is shown; Fig. 12C is corresponding to Fig. 12B Schematic diagram of a partial area REG_E.

[0193] Fig.11 The display substrate 01 shown is Figure 4 The display substrate 01 shown is similar, and only the differences between the two are described here, and the similarities are not repeated. Fig.11 The display substrate 01 shown is Figure 4The difference of the display substrate 01 shown is that the display substrate 01 further includes a third winding portion 24. For example, at least a portion of the third winding portion 24 is routed along a direction intersecting (eg, perpendicular to) the first direction D1.

[0194] For example, Fig.11 and Figure 12A-12B As shown, the first end of the third winding portion 24 is electrically connected to the first sub-portion 211, the second end of the third winding portion 24 is electrically connected to the corresponding first pixel circuit 412, and the first pixel circuit 412 connected to the second winding portion 23 is different from the first pixel circuit 412 connected to the third winding portion 24.

[0195] For example, Fig.11 and Figure 12A-12B As shown, the first pixel circuit 412 connected to the second winding portion 23 and the first pixel circuit 412 connected to the third winding portion 24 are located in the same column, that is, the first pixel circuit 412 connected to the second winding portion 23 and the first pixel circuit 412 connected to the third winding portion 24 are arranged in the first direction D1. For example, the first pixel circuit 412 connected to the second winding portion 23 is the first pixel circuit 412 in the upper half of the first pixel circuit 412 in the same column, and the first pixel circuit 412 connected to the second winding portion 23 is the first pixel circuit 412 in the lower half of the first pixel circuit 412 in the same column.

[0196] For example, by making the first signal line 20 also include a third winding portion 24, the data line can be used to bidirectionally drive the pixel circuits (the first pixel circuit 412 and the second pixel circuit 422) in the area of ​​the second display area 12 that is parallel to the first display area 11 in the second direction D2, that is, data signals are input from above and below the area of ​​the second display area 12 that is parallel to the first display area 11 in the second direction D2 to the pixel circuits located in the area; in this case, the size of the opening of the second display area 12 (for example, the inner edge 121 of the second display area 12) is larger.

[0197] For example, Fig.11 and Figure 12A-12BAs shown, the third winding portion 24 includes a third wire portion 241 and a fourth wire portion 242 connected in sequence; the end of the third wire portion 241 not connected to the fourth wire portion 242 serves as the first end of the third winding portion 24, and the end of the fourth wire portion 242 not connected to the third wire portion 241 serves as the second end of the third winding portion 24; the third wire portion 241 extends along the second direction D2 and is arranged in parallel with the first wire portion 231 in the first direction D1; the fourth wire portion 242 extends along the first direction D1 and is arranged in parallel with the first sub-portion 211 in the second direction D2; during operation, the current direction in the fourth wire portion 242 is the same as the current direction in the main body. For example, the fourth wire portion 242 is a straight line segment. For example, the third wire portion 241 can be a straight line segment. For another example, the third wire portion 241 can have a bending structure and extend along the second direction D2 as a whole.

[0198] For example, the fourth line portion 242 is located at the first electrode layer of the display substrate 01; the third line portion 241 is located at the second electrode layer of the display substrate 01; the third line portion 241 is electrically connected to the first sub-portion 211 and the fourth line portion 242 via the third via hole and the fourth via hole of the insulating layer located between the first electrode layer and the second electrode layer, respectively.

[0199] For example, by making the first wire portion 231 of the second winding portion 23 and the third wire portion 241 of the third winding portion 24 of each first signal line 20 connected to other portions of each first signal line 20 (for example, the fourth wire portion 242 and the first sub-portion 211), the first wire portion 231 of the second winding portion 23 and the third wire portion 241 of the third winding portion 24 of each first signal line 20 can be avoided from being short-circuited with other first signal lines 20.

[0200] For example, Fig. 12C As shown, the first display area 11 only includes a plurality of transparent wirings and anode structures 4111 arranged in parallel, thereby improving the transmittance of the first display area 11. Fig. 12C As shown, Fig. 12C As shown, the plurality of transparent wires arranged in parallel include a connecting wire 60 and a dummy wire 601. For example, the dummy wire 601 has a break, so that the dummy wire 601 is a discontinuous wire. For example, by providing the dummy wire 601 with a break, the etching uniformity of the first display area 11 can be improved. It should be noted that Fig. 12C The line pointed by the arrow in the middle is the shading, not the actual routing.

[0201] It should be noted that Fig.11 and Figure 12A-12BThe first line portion 231 of the display substrate shown is not limited to being located in the peripheral area 14; the third line portion 241 is not limited to being arranged in parallel with the first display area 11 in the first direction D1, and is located at one end of the third display area 13 close to the first display area 11. In one example, the first line portion 231 and the third line portion 241 may both be located in the second display area 12, and the first line portion 231 is located on a side of the first display area 11 away from the third display area 13 in the first direction D1, and the third line portion 241 is located between the first display area 11 and the third display area 13 in the first direction D1. In another example, the first line portion 231 may be located in both the peripheral area 14 and the second display area 12, and the third line portion 241 may be located in both the third display area 13 and the second display area 12.

[0202] It should be noted that although Figure 4 , Figure 6 , Figure 8 , Fig.10 and Fig.11 The shape of the first display area 11 of the display substrate 01 shown is rectangular, but the embodiments of the present disclosure are not limited thereto. For example, according to actual application requirements, the shape of the first display area 11 can also be circular or other applicable shapes; correspondingly, the shape of the first winding portion 22 is adaptively changed. For example, the shape of the first winding portion 22 matches the shape of the first display area 11 to reduce the influence of the first winding portion 22 on the components located in the first display area 11 and the second display area 12. Figures 13A-13D An exemplary description is given.

[0203] Fig.13A yes Figure 2A A schematic plan view of a sixth example of the display substrate 01 shown in FIG. Fig. 13B yes Figure 2A Another schematic plan view of a sixth example of the display substrate 01 shown in FIG. Fig. 13C yes Figure 2A Another schematic plan view of a sixth example of the display substrate 01 is shown. Fig.13D is corresponding to Fig. 13C A schematic plan view of the partial region REG_B is shown.

[0204] It should be noted that, for the sake of clarity, Fig.13A Only part of the second display area 12 and part of the peripheral area 14 of the display substrate 01 are shown. Fig. 13B and Fig. 13C Only a portion of the first display area 11 , a portion of the second display area 12 , and a portion of the peripheral area 14 of the display substrate 01 are shown.

[0205] Figure 13A-13C The display substrate 01 shown is Figure 4 and Figure 5A-Figure 5C The display substrate 01 shown is similar, and only the differences between the two are described here, and the similarities are not repeated. Figure 13A-13C The display substrate 01 shown is Figure 4 and Figure 5A-Figure 5C The difference of the display substrate 01 shown is that Figure 13A-13C The display substrate 01 shown has different shapes of the first display region 11 and the first winding portion 22 .

[0206] like Figure 13A-13C As shown, the shape of the first display area 11 is a circle; the first winding portion 22 is an arc, the first end of the arc is connected to the end of the first sub-portion 211 close to the second sub-portion 212, and the second end of the arc is connected to the end of the second sub-portion 212 close to the first sub-portion 211. For example, the curvature of the arc matches (for example, is equal to) the curvature of the circle.

[0207] It should be noted that, according to actual application requirements, Figure 6 , Figure 8 , Fig.10 and Fig.11 The shape of the first display area 11 of the display substrate 01 is modified into a circle, and the shape of the first winding portion 22 is modified into an arc, which will not be described in detail here.

[0208] For example, Fig. 13C and Fig.13D As shown, the peripheral area 14 also includes a plurality of routing lines 2911 and a plurality of routing lines 2921; the plurality of routing lines 2911 are located in the electrode layer 291, and the plurality of routing lines 2921 are located in the electrode layer 292. For example, the electrode layer 291 and the electrode layer 292 are different electrode layers in a direction perpendicular to the display substrate. For example, the plurality of routing lines 2911 and the plurality of routing lines 2921 are alternately arranged in a direction perpendicular to the extension direction of the routing lines 2911. For example, by making the plurality of routing lines 2911 and the plurality of routing lines 2921 alternately arranged in a direction perpendicular to the extension direction of the routing lines 2911, and making the routing lines 2911 and the routing lines 2921 located in different electrode layers, the arrangement density of the routing lines (the routing lines 2911 and the routing lines 2921 as a whole) can be increased.

[0209] For example, the second sub-portion 212 of the first signal line 20 and the plurality of routing lines 2911 are located in different electrode layers, and the second sub-portion 212 of the first signal line 20 and the plurality of routing lines 2921 are located in different electrode layers. Figure 5H The gate electrode 4222 and the first capacitor plate 4225 are also shown located at the electrode layer 291; Figure 5H The second capacitor plate 4226 is also located on the electrode layer 292; the second sub-portion 212 of the first signal line 20 is connected to the Figure 5HThe source 4223 and the drain 4224 shown are located in the same electrode layer.

[0210] For example, Fig. 13C and Fig.13D As shown, the second sub-portion 212 of the first signal line 20 passing through the second pixel circuit 422 is electrically connected to the corresponding routing 2911 or the corresponding routing 2921 (for example, electrically connected via a via hole), thereby, the signal on the second sub-portion 212 of the first signal line 20 is transferred to the corresponding routing 2911 or the corresponding routing 2921. For example, the routing 2911 or the routing 2921 electrically connected to the second sub-portion 212 of the first signal line 20 is referred to as the first line portion 231. For example, by making the second sub-portion 212 of the first signal line 20 passing through the second pixel circuit 422 electrically connected to the corresponding routing 2911 or the corresponding routing 2921.

[0211] For example, the first signal line (located in the SD layer) coming out of each pixel unit will be switched to the Gat1 (electrode layer 291) or Gat2 layer (electrode layer 292). For example, if the lead line in the longitudinal direction and the lead line in the transverse direction cross each other, the lead line in the longitudinal direction (the second sub-portion 212 of the first signal line 20) uses the SD layer, because the distance between the SD layer and the Gat layer (electrode layer 291 or 292) is greater than the distance between the Gat1 (electrode layer 291) and the Gat2 layer (electrode layer 292), thereby reducing capacitive coupling.

[0212] It should be noted that although Figure 4 , Figure 6 , Figure 8 , Fig.10 , Fig.11 , Figure 13A-13C The second display area 12 of the display substrate 01 shown is rectangular in shape, but the embodiments of the present disclosure are not limited thereto. For example, according to actual application requirements, the second display area 12 can also be circular or other applicable shapes, which will not be described in detail here.

[0213] It should be noted that although Figure 4 , Figure 6 , Figure 8 , Fig.10 , Fig.11 , Figure 13A-13C The first signal line 20 of the display substrate 01 shown in the figure all uses two or more winding parts to wind the first signal line 20 to a position parallel to the first main body 21 (parallel in the second direction D2), but the embodiments of the present disclosure are not limited thereto. For example, according to actual application requirements, the first signal line 20 of the display substrate 01 can use only one winding part to wind the first signal line 20 to a position parallel to the first main body 21 (parallel in the second direction D2). Fig.14 An exemplary description is given.

[0214] Fig.14 yes Figure 2A A schematic plan view of a seventh example of the display substrate 01 is shown. Fig.14 The display substrate 01 shown is Figure 4 The display substrate 01 shown is similar, and only the differences between the two are described here, and the similarities are not repeated. Fig.14 The display substrate 01 shown is Figure 4 The differences of the display substrate 01 shown include: Fig.14 The display substrate 01 shown has only the first winding portion 22 but does not have the second winding portion 23 .

[0215] For example, Fig.14 As shown, the first winding portion 22 surrounds the first display area 11 and is entirely located in the second display area 12. Fig.14 As shown, the first winding portion 22 includes a fifth wire portion 271, a sixth wire portion 272 and a seventh wire portion 273 connected in sequence; the fifth wire portion 271 is electrically connected to the first sub-portion 211, and the seventh wire portion 273 is electrically connected to the second sub-portion 212; the sixth wire portion 272 extends along the first direction D1, and the fifth wire portion 271 and the seventh wire portion 273 extend along the second direction D2 intersecting the first direction D1; the sixth wire portion 272 and a virtual line extending along the first direction D1 between the first sub-portion 211 and the second sub-portion 212 are arranged in parallel in the first direction D1; the sixth wire portion 272 and the first pixel circuit 412 electrically connected to the sixth wire portion 272 at least partially overlap (or are located in the same column, closely adjacent but not overlapping); in operation, the current direction in the sixth wire portion 272 is the same as the current direction in the first main body portion 211. For example, the fifth wire portion 271, the sixth wire portion 272 and the seventh wire portion 273 are all straight line segments.

[0216] For example, the data driving circuit 50 can be implemented as a driving chip. For example, the driving chip can be bonded to the display substrate 01 via a flexible circuit board, and provide a data signal for display to multiple data lines via the flexible circuit to drive the display substrate 01 to realize the display function. For example, the peripheral area 14 can also be provided with a gate driving chip, or a gate driving circuit (GOA, not shown in the figure) on the array substrate is formed, and multiple output ends of the gate driving chip or GOA are respectively connected to multiple gate lines to provide gate scanning signals to the multiple gate lines. It should be noted that the display substrate 01 is not limited to being driven by a single data driving circuit. In some examples, the display substrate 01 can be driven by two data driving circuits, and the above two data driving circuits are located on both sides of the display substrate 01 (for example, on both sides of the display substrate 01 in the first direction D1).

[0217] Fig.15 yes Figure 2A A schematic plan view of an eighth example of the display substrate 01 shown in FIG. Fig.16 yes Figure 2A Another schematic plan view of the eighth example of the display substrate 01 is shown. It should be noted that, for the sake of clarity, Fig.15 Only the first display area 11 and part of the second display area 12 of the display substrate 01 are shown.

[0218] Fig.15 The display substrate 01 shown is Figure 4 The display substrate 01 shown is similar, and only the differences between the two are described here, and the similarities are not repeated. Fig.15 The display substrate 01 shown is Figure 4 The differences of the display substrate 01 shown include: Fig.15 The first direction D1 of the display substrate 01 shown is the row direction of the display panel; Fig.15 The connection line 60 of the display substrate 01 shown in FIG. 15 extends along the column direction; the first signal line 20 of the display substrate 01 shown in FIG. 15 is a gate line, and the second signal line 30 is a data line; Fig.15 The structures of the winding parts of the first signal line 20 and the second signal line 30 of the display substrate 01 are respectively similar to Fig.15 The first signal line 20 and the second signal line 30 of the display substrate 01 shown have different structures of the winding parts.

[0219] For example, Fig.15 As shown, the first winding portion 22 surrounds the first display area 11 and is located in the second display area 12 as a whole; the first winding portion 22 includes an eighth line portion 281 and a ninth line portion 282 connected in sequence; the eighth line portion 281 is electrically connected to the first main body portion 21 and extends along the second direction D2; the ninth line portion 282 extends along the first direction D1 and is arranged in parallel with the virtual extension line of the first main body portion 21 in the first direction D1; in operation, the current direction in the ninth line portion 282 is the same as the current direction in the main body; the ninth line portion 282 is electrically connected to the first pixel circuit 412 configured to drive the first number of first light-emitting elements 411 arranged in parallel along the first direction D1 in the first display area 11. For example, the eighth line portion 281 and the ninth line portion 282 are both straight line segments.

[0220] In some examples, the first main body portion 21 includes a first sub-portion 211 and a second sub-portion 212 (not shown in the figure), and the first winding portion 22 also includes a tenth wire portion (not shown in the figure), the first end of the tenth wire portion is connected to the ninth wire portion 282, the second end of the tenth wire portion is connected to the second sub-portion 212, and the tenth wire portion extends along the second direction D2.

[0221] For example, Fig.15As shown, the second signal line 30 includes a second main body 32, a fourth winding part 33 and a fifth winding part 34; the fourth winding part 33 deviates from the virtual extension line of the second main body 32 along the second direction D2 and is routed; the second main body 32 includes a third sub-part 321 and a fourth sub-part 322 separated by the first display area 11, and the third sub-part 321 and the fourth sub-part 322 are electrically connected via the fourth winding part 33; the fourth winding part 33 deviates from the virtual connection line extending along the second direction D2 between the third sub-part 321 and the fourth sub-part 322 and is routed. For example, at least a portion of the fourth winding part 33 extends in a direction intersecting the second direction D2. For example, at least a portion of the fifth winding part 34 extends in a direction intersecting the second direction D2. For example, the third sub-part 321 and the fourth sub-part 322 are both straight line segments.

[0222] For example, Fig.15 As shown, the fourth winding portion 33 includes a fourth line segment 331, a fifth line segment 332, and a sixth line segment 333 connected in sequence, the end of the fourth line segment 331 not connected to the fifth line segment 332 is connected to the end of the third sub-portion 321 close to the fourth sub-portion 322, the end of the sixth line segment 333 not connected to the fifth line segment 332 is connected to the end of the fourth sub-portion 322 close to the third sub-portion 321, the fourth line segment 331 and the sixth line segment 333 extend along the first direction D1, and the fifth line segment 332 extends along the second direction D2. For example, the fourth line segment 331, the fifth line segment 332, and the sixth line segment 333 are all straight line segments.

[0223] For example, Fig.15 As shown, the first end of the fifth winding portion 34 is electrically connected to the second sub-portion 212, and the second end of the fifth winding portion 34 is electrically connected to the corresponding first pixel circuit 412. Fig.15 As shown, the second end of the fifth winding portion 34 may be electrically connected to the first pixel circuits 412 in the same column (eg, the first pixel circuits 412 in the same column directly adjacent to the second line portion 232 of the second winding portion 23 ).

[0224] For example, Fig.15 As shown, the fifth winding portion 34 includes a seventh line segment 341 and an eighth line segment 342 connected in sequence, an end of the seventh line segment 341 not connected to the eighth line segment 342 serves as the first end of the fifth winding portion 34; an end of the eighth line segment 342 not connected to the seventh line segment 341 serves as the second end of the fifth winding portion 34; the seventh line segment 341 extends along the first direction D1; the eighth line segment 342 extends along the second direction D2 and is arranged in parallel with the second sub-portion 212 in the first direction D1; in operation, the current direction in the eighth line segment 342 is opposite to the current direction in the second sub-portion 212. For example, the seventh line segment 341 and the eighth line segment 342 are both straight line segments.

[0225] For example, Fig.15 As shown, the first light emitting element 411 and the first pixel circuit 412 for driving the first light emitting element 411 are located in adjacent columns of the display panel. Fig.15 As shown, at least one second signal line 30 is configured to drive the first light-emitting element 411 and the second light-emitting element 421 arranged in parallel along the second direction D2, that is, the first light-emitting element 411 and the third light-emitting element 431 driven by the same second signal line 30 are located in the same column of the display substrate 01.

[0226] It should be noted that, in some examples, the first light-emitting element 411 and the first pixel circuit 412 for driving the first light-emitting element 411 may also be located in the same column of the display panel, that is, the first light-emitting element 411 and the first pixel circuit 412 for driving the first light-emitting element 411 are arranged side by side in the column direction.

[0227] For example, Fig.15 As shown, the first direction D1 is the row direction of the display panel, and the second direction D2 is the column direction of the display panel; the first signal line 20 is the gate line, and the second signal line 30 is the data line.

[0228] It should be noted that Fig.15 The connecting wires 60 of the display substrate 01 shown extending in the column direction are not limited to being straight (ie, not limited to being straight line segments). In some examples, Fig.15 The connecting wire 60 of the display substrate 01 shown also includes a portion extending along the row direction.

[0229] For example, the source and drain, the first winding portion, and the second signal line are all located in the first electrode layer, and the first main body, the gate, and the first capacitor plate are located in the second electrode layer. For another example, the first winding portion and the second signal line are all located in the first electrode layer, and the first main body and the second capacitor plate of the storage capacitor are located in the second electrode layer.

[0230] Fig.16 and Fig.15 resemblance, Fig.16 More first signal lines 20 are shown, and Figure 6 The fifth winding portion 34 of the second signal line 30 is not shown and will not be described in detail herein.

[0231] Fig.17 The pixel circuit 921 provided by at least one embodiment of the present disclosure and the light-emitting element 920 driven by the pixel electrode. For example, at least one (for example, all) of the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 provided by at least one embodiment of the present disclosure can be implemented as Fig.17 The pixel circuit 921 is shown.

[0232] For example, Fig.17 As shown, the pixel circuit 921 also includes a first light emitting control circuit 923 and a second light emitting control circuit 924. The driving circuit 922 includes a control terminal, a first terminal, and a second terminal, and is configured to provide a driving current to the organic light emitting element 920 for driving the organic light emitting element 920 to emit light. For example, the first light emitting control circuit 923 is connected to the first terminal of the driving circuit 922 and the first voltage terminal VDD, and is configured to realize the connection between the driving circuit 922 and the first voltage terminal VDD is turned on or off, and the second light emitting control circuit 924 is electrically connected to the second terminal of the driving circuit 922 and the first electrode of the organic light emitting element 920, and is configured to realize the connection between the driving circuit 922 and the organic light emitting element 920 is turned on or off.

[0233] For example, Fig.17 As shown, the pixel circuit 921 further includes a data writing circuit 926, a storage circuit 927, a threshold compensation circuit 928 and a reset circuit 929. The data writing circuit 926 is electrically connected to the first terminal of the driving circuit 922, and is configured to write the data signal into the storage circuit 927 under the control of the scanning signal; the storage circuit 927 is electrically connected to the control terminal and the first voltage terminal VDD of the driving circuit 922, and is configured to store the data signal; the threshold compensation circuit 928 is electrically connected to the control terminal and the second terminal of the driving circuit 922, and is configured to perform threshold compensation on the driving circuit 922; the reset circuit 929 is electrically connected to the control terminal of the driving circuit 922 and the first electrode of the organic light emitting element 920, and is configured to reset the control terminal of the driving circuit 922 and the first electrode of the organic light emitting element 920 under the control of the reset control signal.

[0234] For example, Fig.17 As shown, the driving circuit 922 includes a driving transistor T1, a control end of the driving circuit 922 includes a gate of the driving transistor T1, a first end of the driving circuit 922 includes a first electrode of the driving transistor T1, and a second end of the driving circuit 922 includes a second electrode of the driving transistor T1.

[0235] For example, Fig.17 As shown, the data write circuit 926 includes a data write transistor T2, the storage circuit 927 includes a capacitor C, the threshold compensation circuit 928 includes a threshold compensation transistor T3, the first light-emitting control circuit 923 includes a first light-emitting control transistor T4, the second light-emitting control circuit 924 includes a second light-emitting control transistor T5, the reset circuit 929 includes a first reset transistor T6 and a second reset transistor T7, and the reset control signal may include a first sub-reset control signal and a second sub-reset control signal.

[0236] For example, Fig.17As shown, the first electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1, the second electrode of the data writing transistor T2 is configured to be electrically connected to the data line Vd to receive the data signal, and the gate of the data writing transistor T2 is configured to be electrically connected to the first scanning signal line Ga1 to receive the scanning signal; the first electrode of the capacitor C is electrically connected to the first power supply terminal VDD, and the second electrode of the capacitor C is electrically connected to the gate of the driving transistor T1; the first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the gate of the threshold compensation transistor T3 is configured to be electrically connected to the second scanning signal line Ga2 to receive the compensation control signal; the first electrode of the first reset transistor T6 is configured to be electrically connected to the first reset power supply terminal Vinit1 to receive the first reset signal, the second electrode of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1, and the gate of the first reset transistor T6 is configured to be electrically connected to the first reset control signal line Rst1 to receive the first sub-reset control signal; The first electrode of the reset transistor T7 is configured to be electrically connected to the second reset power supply terminal Vinit2 to receive the second reset signal, the second electrode of the second reset transistor T7 is electrically connected to the first electrode of the organic light emitting element 920, and the gate of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Rst2 to receive the second sub-reset control signal; the first electrode of the first light emitting control transistor T4 is electrically connected to the first power supply terminal VDD, the second electrode of the first light emitting control transistor T4 is electrically connected to the first electrode of the driving transistor T1, and the gate of the first light emitting control transistor T4 is configured to be electrically connected to the first light emitting control signal line EM1 to receive the first light emitting control signal; the first electrode of the second light emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the second light emitting control transistor T5 is electrically connected to the second electrode of the organic light emitting element 920, and the gate of the second light emitting control transistor T5 is configured to be electrically connected to the second light emitting control signal line EM2 to receive the second light emitting control signal; the first electrode of the organic light emitting element 920 is electrically connected to the second power supply terminal VSS.

[0237] For example, one of the first power supply terminal VDD and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal. Fig.17 In the illustrated embodiment, the first power supply terminal VDD is a voltage source to output a constant first voltage, the first voltage being a positive voltage, and the second power supply terminal VSS is a voltage source to output a constant second voltage, the second voltage being a negative voltage, etc. For example, in some examples, the second power supply terminal VSS may be grounded.

[0238] For example, Fig.17As shown, the scanning signal and the compensation control signal can be the same, that is, the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 can be electrically connected to the same signal line, such as the first scanning signal line Ga1, to receive the same signal (for example, scanning signal). In this case, the display substrate 1000 may not be provided with the second scanning signal line Ga2 to reduce the number of signal lines. For another example, the gate of the data writing transistor T2 and the gate of the threshold compensation transistor T3 can also be electrically connected to different signal lines, that is, the gate of the data writing transistor T2 is electrically connected to the first scanning signal line Ga1, and the gate of the threshold compensation transistor T3 is electrically connected to the second scanning signal line Ga2, and the signals transmitted by the first scanning signal line Ga1 and the second scanning signal line Ga2 are the same.

[0239] It should be noted that the scanning signal and the compensation control signal may also be different, so that the gate of the data writing transistor T2 and the threshold compensation transistor T3 can be controlled separately and independently, thereby increasing the flexibility of controlling the pixel circuit.

[0240] For example, Fig.17 As shown, the first light-emitting control signal and the second light-emitting control signal may be the same, that is, the gate of the first light-emitting control transistor T4 and the gate of the second light-emitting control transistor T5 may be electrically connected to the same signal line, such as the first light-emitting control signal line EM1, to receive the same signal (for example, the first light-emitting control signal). In this case, the display substrate 1000 may not be provided with the second light-emitting control signal line EM2, thereby reducing the number of signal lines. For another example, the gate of the first light-emitting control transistor T4 and the gate of the second light-emitting control transistor T5 may also be electrically connected to different signal lines, respectively, that is, the gate of the first light-emitting control transistor T4 is electrically connected to the first light-emitting control signal line EM1, and the gate of the second light-emitting control transistor T5 is electrically connected to the second light-emitting control signal line EM2, and the signals transmitted by the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 are the same.

[0241] It should be noted that when the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are transistors of different types, for example, the first light-emitting control transistor T4 is a P-type transistor and the second light-emitting control transistor T5 is an N-type transistor, the first light-emitting control signal and the second light-emitting control signal may also be different, and the embodiments of the present disclosure are not limited to this.

[0242] For example, the first sub-reset control signal and the second sub-reset control signal may be the same, that is, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may be electrically connected to the same signal line, such as the first reset control signal line Rst1, to receive the same signal (for example, the first sub-reset control signal). In this case, the display substrate 1000 may not be provided with the second reset control signal line Rst2, thereby reducing the number of signal lines. For another example, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 may also be electrically connected to different signal lines, that is, the gate of the first reset transistor T6 is electrically connected to the first reset control signal line Rst1, and the gate of the second reset transistor T7 is electrically connected to the second reset control signal line Rst2, and the signals transmitted by the first reset control signal line Rst1 and the second reset control signal line Rst2 are the same. It should be noted that the first sub-reset control signal and the second sub-reset control signal may also be different.

[0243] For example, in some examples, the second sub-reset control signal may be the same as the scan signal, that is, the gate of the second reset transistor T7 may be electrically connected to the first scan signal line Ga1 to receive the scan signal as the second sub-reset control signal.

[0244] For example, the gate of the first reset transistor T6 and the source of the second reset transistor T7 are connected to the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 respectively, and the first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be DC reference voltage terminals to output a constant DC reference voltage. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be the same, for example, the gate of the first reset transistor T6 and the source of the second reset transistor T7 are connected to the same reset power supply terminal. The first reset power supply terminal Vinit1 and the second reset power supply terminal Vinit2 can be high voltage terminals or low voltage terminals, as long as they can provide the first reset signal and the second reset signal to reset the gate of the driving transistor T1 and the first electrode of the light emitting element 920, and the present disclosure does not limit this.

[0245] It should be noted that Fig.17 The driving circuit 922, data writing circuit 926, storage circuit 927, threshold compensation circuit 928 and reset circuit 929 in the pixel circuit shown are only for illustration. The specific structures of the driving circuit 922, data writing circuit 926, storage circuit 927, threshold compensation circuit 928 and reset circuit 929 can be set according to actual application requirements, and the embodiments of the present disclosure do not specifically limit this.

[0246] For example, according to the characteristics of transistors, transistors can be divided into N-type transistors and P-type transistors. For the sake of clarity, the embodiments of the present disclosure take the transistor as a P-type transistor (for example, a P-type MOS transistor) as an example to elaborate on the technical solution of the present disclosure. That is to say, in the description of the present disclosure, the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6, and the second reset transistor T7 can all be P-type transistors. However, the transistors of the embodiments of the present disclosure are not limited to P-type transistors. Those skilled in the art can also use N-type transistors (for example, N-type MOS transistors) according to actual needs to implement the functions of one or more transistors in the embodiments of the present disclosure.

[0247] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics, and the thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polycrystalline silicon thin film transistors, etc. The source and drain of the transistor may be symmetrical in structure, so the source and drain may be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is directly described as the second electrode, so the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0248] It should be noted that the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 provided in at least one embodiment of the present disclosure are not limited to being implemented as a pixel circuit including seven transistors and one capacitor (that is, not limited to Fig.17 The first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 provided in at least one embodiment of the present disclosure may include an applicable number of transistors and an applicable number of capacitors. For example, according to actual application requirements, the first pixel circuit 412, the second pixel circuit 422, and the third pixel circuit 432 provided in at least one embodiment of the present disclosure may be a 7T2C pixel circuit, a 6T1C pixel circuit, a 6T2C pixel circuit, or a 9T2C pixel circuit.

[0249] Fig.18 yes Fig.17 The 7T1C pixel circuit includes a first transistor T1 to a seventh transistor T7, and the positions of the first transistor T1 to the seventh transistor T7 are as shown in FIG. Fig.18 As shown, no further description is given here.

[0250] Fig.19 is a schematic diagram showing the structure of a sub-pixel according to an embodiment of the present disclosure. Figure 20-23Schematic diagrams respectively illustrate the layout of a certain layer in a sub-pixel according to some embodiments of the present disclosure. Fig. 20 is a schematic plan view showing an LTPS layer (low temperature polysilicon layer) of a sub-pixel according to an embodiment of the present disclosure; Fig.21 is a schematic plan view showing an SD layer (source-drain electrode layer) of a sub-pixel according to an embodiment of the present disclosure; Fig. 22 is a schematic plan view showing a Gat1 layer (first gate layer) of a sub-pixel according to an embodiment of the present disclosure; Fig.23 is a schematic plan view showing a Gat2 layer (second gate layer) of a sub-pixel according to an embodiment of the present disclosure. Fig.24 FIG. 1 is a diagram showing a sub-pixel according to an embodiment of the present disclosure. Fig. 20 , Fig. 22 and Fig.23 Schematic diagram of the layout of the layer stackup shown. Fig.25 FIG. 1 is a diagram showing a sub-pixel according to an embodiment of the present disclosure. Figure 20 to Figure 23 Schematic diagram of the layout of layer stacking shown in FIG. For example, the LTPS layer (low temperature polysilicon layer), Gat1 layer (first gate layer), Gat2 layer (second gate layer) and SD layer (source-drain electrode layer) are arranged in sequence from bottom to top in a direction perpendicular to the sub-pixel. The data line of the SD layer (source-drain electrode layer) is led out and then switched to the Gat1 layer (first gate layer) and Gat2 layer (second gate layer).

[0251] like Fig.19 As shown, the sub-pixel may include a light-emitting element D, a first transistor T1, a capacitor C, a second transistor T2, and a third transistor T3. The light-emitting element D includes an anode D1 and a cathode D2. In some implementations, the light-emitting element D may be an OLED. Here, the first transistor T1 may also be referred to as a switch transistor, the second transistor T2 may also be referred to as a drive transistor, and the third transistor T3 may also be referred to as a reset transistor.

[0252] The first transistor T1 is configured to respond to the scan signal of the gate line Gat, and transmit the data signal from the data line Dat to the second transistor T2 when it is turned on. The second transistor T2 is configured to transmit the driving current Id to the light emitting element D when it is turned on, so as to drive the light emitting element D to emit light. The third transistor T3 is configured to respond to the reset signal of the reset line Rese, and reset the voltage of the gate G2 of the second transistor T2 to the voltage of the initialization voltage line Vinit when it is turned on.

[0253] In various embodiments, Fig.19As shown, the sub-pixel may also include one or more of a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7. Here, the fourth transistor T4 may also be referred to as a compensation transistor, the fifth transistor T5 may also be referred to as a drive control transistor, the sixth transistor T6 may also be referred to as an emission control transistor, and the seventh transistor T7 may also be referred to as a bypass transistor. For example, the fourth transistor T4 is configured to respond to a scan signal of the scan line Gat, and when it is turned on, the second transistor T2 is in a diode connection state. For example, the fifth transistor T5 and the sixth transistor T6 are configured to respond to a control signal of the control line EM, and when they are turned on, the emission current Id flows to the light-emitting element D. For example, the seventh transistor T7 is configured to respond to a reset signal of the reset line Rese, and when it is turned on, a portion of the drive current Id flows as a bypass current Ibp. It should be noted that although Fig.19 The third gate G3 of the third transistor T3 and the seventh gate G7 of the seventh transistor T7 are both connected to the same reset line Rese. However, this is not restrictive. For example, in some embodiments, the seventh gate G7 of the seventh transistor T7 can be connected to another reset line different from the reset line Rese.

[0254] In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all P-channel thin film transistors. In other embodiments, one or more of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be N-channel thin film transistors.

[0255] For example, the active layer of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be as follows: Fig. 20 As shown. The material of the active layer may include polysilicon, such as low temperature polysilicon, etc. The active layer of each transistor includes two electrode regions and a channel region located between the two electrode regions. Here, one of the two electrode regions is a source region and the other is a drain region. It should be understood that the doping concentration in the two electrode regions is greater than the doping concentration in the channel region. In other words, each of the two electrode regions is a conductor region, and the channel region is a semiconductor region.

[0256] See also Fig.19 and Fig. 20 , the first transistor T1 includes a first active layer ACT1 and a first gate G1 connected to a scan line Gat. In some embodiments, the scan line Gat and the first gate G1 may be integrally provided. Fig. 20As shown, the first active layer ACT1 includes a first electrode region ACT11, a second electrode region ACT12, and a first channel region ACT13 located between the first electrode region and the second electrode region. Here, the first electrode region ACT11 is connected to the data line Dat, and the second electrode region ACT12 is connected to the power line VDD. For example, the first electrode region ACT11 can be connected to the data line Dat via Fig.25 The via hole V1 shown is connected to the data line Dat. In some embodiments, the second electrode region ACT12 can be connected to the power line VDD via the fifth active layer ACT5 of the fifth transistor T5. For example, the fifth active layer ACT5 can be connected via Fig.25 The via V2 shown is connected to the power supply line VDD. In some embodiments, see Fig.21 , the data line Dat and the power line VDD can be located on the same layer.

[0257] It should be noted that, in this article, two components are located in the same layer means that the two components are formed by the same patterning process, that is, by patterning the same material layer once; or, the two components are located on the same film layer and are in direct contact with the film layer.

[0258] The capacitor C includes a first electrode plate C1 and a second electrode plate C2 connected to a power line VDD. For example, the second electrode plate C2 may be connected to a power line VDD via Fig.25 Via V3 is shown connected to the power supply line VDD.

[0259] The second transistor T2 includes a second active layer ACT2 and a second gate G2 connected to the first electrode plate C1. In some embodiments, the first electrode plate C1 and the second gate G2 may be integrally provided. Fig. 20 As shown, the second active layer ACT2 includes a third electrode region ACT21, a fourth electrode region ACT22, and a second channel region ACT23 located between the third electrode region ACT21 and the fourth electrode region ACT22. The third electrode region ACT21 is connected to the second electrode region ACT12, and the fourth electrode region ACT22 is connected to the anode D1. In some embodiments, the third electrode region ACT21 and the second electrode region ACT12 can be integrally provided. In some embodiments, the third electrode region ACT21 can be connected to the power supply line VDD via the fifth active layer ACT5 of the fifth transistor T5.

[0260] The third transistor T3 includes a third active layer ACT3 and a third gate G3 connected to a reset line Rese. In some embodiments, the reset line Rese and the third gate G3 may be integrally provided. Fig. 20As shown, the third active layer ACT3 includes a fifth electrode region ACT31, a sixth electrode region ACT32, and a third channel region ACT33 located between the fifth electrode region ACT31 and the sixth electrode region ACT32. The fifth electrode region ACT31 is connected to the first electrode plate C1, and the sixth electrode region ACT32 is connected to the initialization voltage line Vinit. For example, the fifth electrode region ACT31 can be connected to the first electrode plate C1 via the first electrode plate C1. Fig.25 The via V4 shown is connected to the first connector CT1, and the first electrode plate C1 can be connected to the first connector CT1. Fig.25 The via V5 shown is connected to the first connection member CT1. For example, the sixth electrode area ACT32 can be connected via Fig.25 The via V6 shown is connected to the second connection member CT2, and the initialization voltage line Vinit can be connected via Fig.25 The via V7 is shown connected to the second connector CT2. Fig.21 , the first connector CT1, the second connector CT2, the data line Dat and the power line VDD may be located on the same layer. Fig. 22 , the scan line Gat, the first electrode plate C1 and the reset line Rese may be located in the same layer. Fig.23 , the second electrode plate C2 and the initialization voltage line Vinit may be located on the same layer.

[0261] See also Fig. 20 and Fig.24 The first channel region ACT13 may be a region where the first active layer ACT1 overlaps with the scan line Gat, the second channel region ACT23 may be a region where the second active layer ACT2 overlaps with the first electrode plate C1, the third channel region ACT33 may be a region where the third active layer ACT3 overlaps with the reset line Rese, and the fourth channel region ACT43 may be a region where the fourth active layer ACT4 overlaps with the scan line Gat.

[0262] See also Fig.19 and Fig. 20 The light emitting element D includes an anode D1 and a cathode D2. The first transistor T1 includes a first active layer ACT1 and a first gate G1 connected to a scan line Gat. The first active layer ACT1 includes a first electrode region ACT11, a second electrode region ACT12, and a first channel region ACT13 located between the first electrode region and the second electrode region. The first electrode region ACT11 is connected to a data line Dat, and the second electrode region ACT12 is connected to a power line VDD.

[0263] The capacitor C includes a first electrode plate C1 and a second electrode plate C2 connected to a power supply line VDD. The second transistor T2 includes a second active layer ACT2 and a second gate G2 connected to the first electrode plate C1, the second active layer ACT2 includes a third electrode region ACT21, a fourth electrode region ACT22, and a second channel region ACT23 located between the third electrode region ACT21 and the fourth electrode region ACT22, the third electrode region ACT21 is connected to the second electrode region ACT12, and the fourth electrode region ACT22 is connected to the anode D1.

[0264] The third transistor T3 includes a third active layer ACT3 and a third gate G3 connected to a reset line Rese, the third active layer ACT3 includes a fifth electrode region ACT31, a sixth electrode region ACT32, and a third channel region ACT33 located between the fifth electrode region ACT31 and the sixth electrode region ACT32, the fifth electrode region ACT31 is connected to the first electrode plate C1, and the sixth electrode region ACT32 is connected to the initialization voltage line Vinit.

[0265] Combine the following Fig.19 and Fig. 20 The fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 are introduced.

[0266] The fourth transistor T4 includes a fourth active layer ACT4 and a fourth gate G4 connected to the scan line Gat. In some embodiments, the scan line Gat and the fourth gate G4 may be integrally provided. Fig. 20 As shown, the fourth active layer ACT4 includes a seventh electrode region ACT41, an eighth electrode region ACT42, and a fourth channel region ACT43 located between the seventh electrode region ACT41 and the eighth electrode region ACT42. The seventh electrode region ACT41 is connected to the second gate G2, and the eighth electrode region ACT42 is connected to the fourth electrode region ACT22. For example, the seventh electrode region ACT41 can be connected to the second gate G2 via Fig.25 The via V4 shown is connected to the first connection member CT1, and the second gate G2 can be connected to the first connection member CT1. Fig.25 The via V5 shown is connected to the first connector CT1. In some embodiments, the seventh electrode region ACT41 and the fifth electrode region ACT31 can be integrally provided. In some embodiments, the eighth electrode region ACT42 and the fourth electrode region ACT22 can be integrally provided. In some embodiments, the fourth channel region ACT43 can include two spaced-apart portions, that is, the fourth gate G4 can include two gates.

[0267] The fifth transistor T5 includes a fifth active layer ACT5 and a fifth gate G5 connected to the control line EM. Fig. 20As shown, the fifth active layer ACT5 includes a ninth electrode region ACT51, a tenth electrode region ACT52, and a fifth channel region ACT53 located between the ninth electrode region ACT51 and the tenth electrode region ACT52. The ninth electrode region ACT51 is connected to the power line VDD, and the tenth electrode region ACT52 is connected to the second electrode region ACT12. For example, the ninth electrode region ACT51 can be connected to the power line VDD via Fig.25 The via V2 shown is connected to the power line VDD. For example, the tenth electrode area ACT52 can be connected to the second electrode area ACT12 via the third electrode area ACT21. In some embodiments, see Fig. 22 , the control line EM, the scan line Gat, the first electrode plate C1 and the reset line Rese may be located in the same layer.

[0268] The sixth transistor T6 includes a sixth active layer ACT6 and a sixth gate G6 connected to the control line EM. Fig. 20 As shown, the sixth active layer ACT6 includes an eleventh electrode region ACT61, a twelfth electrode region ACT62, and a sixth channel region ACT63 located between the eleventh electrode region ACT61 and the twelfth electrode region ACT62. The eleventh electrode region ACT61 is connected to the fourth electrode region ACT22, and the twelfth electrode region ACT62 is connected to the anode D1. In some embodiments, the eleventh electrode region ACT61 and the fourth electrode region ACT22 can be integrally provided. In some embodiments, the twelfth electrode region ACT62 can be connected to the anode D1 via Fig.25 The via V8 shown is connected to a conductive layer M (eg, a metal layer), which may be connected to the anode D1 via other vias. Fig.21 , the conductive layer M, the first connector CT1, the second connector CT2, the data line Dat and the power line VDD may be located on the same layer.

[0269] The seventh transistor T7 includes a seventh active layer ACT7 and a seventh gate G7 connected to a reset line Rese. In some embodiments, the reset line Rese and the seventh gate G7 may be integrally provided. Fig. 20 As shown, the seventh active layer ACT7 includes a thirteenth electrode region ACT71, a fourteenth electrode region ACT72, and a seventh channel region ACT73 located between the thirteenth electrode region ACT71 and the fourteenth electrode region ACT72. The thirteenth electrode region ACT71 is connected to the twelfth electrode region ACT62, and the fourteenth electrode region ACT72 is connected to the initialization voltage line Vinit. For example, the fourteenth electrode region ACT72 can be connected via Fig.25 The via V6 shown is connected to the second connection member CT2, and the initialization voltage line Vinit can be connected via Fig.25The via V7 is shown to be connected to the second connector CT2. In some embodiments, the fourteenth electrode area ACT72 and the sixth electrode area ACT32 may be integrally provided.

[0270] See also Fig. 20 and Fig.24 The fifth channel region ACT53 may be a region where the fifth active layer ACT5 overlaps with the control line EM, the sixth channel region ACT63 may be a region where the sixth active layer ACT6 overlaps with the control line EM, and the seventh channel region ACT73 may be a region where the seventh active layer ACT7 overlaps with the reset line.

[0271] In some embodiments, see Fig. 20 , the first active layer ACT1 , the second active layer ACT2 , the third active layer ACT3 , the fourth active layer ACT4 , the fifth active layer ACT5 , the sixth active layer ACT6 , and the seventh active layer ACT7 may be located on the same layer.

[0272] The following describes a driving method of a sub-pixel according to some embodiments of the present disclosure. It should be noted that in the following description, it is assumed that the sub-pixel includes T1, T2, T3, T4, T5, T6 and T7, and the transistors T1, T2, T3, T4, T5, T6 and T7 are all P-channel transistors.

[0273] In the reset phase, the third transistor T3 is turned on in response to the reset signal of the reset line Rese, and the second gate G2 of the second transistor T2 is connected to the initialization voltage line Vinit via the third transistor T3. Thus, the voltage of the second gate G2 of the driving transistor T1 is reset to the voltage of the initialization voltage line Vinit.

[0274] In the compensation phase, the first transistor T1 and the fourth transistor T4 are turned on in response to the scan signal of the scan line Gat. In this case, the second transistor T2 is in a diode connection state and is in a forward bias. The voltage of the second gate G2 of the second transistor T2 is the sum of the voltage Vdata of the data signal from the data line Dat and the threshold voltage Vth (negative number) of the second transistor T2, that is, Vdata+Vth. At this time, the voltage of the first electrode plate C1 of the capacitor Cst is Vdata+Vth, and the voltage of the second electrode plate C2 of the capacitor Cst is the voltage ELVDD of the power line VDD. The capacitor Cst is charged with a charge corresponding to the voltage difference between the first electrode plate C1 and the second electrode plate C2.

[0275] In the light emitting stage, the fifth transistor T5 and the sixth transistor T6 are turned on in response to the control signal of the control line EM. In response to the voltage difference between the voltage of the second gate G2 of the second transistor T2 and the voltage of the power line VDD, a driving current Id is generated, and the driving current Id is supplied to the light emitting element D through the sixth transistor T6. In the light emitting stage, the gate-source voltage Vgs of the second transistor T2 is maintained at (Vdata+Vth)-ELVDD. The driving current Id is proportional to (Vdata-ELVDD). 2 Therefore, the driving current Id has nothing to do with the threshold voltage Vth of the first transistor T1.

[0276] In addition, in the reset phase, the seventh transistor T7 is turned on in response to the reset signal of the reset line Rese. In addition, the seventh transistor T7 can be turned on at the same time as the first transistor T1 and the fourth transistor T4. In order to prevent the driving current Id from driving the light-emitting element D to emit light when the second transistor T2 is turned off, a part of the driving current Id can flow out through the seventh transistor T7 as a bypass current Ibp.

[0277] It should be noted that applicable components can be used for other components of the display substrate 01 and the display device 03 (for example, image data encoding / decoding device, clock circuit, etc.), which should be understood by ordinary technicians in this field and will not be elaborated here, nor should they be regarded as limitations on the present disclosure.

[0278] At least one embodiment of the present disclosure further provides a display device, which includes any display substrate of the present disclosure. The display device can be implemented as any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0279] Although the disclosure has been described in detail above with general descriptions and specific implementation methods, it is obvious to those skilled in the art that some modifications or improvements may be made to the embodiments of the disclosure. Therefore, these modifications or improvements made without departing from the spirit of the disclosure are within the scope of protection claimed by the disclosure.

[0280] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: A substrate, comprising a display area and a peripheral area at least partially surrounding the display area, wherein the display area comprises a first display area, a second display area and a third display area, the second display area surrounds the first display area, and the third display area at least partially surrounds the second display area; A plurality of first pixel units, including a plurality of first light-emitting elements located in the first display area and a plurality of first pixel circuits located in the second display area, wherein the first pixel circuits and the corresponding first light-emitting elements are electrically connected via connecting wires, the first pixel circuits are configured to drive the corresponding first light-emitting elements, and the orthographic projections of the plurality of first pixel circuits on the substrate substrate do not overlap with the orthographic projections of the plurality of first light-emitting elements on the substrate substrate; A plurality of third pixel units are located in the third display area, wherein each of the third pixel units comprises a third light-emitting element and a third pixel circuit, the third pixel circuit is configured to drive the corresponding third light-emitting element, and the orthographic projection of the third pixel circuit on the substrate overlaps with the orthographic projection of the corresponding third light-emitting element on the substrate; At least one first signal line is located at least in the second display area and the third display area, wherein the first signal line includes a first main body, a first winding portion and a second winding portion, the first main body includes a first sub-portion and a second sub-portion respectively located on opposite sides of the first display area, the first winding portion is located in the second display area and is electrically connected to the first sub-portion and the second sub-portion respectively, the second winding portion is located in at least one of the second display area and the peripheral area and is electrically connected to the first main body, and the second winding portion is electrically connected to the corresponding first pixel circuit.

2. The display substrate according to claim 1, wherein: The first winding portion includes a first line segment, a second line segment and a third line segment connected in sequence, The end of the first line segment not connected to the second line segment is connected to the end of the first sub-portion close to the second sub-portion, the end of the third line segment not connected to the second line segment is connected to the end of the second sub-portion close to the first sub-portion, the second line segment extends along a first direction, and the first line segment and the third line segment extend along a second direction intersecting the first direction.

3. The display substrate according to claim 2, wherein: The at least one first signal line is also located in the peripheral area, and the second winding portion includes a first line portion and a second line portion connected in sequence. The first line portion is located in the peripheral area and extends along the second direction, and the second line portion extends from the peripheral area to the second display area along the first direction and is electrically connected to the first pixel circuit.

4. The display substrate according to claim 2, wherein: The second winding portion includes a first wire portion and a second wire portion connected in sequence, The first line portion and the second line portion are both located in the second display area, the first line portion extends along the second direction, and the second line portion extends along the first direction and is electrically connected to the first pixel circuit.

5. The display substrate according to claim 2, wherein: The at least one first signal line is also located in the peripheral area, and the second winding portion includes a first line portion and a second line portion connected in sequence. The first line portion extends along the second direction, and the second line portion extends along the first direction and is electrically connected to the first pixel circuit. At least a portion of the first line portion is located in the peripheral area, and at least another portion of the first line portion is located in the second display area. At least a portion of the second line portion is located in the peripheral area, and at least another portion of the second line portion is located in the second display area.

6. The display substrate according to claim 1, wherein: The plurality of first light emitting elements correspond to the plurality of first pixel circuits one by one, and each first pixel circuit is configured to drive a corresponding first light emitting element.

7. The display substrate according to claim 1, further comprising a plurality of second pixel units, in, The plurality of second pixel units are located in the second display area and include a plurality of second light emitting elements and a plurality of second pixel circuits, wherein the second pixel circuits are configured to drive corresponding second light emitting elements, and the orthographic projections of the second pixel circuits on the substrate overlap with the orthographic projections of the corresponding second light emitting elements on the substrate; The plurality of first pixel circuits are located in gaps between the plurality of second pixel circuits, and the plurality of first pixel circuits and the plurality of second pixel circuits are arranged alternately.

8. The display substrate according to claim 7, wherein: Some of the multiple second pixel circuits are located in the second display areas on opposite sides of the first display area, and the first sub-portion and the second sub-portion are electrically connected to the second pixel circuits located on opposite sides of the first display area, respectively.

9. The display substrate according to claim 7, wherein: A distribution density per unit area of ​​the plurality of first light emitting elements located in the first display area is smaller than a distribution density per unit area of ​​the plurality of second light emitting elements located in the second display area.

10. The display substrate according to claim 2, further comprising at least one second signal line, in, The at least one second signal line comprises a second main body portion, and the second main body portion extends along the second direction; A virtual extension line of the first main body extending along the first direction and a virtual extension line of the second main body extending along the second direction intersect within the first display area; as well as The second main body of the at least one second signal line is electrically connected to at least one of the first pixel circuits to provide the first pixel circuit with a second driving signal different from the first driving signal provided by the first signal line.

11. The display substrate according to claim 1, wherein: The first winding portion is an arc, a first end of the arc is connected to an end of the first sub-portion close to the second sub-portion, and a second end of the arc is connected to an end of the second sub-portion close to the first sub-portion.

12. The display substrate according to claim 1, wherein: The at least one first signal line further includes a third winding portion, Among them, the first end of the third winding part is electrically connected to the first sub-part, the second end of the third winding part is electrically connected to the corresponding first pixel circuit, and the first pixel circuit connected to the second winding part is different from the first pixel circuit connected to the third winding part.

13. The display substrate according to claim 12, wherein: The third winding portion includes a third wire portion and a fourth wire portion connected in sequence; One end of the third wire portion not connected to the fourth wire portion serves as the first end of the third winding portion, and one end of the fourth wire portion not connected to the third wire portion serves as the second end of the third winding portion; The third line portion extends along the second direction and is arranged in parallel with the first line portion in the first direction; The fourth line portion extends along the first direction and is arranged in parallel with the first sub-portion in the second direction.

14. The display substrate according to claim 3, wherein: The first main body portion, the first winding portion and the second wire portion are located on a first electrode layer of the display substrate; The first line portion is located on the second electrode layer of the display substrate; The first electrode layer and the second electrode layer are overlapped in a normal direction of a display surface of the display substrate; as well as The first line portion is electrically connected to the second sub-portion and the second line portion through a first via hole and a second via hole of an insulating layer located between the first electrode layer and the second electrode layer, respectively.

15. The display substrate according to claim 14, wherein: Each of the at least one first pixel circuit comprises a thin film transistor; The thin film transistor comprises a gate, a source and a drain; as well as The source electrode and the drain electrode are located in the first electrode layer, and the gate electrode is located in the second electrode layer.

16. The display substrate according to claim 10, wherein: The at least one second signal line further includes a fourth winding portion, and the fourth winding portion deviates from a virtual extension line of the second main body portion along the second direction and is routed; The second main body portion includes a third sub-portion and a fourth sub-portion separated by the first display area, the third sub-portion and the fourth sub-portion being electrically connected via the fourth winding portion; and The fourth winding portion is routed away from a virtual line extending along the second direction and located between the third sub-portion and the fourth sub-portion.

17. The display substrate according to claim 16, wherein: Each of the at least one first pixel circuit includes a thin film transistor, wherein the thin film transistor includes a gate, a source, and a drain; as well as The source electrode, the drain electrode, the first winding portion, and the second signal line are all located on a first electrode layer of the display substrate, and the first main body portion and the gate electrode are located on a second electrode layer of the display substrate.

18. The display substrate according to claim 1, wherein: The portion of the connecting wire located in the first display area is a transparent wire.

19. A display device comprising the display substrate according to claim 1.

20. The display device according to claim 19, further comprising a sensor, wherein: The sensor is disposed on a non-display side of the display substrate, overlapped with the first display area in a normal direction of a display surface of the display substrate, and configured to receive and process an optical signal passing through the first display area.

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