Display panel, display device and crack detection method

Abstract

A display panel includes a substrate (10), a plurality of sub-pixels (PX), a plurality of data lines (DL), first detection lines (31a, 31b), and first detection control units (33a, 33b). The first detection control unit (33a, 33b) is electrically connected to the first detection line (31a, 31b) and is configured to provide a first test signal to the first detection line (31a, 31b). The first detection lines (31a, 31b) are electrically connected to the plurality of sub-pixels (PX) in the display area (AA) by either: the first detection lines (31a, 31b) are electrically connected to the anodes of the light-emitting elements (62) of the plurality of sub-pixels in the display area (AA); the first detection lines (31a, 31b) are electrically connected to sources of data writing transistors of pixel circuits (61) of a plurality of sub-pixels in a display area (AA). The first detection lines (31a, 31b) are electrically connected to a plurality of data lines (DL) of the display area (AA), and the data lines (DL) are electrically connected to a plurality of sub-pixels arranged in the first direction (X).

Description

Display panel, display device, and crack detection method Technical Field

[0001] This article relates to the field of display technology, and in particular to a display panel, a display device, and a crack detection method. Background Art

[0002] A detection module or circuit is usually set up around the periphery of the display panel to detect whether there are crack defects in the periphery (edge ​​area) of the display panel during production and transportation. Currently, the following two detection methods are commonly used: eddy current detection (ET detection) and resistance detection. Eddy current detection uses the panel crack detection (PCD) circuit to detect whether there are bright lines on the screen to determine whether there are cracks around the panel; resistance detection detects the resistance between the PCD circuits, and determines whether there are cracks by whether the resistance value is abnormal. However, the above detection methods can only detect whether there are crack defects in the edge area, and cannot accurately locate the position of the defect. For example, for large-size display panels, staff need to use a microscope to slowly search for the crack location in the entire edge area of ​​the display panel, which will consume a lot of staff time and energy, resulting in extremely low work efficiency.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display panel, a display device, and a crack detection method.

[0006] On the one hand, this embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels and a plurality of data lines, at least one first detection line and at least one first detection control unit. The substrate comprises a display area and a peripheral area located outside the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area, the plurality of sub-pixels and the plurality of data lines are electrically connected, and at least one of the plurality of sub-pixels comprises: a pixel circuit and a light-emitting element, the pixel circuit and the light-emitting element are electrically connected and configured to drive the light-emitting element to emit light. The at least one first detection line and the at least one first detection control unit are located in the peripheral area, the at least one first detection control unit is electrically connected to the at least one first detection line and is configured to provide a first test signal to the at least one first detection line. At least one first detection line is electrically connected to a plurality of sub-pixels in the display area in any of the following ways: at least one first detection line is electrically connected to anodes of light-emitting elements of a plurality of sub-pixels in the display area; at least one first detection line is electrically connected to sources of data writing transistors of pixel circuits of a plurality of sub-pixels in the display area; at least one first detection line is electrically connected to a plurality of data lines in the display area, wherein at least one of the plurality of data lines is electrically connected to a plurality of sub-pixels arranged along a first direction, and at least one first detection line is located at least in peripheral areas on opposite sides of the display area along the first direction.

[0007] In some exemplary embodiments, the at least one first detection line includes: a first main line and a plurality of first sub-lines electrically connected to the first main line, each first sub-line electrically connected to at least one sub-pixel of the display area; the plurality of first sub-lines are arranged in sequence along the extension direction of the first main line.

[0008] In some exemplary embodiments, a gate driving circuit is further provided in the peripheral area. The first main line is located on a side of the gate driving circuit close to the display area, and a portion of each first sub-line is located on a side of the gate driving circuit away from the display area.

[0009] In some exemplary embodiments, a gate driving circuit is further provided in the peripheral area. The first main line is located on a side of the gate driving circuit away from the display area, and the plurality of first sub-lines are located on a side of the first main line close to the display area.

[0010] In some exemplary embodiments, the plurality of sub-pixels electrically connected to the plurality of first sub-lines of the first detection line include: a plurality of sub-pixels in the display area that are closest to the first main line and arranged along an extension direction of the first main line.

[0011] In some exemplary embodiments, each first sub-line includes at least: a first line segment, a second line segment, and a first cross-line, wherein both ends of the first cross-line are electrically connected to the first line segment and the second line segment, respectively, the first line segment is located on a side of the gate drive circuit away from the display area, the second line segment is located on a side of the gate drive circuit close to the display area, and the orthographic projection of the first cross-line on the substrate at least partially overlaps with the orthographic projection of the gate drive circuit on the substrate; the first cross-line is located on a side of the first line segment and the second line segment close to the substrate.

[0012] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes at least: a substrate, and a bottom light-shielding metal layer, a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate. The first crossover line is located in the bottom light-shielding metal layer, and the first line segment and the second line segment are located in the first gate metal layer.

[0013] In some exemplary embodiments, the at least one first detection control unit includes: a first detection transistor, a gate of the first detection transistor is electrically connected to a first detection control line, a first electrode of the first detection transistor is electrically connected to a first test signal transmission line, and a second electrode of the first detection transistor is electrically connected to the first detection line.

[0014] In some exemplary embodiments, the display panel further includes: a second detection line located in the peripheral area and at least one second detection control unit; the at least one second detection control unit is electrically connected to the second detection line and configured to provide a second test signal to the second detection line. The second detection line is electrically connected to the plurality of sub-pixels in the display area. The connection between the second detection line and the plurality of sub-pixels in the display area is different from the connection between the first detection line and the plurality of sub-pixels in the display area.

[0015] In some exemplary embodiments, the second detection line includes: a second main line and a plurality of second sub-lines electrically connected to the second main line; each second sub-line is electrically connected to at least one sub-pixel in the display area, and the plurality of second sub-lines are sequentially arranged along an extension direction of the second main line. The extension direction of the second main line intersects an extension direction of a first main line of the first detection line.

[0016] In some exemplary embodiments, the plurality of first sub-lines of the at least one first detection line are electrically connected to anodes of light-emitting elements of the plurality of sub-pixels in the display area in a one-to-one correspondence, and the plurality of second sub-lines of the second detection line are electrically connected to sources of data writing transistors of pixel circuits of the plurality of sub-pixels in the display area in a one-to-one correspondence.

[0017] In some exemplary embodiments, the plurality of first sub-lines of the at least one first detection line are electrically connected to a plurality of data lines of the display area in a one-to-one correspondence, and the plurality of data lines extend along the first direction. The plurality of second sub-lines of the second detection line are electrically connected to a plurality of first power lines of the display area in a one-to-one correspondence, and the plurality of first power lines extend along a second direction that intersects the first direction.

[0018] In some exemplary embodiments, the peripheral area is further provided with a first power border line, the second main line is located on a side of the first power border line close to the display area, and a portion of each second sub-line is located on a side of the first power border line away from the display area.

[0019] In some exemplary embodiments, the peripheral area is further provided with a first power border line, the second main line is located on a side of the first power border line away from the display area, and the plurality of second sub-lines are located on a side of the second main line close to the display area.

[0020] In some exemplary embodiments, the plurality of sub-pixels electrically connected to the plurality of second sub-lines of the second detection line include: a plurality of sub-pixels in the display area that are closest to the second main line and arranged along an extending direction of the second main line.

[0021] In some exemplary embodiments, each second sub-line includes at least: a third line segment, a fourth line segment and a third cross-line, wherein both ends of the third cross-line are electrically connected to the third line segment and the fourth line segment respectively, the third line segment is located on the side of the first power border line away from the display area, the fourth line segment is located on the side of the first power border line close to the display area, and the orthographic projection of the third cross-line on the substrate at least partially overlaps with the orthographic projection of the first power border line on the substrate; the third cross-line is located on the side of the third line segment and the fourth line segment close to the substrate.

[0022] In some exemplary embodiments, in a direction perpendicular to the display panel, the display panel includes at least: a substrate, and a bottom light-shielding metal layer, a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer disposed on the substrate. The third crossover is located in the bottom light-shielding metal layer, and the third and fourth line segments are located in the first gate metal layer.

[0023] In some exemplary embodiments, the second detection control unit includes: a second detection transistor, a gate of the second detection transistor is electrically connected to the second detection control line, a first electrode of the second detection transistor is electrically connected to the second test signal transmission line, and a second electrode of the second detection transistor is electrically connected to the second detection line.

[0024] On the other hand, this embodiment provides a display device including the display panel as described above.

[0025] On the other hand, this embodiment provides a crack detection method, which is applied to the display panel as described above, including: providing a first test signal to a first detection line through a first detection control unit; determining whether there is a crack in the surrounding area and the location of the crack based on the luminous state of multiple sub-pixels electrically connected to the first detection line.

[0026] In some exemplary embodiments, the crack detection method further includes: providing a second test signal to a second detection line through a second detection control unit; and determining whether there is a crack in the peripheral area and the location of the crack based on the luminous state of multiple sub-pixels electrically connected to the second detection line.

[0027] On the other hand, this embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels, at least one first detection line and at least one first detection control unit. The substrate comprises a display area and a peripheral area located outside the display area. A plurality of sub-pixels are located in the display area. At least one first detection line and at least one first detection control unit are located in the peripheral area, the at least one first detection control unit is electrically connected to the at least one first detection line, and is configured to provide a first test signal to the at least one first detection line. The at least one first detection line is electrically connected to the plurality of sub-pixels in the display area. The at least one first detection line comprises: a first main line, and a plurality of first sub-lines electrically connected to the first main line, the plurality of first sub-lines extending to the display area, each first sub-line being electrically connected to at least one sub-pixel in the display area. A portion of a line segment of at least one of the plurality of first sub-lines is located on a side of the first main line away from the display area.

[0028] In some exemplary embodiments, a gate driving circuit is further provided in the peripheral area. The first main line is located on a side of the gate driving circuit close to the display area, and a portion of each first sub-line is located on a side of the gate driving circuit away from the display area.

[0029] In some exemplary embodiments, the display panel further includes: a second detection line located in the peripheral area and at least one second detection control unit, the at least one second detection control unit being electrically connected to the second detection line and configured to provide a second test signal to the second detection line. The second detection line is electrically connected to the plurality of sub-pixels in the display area. The connection between the second detection line and the plurality of sub-pixels in the display area is different from the connection between the first detection line and the plurality of sub-pixels in the display area.

[0030] In some exemplary embodiments, the second detection line includes: a second main line and a plurality of second sub-lines electrically connected to the second main line; each second sub-line is electrically connected to at least one sub-pixel in the display area, and the plurality of second sub-lines are sequentially arranged along an extension direction of the second main line. The extension direction of the second main line intersects an extension direction of a first main line of the first detection line.

[0031] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0032] Summary of the Figures

[0033] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of one or more components in the accompanying drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0034] FIG1 is a schematic plan view of a display panel according to at least one embodiment of the present disclosure;

[0035] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0036] FIG3 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0037] FIG4 is a schematic diagram of partial wiring of a display panel according to at least one embodiment of the present disclosure;

[0038] FIG5 is a partial cross-sectional schematic diagram of the first sub-line shown in FIG4 ;

[0039] FIG6 is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure;

[0040] FIG7 is another partial wiring diagram of a display panel according to at least one embodiment of the present disclosure;

[0041] FIG8 is a partial cross-sectional schematic diagram of the second sub-line shown in FIG7 ;

[0042] FIG9 is a schematic diagram showing the connection between the second sub-line and the pixel circuit according to at least one embodiment of the present disclosure;

[0043] FIG10A is a schematic diagram of the pixel circuit after the semiconductor layer is formed in FIG9 ;

[0044] FIG10B is a schematic diagram of the pixel circuit after the first gate metal layer is formed in FIG9 ;

[0045] FIG10C is a schematic diagram of the pixel circuit after the second gate metal layer is formed in FIG9 ;

[0046] FIG10D is a schematic diagram of the pixel circuit after the first source / drain metal layer is formed in FIG9 ;

[0047] 11A and 11B are schematic diagrams of display patterns for crack detection in the third and fourth frame regions according to at least one embodiment of the present disclosure;

[0048] FIG12 is a schematic diagram of a display pattern for crack detection in a second border region according to at least one embodiment of the present disclosure;

[0049] FIG13 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure;

[0050] FIG14 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure;

[0051] FIG15 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure;

[0052] FIG16 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure;

[0053] FIG17 is a schematic plan view of another display panel according to at least one embodiment of the present disclosure;

[0054] FIG18 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure;

[0055] FIG19 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure;

[0056] FIG. 20 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0057] Details

[0058] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0059] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0060] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0061] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0062] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0063] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0064] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0065] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. The functions of "source" and "drain" are sometimes interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0066] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0067] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0068] The term "light transmittance" in this disclosure refers to the ability of light to pass through a medium, and is the percentage of the luminous flux passing through a transparent or translucent body to the incident luminous flux.

[0069] In the present disclosure, "about" and "substantially" are used without strict limits and allow for process and measurement errors. In the present disclosure, "substantially the same" means that the numerical values ​​differ by less than 10%.

[0070] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0071] This embodiment provides a display panel, comprising: a substrate, a plurality of sub-pixels and a plurality of data lines, at least one first detection line and at least one first detection control unit. The substrate comprises a display area and a peripheral area located outside the display area. The plurality of sub-pixels and the plurality of data lines are located in the display area, the plurality of sub-pixels and the plurality of data lines are electrically connected, and at least one of the plurality of sub-pixels comprises: a pixel circuit and a light-emitting element, the pixel circuit and the light-emitting element are electrically connected and configured to drive the light-emitting element to emit light. The at least one first detection line and the at least one first detection control unit are located in the peripheral area, the at least one first detection control unit is electrically connected to the at least one first detection line and is configured to provide a first test signal to the at least one first detection line. At least one first detection line is electrically connected to a plurality of sub-pixels in the display area in any of the following ways: at least one first detection line is electrically connected to anodes of light-emitting elements of a plurality of sub-pixels in the display area; at least one first detection line is electrically connected to sources of data writing transistors of pixel circuits of a plurality of sub-pixels in the display area; at least one first detection line is electrically connected to a plurality of data lines in the display area, wherein at least one of the plurality of data lines is electrically connected to a plurality of sub-pixels arranged along a first direction, and at least one first detection line is located at least in peripheral areas on opposite sides of the display area along the first direction.

[0072] In some examples, the first detection line can be electrically connected to the anodes of the light-emitting elements of multiple sub-pixels in the display area. During crack detection, when the anode of a light-emitting element receives a first test signal transmitted by the first detection line, the light-emitting element can be illuminated. Conversely, when a crack is present at the location of the first detection line, the first detection line cannot transmit the first test signal to the anode of the corresponding light-emitting element, and the corresponding light-emitting element does not emit light. In this way, the position of the edge crack can be determined based on the position of the dark line in the display area.

[0073] In some examples, the first detection line can be electrically connected to the source of the data write transistor of the pixel circuit of multiple sub-pixels in the display area. During the crack detection process, when the source of the data write transistor of the pixel circuit receives the first test signal transmitted by the first detection line, the light-emitting element driven by the pixel circuit does not emit light. Conversely, when there is a crack at the location of the first detection line, the first detection line cannot transmit the first test signal to the corresponding pixel circuit, and the light-emitting element driven by the pixel circuit can emit light. In this way, the position of the edge crack can be located based on the position of the bright line in the display area.

[0074] In some examples, the first detection line can be electrically connected to multiple data lines in the display area, and the multiple data lines can extend along a first direction (e.g., horizontal wiring). During the crack detection process, when the data line receives the first test signal transmitted by the first detection line, the pixel circuit connected to the data line can drive the light-emitting element not to emit light. Conversely, when there is a crack at the location of the first detection line, the first detection line cannot transmit the first test signal to the corresponding data line, and the pixel circuit connected to the data line can drive the light-emitting element to emit light. In this way, the position of the edge crack can be located according to the position of the bright line in the display area.

[0075] The display panel provided in this embodiment utilizes a first detection control unit to provide a first test signal to a first detection line. The first detection line is electrically connected to multiple sub-pixels in the display area. Based on the voltage control of the first test signal and the display results of the multiple sub-pixels in the display area, it is easy to determine whether there are cracks in the peripheral area and accurately locate the position of the edge cracks in the peripheral area, thereby improving work efficiency.

[0076] The solution of this embodiment is illustrated below through some examples.

[0077] Figure 1 is a planar schematic diagram of a display panel of at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display panel of this embodiment may include: a display area AA, a peripheral area BB surrounding the display area AA. The peripheral area BB may include: a third border area B3 and a fourth border area B4 located on opposite sides of the display area AA along the first direction X, and a first border area B1 and a second border area B2 located on opposite sides of the display area AA along the second direction Y. Among them, the first border area B1 can also be called a lower border, the second border area B2 can also be called an upper border, the third border area B3 can also be called a left border, and the fourth border area B4 can also be called a right border. The first border area B1 is connected to the third border area B3 and the fourth border area B4, and the second border area B2 is connected to the third border area B3 and the fourth border area B4.

[0078] In some examples, as shown in FIG1 , the display area AA may be a rectangle, such as a rounded rectangle. However, this embodiment is not limited thereto. For example, the display area may be a circle, an ellipse, or other shapes.

[0079] In some examples, as shown in FIG1 , the third frame area B3 and the fourth frame area B4 may include a circuit area, a power line area, a crack dam area, and a cutting area sequentially arranged along the direction of the display area AA. The circuit area may be connected to the display area AA, and the circuit area may include a gate drive circuit. For example, the gate drive circuit may include a plurality of cascaded shift registers, and the plurality of shift registers may be electrically connected to the plurality of gate lines GL in the display area AA. The power line area is connected to the circuit area and may include at least a low-level power line. The low-level power line may extend in a direction parallel to the edge of the display area and be connected to the cathode of the display area AA. The crack dam area may be connected to the power line area and may include at least a plurality of cracks provided on the composite insulating layer. The cutting area may be connected to the crack dam area and may include at least a cutting groove provided on the composite insulating layer. The cutting groove may be configured so that after all the film layers of the display panel are prepared, the cutting arrangement may be cut along the cutting groove respectively.

[0080] In some examples, as shown in FIG1 , the display area AA can be a flat area including a plurality of sub-pixels PX that form a pixel array. The plurality of sub-pixels PX can be configured to display a dynamic image or a still image. The display area AA can be referred to as an active area. In some examples, the display panel can be a flexible panel, and thus the display panel can be deformable, such as being curled, bent, folded, or rolled.

[0081] In some examples, as shown in FIG1 , the display area AA may include at least a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a first direction X, and the plurality of data lines DL may extend along a second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may intersect to form a plurality of sub-pixel regions, and a sub-pixel PX may be provided in each sub-pixel region. The plurality of data lines DL are electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of data lines DL may extend to the first border area B1. The plurality of gate lines GL are electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signals may include scan signals and light-emitting control signals. For another example, the gate control signals may include scan signals, light-emitting control signals, and reset control signals.

[0082] 1 , the first direction X may be the extending direction (row direction) of the gate lines GL in the display area AA, and the second direction Y may be the column direction. The first direction X and the second direction Y may intersect, for example, the first direction X and the second direction Y may be perpendicular to each other.

[0083] In some examples, a pixel unit in display area AA may include three sub-pixels, where the three sub-pixels are red, green, and blue. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, where the four sub-pixels are red, green, blue, and white.

[0084] In some examples, the shape of the sub-pixels can be a rectangle, a diamond, a pentagon, or a hexagon. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0085] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0086] In some examples, the multiple transistors in the pixel circuit can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the difficulty of display panel manufacturing, and improve product yield. In other examples, the multiple transistors in the pixel circuit can include P-type transistors and N-type transistors.

[0087] In some examples, multiple transistors in the pixel circuit may use low-temperature polysilicon thin-film transistors, or may use oxide thin-film transistors, or may use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor uses oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have the advantages of high mobility and fast charging, and oxide thin-film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display panel, that is, an LTPS+Oxide (LTPO for short) display panel, can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0088] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0089] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this example is described using a 7T1C structure as an example.

[0090] 2 , the pixel circuit of this example may include seven transistors (ie, first to seventh transistors T1 to T7 ) and a storage capacitor Cst. The light emitting element EL may include an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.

[0091] In some examples, as shown in FIG2 , the display panel may include: a first scan line GL1 , a second scan line GL2 , a third scan line GL3 , a data line DL, a first power line VDD, a second power line VSS, an emission control line EML, a first initial signal line INIT1 , and a second initial signal line INIT2 .

[0092] In some examples, the first power line VDD can be configured to provide a constant first voltage signal Vdd to the pixel circuit, the second power line VSS can be configured to provide a constant second voltage signal Vss to the pixel circuit, and the first voltage signal Vdd can be greater than the second voltage signal Vss. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit; the data line DL can be configured to provide a data signal to the pixel circuit; the emission control line EML can be configured to provide an emission control signal EM to the pixel circuit; the second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit; and the third scan line GL3 can be configured to provide a third scan signal SCAN3 to the pixel circuit.

[0093] In some examples, the second scan line GL2 electrically connected to the pixel circuit in the nth row can be electrically connected to the first scan line GL1 electrically connected to the pixel circuit in the n-1th row, so as to be input with the first scan signal SCAN1(n-1), that is, the second scan signal SCAN2(n) and the first scan signal SCAN1(n-1) can be the same. The third scan line GL3 of the pixel circuit in the nth row can be electrically connected to the first scan line GL1 of the pixel circuit in the nth row, so as to be input with the first scan signal SCAN1(n), that is, the third scan signal SCAN3(n) and the first scan signal SCAN1(n) can be the same. Wherein, n is an integer greater than 0. In this way, the signal lines of the display panel can be reduced, and a narrow frame design of the display panel can be achieved. However, this embodiment is not limited to this.

[0094] In some examples, the first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and the second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal can be different from the second initial signal. The first initial signal and the second initial signal can be constant voltage signals, and their magnitudes can be, for example, between the first voltage signal Vdd and the second voltage signal Vss, but are not limited thereto. In other examples, the first initial signal and the second initial signal can be the same, and only the first initial signal line can be provided to provide the first initial signal.

[0095] In some examples, as shown in FIG2 , the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The third transistor T3 may also be referred to as a driving transistor. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3. The fourth transistor T4 may also be referred to as a data write transistor. The gate of the second transistor T2 is electrically connected to the first scan line GL1, the first electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3. The second transistor T2 may also be referred to as a threshold compensation transistor. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The fifth transistor T5 and the sixth transistor T6 may also be referred to as emission control transistors. The first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3. The seventh transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first transistor T1 is electrically connected to the second scan line GL2, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the third scan line GL3, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The first transistor T1 and the seventh transistor T7 may also be referred to as reset control transistors. A first plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3 , and a second plate of the storage capacitor Cst is electrically connected to the first power line VDD.

[0096] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3 and the second transistor T2, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4 and the third transistor T3, the third node N3 is the connection point of the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light-emitting element EL.

[0097] The operation process of the pixel circuit is described below. The pixel circuit shown in FIG2 includes a plurality of transistors, all of which are P-type transistors. In this example, the third scan signal provided by the third scan line GL3 may be the same as the first scan signal provided by the first scan line GL1.

[0098] In some examples, during a frame display period, the operation process of the pixel circuit may include: a first stage, a second stage, and a third stage.

[0099] The first phase is called the reset phase. The second scan signal SCAN2 provided by the second scan line GL2 can be a low-level signal, turning on the first transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N1, initializing the first node N1 and clearing the existing data voltage in the storage capacitor Cst. The first scan signal SCAN1 provided by the first scan line GL1 can be a high-level signal, and the emission control signal EM provided by the emission control line EML can be a high-level signal, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this phase, the light-emitting element EL does not emit light.

[0100] The second phase is called the data writing phase or the threshold compensation phase. The first scan signal SCAN1 provided by the first scan line GL1 can be a low-level signal, the second scan signal SCAN2 provided by the second scan line GL2, and the emission control signal EM provided by the emission control line EML can both be high-level signals, and the data line DL outputs the data signal DATA. During this phase, since the first plate of the storage capacitor Cst is at a low level, the third transistor T3 is turned on. The first scan signal SCAN1 is a low-level signal, turning on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on, causing the data voltage Vdata output by the data line DL to be provided to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is then charged into the storage capacitor Cst. The voltage on the first plate of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the second initialization signal provided by the second initialization signal line INIT2 is provided to the anode of the light-emitting element EL, initializing (resetting) the anode of the light-emitting element EL and clearing the pre-stored voltage therein, completing the initialization and ensuring that the light-emitting element EL does not emit light. The second scan signal SCAN2 provided by the second scan line GL2 can be a high-level signal, turning off the first transistor T1. The emission control signal EM provided by the emission control signal line EML is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6.

[0101] The third phase is called the light-emitting phase. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, while the first scan signal SCAN1 provided by the first scan line GL1 and the second scan signal SCAN2 provided by the second scan line GL2 are high-level signals. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The first voltage signal Vdd output from the first power line VDD provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0102] During the pixel circuit driving process, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K×(Vgs-Vth) 2 =K×[(Vdd-Vdata+|Vth|)-Vth] 2=K×[Vdd-Vdata] 2 .

[0103] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and Vdd is the first voltage signal output by the first power line VDD.

[0104] It can be seen from the above formula that the current flowing through the light emitting element EL has nothing to do with the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3.

[0105] FIG3 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG3 , at least one sub-pixel in display area AA may include: a pixel circuit 61 and a light-emitting element 62. The light-emitting element 62 may be located on a side of the pixel circuit 61 away from the substrate. The pixel circuit 61 is electrically connected to the light-emitting element 62 and may be configured to drive the corresponding light-emitting element 62 to emit light. The orthographic projection of the light-emitting element 62 and the connected pixel circuit 61 on the substrate may at least partially overlap. FIG3 illustrates multiple pixel circuits 61 and multiple light-emitting elements 62 as an example, and there may be no electrical connection between the pixel circuits 61 and the light-emitting elements 62 illustrated in FIG3 . In this example, multiple light-emitting elements 62 arranged sequentially along the first direction X may be referred to as a row of light-emitting elements, multiple pixel circuits 61 arranged sequentially along the first direction X may be referred to as a row of pixel circuits, multiple pixel circuits 61 arranged sequentially along the second direction Y may be referred to as a column of pixel circuits, and multiple light-emitting elements 62 arranged sequentially along the second direction Y may be referred to as a column of light-emitting elements.

[0106] In some examples, as shown in FIG3 , the first border area B1 may include a signal access area B11 . The signal access area B11 may be configured to house an integrated circuit, such as a display driver integrated circuit (DDI) or a touch and display driver integrated circuit (TDDI).

[0107] In some examples, as shown in FIG3 , the first border area B1 may be provided with first detection control units 33a and 33b, second detection control units 34a and 34b, and a first power border line 51a. The first power border line 51a may extend at least along the first direction X and be located on a side of the signal access area B11 close to the display area AA in the second direction Y. The first power border line 51a may be electrically connected to a plurality of first power lines extending along the second direction Y within the display area AA, and may be configured to provide a first voltage signal to the plurality of first power lines.

[0108] In some examples, as shown in FIG3 , the first detection control unit 33a and the second detection control unit 34a can be located in the first border area B1 near the third border area B3, and the first detection control unit 33b and the second detection control unit 34b can be located in the first border area B near the fourth border area B4. The first detection control units 33a and 33b, and the second detection control units 34a and 34b can be located on a side of the signal access area B11 near the display area AA. The first detection control unit 33a can be located on a side of the second detection control unit 34a near the edge of the display panel in the first direction X, and the first detection control unit 33b can be located on a side of the second detection control unit 34b near the edge of the display panel in the first direction X.

[0109] In some examples, as shown in FIG3 , the first detection control unit 33a may include a first detection transistor M1. The gate of the first detection transistor M1 may be electrically connected to a first detection control line 35a, the first electrode of the first detection transistor M1 may be electrically connected to a first test signal transmission line 36a, and the second electrode of the first detection transistor M1 may be electrically connected to a first detection line 31a. The first detection control line 35a may extend to the signal access area B11 and be electrically connected to a first detection control pin within the signal access area B11. The first test signal transmission line 36a may extend to the signal access area B11 and be electrically connected to a first test signal pin within the signal access area B11.

[0110] In some examples, as shown in FIG3 , the first detection control unit 33b may include: a first detection transistor M1′. The gate of the first detection transistor M1′ may be electrically connected to the first detection control line 35b, the first electrode of the first detection transistor M1′ may be electrically connected to the first test signal transmission line 36b, and the second electrode of the first detection transistor M1′ may be electrically connected to the first detection line 31b. The first detection control line 35b may extend to the signal access area B11 and be electrically connected to another first detection control pin within the signal access area B11. The first test signal transmission line 36b may extend to the signal access area B11 and be electrically connected to another first test signal pin within the signal access area B11. The first detection control pins transmitting the same first detection control signal within the signal access area B11 may be electrically connected to each other, and the first test signal pins transmitting the same first test signal may be electrically connected to each other.

[0111] In some examples, as shown in FIG3 , the second detection control unit 34a may include a second detection transistor M2. The gate of the second detection transistor M2 may be electrically connected to a second detection control line 37a, the first electrode of the second detection transistor M2 may be electrically connected to a second test signal transmission line 38a, and the second electrode of the second detection transistor M2 may be electrically connected to the second detection line 32. The second detection control line 37a may extend to the signal access area B11 and be electrically connected to a second detection control pin within the signal access area B11. The second test signal transmission line 38a may extend to the signal access area B11 and be electrically connected to a second test signal pin within the signal access area B11.

[0112] In some examples, as shown in FIG3 , the second detection control unit 34b may include: a second detection transistor M2′. The gate of the second detection transistor M2′ may be electrically connected to the second detection control line 37b, the first electrode of the second detection transistor M2′ may be electrically connected to the second test signal transmission line 38b, and the second electrode of the second detection transistor M2′ may be electrically connected to the second detection line 32. The second detection control line 37b may extend to the signal access area B11 and be electrically connected to another second detection control pin within the signal access area B11. The second test signal transmission line 38a may extend to the signal access area B11 and be electrically connected to another second test signal pin within the signal access area B11. The second detection control pins in the signal access area B11 that transmit the same second detection control signal may be electrically connected to each other, and the second test signal pins that transmit the same second test signal may be electrically connected to each other.

[0113] In some examples, as shown in Figure 3, the third border area B3 may be provided with a gate drive circuit 41a, a border initial signal line 42a, and a first detection line 31a. The gate drive circuit 41a may, for example, include a scan drive circuit, and the scan drive circuit may include a plurality of scan shift registers arranged along the second direction Y, and the scan drive circuit may be configured to provide scan signals to the plurality of scan lines of the display area AA (for example, providing a first scan signal to the plurality of first scan lines GL1, providing a second scan signal to the plurality of second scan lines GL2, and providing a third scan signal to the plurality of third scan lines GL3). The border initial signal line 42a may be located on the side of the gate drive circuit 41a close to the display area AA. For example, the border initial signal line 42a may include a first border initial signal line that transmits a first initial signal, or may include a first border initial signal line that transmits a first initial signal and a second border initial signal line that transmits a second initial signal.

[0114] In some examples, as shown in FIG3 , the first detection line 31a may include a first main line 311a and multiple first sub-lines 312a. FIG3 illustrates six first sub-lines 312a as an example; this embodiment does not limit the number of first sub-lines 312a. The multiple first sub-lines 312a are electrically connected to the first main line 311a. The first main line 311a may extend at least along the second direction Y. The multiple first sub-lines 312a may be arranged sequentially along the second direction Y. The first main line 311a may be located on a side of the gate drive circuit 41a and the frame initial signal line 42a that is closer to the display area AA. For example, the first main line 311a may be located on a side of the frame initial signal line 42a that is farther from the gate drive circuit 41a. A portion of each first sub-line 312a may be located on a side of the gate drive circuit 41a that is farther from the display area AA. For example, a portion of each first sub-line 312a may be located in the power line area of ​​the third frame area B3 and on a side of the low-level power line that is farther from the display area AA. After connecting to the first main line 311a, each first sub-line 312a can extend along the first direction X toward the side away from the display area AA, until it passes through the gate drive circuit 41a, then rewind along the first direction X toward the side closer to the display area AA, and ultimately extend to electrically connect to the anode of the light-emitting element 62 of a sub-pixel within the display area AA. This example utilizes a design in which the first sub-line 312a is wound at the edge away from the first main line 311a, which facilitates precise location of edge cracks in the third border area B3, thereby improving work efficiency.

[0115] FIG4 is a schematic diagram of a partial wiring arrangement of a display panel according to at least one embodiment of the present disclosure. FIG4 illustrates the winding arrangement of a first sub-line. In some examples, as shown in FIG3 and FIG4 , a first sub-line 312a may include at least a first line segment 3121, a second line segment 3122, a first crossover 3123, a second crossover 3124, and a first connecting segment 3125. The second crossover 3124, the first line segment 3121, the first crossover 3123, the second line segment 3122, and the first connecting segment 3125 may be electrically connected in sequence. The second crossover 3124 may be electrically connected to the first main line 311a, and the first connecting segment 3125 may be electrically connected to the anode of the light-emitting element 62 of a sub-pixel in the display area AA. For example, the first crossover 3123 and the second crossover 3124 may extend at least along the first direction X, the first line segment 3121 may extend at least along the second direction Y, and the second line segment 3122 and the first connecting segment 3125 may extend at least along the first direction X. In this example, a portion of the first sub-line 312 a located on a side of the gate driving circuit 41 a away from the display area AA may include a first line segment 3121 .

[0116] In some examples, as shown in Figures 3 and 4, the orthographic projections of the first cross-line 3123 and the second cross-line 3124 on the substrate may overlap with the orthographic projections of the gate drive circuit 41a and the frame initial signal line 42a on the substrate, and the orthographic projections of the first line segment 3121 and the second line segment 3122 on the substrate may not overlap with the orthographic projections of the gate drive circuit 41a and the frame initial signal line 42a on the substrate. The first line segment 3121 may be located on the side of the gate drive circuit 41a away from the display area AA, and the second line segment 3122 and the first connecting segment 3125 may be located on the side of the frame initial signal line 42a close to the display area AA. For example, the first cross-line 3123 and the second cross-line 3124 may be in the same layer structure, the first line segment 3121 and the second line segment 3122 may be in the same layer structure, and the first connecting segment 3125 and the second line segment 3122 may be located in different film layers.

[0117] In some examples, as shown in Figures 3 and 4, the first span 3123, the first line segment 3121, and the second span 3124 of the first sub-line 312a can form a fold. However, this embodiment is not limited to this. In other examples, the first sub-line can be a serpentine route with multiple folds. A serpentine route is a meandering curve. For example, after one end of the route extends a certain distance in one direction, it bends and twists and extends a certain distance in the opposite direction, then bends and twists again and extends in the direction, and repeats this bending and twisting several times to form a serpentine route.

[0118] In some examples, as shown in FIG3 , the plurality of first sub-lines 312a of the first detection line 31a can be electrically connected to the light-emitting elements 62 of the plurality of sub-pixels in a one-to-one correspondence. The light-emitting elements 62 of the plurality of sub-pixels connected to the first detection line 31a can be arranged in a column. For example, the light-emitting elements 62 of the plurality of sub-pixels connected to the first detection line 31a can include a column of light-emitting elements 62 closest to the third border area B3. Each first sub-line 312a of the first detection line 31a can be independently electrically connected to a light-emitting element 62. This example can facilitate accurate positioning of the edge crack position of the third border area B3 based on whether the light-emitting element 62 is lit by setting each first sub-line 312a to be independently electrically connected to the light-emitting element 62.

[0119] In some examples, as shown in FIG3 , the fourth border area B4 may be provided with a gate drive circuit 41b, a border initial signal line 42b, and a first detection line 31b. The gate drive circuit 41b may, for example, include a light-emitting drive circuit, which may include a plurality of light-emitting shift registers arranged along the second direction Y. The light-emitting drive circuit may be configured to provide light-emitting control signals to a plurality of light-emitting control lines in the display area AA. The border initial signal line 42b may be located on a side of the gate drive circuit 41b close to the display area AA. The border initial signal line 42a and the border initial signal line 42b may be electrically connected to each other.

[0120] In some examples, as shown in FIG3 , the first detection line 31b may include: a first main line 311b and multiple first sub-lines 312b. FIG3 illustrates six first sub-lines 312b as an example. This embodiment does not limit the number of first sub-lines 312b. Multiple first sub-lines 312b are electrically connected to the first main line 311b. The first main line 311b may extend at least along the second direction Y. The first main line 311b may be located on a side of the gate drive circuit 41b and the frame initial signal line 42b that is close to the display area AA. For example, the first main line 311b may be located on a side of the frame initial signal line 42b that is away from the gate drive circuit 41b. A portion of each first sub-line 312b may be located on a side of the gate drive circuit 41b that is away from the display area AA. For example, a portion of each first sub-line 312b may be located in the power line area of ​​the fourth frame area B4 and on a side of the low-level power line that is away from the display area AA. After connecting to the first main line 311b, each first sub-line 312b can extend along the first direction X toward the side away from the display area AA until it passes through the gate drive circuit 41b, then winds along the first direction X toward the side close to the display area AA, and finally extends to electrically connect to the anode of the light-emitting element 62 of a sub-pixel in the display area AA. This example utilizes a winding design of the first sub-line 312b at the edge away from the first main line 311b, which can facilitate accurate positioning of the edge crack position of the fourth border area B4, thereby improving work efficiency. The winding design of the first sub-line 312b can refer to the description of the first sub-line 312a, so it will not be repeated here.

[0121] In some examples, as shown in FIG3 , the light-emitting elements 62 of the multiple sub-pixels connected to the first detection line 31b can be arranged in a column, for example, including a column of light-emitting elements 62 closest to the fourth border region B4. Each first sub-line 312b of the first detection line 31b can be independently electrically connected to a light-emitting element 62. In this example, by setting each first sub-line 312b to be independently electrically connected to a light-emitting element 62, it is convenient to accurately locate the edge crack position of the fourth border region B4 based on whether the light-emitting element 62 is lit.

[0122] In some examples, as shown in FIG3 , the second border area B2 may be provided with a first power border line 51 b and a second detection line 32 . The first power border line 51 b may extend at least along the first direction X. The first power border line 51 b may be electrically connected to a plurality of first power lines extending along the second direction Y in the display area AA.

[0123] In some examples, as shown in FIG3 , the second detection line 32 may include: a second main line 321 and multiple second sub-lines 322 . FIG3 illustrates four second sub-lines 322 as an example; this embodiment does not limit the number of second sub-lines 322 . The multiple second sub-lines 322 are electrically connected to the second main line 321 . The second main line 321 may extend at least along the first direction X. The multiple second sub-lines 322 may be arranged sequentially along the first direction X. The second main line 321 may be located on the side of the first power border line 51b close to the display area AA. A portion of each second sub-line 322 may be located on the side of the first power border line 51b away from the display area AA. After connecting to the second main line 321, each second sub-line 322 extends along the second direction Y away from the display area AA until it passes the first power border line 51b, then winds along the second direction Y toward the side close to the display area AA, and ultimately extends to electrically connect to the pixel circuit 61 of a sub-pixel within the display area AA.

[0124] FIG7 is another partial schematic diagram of the wiring of a display panel according to at least one embodiment of the present disclosure. FIG7 illustrates the winding arrangement of a second sub-line 322. In some examples, as shown in FIG3 and FIG7, the second sub-line 322 may include at least a third line segment 3221, a fourth line segment 3222, a third crossover 3223, a fourth crossover 3224, and a second connecting segment 3225. The fourth crossover 3224, the third line segment 3221, the third crossover 3223, the fourth line segment 3222, and the second connecting segment 3225 may be electrically connected in sequence. The fourth crossover 3224 may be electrically connected to the second main line 321, and the second connecting segment 3225 may be electrically connected to the pixel circuit 61 of the sub-pixel in the display area AA. For example, the third crossover 3223 and the fourth crossover 3224 may extend at least along the second direction Y, the third line segment 3221 may extend at least along the first direction X, and the fourth line segment 3222 and the second connecting segment 3225 may extend along the second direction Y. In this example, a portion of the second sub-line 322 located on a side of the first power border line 51 b away from the display area AA may include a third line segment 3221 .

[0125] In some examples, as shown in Figures 3 and 7, the orthographic projections of the third cross-line 3223 and the fourth cross-line 3224 on the substrate may overlap with the orthographic projection of the first power border line 51b on the substrate, and the orthographic projections of the third line segment 3221 and the fourth line segment 3222 on the substrate may not overlap with the orthographic projection of the first power border line 51b on the substrate. The third line segment 3221 may be located on the side of the first power border line 51b away from the display area AA, and the fourth line segment 3222 and the second connecting segment 3225 may be located on the side of the first power border line 51b closer to the display area AA. For example, the third cross-line 3223 and the fourth cross-line 3224 may be in the same layer structure, the third line segment 3221 and the fourth line segment 3222 may be in the same layer structure, and the second connecting segment 3225 and the fourth line segment 3222 may be located in different film layers.

[0126] In some examples, as shown in Figures 3 and 7, the third span 3223, the third line segment 3221, and the fourth span 3224 of the second sub-line 322 can form a fold. However, this embodiment is not limited to this. In other examples, the second sub-line can be a serpentine route with multiple folds.

[0127] In some examples, as shown in FIG3 , the plurality of second sub-lines 322 of the second detection line 32 can be electrically connected to the pixel circuits 61 of the plurality of sub-pixels in a one-to-one correspondence. The pixel circuits 61 of the plurality of sub-pixels connected to the second detection line 32 can be arranged in a row. For example, the pixel circuit 61 connected to the second detection line 32 can include the pixel circuits excluding the first and last pixel circuits in the row of pixel circuits 61 closest to the second border area B2. The first pixel circuit in the row of pixel circuits can be electrically connected to one of the light-emitting elements in a column of light-emitting elements closest to the third border area B3, and the last pixel circuit in the row of pixel circuits can be electrically connected to one of the light-emitting elements in a column of light-emitting elements closest to the fourth border area B4. The sub-pixels connected to the first detection lines 31a and 31b of this example are different from the sub-pixels connected to the second detection line 32, so as to avoid mutual influence between the detection effects of the first detection lines 31a and 31b and the second detection line 32.

[0128] In some examples, as shown in FIG3 , each second sub-line 322 of the second detection line 32 can be electrically connected to the source of a data write transistor of a pixel circuit 61 (e.g., the fourth transistor T4 in the aforementioned pixel circuit). Each second sub-line 322 can be independently electrically connected to the data write transistor of the pixel circuit 61. In this example, by setting each second sub-line 322 to be independently electrically connected to the data write transistor of the pixel circuit 61, it is beneficial to accurately locate the edge crack position of the second border area B2 based on whether the light-emitting element connected to the pixel circuit 61 is lit.

[0129] In some examples, as shown in FIG3 , the second frame area B2 may further be provided with a first connecting line 313. The first detection line 31a in the third frame area B3 may be electrically connected to the first detection line 31b in the fourth frame area B4 via the first connecting line 313. The two ends of the first connecting line 313 may be electrically connected to the first main line 311a of the first detection line 31a and the first main line 311b of the first detection line 31b, respectively. The first connecting line 313 may be located on the side of the first power frame line 51b close to the display area AA, for example, it may be located on the side of the second main line 321 of the second detection line 32 close to the first power frame line 51b. However, this embodiment is not limited to this. In this example, the first detection line 31a in the third frame area B3 and the first detection line 31b in the fourth frame area B4 are electrically connected using the first connecting line 313, so that the first test signal can be transmitted in a circular manner within the third frame area B3, the second frame area B2, and the fourth frame area B4, which is beneficial for wiring in the peripheral areas and also beneficial for edge crack detection in the peripheral areas.

[0130] In some examples, as shown in Figure 3, the display area AA may also be provided with second connecting lines 323a and 323b. One end of the second main line 321 of the second detection line 32 of the second frame area B2 can be electrically connected to the second connecting line 323a, and electrically connected to the second detection control unit 34a through the second connecting line 323a. The other end of the second main line 321 can be electrically connected to the second connecting line 323b, and electrically connected to the second detection control unit 34b through the second connecting line 323b. By arranging the second connecting lines 323a and 323b in the display area, it is possible to avoid affecting the transmission of the second test signal by arranging the lines in the third frame area B3 and the fourth frame area B4.

[0131] FIG6 is a partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure. FIG6 is an illustration of two sub-pixels in the display area as an example. In some examples, as shown in FIG6, in a direction perpendicular to the display panel, the display area of ​​the display panel may include at least: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 arranged on the substrate 10. The circuit structure layer 12 may include: a barrier layer 101, a bottom shielding metal (BSM) layer, a buffer layer 102, a semiconductor layer, a first gate insulating layer 103, a first gate metal layer, a second gate insulating layer 104, a second gate metal layer, an interlayer insulating (ILD) layer 105, a first source and drain metal layer, a first planarization (PLN) layer 106, a second source and drain metal layer, and a second planarization layer 107, which are sequentially arranged on the substrate 10. The circuit structure layer 12 in Figure 6 is illustrated by taking a transistor 21 (for example, the sixth transistor in the pixel circuit of the aforementioned embodiment) and a first capacitor 22 (for example, the storage capacitor in the pixel circuit of the aforementioned embodiment) included in each sub-pixel as an example. Among them, the blocking layer 101, the buffer layer 102, the first gate insulating layer 103, the second insulating layer 104, and the interlayer insulating layer 105 can be inorganic insulating layers, and the first flat layer 106 and the second flat layer 107 can be organic insulating layers. The blocking layer 101 and the buffer layer 102 can prevent harmful substances in the substrate 10 from invading the interior of the display panel, and can also increase the adhesion of the film layer in the display panel to the substrate 10. However, this embodiment is not limited to this. In other examples, a passivation layer can also be provided between the first source and drain metal layer and the second source and drain metal layer, and the passivation layer can be located on the side of the first flat layer close to the substrate.

[0132] In some examples, the barrier layer 101, the buffer layer 102, the first gate insulating layer 103, the second insulating layer 104, and the interlayer insulating layer 105 can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The first planarizing layer 106 and the second planarizing layer 107 can be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. The bottom light-shielding metal layer, the first gate metal layer, and the second gate metal layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), and can be a single layer structure. The first source / drain metal layer and the second source / drain metal layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The semiconductor layer can be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology. This embodiment is not limited to this.

[0133] In some examples, as shown in FIG6 , the bottom light-shielding metal layer in the display area can be configured to at least partially cover the active layer of the transistor of the pixel circuit to prevent external light from affecting the performance of the transistor. For example, the bottom light-shielding metal layer can include at least a bottom light-shielding block 20 , the orthographic projection of the bottom light-shielding block 20 on the substrate 10 can cover the orthographic projection of the channel region of the active layer 210 of the transistor 21 on the substrate 10.

[0134] In some examples, as shown in FIG6 , the semiconductor layer of the display area may include at least an active layer 210 of the transistor 21. The active layer 210 of the transistor 21 may include a first region, a second region, and a channel region between the first region and the second region. The first gate metal layer may include at least a gate 213 of the transistor 21 and a first plate 221 of the first capacitor 22. The orthographic projection of the gate 213 of the transistor 21 on the substrate 10 may cover the orthographic projection of the channel region of the active layer 210 on the substrate 10. The second gate metal layer may include at least a second plate 222 of the first capacitor 22. The orthographic projections of the second plate 222 and the first plate 221 of the first capacitor 22 on the substrate 10 may at least partially overlap, for example, the two may coincide. The first source-drain metal layer may include at least a source 211 and a drain 212 of the transistor 21. The interlayer insulating layer 105 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region of the active layer 210. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region of the active layer 210. The source 211 of the transistor 21 can be electrically connected to the first region of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transfer electrode 23. The first transfer electrode 23 can be electrically connected to the drain 212 of the transistor 21 of the pixel circuit through a third pixel via formed in the first planar layer 106. The first switching electrode 23 can be electrically connected to the first electrode 131 (eg, anode) of the light emitting element through the fourth pixel via hole formed in the second planar layer 107. In this example, the first switching electrode 23 can be used to achieve electrical connection between the pixel circuit and the light emitting element.

[0135] In some examples, as shown in FIG6 , the light-emitting structure layer 13 of the display area may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the second planar layer 107 and electrically connected to the first transfer electrode 23 through a fourth pixel via provided in the second planar layer 107. The pixel definition layer 134 is disposed on the first electrode 131 and the second planar layer 107. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first and second electrodes 131 and 133, the organic light-emitting layer 132 may emit light of a corresponding color. An isolation column layer may be further provided on a side of the pixel definition layer 134 away from the substrate 10 . The isolation column layer may include a plurality of isolation columns (PS) 135 .

[0136] In some examples, as shown in FIG6 , the organic light-emitting layer 132 of the light-emitting element in the display area may include an emitting layer (EML), and one or more film layers including a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be utilized to emit light according to the required grayscale.

[0137] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the difficulty of the process and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a one-time process (a one-time evaporation process or a one-time inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0138] In some examples, as shown in FIG6 , the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of an inorganic material, and the second encapsulation layer 142 may be made of an organic material. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0139] In some examples, as shown in FIG6 , the display panel may further include: a touch structure layer 15 and a color filter layer 16 located on a side of the encapsulation structure layer 14 away from the substrate 10. The color filter layer 16 may be located on a side of the touch structure layer 15 away from the encapsulation structure layer 14. The color filter layer 16 may include: a plurality of filter units of different colors (for example, including filter units 163), a black matrix 162 located between the different filter units, a color filter buffer layer (CBL) 161 located on a side of the black matrix 162 and the plurality of filter units close to the substrate 10, and a color filter overcoat (COC) 164 located on a side of the black matrix 162 and the plurality of filter units away from the substrate 10. In some examples, the plurality of filter units of the color filter layer 16 may include: a plurality of red filter units, a plurality of green filter units, and a plurality of blue filter units. The filter units of different colors may correspond to light-emitting elements of the light-emitting structure layer 13 that emit different colors. For example, a blue filter unit may correspond to a blue light-emitting element, and the orthographic projection of the blue filter unit on the substrate may at least partially overlap with the orthographic projection of the light-emitting area of ​​the blue light-emitting element on the substrate. For example, the orthographic projection of the blue filter unit on the substrate may cover the orthographic projection of the light-emitting area of ​​the blue light-emitting element on the substrate. In this example, the filter unit allows a single color of light to pass through and absorbs light of other colors. For example, the blue filter unit allows blue light to pass through and absorbs light of other colors.

[0140] Figure 5 is a partial cross-sectional schematic diagram of the first sub-line shown in Figure 4. In some examples, as shown in Figures 3 to 6, the first segment 3121 and the second segment 3122 of the first sub-line 312a can be located in the first gate metal layer, the first crossover 3123 and the second crossover 3124 can be located in the bottom light-shielding metal layer, and the first connecting segment 3125 can be located in the second source / drain metal layer, for example. The first segment 3121 can be electrically connected to one end of the first crossover 3123 through a first connecting via defined in the first gate insulation layer 103 and the buffer layer 102. The first crossover 3123 can extend from below the gate driver circuit 41a and the frame initial signal line 42a to cross over the gate driver circuit 41a and the frame initial signal line 42a. The gate driver circuit 41a can, for example, include a second capacitor, which can include a first plate 271 located in the first gate metal layer and a second plate 272 located in the second gate metal layer. The connection between the first segment 3121 and the first crossover 3123 can be located on the side of the gate driver circuit 41a away from the display area. The other end of the first jumper 3123 can be electrically connected to the second line segment 3122 via a second connection via defined in the first gate insulation layer 103 and the buffer layer 102. The connection between the first jumper 3123 and the second line segment 3122 can be located on the side of the gate drive circuit 41a and the frame initial signal line 42a that is closer to the display area. The second line segment 3122 can be electrically connected to the first connection segment 3125. For example, the first connection segment 3125 can be electrically connected to the second line segment 3122 located in the first gate metal layer via a third connection via defined in the second planar layer 107, the first planar layer 106, the interlayer insulation layer 105, and the second gate insulation layer 104.

[0141] In some examples, as shown in FIG6 , after the first connecting segment 3125 extends to the display area, it can be electrically connected to the anode 131 of a light-emitting element in the display area near the third frame area. The anode 131 of the light-emitting element can be electrically connected to the first connecting segment 3125 through a fourth connecting via provided in the second planar layer 107, thereby achieving electrical connection between the anode 131 of the light-emitting element and the first sub-line 312 a.

[0142] This example utilizes the first jumper 3123 and the second jumper 3124 arranged in the bottom light-shielding metal layer to make the first sub-line jump in the area where the gate drive circuit and the initial signal line of the frame are located, which can avoid the influence of the first sub-line on the gate drive circuit and the initial signal line of the frame, and facilitates the wiring arrangement, which is conducive to saving space.

[0143] Figure 8 is a partial cross-sectional schematic diagram of the second sub-line shown in Figure 7. In some examples, as shown in Figures 3, 7, and 8, the third segment 3221 and fourth segment 3222 of the second sub-line 322 can be located in the first gate metal layer, and the third crossover 3223 and fourth crossover 3224 can be located in the bottom light-shielding metal layer. The second connecting segment 3225 can, for example, be located in the second source / drain metal layer. The first power border line 51b can, for example, be located in the first source / drain metal layer.

[0144] In some examples, as shown in Figures 7 and 8, the third line segment 3221 of the second sub-line 322 can be electrically connected to one end of the third crossover 3223 through a fifth connection via provided in the first gate insulation layer 103 and the buffer layer 102. The third crossover 3223 can extend from below the first power border line 51b to cross the first power border line 51b. The connection position between the third line segment 3221 and the third crossover 3223 can be located on a side of the first power border line 51b away from the display area. The other end of the third crossover 3223 can be electrically connected to the fourth line segment 3222 through a sixth connection via provided in the first gate insulation layer 103 and the buffer layer 102. The connection position between the third crossover 3223 and the fourth line segment 3222 can be located on a side of the first power border line 51b close to the display area AA. The fourth line segment 3222 can be electrically connected to the second connection segment 3225. For example, the second connection segment 3225 can be electrically connected to the fourth line segment 3222 located in the first gate metal layer through the seventh connection via opened in the second flat layer 107, the first flat layer 106, the interlayer insulating layer 105 and the second gate insulating layer 104.

[0145] Figure 9 is a schematic diagram of the connection between the second sub-line and the pixel circuit according to at least one embodiment of the present disclosure. Figure 10A is a schematic diagram of the pixel circuit after the semiconductor layer is formed in Figure 9. Figure 10B is a schematic diagram of the pixel circuit after the first gate metal layer is formed in Figure 9. Figure 10C is a schematic diagram of the pixel circuit after the second gate metal layer is formed in Figure 9. Figure 10D is a schematic diagram of the pixel circuit after the first source and drain metal layer is formed in Figure 9. The pixel circuit of this example may be the 7T1C pixel circuit shown in the aforementioned embodiment.

[0146] In some examples, as shown in FIG10A , the semiconductor layer of the display area may include: active layers of multiple transistors of the pixel circuit (for example, including: active layer T10 of the first transistor, active layer T20 of the second transistor, active layer T30 of the third transistor, active layer T40 of the fourth transistor, active layer T50 of the fifth transistor, active layer T60 of the sixth transistor, and active layer T70 of the seventh transistor of the pixel circuit in the current row, active layer T70' of the seventh transistor of the pixel circuit in the previous row, and active layer T10' of the first transistor of the pixel circuit in the next row). The active layers of the seven transistors of the pixel circuit may be an interconnected integrated structure.

[0147] In some examples, as shown in FIG10B , the first gate metal layer of the display area may include at least: a first scan line GL1(n), a second scan line GL2(n), a third scan line GL3(n), and a light-emitting control line EML(n). The second scan line GL2(n) can simultaneously serve as the gate of the first transistor T1 of the pixel circuit in this row and the gate of the seventh transistor T7' of the pixel circuit in the previous row. The first scan line GL1(n) can simultaneously serve as the gate of the second transistor T2 and the gate of the fourth transistor T4 of the pixel circuit in this row. The third scan line GL3(n) can simultaneously serve as the gate of the seventh transistor T7 of the pixel circuit in this row and the gate of the first transistor T1' of the pixel circuit in the next row. The light-emitting control line EML(n) can simultaneously serve as the gate of the fifth transistor T5 and the gate of the sixth transistor T6 of the pixel circuit in this row. The first plate 221 of the storage capacitor can simultaneously serve as the gate of the third transistor T3.

[0148] 10C , the second gate metal layer of the display region may include at least: a first initial signal line INIT1, a second plate 222 of the storage capacitor, and a protection block 24. The protection block 24 may prevent other signals from interfering with the data signal.

[0149] In some examples, as shown in FIG10D , the first source-drain metal layer of the display area may include at least a data line DL, a first power line VDD, and a plurality of connection electrodes (e.g., a first connection electrode 251, a second connection electrode 252, a third connection electrode 253, and a fourth connection electrode 254). The first connection electrode 251 may be electrically connected to the active layer T10 of the first transistor T1 and the first initial signal line INIT1. The second connection electrode 252 may be electrically connected to the active layer T20 of the second transistor T2 and the gate electrode of the third transistor T3. The third connection electrode 253 may be electrically connected to the active layer T60 of the sixth transistor T6 and may function as the drain electrode of the sixth transistor T6. The fourth connection electrode 254 may be electrically connected to the first initial signal line INIT1 and the active layer T70 of the seventh transistor T7. The data line DL and the first power line VDD may both extend along the second direction Y. The data line DL may be electrically connected to the active layer of the fourth transistor T4. The first power line VDD may be electrically connected to the protection block 24 , the second plate 222 of the storage capacitor, and the active layer T50 of the fifth transistor T5 .

[0150] In some examples, as shown in FIG9 , the second source-drain metal layer of the display area may include at least a first switching electrode 23 and a second connecting segment 3225 of a second sub-line of a second detection line. The first switching electrode 23 may be electrically connected to the third connecting electrode 253. The second connecting segment 3225 may be electrically connected to the active layer T40 of a data write transistor (i.e., the fourth transistor T4) of a pixel circuit. The second connecting segment 3225 may serve as the source of the data write transistor. A second sub-line 322 may be independently connected to a data write transistor T4 of a pixel circuit, thereby reducing interference with the normal display process.

[0151] The following example illustrates the crack detection method for the display panel of this embodiment. In the following example, the first detection transistor and the second detection transistor are both P-type transistors. However, this embodiment is not limited to this. In other examples, the first detection transistor and the second detection transistor can both be N-type transistors; or the first detection transistor is a P-type transistor and the second detection transistor is an N-type transistor; or the first detection transistor is an N-type transistor and the second detection transistor is a P-type transistor.

[0152] In some examples, as shown in FIG3 , by controlling the voltage Vg1 of the first detection control signal transmitted by the first detection control lines 35a and 35b, the voltage Vg2 of the second detection control signal transmitted by the second detection control lines 37a and 37b, the voltage Vpcd1 of the first test signal transmitted by the first test signal transmission lines 36a and 36b, and the voltage Vpcd2 of the second test signal transmitted by the second test signal transmission lines 38a and 38b, and based on the display effect of the display area, it is possible to determine whether there are cracks in the peripheral area and accurately locate the edge cracks in the peripheral area.

[0153] In some examples, as shown in FIG3 , the first detection transistors M1 and M1′ can be controlled to be turned on by a first detection control signal, and the second detection transistors M2 and M2′ can be controlled to be turned off by a second detection control signal. The first detection transistors M1 and M1′ provide a first test signal to the first detection lines 31a and 31b. The transmission status of the first test signal in the first detection lines 31a and 31b can be determined based on the display effect of the light-emitting elements 62 connected to the first detection lines 31a and 31b in the display area, thereby locating the crack positions in the third border area B3 and the fourth border area B4 in the peripheral area.

[0154] Figures 11A and 11B are schematic diagrams of display patterns for crack detection in the third border area and the fourth border area of ​​at least one embodiment of the present disclosure. In this example, the first detection lines 31a and 31b are each connected to the light-emitting element 62 of a column of sub-pixels as an example. In some examples, during the crack detection process, when there are no cracks in the third border area B3 and the fourth border area B4, the first test signal transmitted by the first detection lines 31a and 31b can be normally provided to the anode of the connected light-emitting element 62, so that the connected light-emitting element 62 displays normally. In some examples, as shown in Figure 11B, the first bright line L1 in the display area can indicate that there are no cracks in the third border area B3, and the second bright line L2 can indicate that there are no cracks in the fourth border area B4. The first bright line L1 and the second bright line L2 can be bright lines that penetrate vertically.

[0155] In some examples, during the crack detection process, when a crack exists in the third frame area B3 or the fourth frame area B4, the first sub-line of the first detection line wound at the crack location cannot transmit the first test signal to the corresponding light-emitting element in the display area. The light-emitting element connected to the first sub-line at the crack location will not be illuminated, and a vertical non-penetrating bright line will appear in the display area, and the bright line at the location corresponding to the crack will be disconnected. As shown in Figure 11A, if a crack occurs at the first location W1 of the third frame area B3, the first sub-line 312a wound at the first location W1 cannot transmit the first test signal to the light-emitting element 62 corresponding to the display area. A first break L10 will exist in the first bright line L1 of the display area. The crack at the first location W1 of the third frame area B3 can be located based on the position of the first break L10. If a crack occurs at the second position W2 of the fourth border area B4, the second sub-line 312b wound at the second position W2 cannot transmit the first test signal to the corresponding light-emitting element in the display area, and a second break L20 will exist on the second bright line L2 of the display area. The crack at the second position W2 of the fourth border area B4 can be located according to the position of the second break L20.

[0156] In some examples, the voltage Vg1 of the first detection control signal is set to -7V, the voltage Vpcd1 of the first test signal is set to 4.6V, the first voltage signal Vdd is 0V, the second voltage signal Vss is 0V, the data voltage Vdata is 0-5V, the voltage Vg2 of the second detection control signal is 7V, and the voltage Vpcd2 of the second test signal is 0V. At this time, the first detection transistors M1 and M1' are turned on, and the second detection transistors M2 and M2' are turned off. In this example, the crack conditions in the third border area B3 and the fourth border area B4 can be determined based on the transmission of the first test signal by the first detection lines 31a and 31b. Since the first detection transistors M1 and M1' are turned on, the voltage Vpcd1 of the first test signal can be transmitted to the first detection lines 31a and 31b, and the first main line 311a of the first detection line 31a and the first main line 311b of the first detection line 31b can transmit the first test signal to the multiple first sub-lines 312a and 312b. Because the first sub-line 312a has a winding design within the third frame area B3, when a crack appears on the edge of the third frame area B3, the first sub-line 312a corresponding to the edge crack position will be disconnected, and the first test signal cannot be transmitted to the corresponding light-emitting element, so that the corresponding light-emitting element will not emit light; the first sub-line 312a at the non-crack position of the third frame area B3 can normally transmit the first test signal to the corresponding light-emitting element, so that the corresponding light-emitting element can emit light normally. Because the first sub-line 312b has a winding design within the fourth frame area B4, when a crack appears on the edge of the fourth frame area B4, the first sub-line 312b corresponding to the edge crack position will be disconnected, and the first test signal cannot be transmitted to the corresponding light-emitting element, so that the corresponding light-emitting element will not emit light; the first sub-line 312b at the non-crack position of the fourth frame area B4 can normally transmit the first test signal to the corresponding light-emitting element, so that the corresponding light-emitting element can emit light normally. This example uses the first detection lines 31a and 31b to accurately locate the crack positions in the third frame area B3 and the fourth frame area B4.

[0157] In some examples, as shown in FIG3 , the first detection transistors M1 and M1′ can be controlled to be disconnected by a first detection control signal, and the second detection transistors M2 and M2′ can be controlled to be turned on by a second detection control signal. The second detection transistors M2 and M2′ provide a second test signal to the second detection line 32. The transmission status of the second test signal in the second detection line 32 can be determined based on the display effect of the light-emitting element connected to the second detection line 32 in the display area, thereby determining whether there is a crack in the second frame area and locating the crack position in the second frame area of ​​the peripheral area.

[0158] FIG12 is a schematic diagram of a display pattern for crack detection in the second border area of ​​at least one embodiment of the present disclosure. In this example, the second detection line 32 is connected to the pixel circuits of the remaining sub-pixels in a row of sub-pixels except for the two ends. In some examples, during the crack detection process, when there is no crack in the second border area B2, the second test signal transmitted by the second detection line 32 can be normally provided to the connected pixel circuit, so that the light-emitting element connected to the pixel circuit does not display. For example, a dark line running horizontally through the display area appears, indicating that there is no crack in the second border area B2.

[0159] In some examples, during the crack detection process, when a crack exists in the second frame area B2, the second sub-line 322 of the second detection line 32 wound at the crack location cannot transmit the second test signal to the pixel circuit corresponding to the display area. In this case, the light-emitting element connected to the pixel circuit 61 connected to the second sub-line 322 at the crack location will be illuminated, and a dark line that does not pass through the horizontal line will appear in the display area. The dark line at the position corresponding to the crack will be disconnected and the bright line will be displayed. As shown in Figure 12, if a crack occurs at the third position W3 of the second frame area B2, the second sub-line 322 wound at the third position W3 cannot transmit the second test signal to the corresponding pixel circuit 61 in the display area, and the display area will display the third bright line L3. Based on the position of the third bright line L3, the crack at the third position W3 of the second frame area B2 can be located.

[0160] In some examples, the voltage Vg1 of the first detection control signal is set to 7V, the voltage Vpcd1 of the first test signal is set to 0V, the voltage Vg2 of the second detection control signal is set to -7V, the voltage Vpcd2 of the second test signal is set to 7V, the first voltage signal Vdd is 4.6V, and the second voltage signal Vss is -2.4. At this time, the first detection transistors M1 and M1' are disconnected, and the second detection transistors M2 and M2' are turned on. This example can determine the crack condition of the second border area B2 based on the transmission of the second test signal by the second detection line 32. Since the second detection transistors M2 and M2' are turned on, the voltage Vpcd2 of the second test signal can be transmitted to the second detection line 32, and the second main line 321 of the second detection line 32 can transmit the second test signal to the multiple second sub-lines 322. Since the second sub-line 322 has a winding design within the second border area B2, when a crack appears at the edge of the second border area B2, the second sub-line 322 corresponding to the edge crack position will be disconnected, and the second test signal cannot be transmitted to the corresponding pixel circuit, so that the light-emitting element connected to the corresponding pixel circuit will be lit. The second sub-line 322 at the non-crack position of the second border area B2 can normally transmit the second test signal to the corresponding pixel circuit, so that the light-emitting element connected to the pixel circuit does not emit light. This example uses the second detection line 322 to determine whether there is a crack in the second border area B2 and accurately locate the crack position in the second border area B2.

[0161] In some examples, during the crack detection process, the voltage Vg1 of the first detection control signal can be set to -7V, and the voltage Vg2 of the second detection control signal can be set to -7V, so that the first detection transistor and the second detection transistor are both turned on, and the display effects of two columns of sub-pixels and one row of sub-pixels are used to determine whether there are cracks in the third border area, the fourth border area, and the second border area and locate the crack positions.

[0162] In some examples, during normal display of the display area, the voltage Vg1 of the first detection control signal can be set to 7V, and the voltage Vg2 of the second detection control signal can be set to 7V, so that both the first detection transistor and the second detection transistor are disconnected to avoid affecting the normal display process.

[0163] In other examples, a second detection line may be set in the first border area of ​​the display panel. The second detection line may be set in a similar manner to the second border area, which is not described in detail in this embodiment.

[0164] The display panel of this example sets a first detection line in the third frame area and the fourth frame area, and sets a second detection line in the second frame area. By utilizing the display effect of the first detection line transmitting the first test signal and the display effect of the second detection line transmitting the second test signal, it is possible to determine whether there is a crack in the frame area, and the location of the crack can be accurately located based on the display effect, thereby improving the efficiency of crack detection.

[0165] FIG13 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG13 , the third border area B3 may be provided with a first detection line 31 a, the fourth border area B4 may be provided with a first detection line 31 b, and the second border area B2 may be provided with a second detection line 32.

[0166] In some examples, as shown in FIG13 , the first detection line 31a may include: a first main line 311a and a plurality of first sub-lines 312a electrically connected to the first main line 311a. The first main line 311a may be located on a side of the gate drive circuit 41a away from the display area AA, and the plurality of first sub-lines 312a may be located on a side of the first main line 311a close to the display area AA. The plurality of first sub-lines 312a may be arranged sequentially along the second direction Y and extend along the first direction X to the display area AA, and be electrically connected one-to-one to the plurality of light-emitting elements 62 within the display area AA. When the first sub-lines 312a pass through the gate drive circuit 41a and the frame initial signal line 42a, a first jumper located in the bottom light-shielding metal layer may be used to implement a jumper to avoid interference and prevent short circuits between different signals.

[0167] In some examples, as shown in FIG13 , the first detection line 31b may include a first main line 311b and a plurality of first sub-lines 312b electrically connected to the first main line 311b. The first main line 311b may be located on a side of the gate drive circuit 41b away from the display area AA, and the plurality of first sub-lines 312b may be located on a side of the first main line 311b close to the display area AA. The plurality of first sub-lines 312b may be arranged sequentially along the second direction Y and extend along the first direction X to the display area AA, and be electrically connected one-to-one to the plurality of light-emitting elements 62 within the display area AA. When the first sub-lines 312b pass through the gate drive circuit 41b and the frame initial signal line 42b, a first jumper located in the bottom light-shielding metal layer may be used to implement a jumper to avoid interference and prevent short circuits between different signals.

[0168] In some examples, as shown in FIG13 , the second detection line 32 may include: a second main line 321 and a plurality of second sub-lines 322 electrically connected to the second main line 321. The second main line 321 may be located on a side of the first power border line 51 b away from the display area AA, and the plurality of second sub-lines 322 may be located on a side of the second main line 321 closer to the display area AA. The plurality of second sub-lines 322 may be arranged sequentially along the first direction X and extend along the second direction Y to the display area AA, and be electrically connected one-to-one to the plurality of pixel circuits 61 within the display area AA. When the second sub-lines 321 pass through the first power border line 51 b, a third jumper located in the bottom light-shielding metal layer may be used to implement a jumper to avoid interference and prevent short circuits between different signals.

[0169] In some examples, during the crack detection process, when a crack exists in the third frame area B3, the first main line 311a and the first sub-line 312a passing through the crack position can no longer transmit the first test signal, and the light-emitting element 62 connected to the crack position and the first sub-line 312a on the side of the crack position away from the first frame area B1 will not receive the first test signal and cannot be illuminated. The display area AA will display a local bright line, and the edge of the third frame area B3 corresponding to the position without a bright line has a crack. When there is no crack in the third frame area B3, the display area AA can display the first bright line L1 as shown in Figure 11B. Similarly, it can be determined whether there is a crack in the fourth frame area B4 and the location of the crack.

[0170] In some examples, during the crack detection process, if a crack exists in the second border region B2, the second main line 321 and second sub-line 322 passing through the crack location can no longer transmit the second test signal. In this case, the light-emitting elements of the pixel circuits connected to the second sub-line 322 that cannot transmit the second test signal are all illuminated, and a corresponding bright line is displayed in the display region AA. The crack location in the second border region B2 can be determined based on the location of the bright line in the display region AA.

[0171] The rest of the description about the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0172] Figure 14 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 14, the third border area B3 may be provided with a first detection line 31a, the first detection line 31a may be electrically connected to the third connection line 314a, and the third connection line 314a may be located in the display area. The fourth border area B4 may be provided with a first detection line 31b, the first detection line 31b may be electrically connected to the third connection line 314b. The third connection line 314b may be located in the display area. In some examples, the third connection line 314a may be located on the side of the second connection line 323a close to the third border area B3, and the third connection line 314b may be located on the side of the second connection line 323b close to the fourth border area B4. In this example, the first detection lines 31a and 31b are not directly connected, but each is connected to the first detection control unit via a third connection line to form a connection loop. This example can avoid occupying the wiring space of the second border area B2.

[0173] The rest of the description about the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0174] FIG15 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG15 , the third border area B3 may be provided with a first detection line 31a, the fourth border area B4 may be provided with a first detection line 31b, and the second border area B2 may be provided with a first detection line 31c. The ends of the first detection line 31c may be electrically connected to the first detection line 31a and the first detection line 31b, respectively. The first detection line 31a may be electrically connected to a first detection control unit 33a, and the first detection line 31b may be electrically connected to a first detection control unit 33b.

[0175] In some examples, as shown in FIG15 , the first detection line 31a may include a first main line 311a and a plurality of first sub-lines 312a. The first main line 311a may be located on a side of the gate drive circuit 41a close to the display area AA, and a portion of each first sub-line 312a (such as the aforementioned first line segment) may be located on a side of the gate drive circuit 41a away from the display area AA. The plurality of first sub-lines 312a may be arranged in sequence along the second direction Y and extend to the display area AA, and be electrically connected to the plurality of pixel circuits 61 in the display area AA in a one-to-one correspondence. When the first sub-line 312a passes through the gate drive circuit 41a and the frame initial signal line 42a, a first cross-line and a second cross-line located in the bottom light-shielding metal layer may be used to implement a jumper to avoid interference and prevent short circuits between different signals.

[0176] In some examples, as shown in FIG15 , the first detection line 31b may include a first main line 311b and a plurality of first sub-lines 312b electrically connected to the first main line 311b. The first main line 311b may be located on a side of the gate drive circuit 41b close to the display area AA, and a portion of each first sub-line 312b may be located on a side of the gate drive circuit 41b away from the display area AA. The plurality of first sub-lines 312b may be arranged sequentially along the second direction Y and extend to the display area AA, and be electrically connected one-to-one to the plurality of pixel circuits 61 within the display area AA. When the first sub-lines 312b pass through the gate drive circuit 41b and the frame initial signal line 42b, a first jumper and a second jumper located in the bottom light-shielding metal layer may be used to implement a jumper to avoid interference and prevent short circuits between different signals.

[0177] In some examples, as shown in FIG15 , the first detection line 31c can include a first main line 311c and a plurality of first sub-lines 312c electrically connected to the first main line 311c. The first main line 311c can be located on a side of the first power border line 51b close to the display area AA. The plurality of first sub-lines 312c can be arranged sequentially along the second direction Y and extend to the display area AA, electrically connected one-to-one to the plurality of pixel circuits 61 within the display area AA. When the first sub-lines 312c pass through the first power border line 51b, they can be jumpered using a jumper located in the bottom light-shielding metal layer to avoid interference and prevent short circuits between different signals.

[0178] In some examples, during the crack detection process, the presence of cracks in the third frame area, the fourth frame area, and the second frame area and the location of the cracks can be determined based on the display conditions of the two columns of sub-pixels and the row of sub-pixels connected to the first detection lines 31a, 31b, and 31c. In this example, the crack position can be located based on the position of the bright line in the display area during the crack detection process. However, this embodiment is not limited to this. In other examples, the first main line of the first detection line can be located on the side of the multiple first sub-lines away from the display area.

[0179] The rest of the description about the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0180] Figure 16 is a schematic diagram of another display panel of at least one embodiment of the present disclosure. In some examples, as shown in Figure 16, the third frame area B3 can be provided with a first detection line 31a, the fourth frame area B4 can be provided with a first detection line 31b, and the second frame area B2 can be provided with a first detection line 31c. The two ends of the first detection line 31c can be electrically connected to the first detection line 31a and the first detection line 31b, respectively. The first detection line 31a can be electrically connected to the first detection control unit 33a, and the first detection line 31b can be electrically connected to the first detection control unit 33b. The first detection lines 31a, 31b and 31c are respectively electrically connected to the anodes of the light-emitting elements 62 of the multiple sub-pixels in the display area. This example can locate the crack position based on the position of the dark line in the display area during the crack detection process. However, this embodiment is not limited to this. In other examples, the first main line of the first detection line can be located on the side of the multiple first sub-lines away from the display area.

[0181] The rest of the description about the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0182] Figure 17 is a schematic plan view of another display panel according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 17, a display area AA may include: a plurality of sub-pixels PX, a plurality of data lines DL extending along a first direction X, and a plurality of first power lines VDD extending along a second direction Y. The plurality of data lines DL may be arranged sequentially along the second direction Y, and the plurality of first power lines VDD may be arranged sequentially along the first direction X. Each data line DL may be electrically connected to the pixel circuits of the plurality of sub-pixels arranged along the first direction X and configured to provide data signals to the plurality of pixel circuits. Each first power line VDD may be electrically connected to the pixel circuits of the plurality of sub-pixels arranged along the second direction Y and configured to provide a first voltage signal to the plurality of sub-pixels. In some examples, the data lines DL and the first power lines VDD may be located in different film layers to avoid mutual interference. For example, the data lines DL may be located in the first source / drain metal layer, and the first power lines VDD may be located in the second source / drain metal layer; alternatively, the data lines DL may be located in the second source / drain metal layer, and the first power lines VDD may be located in the first source / drain metal layer.

[0183] Figure 18 is a schematic diagram of another display panel of at least one embodiment of the present disclosure. In some examples, as shown in Figure 18, multiple data lines DL in the display area AA extend along the first direction X, and multiple first power lines VDD extend along the second direction Y. The third frame area B3 can be provided with a data supply bus (or data supply circuit) 43a and a gate drive circuit 41a. The data supply bus 43a can be located on the side of the gate drive circuit 41a close to the display area AA. The fourth frame area B4 can be provided with a data supply bus 43b and a gate drive circuit 41b. The data supply bus 43b can be located on the side of the gate drive circuit 41b close to the display area AA. The multiple data lines DL in the display area AA can be electrically connected to the data supply buses 43a and 43b. The data supply buses 43a and 43b can be electrically connected to the multiple data pins in the signal access area B11. The integrated circuit provided in the signal access area B11 can be configured to provide data signals through multiple data pins.

[0184] In some examples, as shown in FIG18 , the third border area B3 may be provided with a first detection line 31a. The first detection line 31a may include a first main line 311a and multiple first sub-lines 312a. The first main line 311a may be located on the side of the data supply bus 43a closest to the display area AA. The multiple first sub-lines 312a may be arranged sequentially along the second direction Y and electrically connected to the first main line 311a. For example, the first sub-lines 312a may extend in the first direction X toward the side of the first main line 311a away from the display area AA until they reach the side of the gate drive circuit 41a away from the display area AA. The first sub-lines 312a then wind back along the first direction X toward the side closest to the display area AA, ultimately extending to electrically connect to a data line DL. The multiple first sub-lines 312a and the multiple data lines DL may be electrically connected in a one-to-one correspondence. The connection point between the first sub-lines 312a and the data lines DL may be located on the side of the first main line 311a closest to the display area AA, or may be located within the display area AA. The first sub-line 312a can be jumpered by first and second jumpers located on the bottom light shielding metal layer when passing through the gate driving circuit 41a and the data supply bus 43a to avoid interference and short circuit between different signals.

[0185] In some examples, as shown in FIG18 , the fourth border area B4 may be provided with a first detection line 31b. The first detection line 31b may include a first main line 311b and multiple first sub-lines 312b. The first main line 311b may be located on the side of the data supply bus 43b closest to the display area AA. The multiple first sub-lines 312b may be arranged sequentially along the second direction Y and electrically connected to the first main line 311b. For example, the first sub-lines 312b may extend in the first direction X toward the side of the first main line 311b away from the display area AA until they reach the side of the gate drive circuit 41b away from the display area AA. The first sub-lines 312b may then rewind and extend along the first direction X toward the side closest to the display area AA, ultimately extending to electrically connect to a data line DL. The multiple first sub-lines 312b and the multiple data lines DL may be electrically connected in a one-to-one correspondence. The connection point between the first sub-lines 312b and the data lines DL may be located on the side of the first main line 311b closest to the display area AA, or may be located within the display area AA. The first sub-line 312b can be jumpered by first and second jumpers located on the bottom light shielding metal layer when passing through the gate driving circuit 41b and the data supply bus 43b to avoid interference and short circuit between different signals.

[0186] In some examples, as shown in FIG18 , the second border area B2 may be provided with a first power border line 51b and a second detection line 32. The second detection line 32 may be electrically connected to the second detection control unit 34a via a second connection line 323a located in the display area AA, and electrically connected to the second detection control unit 34b via a second connection line 323b located in the display area AA. The second detection line 32 may include: a second main line 321 and a plurality of second sub-lines 322. The second main line 321 may be located on the side of the first power border line 51b close to the display area AA. A portion of each second sub-line 322 (such as the aforementioned third segment) may be located on the side of the first power border line 51b away from the display area AA. After connecting to the second main line 321, each second sub-line 322 extends along the second direction Y away from the display area AA until it passes through the first power border line 51b, then winds along the second direction Y toward the side close to the display area AA, and ultimately extends to electrically connect to a first power line VDD within the display area AA. The plurality of second sub-lines 322 and the plurality of first power lines VDD can be electrically connected one by one. When the second sub-lines 322 pass through the first power border line 51b, they can be jumpered using the third and fourth jumper wires located in the bottom light-shielding metal layer to avoid interference and prevent short circuits between different signals.

[0187] In some examples, the number of data lines connected to the first detection line 31a and the number of data lines connected to the first detection line 31b can be the same. The multiple data lines connected to the first detection line 31a and the multiple data lines connected to the first detection line 31b can be the same. However, this embodiment is not limited to this. The multiple data lines connected to the first detection line 31a can be different from the multiple data lines connected to the first detection line 31b, so as to better distinguish the crack locations in the third border area B3 and the fourth border area B4. This example does not limit the number of data lines connected to the first detection line 31a and the number of first power lines connected to the second detection line 31b.

[0188] The following is an example of the crack detection method for a display panel of this embodiment, in which the first detection transistor and the second detection transistor are both P-type transistors.

[0189] In some examples, as shown in FIG18 , during the crack detection process, when there are no cracks in the third frame area B3 and the fourth frame area B4, the first test signal transmitted by the first detection lines 31a and 31b can be normally provided to the connected data lines DL, so that the sub-pixels connected to the data lines DL do not emit light, and the display area AA can display multiple dark lines. When there is a crack in the third frame area B3 or the fourth frame area B4, the first sub-line of the first detection line wound at the crack position cannot transmit the first test signal to the corresponding data line, so that the sub-pixels connected to the data lines corresponding to the crack position will be illuminated, and the display area AA will display the corresponding bright line. In this way, whether there are cracks in the third frame area B3 and the fourth frame area B4 and the crack positions in the third frame area B3 and the fourth frame area B4 can be determined based on the positions of the horizontal bright lines in the display area.

[0190] In some examples, the voltage Vg1 of the first detection control signal is set to -7V, the voltage Vpcd1 of the first test signal is set to 7V, the voltage Vg2 of the second detection control signal is set to 7V, the voltage Vpcd2 of the second test signal is set to 0V, and the data voltage Vdata is 7V. At this time, the first detection transistors M1 and M1' are turned on, and the second detection transistors M2 and M2' are turned off. When there are no cracks in the third frame area B3 and the fourth frame area B4, the display area is displayed as a dark line; when there is a crack in the third frame area B3 or the fourth frame area B3, the corresponding position of the display area is displayed as a bright line. In this way, the crack positions of the third frame area B3 and the fourth frame area B4 can be located according to the bright line positions of the display area.

[0191] In some examples, as shown in FIG18 , during the crack detection process, when there is no crack in the second border area B2, the second test signal transmitted by the second detection line 32 can be normally provided to the connected first power line VDD, for example, so that the sub-pixel connected to the first power line VDD can be displayed normally. When there is a crack in the second border area B2, the second test signal transmitted by the second detection line 32 cannot be provided to the connected first power line VDD, for example, so that the sub-pixel connected to the first power line VDD cannot be displayed normally. In this way, the crack position of the second border area B2 can be located according to the position of the dark line in the display area. However, this embodiment is not limited to this. In other examples, when there is no crack in the second border area B2, the second test signal can be used to make the sub-pixel connected to the first power line VDD not display, and when there is a crack in the second border area B2, the sub-pixel connected to the first power line VDD is displayed, thereby locating the crack position according to the position of the bright line in the display area.

[0192] In some examples, the voltage Vg1 of the first detection control signal is set to 7V, the voltage Vpcd1 of the first test signal is set to 0V, the voltage Vg2 of the second detection control signal is set to -7V, the voltage Vpcd2 of the second test signal is set to 4.6V, and the first terminal voltage signal Vdd and the second voltage signal Vss are both 0V. At this time, the first detection transistors M1 and M1' are disconnected, and the second detection transistors M2 and M2' are turned on. When there is no crack in the second frame area B2, the display area can display a bright line; when there is a crack in the second frame area B2, the corresponding position of the display area can display a dark line. In this way, the crack position of the second frame area B2 can be located according to the position of the dark line in the display area.

[0193] In some examples, during the crack detection process, the voltage Vg1 of the first detection control signal can be set to -7V, and the voltage Vg2 of the second detection control signal can be set to -7V, so that the first detection transistor and the second detection transistor are both turned on, and the display effects of sub-pixels in different rows and columns are used to determine whether there are cracks in the third border area, the fourth border area, and the second border area, and the crack positions are located.

[0194] The display panel of this example sets a first detection line in the third frame area and the fourth frame area, and sets a second detection line in the second frame area. By using the display effect of the first detection line transmitting the first test signal to the data line and the display effect of the second detection line transmitting the second test signal to the first power line, it can be determined whether there is a crack in the frame area, and the position of the crack can be accurately located according to the display effect, thereby improving the efficiency of crack detection.

[0195] FIG19 is a schematic diagram of another display panel according to at least one embodiment of the present disclosure. In some examples, as shown in FIG19 , the third border area B3 may be provided with a first detection line 31 a, the fourth border area B4 may be provided with a first detection line 31 b, and the second border area B2 may be provided with a second detection line 32.

[0196] In some examples, as shown in FIG19 , the first detection line 31a can include a first main line 311a and multiple first sub-lines 312a electrically connected to the first main line 311a. The first main line 311a can be located on a side of the gate driver circuit 41a away from the display area AA, and the multiple first sub-lines 312a can be located on a side of the first main line 311a closer to the display area AA. The multiple first sub-lines 312a can be arranged sequentially along the second direction Y and extend along the first direction X to the display area AA, and can be electrically connected one-to-one to the multiple data lines DL within the display area AA. When passing through the gate driver circuit 41a and the data supply bus 43a, the first sub-lines 312a can be jumpered using a first jumper located in the bottom light-shielding metal layer to avoid interference and prevent short circuits between different signals.

[0197] In some examples, as shown in FIG19 , the first detection line 31b can include a first main line 311b and a plurality of first sub-lines 312b electrically connected to the first main line 311b. The first main line 311b can be located on a side of the gate driver circuit 41b away from the display area AA, and the plurality of first sub-lines 312b can be located on a side of the first main line 311b closer to the display area AA. The plurality of first sub-lines 312b can be arranged sequentially along the second direction Y and extend along the first direction X to the display area AA, and can be electrically connected one-to-one to the plurality of data lines DL within the display area AA. When passing through the gate driver circuit 41b and the data supply bus 43b, the first sub-lines 312b can be implemented as jumpers using a first jumper located in the bottom light-shielding metal layer to avoid interference and prevent short circuits between different signals.

[0198] In some examples, as shown in FIG19 , the second detection line 32 may include: a second main line 321 and a plurality of second sub-lines 322 electrically connected to the second main line 321. The second main line 321 may be located on a side of the first power border line 51b away from the display area AA, and the plurality of second sub-lines 322 may be located on a side of the second main line 321 closer to the display area AA. The plurality of second sub-lines 322 may be arranged sequentially along the first direction X and extend along the second direction Y to the display area AA, and be electrically connected one-to-one to the plurality of first power lines VDD within the display area AA. When the second sub-lines 321 pass through the first power border line 51b, a third jumper located in the bottom light-shielding metal layer may be used to implement a jumper to avoid interference and prevent short circuits between different signals.

[0199] In some examples, during the crack detection process, when a crack exists in the third frame area B3, the first main line 311a and the first sub-line 312a passing through the crack position can no longer transmit the first test signal. The crack position and the data line DL connected to the first sub-line 312a on the side of the crack position away from the first frame area B1 will not receive the first test signal, and the sub-pixel connected to the data line DL will be lit. The edge of the third frame area B3 corresponding to the position of the bright line in the display area has a crack. When there is no crack in the third frame area B3, the display area can display a dark line. Similarly, it can be determined whether there is a crack in the fourth frame area B4 and the location of the crack.

[0200] In some examples, during crack detection, if a crack exists in the second border region B2, the second main line 321 and second sub-line 322 passing through the crack location cannot continue to transmit the second test signal. Consequently, the light-emitting element connected to the first power line at the location where the second sub-line 322 cannot transmit the second test signal cannot be illuminated, and a dark line is displayed in the display region AA. The crack location in the second border region B2 can be determined based on the location of the dark line in the display region AA.

[0201] The rest of the description about the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0202] This embodiment also provides a crack detection method, which is applied to the display panel as described above. The crack detection method includes: providing a first test signal to a first detection line through a first detection control unit; and determining whether there is a crack in the surrounding area and the location of the crack based on the luminous state of multiple sub-pixels electrically connected to the first detection line.

[0203] In some exemplary embodiments, the crack detection method of this example may further include: providing a second test signal to a second detection line through a second detection control unit; and determining whether there is a crack in the peripheral area and the location of the crack based on the luminous state of multiple sub-pixels electrically connected to the second detection line.

[0204] The description of the crack detection method of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0205] This embodiment also provides a display panel, comprising: a substrate, a plurality of sub-pixels, at least one first detection line, and at least one first detection control unit. The substrate includes a display area and a peripheral area located outside the display area. A plurality of sub-pixels are located in the display area. At least one first detection line and at least one first detection control unit are located in the peripheral area, the at least one first detection control unit being electrically connected to the at least one first detection line and configured to provide a first test signal to the at least one first detection line. The at least one first detection line is electrically connected to the plurality of sub-pixels in the display area. The at least one first detection line comprises: a first main line, and a plurality of first sub-lines electrically connected to the first main line, the plurality of first sub-lines extending to the display area, each first sub-line being electrically connected to at least one sub-pixel in the display area. A portion of a line segment of at least one of the plurality of first sub-lines is located on a side of the first main line away from the display area. For example, a portion of a line segment of each of the plurality of first sub-lines (such as the first line segment in the aforementioned embodiment) may be located on a side of the first main line away from the display area.

[0206] In some exemplary embodiments, a gate drive circuit may be further provided in the peripheral area. The first main line may be located on a side of the gate drive circuit close to the display area, and a portion of each first sub-line may be located on a side of the gate drive circuit away from the display area.

[0207] In some exemplary embodiments, the display panel may further include: a second detection line located in the peripheral area and at least one second detection control unit, the at least one second detection control unit being electrically connected to the second detection line and configured to provide a second test signal to the second detection line. The second detection line is electrically connected to a plurality of sub-pixels in the display area. The manner in which the second detection line is connected to the plurality of sub-pixels in the display area is different from the manner in which the first detection line is connected to the plurality of sub-pixels in the display area. In some examples, as shown in FIG3 , the first detection line may be electrically connected to the anodes of the light-emitting elements of the plurality of sub-pixels, and the second detection line may be electrically connected to the sources of the data writing transistors of the pixel circuits of the plurality of sub-pixels. In other examples, as shown in FIG18 , the first detection line may be electrically connected to a plurality of data lines, and the second detection line may be electrically connected to a plurality of first power lines.

[0208] In some exemplary embodiments, the second detection line may include: a second main line and a plurality of second sub-lines electrically connected to the second main line; each second sub-line is electrically connected to at least one sub-pixel in the display area, and the plurality of second sub-lines are sequentially arranged along an extension direction of the second main line. The extension direction of the second main line intersects an extension direction of the first main line of the first detection line.

[0209] The description of the display panel of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0210] Figure 20 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 20 , this embodiment provides a display device comprising: a display panel 91; and a sensor 92 located on the light-emitting side of the light-emitting structure layer, away from the display panel 91. Sensor 92 may be located on the non-display surface of the display panel 91. The orthographic projection of sensor 92 on the display panel 91 may overlap with the first display area A1.

[0211] In some exemplary embodiments, the display panel 91 may be a flexible OLED display panel, a QLED display panel, a Micro-LED display panel, or a Mini-LED display panel. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as business query equipment for e-government, banks, hospitals, power departments, etc.), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0212] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

Claims

1. A display panel, comprising: A substrate, comprising a display area and a peripheral area located outside the display area; A plurality of sub-pixels and a plurality of data lines are located in the display area, the plurality of sub-pixels are electrically connected to the plurality of data lines, at least one of the plurality of sub-pixels comprises: a pixel circuit and a light-emitting element, the pixel circuit is electrically connected to the light-emitting element and is configured to drive the light-emitting element to emit light; At least one first detection line and at least one first detection control unit are located in the peripheral area, the at least one first detection control unit is electrically connected to the at least one first detection line and is configured to provide a first test signal to the at least one first detection line; The at least one first detection line is electrically connected to the plurality of sub-pixels in the display area in any of the following ways: The at least one first detection line is electrically connected to anodes of light-emitting elements of a plurality of sub-pixels in the display area; The at least one first detection line is electrically connected to sources of data writing transistors of pixel circuits of a plurality of sub-pixels in the display area; The at least one first detection line is electrically connected to multiple data lines in the display area, at least one of the multiple data lines is electrically connected to multiple sub-pixels arranged along a first direction, and the at least one first detection line is at least located in the peripheral area on two opposite sides of the display area along the first direction.

2. The display panel according to claim 1, wherein: The at least one first detection line includes: a first main line and a plurality of first sub-lines electrically connected to the first main line, each first sub-line being electrically connected to at least one sub-pixel of the display area; the plurality of first sub-lines are arranged in sequence along an extension direction of the first main line.

3. The display panel according to claim 2, wherein: The peripheral area is also provided with a gate drive circuit; The first main line is located at a side of the gate driving circuit close to the display area, and a portion of each first sub-line is located at a side of the gate driving circuit away from the display area.

4. The display panel according to claim 2, wherein: The peripheral area is also provided with a gate drive circuit; The first main line is located at a side of the gate driving circuit away from the display area, and the plurality of first sub-lines are located at a side of the first main line close to the display area.

5. The display panel according to any one of claims 2 to 4, wherein: The plurality of sub-pixels electrically connected to the plurality of first sub-lines of the first detection line include: a plurality of sub-pixels in the display area that are closest to the first main line and arranged along the extension direction of the first main line.

6. The display panel according to claim 3 or 4, wherein: Each first sub-line includes at least: a first line segment, a second line segment and a first cross-line, wherein two ends of the first cross-line are electrically connected to the first line segment and the second line segment respectively, the first line segment is located on a side of the gate drive circuit away from the display area, the second line segment is located on a side of the gate drive circuit close to the display area, and the orthographic projection of the first cross-line on the substrate at least partially overlaps with the orthographic projection of the gate drive circuit on the substrate; the first cross-line is located on a side of the first line segment and the second line segment close to the substrate.

7. The display panel according to claim 6, wherein: In a direction perpendicular to the display panel, the display panel at least comprises: a substrate and a bottom light-shielding metal layer, a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer arranged on the substrate; The first crossing line is located in the bottom light-shielding metal layer, and the first line segment and the second line segment are located in the first gate metal layer.

8. The display panel according to any one of claims 2 to 7, wherein: The at least one first detection control unit includes: a first detection transistor, a gate of the first detection transistor is electrically connected to a first detection control line, a first electrode of the first detection transistor is electrically connected to a first test signal transmission line, and a second electrode of the first detection transistor is electrically connected to the first detection line.

9. The display panel according to any one of claims 2 to 8, further comprising: a second detection line and at least one second detection control unit located in the peripheral area; The at least one second detection control unit is electrically connected to the second detection line and is configured to provide a second test signal to the second detection line; The second detection line is electrically connected to a plurality of sub-pixels in the display area; The connection mode between the second detection line and the plurality of sub-pixels in the display area is different from the connection mode between the first detection line and the plurality of sub-pixels in the display area.

10. The display panel according to claim 9, wherein: The second detection line includes: a second main line and a plurality of second sub-lines electrically connected to the second main line; each second sub-line is electrically connected to at least one sub-pixel of the display area, and the plurality of second sub-lines are arranged in sequence along the extension direction of the second main line; An extending direction of the second main line intersects with an extending direction of the first main line of the first detection line.

11. The display panel according to claim 10, wherein: The plurality of first sub-lines of the at least one first detection line are electrically connected to anodes of light-emitting elements of a plurality of sub-pixels in the display area in a one-to-one correspondence; The plurality of second sub-lines of the second detection line are electrically connected to sources of data writing transistors of pixel circuits of a plurality of sub-pixels in the display area in a one-to-one correspondence.

12. The display panel according to claim 10, wherein: The plurality of first sub-lines of the at least one first detection line are electrically connected to the plurality of data lines of the display area in a one-to-one correspondence; the plurality of data lines extend along the first direction; The plurality of second sub-lines of the second detection line are electrically connected to the plurality of first power lines of the display area in a one-to-one correspondence, and the plurality of first power lines extend along a second direction, and the second direction intersects the first direction.

13. The display panel according to claim 10, wherein: The peripheral area is also provided with a first power border line; The second main line is located on a side of the first power frame line close to the display area, and a portion of each second sub-line is located on a side of the first power frame line away from the display area.

14. The display panel according to claim 10, wherein: The peripheral area is also provided with a first power border line; The second main line is located on a side of the first power frame line away from the display area, and the plurality of second sub-lines are located on a side of the second main line close to the display area.

15. The display panel according to claim 10, wherein: The plurality of sub-pixels electrically connected to the plurality of second sub-lines of the second detection line include: a plurality of sub-pixels in the display area that are closest to the second main line and arranged along the extension direction of the second main line.

16. The display panel according to claim 13 or 14, wherein: Each second sub-line at least includes: a third line segment, a fourth line segment and a third cross-line, wherein two ends of the third cross-line are electrically connected to the third line segment and the fourth line segment respectively, the third line segment is located on a side of the first power border line away from the display area, the fourth line segment is located on a side of the first power border line close to the display area, and the orthographic projection of the third cross-line on the substrate at least partially overlaps with the orthographic projection of the first power border line on the substrate; the third cross-line is located on a side of the third line segment and the fourth line segment close to the substrate.

17. The display panel according to claim 16, wherein: In a direction perpendicular to the display panel, the display panel at least comprises: a substrate and a bottom light-shielding metal layer, a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer and a second source-drain metal layer arranged on the substrate; The third line jumper is located in the bottom light shielding metal layer, and the third line segment and the fourth line segment are located in the first gate metal layer.

18. The display panel according to any one of claims 9 to 17, wherein: The second detection control unit includes: a second detection transistor, a gate of the second detection transistor is electrically connected to a second detection control line, a first electrode of the second detection transistor is electrically connected to a second test signal transmission line, and a second electrode of the second detection transistor is electrically connected to the second detection line.

19. A display device comprising the display panel according to any one of claims 1 to 18.

20. A crack detection method, applied to the display panel according to any one of claims 1 to 18, the crack detection method comprising: Providing a first test signal to the first detection line through a first detection control unit; Whether there is a crack in the peripheral area and the position of the crack are determined according to the light emitting states of a plurality of sub-pixels electrically connected to the first detection line.

21. The crack detection method according to claim 20, further comprising: Providing a second test signal to the second detection line through a second detection control unit; Whether there is a crack in the peripheral area and the position of the crack are determined according to the light emitting states of a plurality of sub-pixels electrically connected to the second detection line.

22. A display panel comprising: A substrate, comprising a display area and a peripheral area located outside the display area; A plurality of sub-pixels are located in the display area; At least one first detection line and at least one first detection control unit are located in the peripheral area, the at least one first detection control unit is electrically connected to the at least one first detection line and is configured to provide a first test signal to the at least one first detection line; The at least one first detection line is electrically connected to a plurality of sub-pixels in the display area; The at least one first detection line comprises: a first main line, and a plurality of first sub-lines electrically connected to the first main line, the plurality of first sub-lines extending to the display area, each first sub-line electrically connected to at least one sub-pixel of the display area; A portion of at least one first sub-line among the plurality of first sub-lines is located at a side of the first main line away from the display area.

23. The display panel according to claim 22, wherein: The peripheral area is also provided with a gate drive circuit; The first main line is located at a side of the gate driving circuit close to the display area, and a portion of each first sub-line is located at a side of the gate driving circuit away from the display area.

24. The display panel according to claim 22, further comprising: a second detection line and at least one second detection control unit located in the peripheral area, wherein the at least one second detection control unit is electrically connected to the second detection line and configured to provide a second test signal to the second detection line; The second detection line is electrically connected to a plurality of sub-pixels in the display area; The connection mode between the second detection line and the plurality of sub-pixels in the display area is different from the connection mode between the first detection line and the plurality of sub-pixels in the display area.

25. The display panel according to claim 24, wherein: The second detection line includes: a second main line and a plurality of second sub-lines electrically connected to the second main line; each second sub-line is electrically connected to at least one sub-pixel of the display area, and the plurality of second sub-lines are arranged in sequence along the extension direction of the second main line; An extending direction of the second main line intersects with an extending direction of the first main line of the first detection line.

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