Dynamic performance of on-chip current sensor

Abstract

The semiconductor device includes a device region and an on-chip sensor region, such as an on-chip current sensor region. The semiconductor device also includes a transition region formed between the device region and the sensor region. A gate contact extends across the transition region. A conductive segment may be formed on the gate contact in the transition region to reduce the resistivity of the material used to form the gate contact. Additionally or alternatively, an isolation region may be formed under the gate contact between a first isolated well region in the device region and a second isolated well region in the sensor region. An isolation region isolates the first isolation well region from the second isolation well region to prevent current in the device region from propagating into the sensor region.

Description

[0001] Priority claim

[0002] This application claims priority to U.S. patent application serial number 17 / 736,720 filed in the U.S. Patent and Trademark Office on May 4, 2022, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices, and in particular, to semiconductor devices having on-chip current sensors. Background Art

[0004] Semiconductor devices are ubiquitous in modern electronics. Wide-bandgap semiconductor material systems such as gallium nitride (GaN) and silicon carbide (SiC) are increasingly used in semiconductor devices to push the boundaries of device performance in areas such as switching speed, power handling capability, and thermal conductivity. Examples include individual devices such as metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), Schottky barrier diodes, PiN diodes, high electron mobility transistors (HEMTs), and integrated circuits such as monolithic microwave integrated circuits (MMICs) that include one or more individual devices.

[0005] Current sensing in semiconductor devices for power switching applications is a method of monitoring the operating load current to detect possible failure mechanisms such as overcurrent or short circuit events. In the example of a MOSFET or metal insulator semiconductor field effect transistor (MISFET), current sensing can be achieved by providing separate source contacts for a small number of active area unit cells. The separate source contacts are arranged to form separate paths for a proportionally small amount of the overall device load current. The amount of load current along the separate paths can be measured and used to calculate the total load current along the rest of the semiconductor device. Although current sensing arrangements in semiconductor devices have been proposed, conventional structures may not be suitable for withstanding the various adverse operating conditions that may be experienced. Summary of the invention

[0006] The present disclosure relates to semiconductor devices. The semiconductor device may include a device region and a sensor region, for example, a current sensor region that occupies a portion of the entire active area of ​​the semiconductor device. The current sensor region may be configured to monitor a device load current in the device region during operation. The semiconductor device also includes a transition region formed between the device region and the sensor region. The gate contact extends across the transition region. A conductive segment may be formed on the gate contact in the transition region to reduce the resistivity of the material used to form the gate contact. Additionally or alternatively, an isolation region may be formed below the gate contact between a first isolation well region in the device region and a second isolation well region in the sensor region. The isolation region isolates the first isolation well region from the second isolation well region to prevent current in the device region from propagating into the sensor region.

[0007] In one aspect, a vertical semiconductor device includes a drift region, a device region including a first portion of the drift region, and a sensor region including a second portion of the drift region. A transition region is formed between the device region and the sensor region. The transition region includes a gate contact and a conductive segment on and in direct contact with the gate contact.

[0008] In another aspect, a vertical semiconductor device includes a drift region, a device region including a first portion of the drift region, and a sensor region including a second portion of the drift region. A transition region is formed between the device region and the sensor region. The transition region includes a gate contact and an isolation region below the gate contact. In one embodiment, the isolation region is between a first isolation well region in the first portion of the drift region and a second isolation well region in the second portion of the drift region.

[0009] In yet another aspect, a vertical semiconductor device includes a drift region, a device region including a first portion of the drift region, and a sensor region including a second portion of the drift region. A transition region is formed between the device region and the sensor region. The transition region includes a gate contact, a conductive segment on and in direct contact with the gate contact, and an isolation region below the gate contact between a first isolation well region in the first portion of the drift region and a second isolation well region in the second portion of the drift region.

[0010] In another aspect, a vertical silicon carbide (SiC) device includes a device region and a sensor region. A transition region is between the device region and the sensor region. The vertical SiC device can be operated to detect a short circuit event in less than one microsecond, in one to three microseconds, in one to five microseconds, or in less than ten microseconds.

[0011] In yet another aspect, a vertical semiconductor device includes a drift region and a device region including a first portion of the drift region. One or more sensor regions each include a second portion of the drift region. Each sensor region includes one or more sensors. Each sensor in a corresponding sensor region is equidistant from a corresponding gate contact that is electrically connected to the one or more sensors in the corresponding sensor region.

[0012] In other aspects, for additional advantages, any of the above aspects, alone or together and / or various individual aspects and features as described herein can be combined. Unless otherwise indicated herein, any of the various features and elements disclosed herein can be combined with one or more other disclosed features and elements.

[0013] After reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will understand the scope of the present disclosure and implement additional aspects thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and together with the description serve to explain the principles of the disclosure.

[0015] Figure 1 illustrates a top view layout of an example semiconductor device according to an embodiment of the present disclosure;

[0016] Figure 2A A first equivalent circuit for implementation of a current sensor for a metal oxide semiconductor field effect transistor (MOSFET) device or a metal insulator semiconductor field effect transistor (MISFET) device according to an embodiment of the present disclosure is illustrated;

[0017] Figure 2B A second equivalent circuit for implementation of a current sensor for a MOSFET device or a MISFET device according to an embodiment of the present disclosure is illustrated;

[0018] Figure 3 illustrates a cross-sectional view of a portion of a semiconductor device including a sensor contact integrated within the semiconductor device;

[0019] Figure 4 The diagram shows Figure 3 a cross-sectional view of a portion of a first semiconductor device similar to the semiconductor device of and further comprising a protection structure disposed in the transition region;

[0020] Figure 5 illustrates a top view of a portion of a semiconductor device according to an embodiment of the present disclosure;

[0021] Figure 6 illustrates a cross-sectional view of a portion of a second semiconductor device including a conductive segment formed on a gate contact according to an embodiment of the present disclosure;

[0022] Figure 7 The present invention is illustrated in accordance with an embodiment of the present disclosure. Figure 4 The first semiconductor device and Figure 6a cross-sectional view of a portion of a third semiconductor device that is similar to the second semiconductor device and includes an insulating layer forming a non-planar shape;

[0023] Figure 8 The present invention is illustrated in accordance with an embodiment of the present disclosure. Figure 4 The first semiconductor device and Figure 6 a cross-sectional view of a portion of a fourth semiconductor device that is similar to the second semiconductor device of FIG. 1 and includes an insulating layer formed to cover a larger portion of a top surface of the drift region;

[0024] Fig. 9 The present invention is illustrated in accordance with an embodiment of the present disclosure. Figure 4 a cross-sectional view of a portion of a fifth semiconductor device that is similar to the first semiconductor device and includes an isolation region between the first isolation well region and the second isolation well region;

[0025] Fig. 10A a diagram illustrating the conduction time of the current sensor and the device MOSFET;

[0026] Fig. 10B a graph illustrating the turn-off time of the current sensor and the device MOSFET;

[0027] Fig.11 The present invention is illustrated in accordance with an embodiment of the present disclosure. Fig. 9 a cross-sectional view of a portion of a sixth semiconductor device similar to the fifth semiconductor device of and operable to detect one or more events in one or more device MOSFETs;

[0028] Fig.12 The present invention is illustrated in accordance with an embodiment of the present disclosure. Figure 7 The third semiconductor device and Fig. 9 a cross-sectional view of a portion of a seventh semiconductor device that is similar to the fifth semiconductor device of FIG. 1 and includes an insulating layer and an isolation region forming a non-planar shape;

[0029] Fig.13 The present invention is illustrated in accordance with an embodiment of the present disclosure. Figure 8 The fourth semiconductor device and Fig. 9 a cross-sectional view of a portion of an eighth semiconductor device that is similar to the fifth semiconductor device of and includes an insulating layer and an isolation region formed to cover a larger portion of a top surface of the drift region;

[0030] Fig.14 illustrates an example first layout of sensor areas;

[0031] Fig.15 illustrates an example second layout of sensor regions according to an embodiment of the present disclosure;

[0032] Fig.16illustrates an example third layout of sensor regions according to an embodiment of the present disclosure; and

[0033] Fig.17 An example fourth layout of first and second sensor regions according to an embodiment of the present disclosure is illustrated. DETAILED DESCRIPTION

[0034] The embodiments described below represent the necessary information to enable those skilled in the art to practice the embodiments, and illustrate the best mode of practicing the embodiments. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure, and will recognize the applications of these concepts not specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0035] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0036] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element or extending "on" another element, it may be directly on the other element or extend directly to the other element, or there may also be an intervening element. In contrast, when an element is referred to as being "directly on" another element or extending "directly" to another element, there are no intervening elements. Similarly, it will be understood that when an element such as a layer, region, or substrate is referred to as being "above" another element or extending "above" another element, it may be directly on the other element or extend directly to the other element, or there may also be an intervening element. In contrast, when an element is referred to as being "directly on" another element or extending "directly" to another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intervening element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0037] As shown in the figures, relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region. It will be understood that these terms and the terms discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0038] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular forms "a / an" and "the" as used herein are also intended to include the plural forms. It will also be understood that the terms "comprises / comprising" and / or "includes / including" when used herein indicate the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and that the terms used herein will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0040] Embodiments are described herein with reference to the schematic diagrams of embodiments of the present disclosure. In this way, the actual sizes of layers and elements may be different, and due to reasons such as manufacturing technology and / or tolerances, changes in the illustrated shapes are expected to occur. For example, an area illustrated or described as a square or rectangular may have circular or curved features, and an area illustrated as a straight line may have some irregularities. Therefore, the areas shown in the figures are schematic, and their shapes are not intended to illustrate the precise shape of the area of ​​the device, and are not intended to limit the scope of the present disclosure. In addition, for the purpose of illustration, the size of an area or structure may be exaggerated relative to other structures or areas, and therefore a size is provided to illustrate the general structure of the subject matter, and may or may not be drawn to scale. Common elements between the drawings may be shown in this article with common element numbers, and may not be re-described subsequently.

[0041] Figure 1A top view layout of an example semiconductor device 100 according to an embodiment of the present disclosure is illustrated. For illustrative purposes, the semiconductor device 100 is a vertical metal oxide semiconductor field effect transistor (MOSFET) device that includes a passivation structure 102 formed with openings for a gate contact 104 and a plurality of source contacts 106. Although a MOSFET is illustrated, the principles of the present disclosure are also applicable to other semiconductor devices, such as other MOSFETs, metal insulator field effect transistors (MISFETs), diodes, Schottky diodes, junction barrier Schottky (JBS) diodes, PiN diodes, and insulated gate bipolar transistors (IGBTs), etc. The semiconductor device 100 can be implemented as a wide bandgap semiconductor device, such as a silicon carbide (SiC) based device, and also a 4H-SiC based device.

[0042] The semiconductor device 100 is a vertical power device in which the drain contact (eg Figure 3 The drain contact 322 in FIG. 1 is located at the back side of the semiconductor device 100. The gate contact 104 and the source contact 106 may be provided as a surface for coupling the semiconductor device 100 to external circuitry.

[0043] The edge termination region 108 may be arranged along the perimeter of the semiconductor device 100. The edge termination region 108 may be arranged to reduce the electric field concentration at the edge of the semiconductor device 100 to improve its performance. For example, over time, the edge termination region 108 may increase the breakdown voltage of the semiconductor device 100 and / or reduce the leakage current of the semiconductor device 100. For example, the edge termination region 108 may include one or more guard rings, junction termination extensions (JTEs), and combinations thereof.

[0044] The semiconductor device 100 may also include a sensor contact 110. The sensor contact 110 may provide contact for any type of sensor that is at least partially contained within the semiconductor device 100, such as a temperature sensor, a strain sensor, or a current sensor. In the case of a current sensor, a current sensor region corresponding to the sensor contact 110 may occupy an area of ​​the semiconductor device 100 that would otherwise form part of an active region 112 of the semiconductor device 100. Figure 1 In the example of FIG. 1 , the edge termination region 108 can be used to mark the boundary of the active region 112 of the semiconductor device 100 and the inactive region 114 of the semiconductor device 100, and the sensor contact 110 defines a current sensor region that would otherwise form a portion of the active region 112. In this regard, the sensor contact 110 can generally have a size that is smaller than the size of the remaining active region 112 of the semiconductor device 100.

[0045] The sensor contact 110 provides a contact pad that can be electrically connected to one or more external circuit elements, such as by wire bonds or other electrical connections, for sensor monitoring. In the case of a current sensor, the sensor contact 110 can be electrically connected to one or more external circuit elements for monitoring a portion of the load current flowing in a sensor region of the semiconductor device 100 that is electrically coupled to the sensor contact 110.

[0046] Figure 2A A first equivalent circuit 200 for implementation of a current sensor for a MOSFET device or a MISFET device according to an embodiment of the present disclosure is illustrated. Figure 2A The dashed box in the Figure 1 The semiconductor device 100, wherein the remaining portion of the first equivalent circuit 200 is outside the semiconductor device 100. By contacting the sensor (eg, Figure 1 The sensor contact 110 is formed as a separate source contact, and the semiconductor device 100 thus includes a device MOSFET (M D ) and the sensing MOSFET (M sense Each MOSFET (M D and M sense ) are connected in parallel so that the current from the drain (I D ) can be across the MOSFET (M D and M sense ) is separated from the device MOSFET (M D ) source current is proportional to the current from the sense MOSFET (M sense ) corresponds to the ratio of the area occupied by the active region of the semiconductor device 100 to the area occupied by the sensor region of the semiconductor device 100.

[0047] For example, Figure 2A An embodiment is illustrated in which the ratio of the current is set to 1:250 based on the relative areas of the active area and the sensor area. In this way, when a current of one ampere (A) flows through the semiconductor device 100, a current of four milliamperes (mA) will flow from the sense MOSFET (M sense ) source path. By following the path from the sense MOSFET (M sense ) in the source path to arrange the sensing resistor (R sense ), the corresponding sensing voltage (V sense ) and the corresponding sensing voltage (V sense ) and the device MOSFET (M D ) is associated with a load current. With the arrangement of the semiconductor device 100 , other current sensing configurations are possible.

[0048] For example, Figure 2B A second equivalent circuit 202 for implementing a current sensor for a MOSFET device or a MISFET device according to an embodiment of the present disclosure is illustrated. The representative second equivalent circuit 202 shows a virtual ground configuration of a portion external to the semiconductor device 100. Virtual ground sensing can be used where a higher sensing voltage (V sense ) value in the application. In this configuration, the operational amplifier (OA) and feedback resistor (Rf) are coupled to the sense MOSFET (M sense ) source path. In this way, the sense voltage (V) can be calculated based on the feedback resistor (Rf) and the output of the operational amplifier (OA). sense ).

[0049] In some cases, the type of current sensor corresponds to the type of semiconductor device. For example, the first equivalent circuit 200 depicts a current sensor for a MOSFET device. D and M sense is implemented as a device MOSFET (M D ) and the sensing MOSFET (M sense ). In other embodiments, M D and M sense This can be implemented with different types of transistors, where the transistor type corresponds to the semiconductor device type.

[0050] Figure 3 The diagram includes Figure 1 1 is a cross-sectional view of a portion of a semiconductor device 300 having a sensor contact 110. By way of example, the semiconductor device 300 is arranged as a planar MOSFET, but the principles of the present disclosure are also applicable to other semiconductor devices, including trench MOSFETs, MISFETs, diodes, Schottky diodes, JBS diodes, PiN diodes, and IGBTs, etc. The semiconductor device 300 includes a substrate 302 and a drift region 304 above the substrate 302. The drift region 304 can be implemented as one or more drift layers of a wide bandgap semiconductor material (e.g., SiC).

[0051] The substrate 302 may have a 1x10 17 cm -3 and 1x10 20 cm -3 In various embodiments, the doping concentration of the substrate 302 may be provided in the range of 1×10 17 cm -3 and 1x10 20 cm -3 For example, the doping concentration of the substrate 302 may be 1×1018 cm -3 and 1x10 20 cm -3 Between 1x10 19 cm -3 and 1x10 20 cm -3 Between 1x10 17 cm -3 and 1x10 19 cm -3 Between 1x10 17 cm -3 and 1x10 18 cm -3 Between, and between 1x10 18 cm -3 and 1x10 19 cm -3 between.

[0052] The drift region 304 may have a 14 cm -3 and 1x10 18 cm -3 In various embodiments, the doping concentration of the drift region 304 may be provided in the range of 1×10 14 cm -3 and 1x10 18 cm -3 For example, the doping concentration of the drift region 304 may be 1×10 15 cm -3 and 1x10 18 cm -3 Between 1x10 16 cm -3 and 1x10 18 cm -3 Between 1x10 17 cm -3 and 1x10 18 cm -3 Between 1x10 14 cm -3 and 1x10 17 cm -3 Between 1x10 14 cm -3 and 1x10 16 cm -3 Between 1x10 14 cm -3 and 1x10 15 cm -3Between 1x10 15 cm -3 and 1x10 17 cm -3 Between 1x10 15 cm -3 and 1x10 16 cm -3 Between, and between 1x10 16 cm -3 and 1x10 17 cm -3 between.

[0053] Vertical dashed lines are provided to indicate one or more transition regions 306 of the semiconductor device 300. T , the one or more transition zones 306 T The boundary between the device area 308 and the sensor area 310 is marked. Figure 1 An embodiment with a single integrated sensor contact 110 is illustrated in a top view of Figure 3 The transition area 306 indicated by the dashed line T may be a continuous transition region 306 surrounding the sensor contact 110 T . The semiconductor device 300 may include one or more unit cells in both the device region 308 and the sensor region 310. A unit cell refers to a single MOSFET transistor or cell. The device region 308 includes one or more unit cells, and the sensor region 310 also includes one or more unit cells. Therefore, the semiconductor device (e.g., MOSFET device) includes a plurality of unit cells. In a non-limiting example, the sensor region 310 includes one or more current sensors.

[0054] exist Figure 3 , the device region 308 and the sensor region 310 include a pair of junction implants 312 provided in the drift region 304 (and specifically, at a top surface 304A of the drift region 304 opposite to the substrate 302 (e.g., in an upper region of the drift region 304 near or adjacent to the top surface 304A)). The junction implants 312 include a well region 312A having an opposite doping type to the drift region 304 and a source region 312B having the same doping type as the drift region 304 and, in some embodiments, having a higher doping concentration than the drift region 304. The junction implants 312 may be separated from each other by junction field effect transistor (JFET) regions 314. The JFET regions 314 have the same doping type as the drift region 304 and, in some embodiments, have a higher doping concentration than the drift region 304.

[0055] A plurality of source contacts 106 are provided over the junction implant 312 on the top surface 304A of the drift region 304 in the device region 308, such that each source contact 106 contacts a portion of the source region 312B and the well region 312A. In a similar manner, sensor contacts 110 are provided over the junction implant 312 on the top surface 304A of the drift region 304 in the sensor region 310, such that each sensor contact 110 contacts a portion of the source region 312B and the corresponding well region 312A. In this regard, the sensor contacts 110 may form a separate source contact for the sensor region 310. In certain embodiments, the drift region 304 may include n-type doping, the source region 312B may include n+ type doping, and the well region 312A may include p-type doping, although the opposite polarity configuration is also applicable to the present disclosure.

[0056] A gate oxide layer or gate insulation layer 316 depending on the device type is provided on the top surface 304A of the drift region 304 above the JFET region 314 and a portion of each junction implant 312, such that the gate insulation layer 316 partially overlaps each source region 312B. In some embodiments, for example, in a MOSFET configuration in which the gate insulation layer 316 may be referred to as a gate oxide layer, the gate insulation layer 316 may include a thin layer of silicon dioxide. In other embodiments, the gate insulation layer 316 may include any insulating material, including non-oxide insulating materials and other oxide materials other than silicon dioxide.

[0057] A gate contact 318 is provided on the gate insulating layer 316. As shown, the gate contact 318 may be provided in the device region 308, in the sensor region 310, and across the transition region 306. T The unit cell of the device region 308 and the sensor region 310 may be provided with a gate contact 318 and a gate insulating layer 316. The gate contact 318 of each unit cell in both the device region 308 and the sensor region 310 may be coupled to Figure 1 In an alternative configuration, the semiconductor device 300 may be implemented as a trench MOSFET, where portions of the gate insulation layer 316 and the gate contact 318 may be located in a trench of the drift region 304 without departing from the principles of the present disclosure.

[0058] A passivation layer 320 is provided over the gate contact 318 to provide electrical insulation of the source contact 106 and the sensor contact 110. In certain embodiments, the passivation layer 320 may include one or more dielectric layers referred to as intermetallic dielectrics. The unit cells may be tiled across the device region 308 and the sensor region 310, or tiled with one or more other semiconductor devices (e.g., diodes) in a desired pattern to provide desired functionality.

[0059] A drain contact 322 is provided on a surface of the substrate 302 opposite the drift region 304. Thus, the portion of the drift region 304 arranged in the device region 308 and the corresponding unit cell(s) are electrically connected between the drain contact 322 and the source contact 106. In a similar manner, the portion of the drift region 304 arranged in the sensor region 310 and the corresponding unit cell(s) are electrically connected between the drain contact 322 and the sensor contact 110. Although only a few unit cells are illustrated, the ratio of the number of unit cells in the sensor region 310 to the number of unit cells in the device region 308 may be on the order of 1:1, or 1:100, or 1:250, or 1:1000,000, depending on the current ratio desired for the sensor region 310. In some embodiments, the sensor region 310 may be arranged to occupy no more than twenty percent (20%), or no more than ten percent (10%), or no more than five percent (5%) of the available active area of ​​the semiconductor device 300 within the edge termination region. For current sensing applications, the sensor region 310 may be referred to as a current sensor region.

[0060] A doped well region 324 of the drift region 304 may be provided. The doped well region 324 and the transition region 306 T The doped well region 324 may include the same doping type as the well region 312A and the opposite doping type as the drift region 304. In this regard, the doped well region 324 may be configured to shield the gate contact 318 from extending across the transition region 306. T However, in this layout, semiconductor device 300 may be susceptible to damage from transient voltage events that may occur during operation and / or device testing. Specifically, a high rate of voltage change over time (dV / dt) may be induced during switching events. High dV / dt may cause transition region 306 to T Dielectric breakdown or other defects and damage in the gate insulation layer 316 in.

[0061] Figure 4 The diagram shows Figure 3 The semiconductor device 300 is similar to the semiconductor device 300 and further includes a transition region 306 disposed in T 4 is a cross-sectional view of a portion of a first semiconductor device 400 that includes a protective structure for shielding a gate insulating layer 316 from transient voltage events, defects, and other related damage. An insulating layer 402 is provided on a top surface 304A of the drift region 304 to provide protection for the gate insulating layer 316. The insulating layer 402 may also be provided on the top surface 304A of the drift region 304 in an area where the top surface 304A includes a doped well region 324. In some embodiments, the insulating layer 402 may be formed on the drift region 304 before the gate insulating layer 316 and the gate contact 318 are formed, thereby arranging the insulating layer 402 in the transition region 306. TIn addition, the insulating layer 402 prevents the thin gate insulating layer 316 from completely covering the transition region 306. T The top surface 304A of the drift region 304 in the transition region 306 T At least a portion of the top surface 304A is free of the gate insulating layer 316. In some embodiments, the insulating layer 402 may be provided between the drift region 304 and the gate contact 318 and on the top surface of the gate contact 318. In addition, in some embodiments, the gate insulating layer 402 may not be provided in the transition region 306. T In any of the above example embodiments, the gate insulating layer 402 provides a gate insulating layer 316 between the insulating layer 402 and the gate contact 318, thereby reducing the overall presence of the gate insulating layer 316. T The gate insulating layer 316 is most susceptible to damage due to the transient voltage event. T A weak point is formed at the interface between the gate insulating layer 316 and the top surface 304A of the drift region 304 .

[0062] In some embodiments, the insulating layer 402 includes a structure having a breakdown voltage higher than the breakdown voltage of the gate insulating layer 316. For example, the breakdown voltage of the insulating layer 402 can be at least 1.5 times, or at least 2 times, or at least 3 times, or at least 5 times, or at least 10 times, or at least 50 times, or at least 100 times, or at least 200 times the breakdown voltage of the gate insulating layer 316, or any range with endpoints defined by any of the foregoing values. For example, the breakdown voltage of the insulating layer 402 can be in the range of 1.5 times to 200 times, or in the range of 1.5 times to 100 times, or in the range of 5 times to 100 times, or in the range of 5 times to 200 times the breakdown voltage of the gate insulating layer 316. In a specific example, the insulating layer 402 includes a breakdown voltage in the range from 650 volts (V) to 750V, while the gate insulating layer 316 includes a breakdown voltage in the range from 40V to 60V.

[0063] In some embodiments, the insulating layer 402 may include a different material having a higher breakdown voltage than the material of the gate insulating layer 316. In such embodiments, the thickness of the insulating layer 402 and the gate insulating layer 316 may be the same or different, as long as the insulating layer 402 has a higher breakdown voltage. In other embodiments, the insulating layer 402 and the gate insulating layer 316 may include the same material, and a higher breakdown voltage is achieved by providing the insulating layer 402 with a thickness or height from the drift region 304 that is thicker than the corresponding thickness or height of the gate insulating layer 316. For example, the thickness of the insulating layer 402 may be at least 1.5 times, or at least 2 times, or at least 3 times, or at least 100 times, or in the range from 1.5 times to 50 times, or in the range from 1.5 times to 100 times, or in the range from 2 times to 50 times, or in the range from 2 times to 100 times, of the thickness of the gate insulating layer 316. In a specific example, the insulating layer 402 includes a thickness in a range from 550 nanometers (nm) to 650 nm, and the gate insulating layer 316 includes a thickness in a range from 30 nm to 50 nm. For MOSFET applications, the gate insulating layer 316 may include a gate oxide, and the insulating layer 402 may include a thicker field oxide layer as described above. In such an embodiment, both the gate insulating layer 316 and the insulating layer 402 may include silicon dioxide, as well as other gate oxides used in MOSFET applications.

[0064] By having a protection structure provided by the insulating layer 402, the overall structure of the first semiconductor device 400 is more robust to handling transient voltage events, including one or more dV / dt events that may be induced during high-speed switching. For example, a SiC MOSFET device having the insulating layer 402 of the present disclosure can therefore be configured to withstand or be rated for a dV / dt of at least 10 kilovolts per microsecond (kV / µs) without device failure. In further embodiments, the SiC MOSFET device is configured to withstand dV / dt at least 30 kV / µs, or at least 50 kV / µs, or at least 100 kV / µs, or in a range from 10 kV / µs to 100 kV / µs, or in a range from 10 kV / µs to 200 kV / µs, or in a range from 50 kV / µs to 150 kV / µs, or in a range from 100 kV / µs to 200 kV / µs, or in any range with endpoints determined by any of the foregoing values ​​without device failure. In further embodiments, the SiC MOSFET device is capable of withstanding any of the foregoing dV / dt values ​​from a single switching cycle to at least 1000 switching cycles or more. In any of the foregoing embodiments, the exemplary SiC MOSFET may include a 4H-SiC MOSFET device.

[0065] In some examples, for forming a gate contact (e.g., Figure 3 The material of the gate contact 318 in the embodiment is resistive or highly resistive. In a non-limiting, non-exclusive embodiment, the material used to form the gate contact is p-type polysilicon. The higher resistivity of p-type polysilicon can cause the potential across the gate contact to vary based on the position of the gate contact relative to the input of the gate signal. These potential differences can cause propagation delays (e.g., resistance and capacitance (RC) delays) in the gate signal, which causes the transistor to turn on at different times (e.g., Figure 2A and Figure 2B The transistor M in D and M sense ). Generally, it is preferred to turn on the transistors, especially the transistors in the sensor region, as a unit. When the transistors are turned on as a unit, the transistors are turned on simultaneously (or substantially simultaneously).

[0066] One technique that can be used to turn on the transistors in the sensor region as a cell is to reduce the resistance of the gate contact material. Figure 5 FIG. 5 shows a top view of a portion of a semiconductor device having a gate contact material with reduced resistance according to an embodiment of the present disclosure. Figure 3 sensor region 310 in the embodiment of the present invention) through a gate contact 504 (eg Figure 4 The gate contact 318 in the sensor region 310 of the transistor is electrically connected to a power supply (PS) 502. A conductive segment 506 is disposed above the gate contact 504. In some embodiments, the conductive segment 506 is in direct contact with the gate contact 504. The conductive segment 506 reduces the resistivity of the material in the gate contact 504, which in turn reduces or eliminates propagation delays to the transistor (e.g., propagation delays of the signal to the gate). For example, the conductive segment 506 can average the propagation delays to reduce the overall delay.

[0067] Source contacts (e.g., source contact 106), sensor contacts (e.g., sensor contact 110), drain contacts (e.g., drain contact 322), and conductive segments 506 may all be made of the same conductive material, or at least one may be made of a different conductive material. In addition, source contacts, sensor contacts, drain contacts, and conductive segments 506 may be implemented as one or more layers of one or more conductive materials. One example of a conductive material is a metal.

[0068] Figure 6 The present invention is illustrated in accordance with an embodiment of the present disclosure. Figure 4 FIG. 4 is a cross-sectional view of a portion of a second semiconductor device 600 that is similar to the first semiconductor device 400 and includes a conductive segment 602 formed over the gate contact 318. The conductive segment 602 is disposed in the corresponding transition region 306. TIn the illustrated embodiment, the conductive segment 602 is in direct contact with the gate contact 318.

[0069] The conductive segment 602 is disposed in the transition region 306 between the source contact 106 and the sensor contact 110. T The conductive segment 602 does not directly contact the source contact 106 and the sensor contact 110. The conductive segment 602 is disposed in the transition region 306. T The passivation layer 320 is not disposed in the transition region 306. T On the conductive segment 602 in .

[0070] Conductive segments 602 reduce the resistivity of the material used to form gate contacts 318. As previously described, reducing the resistivity can reduce or eliminate propagation delays in gate signals applied to gate contacts 318 of transistors in device region 308 and sensor region 310. In a non-limiting, non-exclusive example, metal is used to form conductive segments 602, and polysilicon is used to form gate contacts 318.

[0071] Figure 7 The present invention is illustrated in accordance with an embodiment of the present disclosure. Figure 4 The first semiconductor device 400 and Figure 6 A cross-sectional view of a portion of a third semiconductor device 700 that is similar to the second semiconductor device 600 and includes an insulating layer 402 that forms a non-planar shape. Figure 7 In the embodiment, a thicker portion 402' of the insulating layer 402 is formed along the center of the insulating layer 402 to form one or more non-planar surfaces thereof opposite to the drift region 304. In this way, the transition region 306 can be formed. T An increased amount of protection structure provided by the insulating layer 402 is formed in the device region 308 without increasing the lateral coverage area of ​​the insulating layer 402 relative to the drift region 304. Although the increased thickness portion 402' of the insulating layer 402 is illustrated at the center of the insulating layer 402, the increased thickness portion 402' may also be arranged closer to the sensor region 310 or the device region 308 depending on the embodiment. In further embodiments, the insulating layer 402 may be formed with multiple increased thickness portions 402'. Figure 7 In the embodiment, the increased thickness portion 402' forms a stepped profile of the insulating layer 402. In other embodiments, the increased thickness portion 402' may form a peak that slopes toward the lateral edge of the insulating layer 402 in one or more of a linear and / or curved manner.

[0072] The third semiconductor device 700 further includes a transition region 306 TAs previously described, the conductive segment 602 is disposed between the source contact 106 and the sensor contact 110 (and does not contact the source contact 106 and the sensor contact 110). The conductive segment 602 is disposed in the transition region 306 T The substrate is located between portions of the passivation layer 320 and is not covered by the passivation layer 320 .

[0073] Figure 8 The present invention is illustrated in accordance with an embodiment of the present disclosure. Figure 4 The first semiconductor device 400 and Figure 6 FIG. 8 is a cross-sectional view of a portion of a fourth semiconductor device 800 that is similar to the second semiconductor device 600 and includes an insulating layer 402 formed to cover a larger portion of the top surface of the drift region 304. As shown, the insulating layer 402 can be formed to have a lateral width that is close to or the same as the lateral width of the doped well region 324 of the drift region 304. In this manner, the fourth semiconductor device 800 can be formed along the transition region 306. T The amount of material used for the gate insulating layer 316 is further reduced in the region of the transition region 306. In embodiments where the gate insulating layer 316 is not formed over the insulating layer 402, the gate insulating layer 316 is thus T spaced further apart to further reduce the impact from transient voltage events. Figure 8 4 is shown as having the same lateral width as the lateral width of the doped well region 324, but the insulating layer 402 may be formed with an increased width that is less than the width of the doped well region 324. For example, in various embodiments, the insulating layer 402 may be formed with a width of at least 50%, or at least 75%, or at least 90%, or in a range from 50% to 100% of the width of the doped well region 324.

[0074] The fourth semiconductor device 800 further includes a transition region 306 T As previously described, the conductive segment 602 is disposed between the source contact 106 and the sensor contact 110 (and does not contact the source contact 106 and the sensor contact 110). The conductive segment 602 is disposed in the transition region 306 T The substrate is located between portions of the passivation layer 320 and is not covered by the passivation layer 320 .

[0075] like Figure 4 As shown, each doped well region 324 is formed below the gate contact 318 and extends across the corresponding transition region 306. T and enter the device region 308 and the sensor region 310 in the corresponding transition region 306 TIn some cases, such as when a transistor in device region 308 switches from an off state to an on state, the current in device region 308 may propagate into adjacent sensor region 310. The migrated current in sensor region 310 may cause several transistors (e.g., current sensors) in sensor region 310 to switch to an on state, and in some cases, several transistors (e.g., current sensors) in sensor region 310 to switch to an on state even before the transistor in device region 308 switches to an on state. When the transistor in sensor region 310 switches to an on state based on the migrated current, the current ratio set for the semiconductor device at a specific ratio (e.g., a ratio of 1:250) may not remain unchanged.

[0076] One technique that may be used to reduce or eliminate current migration into the sensor region 310 is to isolate the doped well regions in the device region 308 from the doped well regions in the sensor region 310 . Fig. 9 The present invention is illustrated in accordance with an embodiment of the present disclosure. Figure 4 FIG. 4 is a cross-sectional view of a portion of a fifth semiconductor device 900 that is similar to the first semiconductor device 400 and includes an isolation region 902 located between an isolation well region 904 in the device region 308 and an isolation well region 906 in the sensor region 310. The isolation region 902 is formed in the transition region 306. T In a portion of the drift region 304, the isolation well region 904 in the portion of the drift region 304 in the device region 308 is isolated from the isolation well region 906 in the portion of the drift region 304 in the sensor region 310. In essence, the isolation region 902 Figure 4 The doped well region 324 in the transition region 306 is divided into two isolated well regions 904 and 906. T to locate the isolation region 902 (eg, with the transition region 306 T Registration).

[0077] In a non-limiting, non-exclusive embodiment, the isolation region 902 and the JFET region 314 are associated with the same or substantially similar electric fields such that the isolation region 902 forms a current mirror for the JFET region 314. As such, the isolation region 902 is formed of the same material as the JFET region 314 and has the same doping type and doping concentration as the JFET region 314. Additionally or alternatively, the isolation region 902 has a width or area that is equal to or substantially equal to a width or area of ​​the JFET region 314.

[0078] An isolation well region 904 in the device region 308 is formed between the JFET region 314 and a first edge or side of the isolation region 902. At least a portion of the isolation well region 904 is also formed under the gate contact 318. Similarly, an isolation well region 906 in the sensor region 310 is formed between another JFET region 314 and a second edge of the isolation region 902 opposite the first edge of the isolation region 902. Like the isolation well region 904, at least a portion of the isolation well region 906 is formed under the gate contact 318. In the illustrated embodiment, at least a portion of the isolation well region 904 and at least a portion of the isolation well region 906 are formed under portions of the insulating layer 402.

[0079] The isolation region 902 prevents the current in the device region 308 from propagating into the adjacent sensor region 310. The transistor(s) in the sensor region 310 will remain in the off state, while the transistor(s) in the device region 308 are turned into the on state. Thus, during the switching operation, the current ratio of the semiconductor device set at a specific ratio (e.g., a ratio of 1:250) is maintained.

[0080] Figure 10A-10B The waveforms of the device MOSFET and the sense MOSFET during switching operation are shown. Specifically, Fig. 10A The waveform 1000 shows when the sense MOSFET (e.g., Figure 2A and Figure 2B M sense ) switches to the on state, and waveform 1002 represents the current when the device MOSFET (e.g. Figure 2A and Figure 2B M D ) is switched to the on state. The sense MOSFET is implemented as a current sensor, and waveform 1000 represents the current when the current sensor is switched to the on state.

[0081] Fig. 10B The waveforms 1004 and 1006 in FIG. 1 depict the current when the current sensor and the device MOSFET are switched to the off state, respectively. Fig. 10A and Fig. 10B As shown, the waveforms 1000 and 1004 of the current sensors follow the waveforms 1002 and 1006 of the device MOSFETs, respectively, except for the change regions 1008 and 1010. The change region 1008 indicates the time period when several current sensors switch to the on state before the remaining current sensors switch to the on state. The change region 1010 indicates the time period when several current sensors switch to the off state before the remaining current sensors switch to the off state.

[0082] When the slopes of waveforms 1000, 1004 are as shown in the change regions 1008, 1010, the current in the device MOSFET cannot be detected by the current sensor. When waveforms 1000, 1004 follow waveforms 1002, 1006 respectively, the current sensor can be used to detect changes or events in the device MOSFET when an event occurs or as an event occurs. In a non-limiting, non-exclusive example, the current sensor can be used to detect a short circuit event in the device MOSFET. In another non-limiting, non-exclusive example, under the low Rds_on condition of a solid-state relay, the current in the device MOSFET is continuously or at a selected time. Additionally or alternatively, the current sensor can be used for cycle-by-cycle control, wherein the current sensor can eliminate the Hall effect current sensor to save cost and die area (e.g., in an inverter circuit).

[0083] Fig.11 The present invention is illustrated in accordance with an embodiment of the present disclosure. Fig. 9 A cross-sectional view of a portion of a sixth semiconductor device 1100 that is similar to the fifth semiconductor device 900 and operable to detect one or more events in one or more MOSFET devices. The sixth semiconductor device 1100 includes a conductive segment 602 formed on a gate contact 318 and a conductive segment 606 formed below the gate contact 318 in a transition region 306. T 902 in the gate contact 318. As previously described, the isolation region 902 prevents current in the corresponding device region 308 (e.g., one or more device MOSFETs) from propagating into the adjacent sensor region 310. The isolation region 902 reduces or eliminates the variation region (e.g., variation region 1008, 1010) in the current waveform of the current sensor, so that the current waveform follows (or substantially follows) the current waveform of the one or more device MOSFETs (e.g., device region 308). The conductive segment 602 reduces the resistivity of the material in the gate contact 318 and enables the current sensors to switch to the on state simultaneously (or substantially simultaneously).

[0084] The combination of the isolation region 902 and the conductive segment 602 for isolating the isolation well regions 904, 906 enables the sixth semiconductor device 1100 to detect events in one or more device MOSFETs, such as short circuit events. In some on-chip sensors such as on-chip current sensors, the time period for detecting the current and / or events in the device MOSFET is one or more microseconds. This allows the device MOSFET to be turned off or isolated to prevent the device MOSFET from being damaged. In an example embodiment, the sixth semiconductor device 1100 (e.g., the current sensor in the sixth semiconductor device 1100) can detect an event (e.g., a short circuit event) in less than one microsecond. In another example embodiment, the sixth semiconductor device 1100 (e.g., the current sensor in the sixth semiconductor device 1100) can detect an event such as a short circuit event in one to five microseconds or less than ten microseconds. In yet another example embodiment, the sixth semiconductor device 1100 (e.g., the current sensor in the sixth semiconductor device 1100) can detect an event in tens of microseconds.

[0085] Fig.12 The present invention is illustrated in accordance with an embodiment of the present disclosure. Figure 7 The third semiconductor device 700 and Fig. 9 A cross-sectional view of a portion of a seventh semiconductor device 1200 that is similar to the fifth semiconductor device 900 and includes an insulating layer 402 and an isolation region 902 formed in a non-planar shape. Figure 7 Similarly, a thicker portion 402' of the insulating layer 402 is formed over the insulating layer 402 to form one or more non-planar surfaces thereof opposite the drift region 304. The increased thickness portion 402' may be formed in any shape or profile, such as a stepped profile or a peak that slopes toward a lateral edge of the insulating layer 402 in one or more of a linear and / or curved manner. Although the increased thickness portion 402' of the insulating layer 402 is illustrated in the center of the insulating layer 402, the increased thickness portion 402' may be disposed closer to the sensor region 310 or the device region 308, depending on the embodiment. In further embodiments, the insulating layer 402 may be formed with a plurality of increased thickness portions 402'.

[0086] The seventh semiconductor device 1200 may further include an isolation region 902 located between the isolation well regions 904 and 906 in the device region 308 and the sensor region 310, respectively. The isolation region 902 is formed in the transition region 306. T314, to separate or isolate the isolation well region 904 from the isolation well region 906. The isolation region 902 may be formed of the same material as the JFET region 314 and have the same doping type, doping concentration, and width as the JFET region 314. In some embodiments, the isolation region 902 and the isolation well regions 904, 906 are omitted. In such embodiments, the doped well region 324 extends through the corresponding transition region 306. T , and enter the corresponding sensor area 310 and the corresponding device area 308.

[0087] The seventh semiconductor device 1200 may optionally include a conductive segment 602 (shown in dashed lines). The conductive segment 602 is disposed between the source contact 106 and the sensor contact 110 (and does not contact the source contact 106 and the sensor contact 110). The conductive segment 602 is disposed in the transition region 306 T The substrate is located between portions of the passivation layer 320 and is not covered by the passivation layer 320 .

[0088] As previously described, the conductive segments 602 reduce the resistivity of the material used to form the gate contact 318. The reduced resistivity can reduce or eliminate propagation delays in gate signals applied to the gate contacts 318 of transistors in the sensor region 310. In addition, the combination of the isolation region 902 and the conductive segments 602 used to isolate the isolation well regions 904, 906 enables the seventh semiconductor device 1200 to detect events in the device MOSFET, such as short circuit events.

[0089] Fig.13 The present invention is illustrated in accordance with an embodiment of the present disclosure. Figure 8 The fourth semiconductor device 800 and Fig. 9 FIG. 1 is a cross-sectional view of a portion of an eighth semiconductor device 1300 similar to the fifth semiconductor device 900 and including an isolation region 902 and an insulating layer 402 formed to cover a larger portion of the top surface of the drift region 304. As shown, the insulating layer 402 can be formed to have a lateral width that is close to or equal to the lateral width of the doped well region 324 of the drift region 304. In this manner, the eighth semiconductor device 1300 can be provided along the transition region 306. T In the embodiment where the gate insulating layer 316 is not formed over the insulating layer 402, the gate insulating layer 316 is thus separated from the transition region 306. T spaced farther apart to further reduce the effects from transient voltage events.

[0090] Although the insulating layer 402 is shown to have the same lateral width as the lateral width of the isolation region 902 and the isolation well regions 904, 906 combined, the insulating layer 402 may be formed to have an increased width that is less than the width of the doped well region 324. For example, in various embodiments, the insulating layer 402 may be formed to have a width that is at least 50%, or at least 75%, or at least 90%, or in a range from 50% to 100% of the width of the isolation region 902 and the isolation well regions 904, 906 combined.

[0091] The eighth semiconductor device 1300 may further include an isolation region 902 located between the isolation well region 904 in the device region 308 and the isolation well region 906 in the sensor region 310. The isolation region 902 is formed in the transition region 306. T 314, to separate or isolate the isolation well region 904 from the isolation well region 906. The isolation region 902 may be formed of the same material as the JFET region 314 and have the same doping type, doping concentration, and width as the JFET region 314. In some embodiments, the isolation region 902 and the isolation well regions 904, 906 are omitted. In such embodiments, the doped well region 324 extends through the corresponding transition region 306. T , and enter the corresponding sensor area 310 and the corresponding device area 308.

[0092] The eighth semiconductor device 1300 may optionally include a conductive segment 602 (shown in dashed lines). The conductive segment 602 is disposed between the source contact 106 and the sensor contact 110 (and does not contact the source contact 106 and the sensor contact 110). The conductive segment 602 is disposed in the transition region 306 T The substrate is located between portions of the passivation layer 320 and is not covered by the passivation layer 320 .

[0093] As previously described, the conductive segments 602 reduce the resistivity of the material used to form the gate contact 318. The reduced resistivity can reduce or eliminate propagation delays in gate signals applied to the gate contacts 318 of transistors in the sensor region 310. In addition, the combination of the isolation region 902 and the conductive segments 602 used to isolate the isolation well regions 904, 906 enables the eighth semiconductor device 1300 to detect events in the device MOSFET, such as short circuit events.

[0094] Delay between current sensors and delay from gate signal are two characteristics that affect the performance of current sensors. Delay between current sensors represents the delay between the time when the first current sensor in the sensor area transitions to the on state (conducts) and the time when the last current sensor in the sensor area turns on. Delay from gate signal represents the delay between the time when the gate signal is applied to the sensor contact and the time when the current sensors in the sensor area turn on. The layout of the sensor area within the active area can have an impact on these types of delays.

[0095] Fig.14 An example first layout 1400 of a sensor region 1402 is illustrated. The sensor region 1402 is arranged in a rectangular shape and is located in the center of a rectangular active region 1404. A gate contact 1406 surrounds the sensor region 1402. When a gate signal is applied to the gate contact 1406 via a gate signal line 1408, the current sensors in the sensor region 1402 receive the gate signal from all directions. Therefore, the current sensors are turned on at different times because the gate signal propagates to the current sensors at different times. Both the delay between the current sensors and the delay from the gate signal may adversely affect the performance of the sensor region 1402.

[0096] Figure 15-17 An example layout that can reduce delays between current sensors and / or delays from gate signals is depicted. The device area ( Figure 15-17 not shown) and Figure 15-17 The sensor area shown in can be implemented as Figure 6-Figure 9 and Figure 11-13 Any one of the embodiments shown in .

[0097] Fig.15 An example second layout 1500 of a sensor region 1502 according to an embodiment of the present disclosure is illustrated. In the second layout 1500, the sensor region 1502 is arranged in a stripe or rectangular shape and is located along the left edge 1504 of the active region 1404. The gate contact 1506 is arranged in a stripe or rectangular shape and is located between the sensor region 1502 and the left edge 1504 of the active region 1404. The gate signal line 1508 is electrically connected to the gate contact 1506 and is used to apply a gate signal to the current sensor in the sensor region 1502.

[0098] The gate conductor 1510 is routed along the left edge 1504 of the active area 1404. The gate conductor 1510 electrically connects the contact pad 1512 to the gate signal line 1508. The contact pad 1512 is operable to receive a power signal for activating or turning on the current sensors in the sensor area 1502. The power signal propagates on the gate conductor 1510, and the gate signal is applied to the gate contact 1506 via the gate signal line 1508. When the gate signal is applied to the gate contact 1506, the current sensors in the sensor area 1502 are turned on at the same time or substantially at the same time. The current sensors in the sensor area 1502 are turned on at the same time (or substantially at the same time) because the gate signal propagates to the current sensors substantially at the same time. The current sensors in the sensor area 1502 are located at an equal distance (or substantially equal distance) from the gate contact 1506. The delay between the current sensors and / or the delay from the gate signal is reduced or minimized, which improves the performance of the sensor area 1502.

[0099] Other embodiments are not limited to the shape, size, and / or location of the sensor region 1502, gate contact 1506, and / or gate conductor 1510. In a non-limiting example, the sensor region 1502 can be positioned along the top edge of the active region 1404, and the gate contact 1506 can be between the sensor region 1502 and the top edge of the active region 1404. In such an embodiment, the gate conductor 1510 can be routed along the top edge of the active region 1404. In addition, the active region 1404 can have a Fig.15 The rectangular shape shown in the figure is different from the shape.

[0100] Fig.16 An example third layout 1600 of a sensor region 1602 according to an embodiment of the present disclosure is illustrated. The sensor region 1602 is arranged in an "L" shape and is located near the lower left corner 1604 and along the left edge 1606 and the bottom edge 1608 of the active region 1404. The gate contact 1610 is arranged in an "L" shape and is located between the sensor region 1602, the left edge 1606 and the bottom edge 1608 of the active region 1404. A first gate signal line 1612 is electrically connected to the gate contact 1610 at the left edge 1606, and a second gate signal line 1614 is electrically connected to the gate contact 1610 at the bottom edge 1608. The first gate signal line 1612 and the second gate signal line 1614 are used to apply a gate signal to the current sensor in the sensor region 1602.

[0101] The gate conductor 1616 is routed along the left edge 1606 and the bottom edge 1608 of the active area 1404. The gate conductor 1616 electrically connects the contact pad 1512 to the first gate signal line 1612 and the second gate signal line 1614. As previously described, the contact pad 1512 is operable to receive a power supply signal for turning on the current sensors in the sensor area 1602. The power supply signal propagates on the gate conductor 1616, and the gate signal is applied to the gate contact 1610 via the first gate signal line 1612 and the second gate signal line 1614. When the gate signal is applied to the gate contact 1610, the current sensors in the sensor area 1602 are turned on simultaneously or substantially simultaneously because the gate signal propagates to the current sensors substantially simultaneously. The current sensors in the sensor area 1602 are located at an equal distance (or substantially equal distance) from the gate contact 1610. The delay between the current sensors and / or the delay from the gate signal is reduced or minimized, which improves the performance of the sensor area 1602.

[0102] Other embodiments are not limited to the shape, size, and / or location of the sensor region 1602, gate contact 1610, and / or gate conductor 1616. In a non-limiting example, the sensor region 1602 can be located near the upper corner of the active region along the top and right edges of the active region 1404. The gate contact 1610 can be between the sensor region 1602, the top and right edges of the active region 1404. The gate conductor 1616 can be routed along the top and right edges of the active region 1404. In addition, the active region 1404 can have a Fig.16 The rectangular shape shown in the figure is different from the shape.

[0103] Fig.17 An example fourth layout 1700 of a first sensor region 1702 and a second sensor region 1704 according to an embodiment of the present disclosure is illustrated. The first sensor region 1702 is arranged in a stripe or rectangular shape and is located along a left edge 1706 of the active region 1404. The first gate contact 1708 is arranged in a stripe or rectangular shape and is located between the first sensor region 1702 and the left edge 1706 of the active region 1404. The first gate signal line 1710 is electrically connected to the first gate contact 1708 and is used to apply a gate signal to the current sensor in the first sensor region 1702.

[0104] The second sensor region 1704 is arranged in a stripe or rectangular shape and is located along the right edge 1712 of the active region 1404. The second gate contact 1714 is arranged in a stripe or rectangular shape and is located between the second sensor region 1704 and the right edge 1712 of the active region 1404. The second gate signal line 1716 is electrically connected to the second gate contact 1714 and is used to apply a gate signal to the current sensor in the second sensor region 1704.

[0105] The gate conductor 1718 is routed along the top edge 1720, the left edge 1706, and the right edge 1712 of the active area 1404. The gate conductor 1718 electrically connects the contact pad 1512 to the first gate signal line 1710 and the second gate signal line 1716. As previously described, the contact pad 1512 is operable to receive a power supply signal for turning on the current sensors in the first sensor region 1702 and the second sensor region 1704. The power supply signal propagates on the gate conductor 1718, and the gate signal is applied to the first gate contact 1708 via the first gate signal line 1710, and to the second gate contact 1714 via the second gate signal line 1716.

[0106] When the gate signal is applied to the first gate contact 1708 and the second gate contact 1714, the current sensors in the first sensor region 1702 and the second sensor region 1704 are turned on simultaneously or substantially simultaneously because the gate signal propagates to the current sensors substantially simultaneously. The current sensors in the first sensor region 1702 are located at an equal distance (or substantially equal distance) from the first gate contact 1708. Similarly, the current sensors in the second sensor region 1704 are located at an equal distance (or substantially equal distance) from the second gate contact 1714. Therefore, the delay between the current sensors and / or the delay from the gate signal is reduced or minimized, which improves the performance of the sensor region 1602.

[0107] Other embodiments are not limited to the shape, size, and / or location of the first sensor region 1702, the first gate contact 1708, the second sensor region 1704, the second gate contact 1714, and / or the gate conductor 1718. In a non-limiting example, the first sensor region 1702 can be positioned along the top edge 1720 of the active region 1404, the second sensor region 1704 can be positioned along the bottom edge of the active region 1404, the first gate contact 1708 can be positioned between the first sensor region 1702 and the top edge 1720, and the second gate contact 1714 can be positioned between the bottom edge and the second sensor region 1704. In such an embodiment, the gate conductor 1718 can be routed along the top and bottom edges of the active region 1404. In addition, the active region 1404 can have a Fig.17 The rectangular shape shown in the figure is different from the shape.

[0108] Figure 15-17Example sensor region shapes and sizes, gate contact shapes and sizes, gate conductors, and layouts that improve the performance of the sensor regions are depicted. Other embodiments are not limited to these layouts, the shapes and / or sizes of the illustrated sensor regions and gate contacts, or the routing and shapes of the gate conductors. Any layout that positions the current sensors in one or more sensor regions at an equal distance (or substantially an equal distance) from the corresponding gate contacts that are electrically connected to the corresponding sensor regions may be used. The layout of the one or more sensor regions may depend on several factors, including, but not limited to, the number of sensor regions, the shape of the sensor region(s), the shape of the gate contact(s), and the routing of the one or more gate conductors.

[0109] It is contemplated that any of the above aspects and / or the various individual aspects and features described herein may be combined for additional advantage. Unless otherwise indicated herein, any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments.

[0110] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A vertical semiconductor device, comprising: Drift zone; a device region, the device region including a first portion of the drift region; a sensor region including a second portion of the drift region; as well as A transition region, the transition region being between the device region and the sensor region, the transition region comprising: gate contact, and A conductive segment is on and in direct contact with the gate contact.

2. The vertical semiconductor device according to claim 1, further comprising: an insulating layer, the insulating layer being between the gate contact and the drift region; as well as A gate insulating layer is provided between the gate contact and the drift region. 3 . The vertical semiconductor device of claim 2 , wherein a thickness of the insulating layer is at least 1.5 times a thickness of the gate insulating layer. 4 . The vertical semiconductor device according to claim 2 , wherein a thickness of the insulating layer is in a range from 1.5 times to 100 times a thickness of the gate insulating layer. 5 . The vertical semiconductor device of claim 2 , wherein a portion of the insulating layer has a thickness greater than a thickness of other portions of the insulating layer.

6. A vertical semiconductor device according to any preceding claim, wherein the sensor region comprises one or more current sensors.

7. A vertical semiconductor device according to any preceding claim, wherein the first portion of the drift region is electrically connected between a first contact and a second contact, and the second portion of the drift region is electrically connected between the first contact and a sensor contact. 8 . The vertical semiconductor device of claim 7 , wherein the vertical semiconductor device comprises a metal oxide semiconductor field effect transistor (MOSFET), and the first contact is a drain contact and the second contact is a source contact.

9. The vertical semiconductor device according to claim 1, further comprising: a first isolation well region, the first isolation well region being below the gate contact in the first portion of the drift region; a second isolation well region, the second isolation well region being below the gate contact in the second portion of the drift region; as well as An isolation region is provided between the first isolation well region and the second isolation well region in the transition region below the gate contact.

10. The vertical semiconductor device of claim 9, wherein the isolation region and the conductive segment separating the first isolation well region and the second isolation well region enable detection of a short circuit event within less than one microsecond of the event occurring.

11. The vertical semiconductor device of claim 9, wherein the isolation region and the conductive segment isolating the first isolation well region from the second isolation well region enable a short circuit event to be detected within one microsecond to five microseconds of its occurrence.

12. The vertical semiconductor device according to any one of claims 1 to 11, wherein: The device region and the sensor region are located in an active region of the vertical semiconductor device; The sensor area is arranged in a strip shape and is located along an edge of the active area; The sensor region includes one or more current sensors; as well as Each current sensor in the sensor region is at an equal distance from a gate contact that is electrically connected to the one or more current sensors in the sensor region.

13. The vertical semiconductor device according to any one of claims 1 to 11, wherein: The device region and the sensor region are located in an active region of the vertical semiconductor device; The sensor area is arranged in an "L" shape and the lower corner of the sensor area is located near the corner of the active area; The sensor region includes one or more current sensors; as well as Each current sensor in the sensor region is at an equal distance from a gate contact that is electrically connected to the one or more current sensors in the sensor region.

14. A vertical semiconductor device comprising: Drift zone; a device region, the device region including a first portion of the drift region; a sensor region including a second portion of the drift region; A transition region, the transition region being between the device region and the sensor region, the transition region comprising: a gate contact over the drift region, and An isolation region in the drift region.

15. The vertical semiconductor device of claim 14, further comprising a conductive segment in the transition region directly on the gate contact.

16. The vertical semiconductor device of claim 15, wherein the conductive segments and the isolation regions enable detection of a short circuit event within less than one microsecond of its occurrence.

17. The vertical semiconductor device of claim 15, wherein the conductive segments and the isolation regions enable detection of a short circuit event within one microsecond to five microseconds of its occurrence.

18. The vertical semiconductor device of claim 14, wherein: the first portion of the drift region being in the device region; the second portion of the drift region being in the sensor region; The isolation region is an n-type isolation region; The first isolation well region is a first p-well region; as well as The second isolation well region is a second p-well region.

19. The vertical semiconductor device of claim 14, further comprising an insulating layer between the gate contact and the drift region. 20 . The vertical semiconductor device of claim 19 , wherein a portion of the insulating layer has a thickness greater than a thickness of other portions of the insulating layer.

21. A vertical semiconductor device according to any one of claims 14 to 20, wherein: The sensor region forms a current sensor; and The vertical semiconductor device comprises a metal oxide semiconductor field effect transistor (MOSFET), wherein the first portion of the drift region is electrically connected between a drain contact and a source contact, and the second portion of the drift region is electrically connected between the drain contact and a sensor contact.

22. The vertical semiconductor device according to any one of claims 14 to 21, wherein: The device region and the sensor region are located in an active region of the vertical semiconductor device; The sensor area is arranged in a strip shape and is located along an edge of the active area; The sensor region includes one or more current sensors; as well as Each current sensor in the sensor region is at an equal distance from a gate contact that is electrically connected to the one or more current sensors in the sensor region.

23. A vertical silicon carbide SiC device, comprising: Device area; Sensor area; as well as A transition region is provided between the device region and the sensor region, wherein the vertical SiC device is operable to detect a short circuit event within one microsecond to three microseconds.

24. The vertical SiC device according to claim 23, further comprising: a conductive segment on the gate contact; as well as An isolation region is formed below the gate contact and in the drift region.

25. The vertical SiC device of claim 24, further comprising: a well region formed in the drift region adjacent to the isolation region; as well as A junction field effect transistor (JFET) region is formed in the drift region adjacent to the well region, wherein the isolation region is a current mirror of the JFET region.

26. A vertical SiC device according to any one of claims 23 to 25, wherein: The device region and the sensor region are located in an active region of the vertical SiC device; The sensor area is arranged in a strip shape and is located along an edge of the active area; The sensor area includes one or more sensors; as well as Each sensor in the sensor region is at an equal distance from a gate contact that is electrically connected to the one or more sensors in the sensor region.

27. A vertical SiC device according to any one of claims 23 to 25, wherein: The device region and the sensor region are located in an active region of the vertical SiC device; The sensor area is arranged in an "L" shape and the lower corner of the sensor area is located near the corner of the active area; The sensor area includes one or more sensors; and Each sensor in the sensor region is at an equal distance from a gate contact that is electrically connected to the one or more sensors in the sensor region.

28. A vertical SiC device according to any one of claims 23 to 27, wherein: The device region is a metal oxide semiconductor field effect transistor MOSFET device region, and the MOSFET device region includes one or more MOSFET transistors; and The sensor region is a current sensor region comprising one or more current sensors.

29. A vertical semiconductor device comprising: Drift zone; a device region, the device region including a first portion of the drift region; as well as one or more sensor regions, each of the one or more sensor regions comprising a second portion of the drift region, wherein: Each sensor zone includes one or more sensors, and Each sensor in a respective sensor region is at an equal distance from a respective gate contact that is electrically connected to one or more sensors in the respective sensor region.

30. The vertical semiconductor device of claim 29, further comprising a transition region between the device region and a corresponding sensor region, the transition region comprising: a gate contact above the drift region; as well as An isolation region in the drift region.

31. The vertical semiconductor device of claim 29, further comprising a transition region between the device region and a corresponding sensor region, the transition region comprising: Gate contact; as well as A conductive segment is on and in direct contact with the gate contact.

32. The vertical semiconductor device of claim 29, wherein: The one or more sensor regions is a sensor region; each sensor in the sensor region is at an equal distance from a gate contact, the gate contact being electrically connected to the one or more sensors in the sensor region; as well as The one or more sensors are one or more current sensors.

33. The vertical semiconductor device of claim 29, wherein: The one or more sensor regions are a first sensor region and a second region; The first sensor zone includes one or more first sensors; each first sensor in the first sensor region is at an equal distance from a first gate contact, the first gate contact being electrically connected to the one or more first sensors in the first sensor region; The second sensor zone includes one or more second sensors; each second sensor in the second sensor region is at an equal distance from a second gate contact, the second gate contact being electrically connected to the one or more second sensors in the second sensor region; The one or more first sensors are one or more first current sensors; as well as The one or more second sensors are one or more second current sensors.

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