Camera Serial Interface Controller Test System and Method Based on ZYNQ and HAPS

Abstract

The present invention discloses a camera serial interface controller test system and method based on ZYNQ and HAPS. The system includes a ZYNQ FPGA device as the master device and a HAPS FPGA device as the slave device; wherein, the ZYNQ FPGA device internally includes a D-PHY module and a C IL module, and the HAPS FPGA device internally includes a CS I controller and a DDR memory; the ZYNQ FPGA device is connected to a camera, and the camera transmits image data to the ZYNQ FPGA device through a MIPI interface. The ZYNQ FPGA device converts the image data into a PPI interface signal and transmits it to the CS I controller in the HAPS FPGA device; the CS I controller processes the PPI interface signal, extracts the image data therefrom, and stores it in the DDR memory. By combining the use of the ZYNQ FPGA device and the HAPS FPGA device, the present invention can realize the reception, conversion and processing of the MIPI analog signal output by the camera, and further verify the performance and reliability of the CS I controller.

Description

Technical Field

[0001] The present invention relates to a camera serial interface (CSI) controller test system, in particular to a camera serial interface controller test system based on ZYNQ and HAPS, and also to a corresponding test method, belonging to the field of image communication testing. Background Art

[0002] ZYNQ is a fully programmable system-on-chip launched by Xilinx. Its design concept is to integrate the ARM processor and FPGA on a single chip. This design allows developers to use the ARM processor for advanced processing and control, while using FPGA to implement customized hardware to meet the needs of specific applications. The architecture of the ZYNQ system allows the ARM processor and FPGA to maximize their respective performance, while achieving high-speed, low-latency connection between the two through the AXI interface.

[0003] On the other hand, HAPS (High-Performance ASIC Prototyping System) is an FPGA-based hardware prototyping platform. It was developed by Synopsys to provide fast and efficient physical prototyping during the verification phase of ASIC (Application Specific Integrated Circuit) or SoC (System-on-Chip) design. The HAPS system reduces risk and cost by using FPGA (Field Programmable Gate Array) to simulate the behavior of ASIC, allowing designers to test and verify the design before actual silicon production.

[0004] At present, advanced driver assistance systems (ADAS) are increasingly being used in automobiles to improve driving safety and comfort. Among them, the CSI controller plays a vital role. It is responsible for receiving image data captured by the camera sensor and transmitting the data to the vehicle's central processing unit or other processor through high-speed serial communication to process high-resolution video streams. In order to ensure the performance and reliability of the CSI controller, it is particularly important to carry out simulation testing on it. For example, in the Chinese invention patent with patent number ZL 201811518013.2, a camera controller test system and test method are disclosed. The system uses a simulation host to create virtual driving scenes, the video signal processing module obtains the data of these scenes from the simulation host, and then the CSI controller processes these data to generate corresponding control signals. The simulation host then simulates the dynamic response of the vehicle based on these control signals, and finally outputs the test results of the CSI controller.

[0005] However, existing HAPS systems have significant limitations when simulating CSI controllers. In particular, HAPS systems cannot directly simulate MIPI DPHY, which is a high-speed serial interface connecting camera sensors to application processors. Since the camera outputs analog signals and HAPS systems cannot directly receive and process these signals, they cannot be used to verify the CSI controller in a prototype chip. This means that the functional verification of the CSI controller often has to wait until the ASIC chip is manufactured. This not only increases the risk of R & D projects but also may lead to an extended development cycle. Summary of the Invention

[0006] The primary technical problem to be solved by the present invention is to provide a camera serial interface controller test system based on ZYNQ and HAPS.

[0007] Another technical problem to be solved by the present invention is to provide a camera serial interface controller test method based on ZYNQ and HAPS.

[0008] To achieve the above technical objectives, the present invention adopts the following technical solutions:

[0009] According to the first aspect of the embodiments of the present invention, a camera serial interface controller test system based on ZYNQ and HAPS is provided, including a ZYNQ FPGA device as the master device and a HAPS FPGA device as the slave device; wherein,

[0010] The ZYNQ FPGA device internally includes a D-PHY module and a CIL module, and the HAPS FPGA device internally includes a CSI controller and a DDR memory;

[0011] The ZYNQ FPGA device is connected to the camera, and the camera transmits image data to the ZYNQ FPGA device through the MIPI interface. The ZYNQ FPGA device converts the image data into a PPI interface signal and transmits it to the CSI controller in the HAPS FPGA device;

[0012] The CSI controller processes the PPI interface signal, extracts the image data therefrom, and stores it in the DDR memory.

[0013] Preferably, the camera outputs MIPI analog signals through the MIPI data channel, and the D-PHY module receives the MIPI analog signals and converts them into digital signals, which are input into the CIL module.

[0014] Preferably, the CIL module outputs the decomposed signals in the form of PPI interface signals to the CSI controller inside the HAPS FPGA device.

[0015] According to the second aspect of the embodiments of the present invention, a method for testing a camera serial interface controller based on ZYNQ and HAPS is provided, including the following steps:

[0016] Step 1: Burn FPGA logic into the ZYNQ FPGA device so that the ZYNQ FPGA device can be compatible with and process MIPI analog signals from the camera;

[0017] Step 2: Burn FPGA logic into the HAPS FPGA device to implement the control functions of the CSI controller, CPU, and DDR memory;

[0018] Step 3: The camera transmits image data to the ZYNQ FPGA device through the MIPI interface. The ZYNQ FPGA device converts the image data into a PPI interface signal and transmits it to the CSI controller in the HAPS FPGA device; the CSI controller extracts the image data and stores it in the DDR memory in the HAPS FPGA device; by observing the correctness of the image data exported from the DDR memory, it is judged whether the logic of the CSI controller works as expected.

[0019] Preferably, in the first step, the FPGA logic burned into the ZYNQ FPGA device executes a configuration program to perform initialization settings on the camera.

[0020] Preferably, in the first step, the Vivado development environment is used for the design and development of FPGA logic, and at the same time, the bare-metal software development of the ZYNQ FPGA device is carried out with the development tools under the Vitis development environment.

[0021] Preferably, in the second step, first, download the clock configuration file using the HAPS Configuration Tool, and then download the FPGA logic including the CSI controller and the ARM core; after the FPGA logic is downloaded, instantiate the HAPS FPGA device into a fully functional system-on-chip.

[0022] Preferably, in the second step, the camera outputs an MIPI clock signal through the MIPI interface. The MIPI clock signal is processed by the D-PHY module of the ZYNQ FPGA device and converted into a PPI clock signal, and then transmitted to the HAPS FPGA device. The CSI controller in the HAPS FPGA device uses the PPI clock signal to synchronously acquire image data.

[0023] Preferably, in step 3, a series of configurations are performed during the initialization phase of the CSI controller, including setting the DDR memory address, resolution, and image format for storing image data, enabling developers to determine from which location in the DDR memory to export data and the size of the exported data. After the CSI controller starts working, it collects the image data transmitted by the camera through the MIPI interface and stores it in the DDR memory.

[0024] Preferably, in step 3, the camera is set to the test mode to output a fixed and predictable color bar image. By comparing the exported image file with the expected color bar image, it is checked whether there is local damage to the image data.

[0025] Compared with the prior art, the present invention provides a camera serial interface controller test system and method based on ZYNQ and HAPS, effectively solving the problem that the existing HAPS system cannot directly simulate the MIPI DPHY analog signal, and thus the limitation that it cannot be used to verify the prototype chip with a CSI controller. By combining the use of ZYNQ FPGA device and HAPS FPGA device, the present invention can realize the reception, conversion, and processing of the MIPI analog signal output by the camera, and further verify the performance and reliability of the CSI controller. The ZYNQ FPGA device is responsible for directly docking with the camera interface, collecting the MIPI analog signal and converting it into a PPI interface signal, while the HAPS FPGA device processes these signals and verifies the CSI controller. This method significantly reduces the risk of problems with the CSI controller, improves the success rate of chip tape-out, speeds up the verification process, and reduces the risk and cost of R & D projects. In addition, the present invention also provides a test method. By setting the camera to the test mode to output a fixed image and comparing the exported image data with the expected image, the correctness of the CSI controller logic and the integrity of the image data are further ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic framework diagram of the camera serial interface controller test system provided by the embodiment of the present invention;

[0027] Figure 2 It is a flowchart of the camera serial interface controller test method provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The technical content of the present invention will be described in detail below with reference to the drawings and specific embodiments.

[0029] In the prior art, the HAPS system cannot directly simulate the analog signals of MIPI DPHY, which limits its application in verifying prototype chips with CSI controllers. To solve this problem, the technical concept of the present invention is to use two FPGA devices in combination, with one ZYNQ FPGA device as the master device and the other HAPS FPGA device as the slave device. Among them, the ZYNQ FPGA device plays a key role. It is directly connected to the camera interface and is responsible for collecting the MIPI analog signals output by the camera. The logic circuit inside the ZYNQ FPGA device performs necessary processing on these MIPI data and converts them into interface signals of the Parallel Peripheral Interface (PPI for short). This conversion process is crucial because the CSI controller only supports PPI interface signals and cannot directly process the analog signals of MIPI DPHY. The converted PPI interface signals are then transmitted to the HAPS FPGA device through the logic interface circuit. On the HAPS FPGA device, a logic circuit containing relevant logics such as CSI controller, CPU, and DDR memory has been pre-burned. These logic circuits are responsible for receiving and processing the PPI interface signals from the ZYNQ FPGA device. After the CSI controller receives the PPI interface signals on the HAPS FPGA device, it further processes them and finally transmits the image data to the DDR memory. Through the above test solution that combines the ZYNQ FPGA device and the HAPS FPGA device, the CSI controller can be effectively tested in the FPGA prototype verification stage, thus solving the problem that the HAPS system cannot directly process MIPI analog signals, significantly reducing the risk of problems with the CSI controller, and improving the success rate of chip tape-out.

[0030] As Figure 1As shown, in the camera serial interface controller test system provided by the embodiments of the present invention, it includes a ZYNQ FPGA device as the master device and a HAPS FPGA device as the slave device. Among them, the ZYNQ FPGA device internally includes a D-PHY module and a CIL (Control and Interface Logic) module, and the HAPS FPGA device internally includes a CSI controller and a DDR memory. The ZYNQ FPGA device and the HAPS FPGA device work together to verify the CSI controller. The ZYNQ FPGA device, as the master device, is responsible for directly docking with the camera interface, while the HAPS FPGA device, as the slave device, is responsible for processing and verifying the CSI controller. The camera outputs MIPI analog signals through the MIPI data channel (lane), and these signals are first sent to the ZYNQ FPGA device. The D-PHY module inside the ZYNQ FPGA device is responsible for receiving the MIPI analog signals of the camera. The D-PHY module converts these signals into digital signals for further processing. The D-PHY module supports two modes: high speed (HS) and low power (LP), and can dynamically switch according to needs to optimize the data transmission speed and power consumption. The digital signals processed by the D-PHY module enter the CIL module of the ZYNQ FPGA device. The CIL module is responsible for decomposing these signals into clock signals, data signals, and control signals to prepare for the interface with the HAPS FPGA device. The CIL module outputs the decomposed signals in the form of PHY-Protocol Interface (PPI) interface signals. The PPI interface signal is a digital interface that transmits the signals to the HAPS FPGA device. The HAPS FPGA device internally contains a CSI controller, which receives the PPI interface signals from the ZYNQ FPGA device through the PPI interface. The CSI controller is responsible for processing these signals and extracting the image data from the data channel. The processed image data is finally transmitted to the DDR memory in the HAPS FPGA device. The DDR memory is used to store the image data for further analysis and verification.

[0031] Next, in combination with Figure 2 the specific steps shown below, the camera serial interface controller test method provided by the embodiments of the present invention will be described in detail.

[0032] Step 1: Burn the FPGA logic into the ZYNQ FPGA device so that the ZYNQ FPGA device can be compatible with and process the MIPI analog signals from the camera.

[0033] In this step, efforts are made to burn specialized FPGA logic into the ZYNQ FPGA device. This logic is carefully designed to ensure that it can be fully compatible with and process the MIPI analog signals from the camera. The MIPI analog signal is the industry standard for communication between the camera and the processor in mobile devices.

[0034] The FPGA logic burned into the ZYNQ FPGA device can not only process MIPI analog signals but also has the ability to initialize the camera. The initialization process includes powering on the camera, which is a necessary step to start the camera and prepare it for image capture. Once the camera is powered on, the FPGA logic will execute the configuration program to initialize the camera settings. This includes adjusting the camera parameters such as resolution, frame rate, and exposure settings to ensure that it can work properly according to the predetermined performance standards.

[0035] After the configuration is completed, the camera will start to capture and output images. These image data will be transmitted through the FPGA logic in the format of MIPI analog signals, providing input for subsequent processing and verification steps.

[0036] In an embodiment of the present invention, the ZYNQ UltraScale+ MP SoC series platform of Xilinx is adopted. This platform integrates two major functional blocks, namely the PS (Processing System) and the PL (Programmable Logic). Among them, the PS part integrates an ARM processor, and the PL part provides flexible FPGA logic. To meet the test requirements, a dedicated development board can be built. It is not only equipped with download interfaces such as JTAG but also designed with the necessary interfaces for docking with the HAPS FPGA device.

[0037] The specific development process is carried out on the Windows operating system. The Vivado development environment of Xilinx is used for the design and development of FPGA logic, and the development tools under the Vitis development environment are used for the bare-metal software development of the ZYNQ FPGA device. In the Vivado development environment, the MIPI DPHY IP core provided by Xilinx is used, which is designed specifically for receiving and processing camera data. By creating programmable logic (PL), adding IP cores, allocating pins, setting pin constraints, and adding timing constraints, the FPGA logic design is completed, and an XSA (Xilinx Software Archive) file is generated. In the Vitis development environment, the XSA file is imported as a hardware platform project, and an APP software project is created on this basis. In the APP software project, code is written to initialize the relevant peripherals on the processing system (PS) side. After compilation, the final executable and linkable format (ELF) file is generated.

[0038] In terms of physical connection, the development board is connected to the computer through a JTAG cable, and a USB cable of UART is used for communication. After setting the startup mode of the development board to JTAG mode, power it on again, and burn the program into the ZYNQ FPGA device through the Vitis development environment, thus completing the entire development and verification process.

[0039] It should be noted that when processing the MIPI analog signal data output by the camera, the key component is the D-PHY module, which is responsible for implementing signal reception and processing in the programmable logic (PL) part of the ZYNQ FPGA device. In the Vivado development environment of Xilinx, the IP core of the D-PHY module is used to implement this function, and careful configuration is required to ensure smooth docking with another FPGA device - the HAPS FPGA device. This includes allocating IO output pins for the PPI (PHY-Protocol Interface) interface, setting the number of MIPI data channels (lanes), and configuring the data transfer rate (lane rate) of each MIPI data channel.

[0040] Among them, the data transfer rate (lane rate) of each MIPI data channel is calculated based on the configuration of the camera. The formula for calculating this data transfer rate involves the resolution, frame rate, pixel bit depth of the camera, and an empirical coefficient of 1.2. Generally, the data transfer rate of each MIPI data channel can be estimated by multiplying the frequency of the MIPI clock signal output by the camera by 2. In practical applications, the setting of this data transfer rate does not need to match the output of the camera exactly, because the D-PHY module has good adaptability and can work properly within a certain range.

[0041] For the configuration of the camera, a corresponding software program needs to be developed in the Vitis development environment to access and set the registers of the camera through the I2C interface. The configuration content includes the output format, resolution, frame rate of the camera, and the number of MIPI data channels used. In a preferred embodiment of the present invention, the camera is set to output the RAW10 pixel format, with a resolution of VGA (640*480), a frame rate of 10fps, and a single MIPI data channel is used for data transmission.

[0042] Through the above configuration, it can be ensured that the image data of the camera is efficiently transmitted to the ZYNQ FPGA device through the MIPI interface, and then transmitted to the HAPS FPGA device through the PPI interface, and finally the storage and further processing of the image data are realized.

[0043] Step 2: Burn the FPGA logic into the HAPS FPGA device to implement the control functions of the CSI controller, CPU, and DDR memory.

[0044] In this step, the logic burning of the HAPS FPGA device will be carried out. This process involves burning the FPGA logic code containing key functions into the HAPS FPGA device. These key functions include the control functions of the CSI controller, CPU, and DDR memory, which are the key components to realize the complete functions of the entire test system.

[0045] The CSI controller is the core component responsible for managing and processing the image data from the camera. It ensures that the image data can be efficiently received and necessary processing is carried out for subsequent use. The CPU is responsible for executing the operation and control tasks of the entire test system. The DDR memory is responsible for managing the interface with the DDR memory to ensure that data can be transmitted quickly and stably between the FPGA device and the memory.

[0046] The FPGA logic code burned into the HAPS FPGA device will initialize and configure the above-mentioned functional components to ensure their coordinated operation. Among them, the CSI controller will be set to match the output specifications of the camera, including data format, resolution, and frame rate. The CPU will load the necessary operating system and applications to support the execution of image processing and other tasks. The DDR memory will be configured to optimize the data transfer rate and improve the memory access efficiency.

[0047] After the burning is completed, the HAPS FPGA device will be ready to receive image data from the ZYNQ FPGA device and process and verify it through its internal logic. Through this process, it can be ensured that the HAPS FPGA device can efficiently process image data and be prepared for final storage and analysis.

[0048] In an embodiment of the present invention, the HAPS series verification platform provided by Synopsys is adopted. This is a high-performance prototype verification hardware platform specifically developed to cope with complex and large-scale FPGA / ASIC designs. The design of this platform aims to accelerate the design verification process by providing a prototype close to the performance of the final product.

[0049] The process of burning the FPGA logic into the HAPS FPGA device is completed through the dedicated software provided by Synopsys - the HAPS Configuration Tool. This tool is designed for the Windows operating system and realizes the connection with the HAPS FPGA device through the USB interface. At the beginning of the operation, first use the HAPS Configuration Tool to download the clock configuration file, which is responsible for establishing the clock resources required by the system. These clock resources are crucial for driving each IP core in the system.

[0050] Next, the FPGA logic containing key IP cores such as the CSI controller, ARM core, SRAM, and DDR will be downloaded. These IP cores constitute the core functions of the entire test system. After the FPGA logic is downloaded, the HAPS FPGA device is instantiated as a fully functional SoC (system-on-chip). At this time, the HAPS FPGA device already has the ability to execute complex tasks, including image processing, data storage, and system control, etc.

[0051] To achieve an effective connection with external devices, the HAPS FPGA device provides multiple external interfaces. In a preferred embodiment of the present invention, a functional daughter board can be designed to dock with the HAPS FPGA device. For example, the previously mentioned PPI interface can be connected to the ZYNQ FPGA device through these functional daughter boards. Such a design not only ensures efficient data transmission between the HAPS FPGA device and the ZYNQ FPGA device, but also facilitates the integration and testing of the entire test system.

[0052] Through this series of configuration and programming steps, the HAPS FPGA device can accurately simulate the behavior of the final product, enabling technicians to comprehensively test and verify the entire design solution before actual production.

[0053] When implementing the test solution for the CSI controller, in order to ensure the utilization of only necessary resources, a development board based on the ZYNQ core board is specifically designed in a preferred embodiment of the present invention, which is equipped with carefully selected peripheral circuits. Such a design strategy aims to construct a system dedicated to verifying the logic of the CSI controller IP part in the HAPS FPGA device.

[0054] On the development board, the configuration of logic units, memories, and I / O ports entirely depends on the functions required for verifying the CSI controller. This means that only those IP cores and resources that are crucial for achieving this goal are incorporated into the design. This selective resource configuration method helps improve development efficiency and ensures that resources are not wasted on unnecessary functions.

[0055] In terms of I / O allocation and configuration, the same principle is followed. Only those I / O ports that are crucial for the verification process are allocated and configured. This not only simplifies the system design but also helps reduce potential errors and complexities, thus ensuring the smooth progress of the verification process.

[0056] In addition, during the process of verifying the correctness of the CSI controller, clock synchronization is a crucial step. The starting point of clock synchronization is the crystal oscillator inside the camera, which provides the necessary operating clock for the camera. Once the camera is initialized through the program of the ZYNQ device - this process involves configuring the camera through the I2C interface, including setting the resolution, the number of MIPI data channels, and the output image format, etc. - the camera starts to work normally and outputs the MIPI clock signal (clk) and data signal (data) through the MIPI interface.

[0057] The frequency of the MIPI clock signal output by the camera is determined by the operating clock of the camera. In some configurations, this rate may be half of the operating clock frequency. This operating clock then becomes the synchronization reference clock for the entire signal transmission path. The MIPI clock signal (clk) and data signal (data) enter the D-PHY module of the ZYNQ FPGA device for processing, where they are converted into parallel signals of the PPI interface. The PPI interface includes a PPI clock, eight data lines, and some status and control signals. The frequency of the PPI clock signal is one-fourth of the operating clock frequency, that is, one-eighth of the frequency of the MIPI clock signal.

[0058] On the development board, the PPI interface is connected to the HAPS FPGA device through a predefined connection method. Inside the HAPS FPGA device, the CSI controller uses the input PPI clock signal as the synchronization signal for collecting data. When the CSI controller receives the PPI interface signal from the ZYNQ FPGA device, it starts to collect image data and stores this data in the DDR memory.

[0059] In summary, the synchronization process of the entire clock signal can be summarized as follows: The camera outputs the MIPI clock signal through the MIPI interface. After being processed by the D-PHY module of the ZYNQ FPGA device, this MIPI clock signal is converted into the PPI clock signal, which is then transmitted to the HAPS FPGA device through the ZYNQ development board. Finally, the CSI controller in the HAPS FPGA device uses this PPI clock signal to synchronize the collection of image data. Such a clock synchronization mechanism ensures the consistency and accuracy of the image data throughout the process from the camera to the final storage.

[0060] Step 3: The camera transmits image data to the ZYNQ FPGA device through the MIPI interface. The ZYNQ FPGA device converts the image data into PPI interface signals and transmits them to the CSI controller in the HAPS FPGA device. The CSI controller extracts the image data and stores it in the DDR memory of the HAPS FPGA device. By observing the correctness of the image data exported from the DDR memory, it is judged whether the logic of the CSI controller works as expected.

[0061] During the testing process of the CSI controller, a specific program firmware needs to be burned onto the HAPS FPGA device. This program firmware is designed to test the function of the CSI controller to ensure that it can correctly process image data. The burning process is completed through a dedicated configuration tool, which loads the program firmware into the memory of the HAPS FPGA device.

[0062] Once the program firmware is burned onto the HAPS FPGA device, it will automatically run and start the initialization process. This includes the initialization of related peripherals such as the CSI controller and DDR memory. The CSI controller is a key component responsible for receiving and processing image data from the camera, while the DDR memory manages the storage of image data. Initialization ensures that these peripherals are configured as expected and ready to receive and process the upcoming data stream.

[0063] After initialization is completed, the CSI controller starts to work, collecting the image data transmitted by the camera through the MIPI interface. The collected image data is then stored in the DDR memory. To test whether the logic of the CSI controller is correct, it is necessary to inspect the image data stored on the DDR. This is usually done through specialized tools that export the image data from the DDR memory for further analysis.

[0064] The ultimate goal of the testing process is to confirm whether the CSI controller can accurately process and store image data. By observing the correctness of the image data exported from the DDR memory, it can be determined whether the logic of the CSI controller works as expected. If the image data is correct, this indicates that the logic of the CSI controller is correct, thus testing the function of the prototype chip.

[0065] In an embodiment of the present invention, U-Boot can be selected when developing the program for the CSI controller. U-Boot is an open-source bootloader that is widely used in various embedded devices. It was originally designed for the PowerPC architecture but now supports a variety of different processor architectures, including ARM, MIPS, x86, etc. As an open-source software tool well-known in the industry, it will not be elaborated here in detail.

[0066] The main function of the CSI controller program is to initialize peripherals on the HAPS FPGA device, such as the UART serial port. The UART serial port is an important tool for monitoring the running status of the CSI controller program. After completing the program development in the software environment, the source code is compiled into the final bin file, the executable file, through an open-source cross-compiler. A cross-compiler is a special compiler that can generate code to run on a target platform different from the compiler's running environment, allowing developers to compile programs that run on the target hardware on the host system.

[0067] After compilation, use a JTAG emulator to download the bin file of the executable program into the RAM of the HAPS FPGA device. The JTAG emulator is a standard test access port that allows developers to program and debug the target hardware. After running the program on the HAPS FPGA device, the running status of the program can be observed by connecting to the UART serial port of the computer. On the computer side, use serial port debugging assistant software to receive and display the information sent by the HAPS FPGA device through the UART serial port, so as to realize real-time monitoring of the running status of the CSI controller program.

[0068] In a preferred embodiment of the present invention, the TRACE32 PowerView for ARM software can be used to easily export image data from the DDR memory. Specifically, during the initialization phase of the CSI controller, a series of configurations are performed, including setting the DDR memory address, resolution, and image format where the image data is stored. These configuration information enable developers to determine from which location in the DDR memory to start exporting data and the size of the exported data (determined by the resolution and image format). Subsequently, these data are output in the form of an image file through the TRACE32 PowerView for ARM software. To ensure the accuracy of the exported image data, the camera is set to the test mode to output a fixed and predictable color bar image. In this mode, the image data generated by the camera can be expected, thus providing a benchmark to test the exported image file. By comparing the exported image file with the expected color bar image, it can be checked whether there are local damages or other problems in the image data. This comparison process is an effective method to judge whether the CSI controller captures images correctly.

[0069] Through the above test process, the accuracy and reliability of the CSI controller in receiving and processing image data can be ensured, thus providing a solid foundation for the successful deployment and operation of the entire test system.

[0070] Compared with the prior art, the present invention provides a camera serial interface controller test system and method based on ZYNQ and HAPS, effectively solving the problem that the existing HAPS system cannot directly simulate MIPI D-PHY analog signals, thus being unable to be used to verify the limitations of prototype chips with CSI controllers. By combining the use of ZYNQ FPGA devices and HAPS FPGA devices, the present invention can achieve the reception, conversion, and processing of MIPI analog signals output by the camera, and further verify the performance and reliability of the CSI controller. The ZYNQ FPGA device is responsible for directly docking with the camera interface, collecting MIPI analog signals and converting them into PPI interface signals, while the HAPS FPGA device processes these signals and verifies the CSI controller. This method significantly reduces the risk of problems with the CSI controller, improves the success rate of chip tape-out, speeds up the verification process, and reduces the risks and costs of R & D projects. In addition, the present invention also provides a test method, by setting the camera to the test mode to output a fixed image, comparing the exported image data with the expected image, further ensuring the correctness of the CSI controller logic and the integrity of the image data.

[0071] It should be noted that the above embodiments are only examples. The technical solutions of each embodiment can be combined and are all within the protection scope of the present invention.

[0072] The above has described in detail the camera serial interface controller test system and method based on ZYNQ and HAPS provided by the present invention. For those of ordinary skill in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A camera serial interface controller test method based on ZYNQ and HAPS, wherein the ZYNQ FPGA device is used as a master device and the HAPS FPGA device is used as a slave device; the ZYNQ FPGA device includes a D-PHY module and a CIL module, and the HAPS FPGA device includes a CSI controller and a DDR memory; The ZYNQ FPGA device is connected to a camera, and the camera transmits image data to the ZYNQ FPGA device through a MIPI interface. The ZYNQ FPGA device converts the image data into a PPI interface signal and transmits it to a CSI controller in the HAPS FPGA device. The CSI controller processes the PPI interface signal, extracts image data from it, and stores it in the DDR memory, characterized in that The steps include: Step 1: Burning FPGA logic for the ZYNQ FPGA device so that the ZYNQ FPGA device can be compatible with and process the MIPI analog signal from the camera; Step 2: Burn FPGA logic for the HAPS FPGA device to realize the control functions of the CSI controller, CPU and DDR memory; Step 3: The camera transmits image data to the ZYNQ FPGA device through the MIPI interface. The ZYNQ FPGA device converts the image data into a PPI interface signal and transmits it to the CSI controller in the HAPS FPGA device. The CSI controller extracts the image data and stores it in the DDR memory in the HAPS FPGA device. By observing the correctness of the image data exported from the DDR memory, it is determined whether the logic of the CSI controller works as expected.

2. The camera serial interface controller testing method as claimed in claim 1, characterized in that: In the step 1, the FPGA logic executed by the ZYNQ FPGA device is burned into a configuration program to initialize the camera.

3. The camera serial interface controller testing method as claimed in claim 1, characterized in that: In step 1, the Vivado development environment is used to design and develop FPGA logic, and the bare metal software development of the ZYNQ FPGA device is carried out with the help of the development tools in the Vitis development environment.

4. The camera serial interface controller testing method as claimed in claim 1, characterized in that: In the step 2, the clock configuration file is first downloaded using the HAPS Configuration Tool, and then the FPGA logic including the CSI controller and the ARM core is downloaded; after the FPGA logic is downloaded, the HAPS FPGA device is instantiated into a fully functional system-level chip.

5. The camera serial interface controller testing method as claimed in claim 4, characterized in that: In the step 2, the camera outputs a MIPI clock signal through the MIPI interface. The MIPI clock signal is converted into a PPI clock signal after being processed by the D-PHY module of the ZYNQ FPGA device, and then transmitted to the HAPS FPGA device. The CSI controller in the HAPS FPGA device uses the PPI clock signal to synchronously collect image data.

6. The camera serial interface controller testing method as claimed in claim 1, characterized in that: In the step three, a series of configurations are performed during the initialization phase of the CSI controller, including setting the DDR memory address, resolution, and image format for storing image data, so that the developer can determine the location of the DDR memory from which to start exporting data and the size of the exported data; after the CSI controller starts working, it collects image data transmitted by the camera through the MIPI interface and stores it in the DDR memory.

7. The camera serial interface controller testing method as claimed in claim 6, characterized in that: In the step three, the camera is set to a test mode to output a fixed, predictable color bar image; by comparing the exported image file with the expected color bar image, it is checked whether the image data has local damage.

8. The camera serial interface controller testing method according to claim 1, wherein: The camera outputs a MIPI analog signal through a MIPI data channel, and the D-PHY module receives the MIPI analog signal and converts it into a digital signal, which is then input into the CIL module.

9. The camera serial interface controller testing method as claimed in claim 8, characterized in that: The CIL module outputs the decomposed signal to the CSI controller inside the HAPS FPGA device in the form of a PPI interface signal.

Images