Driving stage circuit, display device and electronic device

Abstract

An embodiment of the present invention relates to a driving stage circuit, a display device, and an electronic device, the driving stage circuit comprising: a driving unit that receives a start signal and generates a first signal and an inverted first signal using a first clock signal and a second clock signal; and a first generation unit that generates a second signal using a preceding-stage first signal and a preceding-stage inverted first signal supplied from the driving unit of the preceding-stage driving stage circuit, and a backward-stage first signal supplied from the driving unit of the backward-stage driving stage circuit. The drive unit and the first generation unit are electrically connected to a first power supply input terminal to which a first power supply is input and a second power supply input terminal to which a second power supply is input.

Description

Technical Field

[0001] The present invention relates to a driving stage circuit, a display device having the driving stage circuit, and an electronic device having the display device. Background Art

[0002] As the information society develops, the demand for display devices for displaying images in various forms is increasing. For example, display devices are used in various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and digital televisions.

[0003] The display device displays an image using pixels and may include a plurality of scanning drive units and light emission drive units in order to drive the pixels.

[0004] In order to drive the display device at a high driving frequency while minimizing power consumption, a pixel may include a P-type transistor (PMOS as an example) and an N-type transistor (NMOS as an example).

[0005] In the case where a pixel includes a P-type transistor and an N-type transistor, in order to drive the pixel, the display device may include a plurality of driving parts, thereby increasing dead space. In addition, in the case where the display device includes a plurality of driving parts, power consumption may increase. Summary of the invention

[0006] An object of the present invention is to provide a driving stage circuit capable of reducing ineffective space and power consumption, a display device having the driving stage circuit, and an electronic device having the display device.

[0007] The driving stage circuit involved in the embodiment of the present invention comprises: a driving unit, which receives a start signal and generates a first signal and an inverted first signal using a first clock signal and a second clock signal; and a first generating unit, which generates a second signal using a preceding stage first signal and an inverted preceding stage first signal supplied from a driving unit of a preceding stage driving stage circuit and a succeeding stage first signal supplied from a driving unit of a succeeding stage driving stage circuit, wherein the driving unit and the first generating unit are electrically connected to a first power input terminal for inputting a first power supply and a second power input terminal for inputting a second power supply.

[0008] According to an embodiment, the first clock signal and the second clock signal have the same period and opposite phases.

[0009] According to an embodiment, the driving unit includes: an input unit, which controls the voltage of the first node using the start signal, the first clock signal and the second clock signal; a first output unit, which is connected to the first power input terminal and the second power input terminal, and controls the voltage of the first output terminal corresponding to the voltage of the first node; and a second output unit, which is connected to the first power input terminal and the second power input terminal, and controls the voltage of the second output terminal corresponding to the voltage of the first output terminal.

[0010] According to an embodiment, the first output terminal outputs the inverted first signal, and the second output terminal outputs the first signal.

[0011] According to an embodiment, the input unit includes: a first transistor and a second transistor, which are connected in parallel between a first input terminal for inputting the start signal and the first node, a gate electrode of the first transistor is connected to a second input terminal for inputting the first clock signal, and a gate electrode of the second transistor is connected to a third input terminal for inputting the second clock signal.

[0012] According to an embodiment, the first transistor is an N-type transistor and the second transistor is a P-type transistor.

[0013] According to an embodiment, the first output section and the second output section are inverters, respectively.

[0014] According to an embodiment, the first output unit includes: a P-type third transistor and an N-type fourth transistor, which are arranged in series between the first power input terminal and the second power input terminal, the gate electrodes of the third transistor and the fourth transistor are connected to the first node, and the common node between the third transistor and the fourth transistor is connected to the first output terminal.

[0015] According to an embodiment, the second output unit includes: a P-type fifth transistor and an N-type sixth transistor, which are arranged in series between the first power input terminal and the second power input terminal, the gate electrodes of the fifth transistor and the sixth transistor are connected to the first output terminal, and the common node between the fifth transistor and the sixth transistor is connected to the second output terminal.

[0016] According to an embodiment, the driving unit further includes: a first capacitor connected between the first node and the second power input terminal.

[0017] According to an embodiment, the first generating unit includes: a control unit, which controls the voltage of the first node using a first input signal supplied to a first signal input terminal and a second input signal supplied to a second signal input terminal; and an output unit, which outputs the second signal to the output terminal corresponding to a third input signal supplied to a third signal input terminal and the voltage of the first node.

[0018] According to an embodiment, the first input signal is the subsequent stage first signal, the second input signal is the inverted first signal of the previous stage, and the third input signal is the previous stage first signal.

[0019] According to an embodiment, the control unit comprises: a P-type first transistor connected between the first power input terminal and the first node, and a gate electrode connected to the first signal input terminal; and an N-type second transistor connected between the first node and the second power input terminal, and a gate electrode connected to the second signal input terminal.

[0020] According to an embodiment, the output unit comprises: a P-type third transistor connected between the first power input terminal and the output terminal, and a gate electrode connected to the third signal input terminal; and an N-type fourth transistor connected between the output terminal and the second power input terminal, and a gate electrode connected to the first node.

[0021] According to an embodiment, the first generating unit further includes: a second capacitor connected between the first node and the second power input terminal.

[0022] According to an embodiment, the first power source is set to a high level voltage, and the second power source is set to a low level voltage which is a voltage lower than the first power source.

[0023] According to an embodiment, the driving stage circuit also has: a second generating unit, including a circuit identical to the first generating unit, outputting a third signal using a fourth input signal input to a fourth signal input terminal, a fifth input signal input to a fifth signal input terminal, and a sixth input signal input to a sixth signal input terminal.

[0024] According to an embodiment, the fourth input signal is different from the first input signal, the fifth input signal is different from the second input signal, and the sixth input signal is different from the third input signal.

[0025] A display device according to an embodiment of the present invention comprises: a plurality of pixels, which are arranged to be connected to a plurality of scanning lines, a plurality of light-emitting control lines and a plurality of data lines; and a scanning / light-emitting driving section, which comprises a plurality of driving stage circuits for driving at least one of the plurality of scanning lines and the plurality of light-emitting control lines, a plurality of first dummy driving stage circuits located at the front stage of the plurality of driving stage circuits and a plurality of second dummy driving stage circuits located at the rear stage of the plurality of driving stage circuits, wherein the i-th driving stage circuit among the plurality of driving stage circuits comprises: a driving section, which receives a start signal and generates a first signal and an inverted first signal using a first clock signal and a second clock signal; and a generating section, which generates a second signal using a preceding stage first signal and an inverted preceding stage first signal supplied from a driving section of a preceding stage driving stage circuit and a rear stage first signal supplied from a driving section of a rear stage driving stage circuit, wherein the start signal is a first signal of an i-1-th driving stage circuit, the first signal is a first scanning signal supplied to an i-th first scanning line, and the second signal is a second scanning signal supplied to an i-th second scanning line or a light-emitting control signal supplied to an i-th light-emitting control line.

[0026] An electronic device according to an embodiment of the present invention comprises: a display module including a display panel for displaying a predetermined image; a processor for supplying data corresponding to the predetermined image to the display module; a gate driver included in the display module, and comprising a plurality of drive-stage circuits, a plurality of first dummy drive-stage circuits located at the front stage of the plurality of drive-stage circuits, and a plurality of second dummy drive-stage circuits located at the rear stage of the plurality of drive-stage circuits in order to supply at least one of a scan signal and a light-emission control signal to a plurality of pixels included in the display panel, wherein the i-th drive-stage circuit among the plurality of drive-stage circuits comprises: a drive unit for receiving a start signal and generating a first signal and an inverted first signal using a first clock signal and a second clock signal; and a generation unit for generating a second signal using a front-stage first signal and a front-stage inverted first signal supplied from a drive unit of a front-stage drive-stage circuit and a rear-stage first signal supplied from a drive unit of a rear-stage drive-stage circuit, wherein the start signal is a first signal of an i-1-th drive-stage circuit, the first signal is a first scan signal supplied to an i-th first scan line, and the second signal is a second scan signal supplied to an i-th second scan line or a light-emission control signal supplied to an i-th light-emission control line.

[0027] The subject of the present invention is not limited to the subject mentioned above, and those skilled in the art should be able to understand other technical subjects not mentioned through the following description.

[0028] (Effects of the Invention)

[0029] According to the driving stage circuit, the display device having the driving stage circuit, and the electronic device having the display device involved in the embodiments of the present invention, a low-level first signal and a high-level second signal can be generated by using one driving stage circuit.

[0030] That is, in the embodiment of the present invention, one driving stage circuit may be used to generate signals for driving the P-type transistor and the N-type transistor, thereby minimizing the dead space.

[0031] However, the effects of the present invention are not limited to the above-mentioned effects, and various extensions can be made without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 FIG. 1 is a diagram showing a driving stage circuit according to an embodiment of the present invention.

[0033] Figure 2 Yes means Figure 1 FIG. 1 is a diagram showing an embodiment of a driving method for a driver stage circuit.

[0034] Figure 3 Yes means Figure 1 FIG. 1 is a diagram showing an embodiment of a driving method for a driver stage circuit.

[0035] Figure 4 FIG. 1 is a diagram showing a driving stage circuit according to an embodiment of the present invention.

[0036] Figure 5 It is a diagram showing a display device according to an embodiment of the present invention.

[0037] Figure 6 Yes means Figure 5 A diagram of an embodiment of a pixel is shown.

[0038] Figure 7 Yes means Figure 6 FIG. 1 is a waveform diagram of an embodiment of a pixel driving method shown in FIG.

[0039] Figure 8 Yes means Figure 5 A diagram of an embodiment of a scanning / light-emitting driving unit is shown.

[0040] Fig. 9 It means Figure 8 The diagram shows the terminals of the driver stage circuit connections.

[0041] Fig.10 It is separated by function Fig. 9 Diagram of the driver stage circuit.

[0042] Fig.11 It is a diagram showing a display device according to an embodiment of the present invention.

[0043] Fig.12 It is a diagram showing a display device according to an embodiment of the present invention.

[0044] Fig.13 Yes means Fig.12 A diagram of an embodiment of a scan driving unit is shown.

[0045] Fig.14 It means Fig.13 The diagram shows the terminals of the driver stage circuit connections.

[0046] Fig.15 It is separated by function Fig.14 Diagram of the driver stage circuit.

[0047] Fig.16 Yes means Fig.12 A diagram of an embodiment of a light emitting driving unit is shown.

[0048] Fig.17 It means Fig.16 The diagram shows the terminals of the driver stage circuit connections.

[0049] Fig.18 It is separated by function Fig.17 Diagram of the driver stage circuit.

[0050] Fig.19 It is a diagram showing an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0051] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be implemented in various different ways and is not limited to the embodiments described herein.

[0052] In order to clearly explain the present invention, parts not related to the explanation are omitted, and the same or similar components are given the same symbols throughout the specification. Therefore, the symbols explained above can be used in other drawings.

[0053] In addition, the size and thickness of each structure shown in the figure are arbitrarily shown for convenience of explanation, and therefore the present invention is not necessarily limited to the cases shown in the figure.

[0054] Furthermore, the expression "same" in the description may mean "substantially the same". That is, it may mean the sameness to a degree that can be recognized by a person skilled in the art. Other expressions may be expressions in which "substantially" is omitted.

[0055] Some embodiments are described in the accompanying drawings associated with functional blocks, units and / or modules. Those skilled in the art should be able to understand that such blocks, units and / or modules can be physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, wiring connections and other electronic circuits. It can be formed using semiconductor-based manufacturing technology or other manufacturing technology. In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, software can be used to program or control, so as to perform various functions discussed in the present invention, and optionally, it can be driven by firmware and / or software. In addition, blocks, units and / or modules can be implemented by dedicated hardware, or they can be implemented by a combination of dedicated hardware that performs some functions and processors that perform other functions (for example, more than one programmed microprocessor and related circuits). In addition, in some embodiments, blocks, units and / or modules can also be physically separated into more than two separate blocks, units and / or modules that interact with each other without exceeding the scope of the concept of the present invention. In addition, in some embodiments, blocks, units and / or modules can also be physically combined into more complex blocks, units and / or modules without exceeding the scope of the concept of the present invention.

[0056] The term "connection" between two components may refer to both electrical connection and physical connection, but is not necessarily limited to this. For example, the term "connection" used with reference to a circuit diagram may refer to electrical connection, and the term "connection" used with reference to a cross-sectional view or a plan view may refer to physical connection.

[0057] Although the terms "first" and "second" are used to describe various components, these components are certainly not limited to these terms. These terms are used only to distinguish one component from other components. Therefore, the first component mentioned below can also be the second component within the technical concept of the present invention.

[0058] On the other hand, the present invention is not limited to the embodiments disclosed below, and can be implemented in various forms. In addition, each embodiment disclosed below can be implemented alone, or can be combined with at least one other embodiment to implement in combination.

[0059] Figure 1 FIG. 1 is a diagram showing a driving stage circuit according to an embodiment of the present invention.

[0060] Reference Figure 1 The driving stage circuit 200 according to an embodiment of the present invention may include a driving unit 210 and a generating unit 220 .

[0061] The driving unit 210 and the generating unit 220 may be connected to a first power input terminal 231 and a second power input terminal 232. The first power input terminal 231 may receive a first power supply VGH, and the second power input terminal 232 may receive a second power supply VGL. Here, the first power supply VGH may be set to a voltage higher than the second power supply VGL.

[0062] As an example, the voltage of the first power supply VGH can be set to the gate-off voltage of a P-type transistor or the gate-on voltage of an N-type transistor. As an example, the voltage of the second power supply VGL can be set to the gate-on voltage of a P-type transistor or the gate-off voltage of an N-type transistor.

[0063] The driving unit 210 may output a first signal FS for driving a first type (for example, a P-type) transistor. To this end, the driving unit 210 may include an input unit 230, a first output unit 240, a second output unit 250, and a first capacitor C1.

[0064] The input unit 230 may be electrically connected to the first input terminal 211, the second input terminal 212, and the third input terminal 213. The first input terminal 211 may receive the start signal FLM, the second input terminal 212 may receive the first clock signal CLK1, and the third input terminal 213 may receive the second clock signal CLK2.

[0065] The start signal FLM may be supplied from a timing control unit (not shown). The start signal FLM may be an output signal (or a first signal) of a driver unit of a preceding driver stage.

[0066] like Figure 2 As shown, the first clock signal CLK1 can be a rectangular wave signal that repeatedly has a high voltage and a low voltage. The high voltage of the first clock signal CLK1 can be set to the gate cut-off voltage of the P-type transistor or the gate on voltage of the N-type transistor. The low voltage of the first clock signal CLK1 can be set to the gate on voltage of the P-type transistor or the gate cut-off voltage of the N-type transistor.

[0067] like Figure 2 As shown, the second clock signal CLK2 can be a rectangular wave signal that repeatedly has a high voltage and a low voltage. The high voltage of the second clock signal CLK2 can be set to the gate cut-off voltage of the P-type transistor or the gate on voltage of the N-type transistor. The low voltage of the second clock signal CLK2 can be set to the gate on voltage of the P-type transistor or the gate cut-off voltage of the N-type transistor. The first clock signal CLK1 and the second clock signal CLK2 can be signals with the same period and inverted phases.

[0068] The input unit 230 may control the voltage of the first node N1 connected to the first output unit 240 in accordance with the clock signals CLK1 and CLK2 supplied to the second input terminal 212 and the third input terminal 213. The input unit 230 may include a first transistor M1 and a second transistor M2 connected in parallel between the first input terminal 211 and the first node N1.

[0069] The first transistor M1 is formed by an N-type transistor and is connected between the first input terminal 211 and the first node N1. Here, the meaning of connection may include the meaning of electrical connection. The gate electrode of the first transistor M1 is connected to the second input terminal 212. The first transistor M1 as described above can be turned on or off corresponding to the first clock signal CLK1 supplied to the second input terminal 212 while controlling the electrical connection between the first input terminal 211 and the first node N1.

[0070] The second transistor M2 is formed by a P-type transistor and is connected between the first input terminal 211 and the first node N1. The gate electrode of the second transistor M2 is connected to the third input terminal 213. As described above, the second transistor M2 can be turned on or off corresponding to the second clock signal CLK2 supplied to the third input terminal 213, while controlling the electrical connection between the first input terminal 211 and the first node N1.

[0071] The first transistor M1 and the second transistor M2 are set as transistors of different types and connected in parallel between the first input terminal 211 and the first node N1. That is, the first transistor M1 and the second transistor M2 can be configured as a transmission gate circuit (Transmission Gate), which transmits the start signal FLM supplied to the first input terminal 211 to the first node N1 corresponding to the clock signals CLK1 and CLK2.

[0072] On the other hand, the second input terminal included in the subsequent driver stage circuit can receive the second clock signal CLK2, and the third input terminal included in the subsequent driver stage circuit can receive the first clock signal CLK1. Thus, the continuous driver stage circuits can be driven in the manner of a shift register, and the first signal FS can be shifted and outputted every half cycle of the clock signals CLK1 and CLK2.

[0073] The first output unit 240 may be driven in an inverter manner to control the voltage of the first output terminal 214 corresponding to the voltage of the first node N1. To this end, the first output unit 240 may include a third transistor M3 and a fourth transistor M4 connected in series between the first power input terminal 231 and the second power input terminal 232. The gate electrodes of the third transistor M3 and the fourth transistor M4 may be connected to the first node N1.

[0074] The third transistor M3 may be formed of a P-type transistor and connected between the first power input terminal 231 and the first output terminal 214. The third transistor M3 as described above may control the electrical connection between the first power input terminal 231 and the first output terminal 214 corresponding to the voltage of the first node N1.

[0075] The fourth transistor M4 may be formed of an N-type transistor and connected between the second power input terminal 232 and the first output terminal 214. The fourth transistor M4 as described above may control the electrical connection between the second power input terminal 232 and the first output terminal 214 corresponding to the voltage of the first node N1.

[0076] The first output terminal 214 may output the voltage supplied from the first output unit 240 as an inverted first signal / FS.

[0077] The second output unit 250 may be driven in an inverter manner, and the voltage of the first output terminal 214 may be inverted to supply it to the second output terminal 215. In this case, the first signal FS may be output to the second output terminal 215. The inverted first signal / FS may have a voltage obtained by inverting the first signal FS. As an example, when the first signal FS is set to a high voltage (or a low voltage), the inverted first signal / FS may be set to a low voltage (or a high voltage).

[0078] The second output unit 250 may include a fifth transistor M5 and a sixth transistor M6 connected in series between the first power input terminal 231 and the second power input terminal 232. Gate electrodes of the fifth transistor M5 and the sixth transistor M6 may be connected to the first output terminal 214.

[0079] The fifth transistor M5 may be formed of a P-type transistor and connected between the first power input terminal 231 and the second output terminal 215. The fifth transistor M5 as described above may control the electrical connection between the first power input terminal 231 and the second output terminal 215 corresponding to the voltage of the first output terminal 214.

[0080] The sixth transistor M6 may be formed of an N-type transistor and connected between the second power input terminal 232 and the second output terminal 215. The sixth transistor M6 as described above may control the electrical connection between the second power input terminal 232 and the second output terminal 215 corresponding to the voltage of the first output terminal 214.

[0081] The second output terminal 215 may output the voltage supplied from the second output part 250 as the first signal FS.

[0082] The first capacitor C1 may be connected between the first node N1 and the second power input terminal 232. The first capacitor C1 as described above may store the voltage of the first node N1.

[0083] The generator 220 may output a second signal SS for driving the second type (for example, N-type) and / or first type (for example, P-type) transistors. To this end, the generator 220 may include a controller 260, an output unit 270, and a second capacitor C2.

[0084] The control unit 260 may be electrically connected to the first signal input terminal 221 and the second signal input terminal 222. The first signal input terminal 221 may receive a first signal (or a first input signal) FS_N of a subsequent driving stage circuit.

[0085] The predetermined driving section (scanning driving section, light emitting driving section, scanning / light emitting driving section, etc.) may include a plurality of driving stage circuits 200, and the plurality of driving stage circuits 200 may be driven in a shift register manner while sequentially outputting a first signal FS and a second signal SS. Assuming that the driving stage circuit 200 is located at the i-th (i is a natural number) pixel row (or horizontal line), the first signal (or first input signal) FS_N of the subsequent driving stage circuit may be the first signal outputted from any one of the plurality of driving stage circuits located after the i-th pixel row.

[0086] The second signal input terminal 222 can receive the inverted first signal (or second input signal) / FS_F of the previous driver stage circuit. Assuming that the driver stage circuit 200 is located at the i-th pixel row (or horizontal line), the inverted first signal (or second input signal) / FS_F of the previous driver stage circuit can be an inverted first signal output from any one of the plurality of driver stage circuits located before the i-th pixel row.

[0087] The control unit 260 may control the voltage of the first node N11 in accordance with the first input signal FS_N and the second input signal / FS_F supplied to the first signal input terminal 221 and the second signal input terminal 222. The control unit 260 may include a first transistor M11 and a second transistor M12 connected in series between the first power input terminal 231 and the second power input terminal 232.

[0088] The first transistor M11 may be formed of a P-type transistor and connected between the first power input terminal 231 and the first node N11. The gate electrode of the first transistor M11 may be connected to the first signal input terminal 221. The first transistor M11 as described above may be turned on or off corresponding to the first input signal FS_N supplied to the first signal input terminal 221 while controlling the electrical connection between the first power input terminal 231 and the first node N11.

[0089] The second transistor M12 may be formed of an N-type transistor and connected between the first node N11 and the second power input terminal 232. The gate electrode of the second transistor M12 may be connected to the second signal input terminal 222. The second transistor M12 as described above may be turned on or off corresponding to the second input signal / FS_F supplied to the second signal input terminal 222 while controlling the electrical connection between the second power input terminal 232 and the first node N11.

[0090] The output unit 270 may control the voltage of the output terminal 224 in accordance with the voltage of the first node N11. As an example, the output unit 270 may output the second signal SS to the output terminal 224. To this end, the output unit 270 may include a third transistor M13 and a fourth transistor M14 connected in series between the first power input terminal 231 and the second power input terminal 232.

[0091] The third transistor M13 may be formed of a P-type transistor, and connected between the first power input terminal 231 and the output terminal 224. The gate electrode of the third transistor M13 may be connected to the third signal input terminal 223. As described above, the third transistor M13 may be turned on or off corresponding to the first signal (or third input signal) FS_F of the front-stage driver stage supplied to the third signal input terminal 223, and control the electrical connection between the first power input terminal 231 and the output terminal 224.

[0092] Assuming that the driver stage circuit 200 is located in the i-th pixel row (or horizontal line), the first signal (or third input signal) FS_F of the previous driver stage circuit may be a first signal output from any one of the plurality of driver stage circuits located before the i-th pixel row. The third input signal FS_F may be equivalent to a signal obtained by inverting the second input signal / FS_F. That is, the second input signal / FS_F and the third input signal FS_F may be output signals of the same driver stage circuit.

[0093] The fourth transistor M14 may be formed of an N-type transistor and connected between the output terminal 224 and the second power input terminal 232. The gate electrode of the fourth transistor M14 may be connected to the first node N11. As described above, the fourth transistor M14 may be turned on or off corresponding to the voltage of the first node N11 while controlling the electrical connection between the second power input terminal 232 and the output terminal 224.

[0094] The second capacitor C2 may be connected between the first node N11 and the second power input terminal 232. The second capacitor C2 as described above may store the voltage of the first node N11.

[0095] Figure 2 Yes means Figure 1 FIG. 1 is a diagram showing an embodiment of a driving method for a driver stage circuit. Figure 3 Yes means Figure 1 FIG. 1 is a diagram showing an embodiment of a driving method for a driver stage circuit.

[0096] exist Figure 2 In the figure, it is assumed that the driver stage circuit 200 is located at the i-th horizontal line. In addition, it is assumed that the first input signal FS_N is the first signal FSi+4 of the i+4th driver stage circuit, the second input signal / FS_F is the inverted first signal / FSi-2 of the i-2th driver stage circuit, and the third input signal FS_F is the first signal FSi-2 of the i-2th driver stage circuit.

[0097] Reference Figure 2 , the first clock signal CLK1 and the second clock signal CLK2 have the same period and are inverted in phase.

[0098] First, at the first time point t1 , a high level (or high voltage) second input signal / FS_F is input to the second signal input terminal 222 , and a low level (or low voltage) third input signal FS_F is input to the third signal input terminal 223 .

[0099] When the second input signal / FS_F of high level is input to the second signal input terminal 222, the second transistor M12 is turned on. When the second transistor M12 is turned on, the second power source VGL is supplied to the first node N11. When the second power source VGL is supplied to the first node N11, the fourth transistor M14 is turned off.

[0100] If the third input signal FS_F of a low level is input to the third signal input terminal 223, the third transistor M13 is turned on. If the third transistor M13 is turned on, the voltage of the first power supply VGH is supplied to the output terminal 224. The voltage of the first power supply VGH supplied to the output terminal 224 can be supplied to a separate signal line (for example, a scan line or a light emission control line) as a second signal (or a high-level second signal) SSi.

[0101] At the second time point t2, a low-level start signal FLM is supplied to the first input terminal 211. Here, the start signal FLM may be the first signal FSi-1 of the i-1th driver stage circuit. At the second time point t2, the first clock signal CLK1 is set to a low level and the second clock signal CLK2 is set to a high level, so the first transistor M1 and the second transistor M2 maintain an off state.

[0102] At the third time point t3 , the second input signal / FS_F of a low level is input to the second signal input terminal 222 , and the third input signal FS_F of a high level is input to the third signal input terminal 223 .

[0103] If the second input signal / FS_F of a low level is input to the second signal input terminal 222, the second transistor M12 is turned off. At this time, the fourth transistor M14 is kept turned off according to the voltage charged in the second capacitor C2.

[0104] If the third input signal FS_F of a high level is input to the third signal input terminal 223, the third transistor M13 is turned off. At this time, the output terminal 224 can maintain the voltage of the second signal SSi of a high level according to the parasitic capacitance of the output terminal 224 and the separate signal line.

[0105] At the third time point t3, the high level first clock signal CLK1 is supplied to the second input terminal 212, thereby turning on the first transistor M1. At the third time point t3, the low level second clock signal CLK2 is supplied to the third input terminal 213, thereby turning on the second transistor M2.

[0106] If the first transistor M1 and the second transistor M2 are turned on, a low level start signal FLM may be supplied to the first node N1. If a low level start signal FLM is supplied to the first node N1, the third transistor M3 may be turned on, and the fourth transistor M4 may be turned off.

[0107] When the third transistor M3 is turned on, the voltage of the first power source VGH is supplied to the first output terminal 214. The first power source VGH supplied to the first output terminal 214 may be supplied to a subsequent driver stage (for example, the i+2 th driver stage) as an inverted first signal / FSi.

[0108] If the voltage of the first power supply VGH is supplied to the first output terminal 214, the fifth transistor M5 is turned off and the sixth transistor M6 is turned on. If the sixth transistor M6 is turned on, the voltage of the second power supply VGL is supplied to the second output terminal 215. The voltage of the second power supply VGL supplied to the second output terminal 215 can be supplied to a separate signal line (for example, a scanning line) as a first signal (or a low-level first signal) FSi.

[0109] At the fourth time point t4, a high voltage (or a high start signal FLM) is supplied to the first input terminal 211. At the fourth time point t4, the first clock signal CLK1 is set to a low level and the second clock signal CLK2 is set to a high level, so the first transistor M1 and the second transistor M2 maintain an off state.

[0110] At the fifth time point t5 , the first clock signal CLK1 is set to a high level and the second clock signal CLK2 is set to a low level, so that the first transistor M1 and the second transistor M2 are turned on.

[0111] If the first transistor M1 and the second transistor M2 are turned on, a high level voltage may be supplied to the first node N1, so that the third transistor M3 may be turned off and the fourth transistor M4 may be turned on.

[0112] When the fourth transistor M4 is turned on, the voltage of the second power supply VGL is supplied to the first output terminal 214. When the voltage of the second power supply VGL is supplied to the first output terminal 214, the supply of the inverted first signal / FSi can be interrupted (or the inverted first signal / FSi of a low level is supplied).

[0113] If the voltage of the second power supply VGL is supplied to the first output terminal 214, the fifth transistor M5 is turned on and the sixth transistor M6 is turned off. If the fifth transistor M5 is turned on, the voltage of the first power supply VGH is supplied to the second output terminal 215. If the voltage of the first power supply VGH is supplied to the second output terminal 215, the supply of the first signal FSi can be interrupted (or the first signal FSi of a high level is supplied).

[0114] At the sixth time point t6, the first input signal FS_N of a low level is input to the first signal input terminal 221. If the first input signal FS_N of a low level is input to the first signal input terminal 221, the first transistor M11 is turned on.

[0115] If the first transistor M11 is turned on, the voltage of the first power supply VGH is supplied to the first node N11. If the voltage of the first power supply VGH is supplied to the first node N11, the fourth transistor M14 is turned on. If the fourth transistor M14 is turned on, the voltage of the second power supply VGL is supplied to the output terminal 224. If the voltage of the second power supply VGL is supplied to the output terminal 224, the output of the second signal SSi is interrupted (or the second signal SSi of a low level is supplied).

[0116] As described above, the driving stage circuit 200 according to the embodiment of the present invention can supply the start signal FLM to the driving unit 210, so that the low-level first signal FSi can be output from the driving unit 210. The low-level first signal FSi output from the driving unit 210 can be supplied to the P-type transistor as a scanning signal.

[0117] In addition, the driving stage circuit 200 according to the embodiment of the present invention can supply the first input signal FS_N, the second input signal / FS_F and the third input signal FS_F to the generating unit 220, thereby outputting the high-level second signal SSi. The high-level second signal SSi output from the generating unit 220 can be supplied to the P-type transistor as a light emitting control signal. In addition, the high-level second signal SSi output from the generating unit 220 can be supplied to the N-type transistor as a scanning signal.

[0118] Furthermore, in the embodiment of the present invention, the first input signal FS_N, the second input signal / FS_F, and the third input signal FS_F supplied to the generating unit 220 are controlled, so that the supply period of the high-level second signal SSi can be controlled. Figure 2 In the embodiment, the second signal SSi can maintain a high-level voltage within three cycles of the first clock signal CLK1.

[0119] As an example, Figure 3 As shown, the first input signal FS_N may be the first signal FSi+7 of the i+7th driver stage circuit, the second input signal / FS_F may be the inverted first signal / FSi-4 of the i-4th driver stage circuit, and the third input signal FS_F may be the first signal FSi-4 of the i-4th driver stage circuit. In this case, the second signal SSi may maintain a high level voltage during more than five cycles of the first clock signal CLK1.

[0120] Figure 4 FIG. 1 is a diagram showing a driving stage circuit according to an embodiment of the present invention. Figure 4 When Figure 1 Detailed description of the same composition.

[0121] Reference Figure 4 The driving stage circuit 200 a according to an embodiment of the present invention may include a driving unit 210 and a generating unit 220 .

[0122] The driving unit 210 and the generating unit 220 may be electrically connected to the first power input terminal 231 and the second power input terminal 232 .

[0123] The driving unit 210 can output the first signal FS and the inverted first signal / FS. To this end, the driving unit 210 can include an input unit 230, a first output unit 240, a second output unit 250, and a first capacitor C1. Figure 1 Therefore, repeated description is omitted.

[0124] The generating unit 220 may output the second signals SSa and SSb. To this end, the generating unit 220 may include a first generating unit 220a, a second generating unit 220b, and a plurality of second capacitors C2.

[0125] The first generating unit 220a may include a control unit 260a, an output unit 270a, and a second capacitor C2. The control unit 260a and the output unit 270a are configured similarly to Figure 1 The control unit 260 and the output unit 270 shown are the same, and duplicate descriptions are omitted.

[0126] The first signal input terminal 221a of the first generating unit 220a can receive the first input signal FS_Na, the second signal input terminal 222a can receive the second input signal / FS_Fa, and the third signal input terminal 223a can receive the third input signal FS_Fa. The first generating unit 220a as described above can output the second signal SSa to the output terminal 224a corresponding to the first input signal FS_Na, the second input signal / FS_Fa, and the third input signal FS_Fa.

[0127] The second generating unit 220b may include a control unit 260b, an output unit 270b, and a second capacitor C2. The control unit 260b and the output unit 270b are configured similarly to Figure 1 The control unit 260 and the output unit 270 shown are the same, and duplicate descriptions are omitted.

[0128] The first signal input terminal (or the fourth signal input terminal) 221b of the second generating unit 220b can receive the first input signal (or the fourth input signal) FS_Nb, the second signal input terminal (or the fifth signal input terminal) 222b can receive the second input signal (or the fifth input signal) / FS_Fb, and the third signal input terminal (or the sixth signal input terminal) 223b can receive the third input signal (or the sixth input signal) FS_Fb. The second generating unit 220b as described above can output the second signal (or the third signal) SSb to the output terminal 224b corresponding to the first input signal FS_Nb, the second input signal / FS_Fb and the third input signal FS_Fb.

[0129] Here, the width (or length) of the high-level second signal SSa output from the first generating section 220a is different from the width (or length) of the high-level second signal SSb output from the second generating section 220b.

[0130] As an example, the first input signal FS_Na may be the first signal of the i+4th driver stage circuit, the second input signal / FS_Fa may be the inverted first signal of the i-2nd driver stage circuit, and the third input signal FS_Fa may be the first signal of the i-2nd driver stage circuit. In this case, the high-level second signal SSa outputted from the first generating unit 220a may maintain a high-level voltage within three cycles of the first clock signal CLK1.

[0131] As an example, the first input signal FS_Nb may be the first signal of the i+7th driver stage circuit, the second input signal / FS_Fb may be the inverted first signal of the i-4th driver stage circuit, and the third input signal FS_Fb may be the first signal of the i-4th driver stage circuit. In this case, the high-level second signal SSb output from the second generating unit 220b may maintain a high-level voltage during more than five cycles of the first clock signal CLK1.

[0132] That is, in the embodiment of the present invention, the driving stage circuits 200 and 200 a may include a plurality of generating units 220 as needed, and accordingly may generate the second signal SS having various widths.

[0133] The driver stage circuits 200 and 200a involved in the above-mentioned embodiments of the present invention can generate low-level signals and high-level signals using one driver stage, thereby minimizing the installation area of ​​the driver stage circuits 200 and 200a. In addition, the driver stage circuits 200 and 200a involved in the embodiments of the present invention use two clock signals CLK1 and CLK2, one start signal FLM, and two power supplies VGH and VGL, so the installation area of ​​the driver stage circuits 200 and 200a can be minimized (i.e., reducing the dead space).

[0134] Furthermore, in the embodiment of the present invention, various signals may be generated using two clock signals CLK1 , CLK2 , thereby minimizing power consumption caused by charging and discharging of the capacitors C1 , C2 .

[0135] Figure 5 It is a diagram showing a display device according to an embodiment of the present invention.

[0136] Reference Figure 5 The display device 100 according to an embodiment of the present invention may include a pixel unit (or panel) 110, a timing control unit 120, a scanning / light-emitting driving unit 130, a data driving unit 140, and a power supply unit 150. The above-mentioned structures may be implemented by a separate integrated circuit, and two or more of the above-mentioned structures may be combined into one integrated circuit for implementation. In addition, the scanning / light-emitting driving unit 130 may be formed in the pixel unit 110.

[0137] The pixel portion 110 may include pixels PX (here, n and m are natural numbers) connected to the first scan lines SL11, SL12, ..., SL1n, the second scan lines SL21, SL22, ..., SL2n, the third scan lines SL31, SL32, ..., SL3n, the fourth scan lines SL41, SL42, ..., SL4n, the data lines DL1, DL2, ..., DLm, the light emitting control lines EL1, EL2, ..., ELn and the power lines PL1, PL2, PL3, PL4.

[0138] As an example, a pixel PXij (refer to Figure 6 ) can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the i-th light emitting control line ELi and the j-th data line DLj.

[0139] When the first scan signal is supplied to the first scan lines SL11 to SL1n, the pixels PX can be selected in units of horizontal lines (for example, the pixels PX connected to the same scan line can be classified into one horizontal line (or pixel row)), and the pixels PX selected according to the first scan signal can receive a data signal from a data line (any one of DL1 to DLm) connected to the pixels PX. The pixels PX that have received the data signal can generate light of a predetermined brightness corresponding to the voltage of the data signal.

[0140] The scanning / light-emitting driving part 130 may receive a first driving control signal SCS from the timing control part 120. The first driving control signal SCS may include a start signal FLM and clock signals CLK1 and CLK2 required for driving the scanning / light-emitting driving part 130.

[0141] The scanning / light-emitting driving unit 130 can use the clock signals CLK1 and CLK2 to shift the start signal FLM and generate a first signal FS. Here, the first signal FS can be a first scanning signal. The scanning / light-emitting driving unit 130 can use the first signal FS to generate at least one second signal SS. Here, the second signal SS can be a second scanning signal and / or a light-emitting control signal. The scanning / light-emitting driving unit 130 has a plurality of driving stage circuits, and detailed descriptions thereof will be described later.

[0142] The scanning signal may be set to a gate-on voltage so as to turn on the transistor included in the pixel PX. As an example, the scanning signal supplied to the P-type transistor may be set to a low level. As an example, the scanning signal supplied to the N-type transistor may be set to a high level. Hereinafter, supplying the scanning signal may indicate supplying a gate-on voltage to the scanning lines SL1, SL2, SL3, and SL4. In addition, not supplying the scanning signal may indicate supplying a gate-off voltage to the scanning lines SL1, SL2, SL3, and SL4.

[0143] The light emitting control signal may be set to a gate-off voltage so as to turn off the transistor included in the pixel PX. As an example, the light emitting control signal supplied to the P-type transistor may be set to a high level. As an example, the light emitting control signal supplied to the N-type transistor may be set to a low level. Hereinafter, supplying the light emitting control signal may indicate supplying the gate-off voltage to the light emitting control line EL. In addition, not supplying the light emitting control signal may indicate supplying the gate-on voltage to the light emitting control line EL.

[0144] The data driving unit 140 may receive the output data Dout and the second driving control signal DCS from the timing control unit 120. The second driving control signal DCS may include a sampling signal and / or a timing signal required for driving the data driving unit 140. The data driving unit 140 may generate a data signal based on the second driving control signal DCS and the output data Dout. As an example, the data driving unit 140 may generate an analog data signal based on the grayscale of the output data Dout. The data driving unit 140 may supply the data signal in units of 1 horizontal period.

[0145] The timing control unit 120 may receive input data Din and control signal CS from the main system through an interface. As an example, the timing control unit 120 may receive input data Din and control signal CS from at least one of a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), and an AP (Application Processor) included in the main system. The control signal CS may include various signals including a clock signal.

[0146] The timing control part 120 may generate a first driving control signal SCS and a second driving control signal DCS based on the control signal CS. The first driving control signal SCS may be supplied to the scanning / light-emission driving part 130 , and the second driving control signal DCS may be supplied to the data driving part 140 .

[0147] The timing control unit 120 may realign the input data Din according to the specification of the display device 100. In addition, the timing control unit 120 may correct the input data Din to generate the output data Dout, and supply the output data Dout to the data driving unit 140. In an embodiment, the timing control unit 120 may correct the input data Din corresponding to the optical measurement result measured during the process.

[0148] The power supply unit 150 may generate various power sources required for driving the display device 100. For example, the power supply unit 150 may generate a first driving power source VDD, a second driving power source VSS, a first initialization power source Vint1, and a second initialization power source Vint2.

[0149] The first driving power source VDD may be a power source for supplying driving current to the pixel PX. The second driving power source VSS may be a power source for receiving driving current from the pixel PX. During the period when the pixel PX is set to the light emitting state, the first driving power source VDD may be set to a voltage higher than the second driving power source VSS.

[0150] The first initialization power source Vint1 is a power source for initializing the gate electrode of the driving transistor included in each pixel PX. The second initialization power source Vint2 is a power source for initializing the light emitting element LD included in each pixel PX (refer to Figure 6 ). The first initialization power Vint1 may be set to a voltage that is the same as or different from the second initialization power Vint2. The first initialization power Vint1 may be set to a voltage lower than the data signal.

[0151] The first driving power VDD generated by the power supply unit 150 may be supplied to the first power line PL1, the second driving power VSS generated by the power supply unit 150 may be supplied to the second power line PL2, the first initialization power Vint1 generated by the power supply unit 150 may be supplied to the third power line PL3, and the second initialization power Vint2 generated by the power supply unit 150 may be supplied to the fourth power line PL4. The first power line PL1, the second power line PL2, the third power line PL3, and the fourth power line PL4 may be commonly connected to the pixel PX, but the embodiment of the present invention is not limited thereto.

[0152] In an embodiment, the first power line PL1 may be composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the second power line PL2 may be composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the third power line PL3 may be composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. In an embodiment, the fourth power line PL4 may be composed of a plurality of power lines, and the plurality of power lines may be connected to different pixels PX. That is, in an embodiment of the present invention, the pixel PX may be connected to any one of the first power line PL1, any one of the second power line PL2, any one of the third power line PL3, and any one of the fourth power line PL4.

[0153] Figure 6 Yes means Figure 5FIG. 1 is a diagram of an embodiment of a pixel shown in FIG. Figure 6 , pixels located at the i-th horizontal line and the j-th vertical line are shown.

[0154] Reference Figure 6 , the pixel PXij involved in the embodiment of the present invention can be connected to the corresponding signal lines SL1i, SL2i, SL3i, SL4i, ELi, and DLj. For example, the pixel PXij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th fourth scan line SL4i, the i-th light emitting control line ELi, and the j-th data line DLj. In the following, for the sake of convenience of explanation, prefixes such as "i-th" or "j-th" may not be added. In the embodiment, the pixel PXij can also be connected to the first power line PL1, the second power line PL2, the third power line PL3, and the fourth power line PL4.

[0155] The i-th third scan line SL3i may be the i-1-th second scan line SL2i-1. The i-th fourth scan line SL4i may be the i-1-th first scan line SL1i-1. In this case, in practice, the signals required for driving the pixel PXij are set to the first scan signal GW, the second scan signal GC, and the light emitting control signal EM. That is, the i-th third scan line SL3i is driven according to the second scan signal of the previous pixel row, and the i-th fourth scan line SL4i is driven according to the first scan signal of the previous pixel row.

[0156] The pixel PXij according to the embodiment of the present invention may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0157] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2. As an example, the first electrode (or anode) of the light emitting element LD may be electrically connected to the first power line PL1 via the sixth transistor M26, the third node N23, the first transistor M21, the second node N22, and the fifth transistor M25, and the second electrode (or cathode) of the light emitting element LD may be electrically connected to the second power line PL2. The light emitting element LD may generate light of a predetermined brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0158] The light emitting element LD may be an organic light emitting diode. In addition, the light emitting element LD may be an inorganic light emitting diode such as a micro LED or a quantum dot light emitting diode. In addition, the light emitting element LD may be a composite element of organic and inorganic substances. Figure 6 , the pixel PXij includes a single light emitting element LD, but in other embodiments, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected in series, in parallel, or in series and in parallel.

[0159] The pixel circuit may include a first transistor M21, a second transistor M22, a third transistor M23, a fourth transistor M24, a fifth transistor M25, a sixth transistor M26, a seventh transistor M27 and a storage capacitor Cst.

[0160] A first electrode of the first transistor (or driving transistor) M21 may be connected to the second node N22, and a second electrode of the first transistor M21 may be connected to the third node N23. In addition, a gate electrode of the first transistor M21 may be connected to the first node N21. The first transistor M21 may control the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the light emitting element LD in correspondence with the voltage of the first node N21.

[0161] The second transistor M22 may be connected between the data line DLj and the second node N22. In addition, the gate electrode of the second transistor M22 may be electrically connected to the first scan line SL1i. The second transistor M22 as described above may be turned on when the first scan signal GW is supplied to the first scan line SL1i, thereby electrically connecting the data line DLj and the second node N22.

[0162] A first electrode of the third transistor M23 may be connected to the first node N21, and a second electrode of the third transistor M23 may be electrically connected to the third power line PL3. In addition, a gate electrode of the third transistor M23 may be electrically connected to the third scan line SL3i. The third transistor M23 may be turned on when the third scan signal GI is supplied to the third scan line SL3i, thereby supplying a voltage of the first initialization power supply Vint1 to the first node N21. The first initialization power supply Vint1 may be set to a voltage lower than a data signal supplied to the data line DLj.

[0163] The fourth transistor M24 may be connected between the first node N21 and the third node N23. In addition, the gate electrode of the fourth transistor M24 may be electrically connected to the second scan line SL2i. The fourth transistor M24 as described above may be turned on when the second scan signal GC is supplied to the second scan line SL2i, thereby electrically connecting the first node N21 and the third node N23. That is, if the fourth transistor M24 is turned on, the first transistor M21 may be connected as a diode.

[0164] A first electrode of the fifth transistor M25 may be electrically connected to the first power line PL1, and a second electrode of the fifth transistor M25 may be connected to the second node N22. In addition, a gate electrode of the fifth transistor M25 may be electrically connected to the light emission control line ELi. The fifth transistor M25 may be turned off when the light emission control signal EM is supplied to the light emission control line ELi, and may be turned on when the light emission control signal EM is not supplied.

[0165] The sixth transistor M26 may be connected between the third node N23 and the first electrode of the light emitting element LD. In addition, the gate electrode of the sixth transistor M26 may be electrically connected to the light emitting control line ELi. The sixth transistor M26 may be turned off when the light emitting control signal EM is supplied to the light emitting control line ELi, and may be turned on when the light emitting control signal EM is not supplied.

[0166] The first electrode of the seventh transistor M27 may be connected to the first electrode of the light emitting element LD, and the second electrode of the seventh transistor M27 may be electrically connected to the fourth power line PL4. In addition, the gate electrode of the seventh transistor M27 may be electrically connected to the fourth scan line SL4i. The seventh transistor M27 as described above may be turned on when the fourth scan signal GB is supplied to the fourth scan line SL4i, thereby supplying the voltage of the second initialization power supply Vint2 to the first electrode of the light emitting element LD.

[0167] If the voltage of the second initialization power supply Vint2 is supplied to the first electrode of the light emitting element LD, the parasitic capacitance of the light emitting element LD can be discharged. As the residual voltage charged in the parasitic capacitance of the light emitting element LD is discharged (or removed), undesired fine light emission can be prevented. Therefore, the black performance capability of the pixel PXij can be improved.

[0168] The storage capacitor Cst may be connected between the first power line PL1 and the first node N21. The storage capacitor Cst may store a voltage applied to the first node N21.

[0169] In one embodiment, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26 and the seventh transistor M27 may be formed by polycrystalline silicon semiconductor transistors. For example, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26 and the seventh transistor M27 may include a polycrystalline silicon semiconductor layer formed by an LTPS (low temperature poly-silicon) process in the active layer (channel). In addition, the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26 and the seventh transistor M27 may be P-type transistors (e.g., PMOS transistors). Thus, the gate-on voltage that turns on the first transistor M21, the second transistor M22, the fifth transistor M25, the sixth transistor M26 and the seventh transistor M27 may be a logic low level. Polycrystalline silicon semiconductor transistors have the advantage of fast response speed, and therefore can be applied to switch elements that require fast switching.

[0170] In one embodiment, the third transistor M23 and the fourth transistor M24 may be formed by oxide semiconductor transistors. For example, the third transistor M23 and the fourth transistor M24 may be N-type oxide semiconductor transistors (e.g., NMOS transistors), including an oxide semiconductor layer as an active layer. Thus, the gate-on voltage that turns on the third transistor M23 and the fourth transistor M24 may be a logic high level.

[0171] Oxide semiconductor transistors can realize low temperature processes and have low charge mobility compared to polysilicon semiconductor transistors. That is, oxide semiconductor transistors have excellent cut-off current characteristics. Therefore, if the third transistor M23 and the fourth transistor M24 are formed by oxide semiconductor transistors, the leakage current caused by low-frequency driving can be minimized, thereby improving the display quality.

[0172] Figure 7 Yes means Figure 6 FIG. 1 is a waveform diagram of an embodiment of a pixel driving method shown in FIG. Figure 7 In the figure, it is assumed that the i-th third scan line SL3i is the i-1th second scan line SL2i-1 and the i-th fourth scan line SL4i is the i-1th first scan line SL1i-1.

[0173] Reference Figure 7 A frame interval may include a non-luminous interval P_NE, and the non-luminous interval P_NE may include an initialization interval P_INT, a compensation interval P_C, and a writing interval P_W. The writing interval P_W may be included in the compensation interval P_C.

[0174] In the non-light emitting interval P_NE, the light emitting control signal EM may have a high level. In this case, in response to the high level of the light emitting control signal EM, the fifth transistor M25 and the sixth transistor M26 are turned off, and the pixel PXij may not emit light.

[0175] In the initialization interval P_INT, the third scan signal GI may have a high level. In this case, in response to the high level third scan signal GI, the third transistor M23 may be turned on and may supply the voltage of the first initialization power Vint1 of the third power line PL3 to the first node N21.

[0176] Next, in the compensation period P_C, the second scan signal GC may have a high level. In response to the high level of the second scan signal GC, the fourth transistor M24 may be turned on, and the first transistor M21 may be diode-connected.

[0177] In the write interval P_W, the first scan signal GW may have a low level. In this case, in response to the low-level first scan signal GW, the second transistor M22 may be turned on, and a data signal may be provided from the j-th data line DLj to the second node N22. In addition, in response to the high-level second scan signal GC, the fourth transistor M24 may be in a turned-on state, so that a data signal may be transmitted from the second node N22 to the first node N21 via the first transistor M21 and the fourth transistor M24. Through the turned-on fourth transistor M24, the first transistor M21 may maintain a diode-connected state, so that the first node N21 may have a voltage that compensates for the threshold voltage of the first transistor M21 based on the data signal.

[0178] Before the writing interval P_W, the fourth scan signal GB may have a low level. In this case, in response to the low level fourth scan signal GB, the seventh transistor M27 may be turned on and the voltage of the second initialization power supply Vint2 may be supplied to the first electrode of the light emitting element LD.

[0179] Then, the non-luminous interval P_NE ends, and the light-emitting control signal EM may have a low level. In this case, in response to the low-level light-emitting control signal EM, the fifth transistor M25 and the sixth transistor M26 are turned on. If the fifth transistor M25 and the sixth transistor M26 are turned on, a current moving path is formed from the first power line PL1 through the fifth transistor M25, the first transistor M21, the sixth transistor M26 and the light-emitting element LD to the second power line PL2. At this time, through the operation of the first transistor M21, the driving current corresponding to the voltage of the first node N21 flows through the light-emitting element LD, and the light-emitting element LD can emit light at a brightness corresponding to the driving current.

[0180] Figure 8 Yes means Figure 5 A diagram of an embodiment of a scanning / light-emitting driving unit is shown.

[0181] Reference Figure 8 A scanning / light-emitting driving unit 130 according to an embodiment of the present invention includes a plurality of first dummy driving stage circuits FDST1, FDST2, ..., driving stage circuits ST1, ..., STi, ..., STn and second dummy driving stage circuits SDST1, SDST2, ...

[0182] The first dummy driving stage circuit FDST, the driving stage circuit ST, and the second dummy driving stage circuit SDST may have Figure 4 As an example, the first dummy driver stage circuit FDST, the driver stage circuit ST, and the second dummy driver stage circuit SDST may include a driver unit 210, a first generator 220a, and a second generator 220b, respectively.

[0183] The first dummy driving stage circuit FDST may sequentially generate a first scanning signal GW (ie, first signal FS) and an inverted first scanning signal / GW (ie, inverted first signal / FS) while alternately receiving the first clock signal CLK1 and the second clock signal CLK2 .

[0184] The inverted first scanning signal / GW generated by the first dummy driving stage circuit FDST can be used as the second input signal / FS_Fa, / FS_Fb of the first generating section 220a and the second generating section 220b included in any one of the plurality of driving stage circuits ST. The first scanning signal GW generated by the first dummy driving stage circuit FDST can be used as the third input signal FS_Fa, FS_Fb of the first generating section 220a and the second generating section 220b included in any one of the plurality of driving stage circuits ST.

[0185] The number of first dummy driving stage circuits FDST may be determined in accordance with the width of the high-level emission control signal EM and / or the high-level second scanning signal GC. For example, the number of first dummy driving stage circuits FDST may increase as the width of the high-level emission control signal EM increases.

[0186] The second dummy driving stage circuit SDST may generate the first scanning signal GW (ie, the first signal FS) while alternately receiving the first clock signal CLK1 and the second clock signal CLK2 .

[0187] The first scan signal GW generated by the second dummy driving stage circuit SDST may be used as the first input signals FS_Na, FS_Nb of the first generating section 220 a and the second generating section 220 b included in any one of the plurality of driving stage circuits ST.

[0188] The number of second dummy driving stage circuits SDST may be determined in accordance with the width of the high-level emission control signal EM and / or the high-level second scanning signal GC. For example, the number of second dummy driving stage circuits SDST may increase as the width of the high-level emission control signal EM increases.

[0189] The driving stage circuit ST may generate a first scanning signal GW (ie, first signal FS), a second scanning signal GC (ie, second signal SSa), and a light emitting control signal EM (ie, second signal SSb) while alternately receiving the first clock signal CLK1 and the second clock signal CLK2.

[0190] Each driver stage circuit ST can use Figure 4 The driving unit 210 shown in the figure generates the first scanning signal GW, the first generating unit 220a generates the second scanning signal GC, and the second generating unit 220b generates the light emitting control signal EM. The working process of each driving stage circuit ST as described above is the same as Figure 4 same.

[0191] Fig. 9 It means Figure 8 The diagram shows the terminals of the driver stage circuit connections. Fig.10 It is separated by function Fig. 9 The driver stage circuit diagram is shown in Figure 1. Fig. 9 and Fig.10 The i-th driving stage circuit STi is shown in FIG.

[0192] Reference Figure 1 , Figure 4 , Fig. 9 and Fig.10 The i-th driving stage circuit STi includes a driving section 210, a first generating section 220a and a second generating section 220b. As described above, the driving section 210, the first generating section 220a and the second generating section 220b are configured similarly to the above. Figure 4 The driver stage circuit 200a shown is identical.

[0193] The i-th driving stage circuit STi can be connected to the first input terminal 211, the second input terminal 212, the third input terminal 213, the first signal input terminal 221a, the second signal input terminal 222a, the third signal input terminal 223a, the first signal input terminal 221b, the second signal input terminal 222b, the third signal input terminal 223b, the first output terminal 214, the second output terminal 215, the output terminal 224a, the output terminal 224b, the first power supply input terminal 231 and the second power supply input terminal 232.

[0194] The first input terminal 211 receives the start signal FLM (or the scanning signal GWi-1 of the previous driving stage circuit), the second input terminal 212 receives the first clock signal CLK1, and the third input terminal 213 receives the second clock signal CLK2. The driving unit 210 can use the start signal FLM (or GWi-1), the first clock signal CLK1 and the second clock signal CLK2 to output the inverted scanning signal / GW to the first output terminal 214 and output the scanning signal GW to the second output terminal 215. The scanning signal GW output to the second output terminal 215 can be supplied to the i-th first scanning line SL1i.

[0195] The first signal input terminal 221a receives the first input signal FS_Na (or GW_Na), the second signal input terminal 222a receives the second input signal / FS_Fa (or / GW_Fa), and the third signal input terminal 223a receives the third input signal FS_Fa (or GW_Fa). The first generating unit 220a can output the scanning signal GC to the output terminal 224a corresponding to the first input signal FS_Na (or GW_Na), the second input signal / FS_Fa (or / GW_Fa), and the third input signal FS_Fa (or GW_Fa). The scanning signal GC output to the output terminal 224a can be supplied to the i-th second scanning line SL2i. Here, the width of the scanning signal GC can be determined corresponding to the first input signal FS_Na (or GW_Na), the second input signal / FS_Fa (or / GW_Fa), and the third input signal FS_Fa (or GW_Fa).

[0196] The first signal input terminal 221b receives the first input signal FS_Nb (or GW_Nb), the second signal input terminal 222b receives the second input signal / FS_Fb (or / GW_Fb), and the third signal input terminal 223b receives the third input signal FS_Fb (or GW_Fb). The second generating unit 220b may output the light emitting control signal EM to the output terminal 224b corresponding to the first input signal FS_Nb (or GW_Nb), the second input signal / FS_Fb (or / GW_Fb), and the third input signal FS_Fb (or GW_Fb). The light emitting control signal EM output to the output terminal 224b may be supplied to the i-th light emitting control line ELi. Here, the width of the light emitting control signal EM may be determined corresponding to the first input signal FS_Nb (or GW_Nb), the second input signal / FS_Fb (or / GW_Fb), and the third input signal FS_Fb (or GW_Fb).

[0197] The first input signal FS_Na (or GW_Na) of the first generating unit 220a may be a signal different from the first input signal FS_Nb (or GW_Nb) of the second generating unit 220b. As an example, the first input signal FS_Na (or GW_Na) of the first generating unit 220a and the first input signal FS_Nb (or GW_Nb) of the second generating unit 220b may be output signals of different driving stage circuits.

[0198] In addition, the second input signal / FS_Fa (or / GW_Fa) (and the third input signal FS_Fa (or GW_Fa)) of the first generating unit 220a may be a signal different from the second input signal / FS_Fb (or / GW_Fb) (and the third input signal FS_Fb (or GW_Fb)) of the second generating unit 220b. As an example, the second input signal / FS_Fa (or / GW_Fa) (and the third input signal FS_Fa (or GW_Fa)) of the first generating unit 220a and the second input signal / FS_Fb (or / GW_Fb) (and the third input signal FS_Fb (or GW_Fb)) of the second generating unit 220b may be output signals of different driving stage circuits.

[0199] Fig.11 FIG. 2 is a diagram showing a display device according to an embodiment of the present invention. Fig.11 When Figure 5 The repeated description of the same parts will be omitted.

[0200] Reference Fig.11 The display device 100a according to the embodiment of the present invention includes a first scanning / light-emitting driving unit 130a and a second scanning / light-emitting driving unit 130b. The first scanning / light-emitting driving unit 130a may be located at one side of the pixel unit 110, and supplies scanning signals to the scanning lines SL1, SL2, SL3, and SL4, and supplies light-emitting control signals to the light-emitting control line EL. The second scanning / light-emitting driving unit 130b may be located at the other side of the pixel unit 110, and supplies scanning signals to the scanning lines SL1, SL2, SL3, and SL4, and supplies light-emitting control signals to the light-emitting control line EL.

[0201] The first scanning / light-emitting driving unit 130a and the second scanning / light-emitting driving unit 130b may have Figure 5 The scanning / light-emitting driving unit 130 has substantially the same structure as that of the scanning / light-emitting driving unit 130. Therefore, detailed description thereof will be omitted.

[0202] Fig.12 FIG. 2 is a diagram showing a display device according to an embodiment of the present invention. Fig.12 When Figure 5 The repeated description of the same parts will be omitted.

[0203] Reference Fig.12 The display device 100 b according to the embodiment of the present invention may include a scanning driving unit 132 located on one side of the pixel unit 110 and a light emitting driving unit 134 located on the other side of the pixel unit 110 .

[0204] The scan driving part 132 may receive a first driving control signal SCS from the timing control part 120. The first driving control signal SCS may include a start signal FLM and clock signals CLK1 and CLK2 required for driving the scan driving part 132.

[0205] The scanning driving unit 132 can use the clock signals CLK1 and CLK2 to shift the start signal FLM and generate scanning signals in sequence. Fig.13 As shown, the scan driving part 132 may generate a first scan signal GW and a second scan signal GC.

[0206] The light-emitting driving unit 134 may receive the third driving control signal ECS from the timing control unit 120. The third driving control signal ECS may include the start signal FLM and the clock signals CLK1 and CLK2 required for driving the light-emitting driving unit 134. The light-emitting driving unit 134 may use the clock signals CLK1 and CLK2 to shift the start signal FLM and generate the light-emitting control signals in sequence. As an example, Fig.16 As shown, the light emitting driving unit 134 may generate a light emitting control signal EM.

[0207] Fig.13 Yes means Fig.12 A diagram of an embodiment of a scan driving unit is shown.

[0208] Reference Fig.13 The scanning driving unit 132 involved in one embodiment of the present invention includes a plurality of first dummy driving stage circuits FDST1a, FDST2a, ..., driving stage circuits ST1a, ..., STia, ..., STna and second dummy driving stage circuits SDST1a, SDST2a, ...

[0209] The first dummy driving stage circuit FDSTa, the driving stage circuit STa, and the second dummy driving stage circuit SDSTa may have Figure 1 As an example, the first dummy driver stage circuit FDSTa, the driver stage circuit STa, and the second dummy driver stage circuit SDSTa may include a driving section 210 and a generating section 220, respectively.

[0210] The first dummy driving stage circuit FDSTa may alternately receive the first clock signal CLK1 and the second clock signal CLK2 while sequentially generating a first scanning signal GW (ie, a first signal FS) and an inverted first scanning signal / GW (ie, an inverted first signal / FS).

[0211] The inverted first scanning signal / GW generated by the first dummy driving stage circuit FDSTa may be used as a second input signal / FS_F of the generating section 220 included in any one of the plurality of driving stage circuits STa. The first scanning signal GW generated by the first dummy driving stage circuit FDSTa may be used as a third input signal FS_F of the generating section 220 included in any one of the plurality of driving stage circuits STa.

[0212] The number of the first dummy driving stage circuits FDSTa may be determined in accordance with the width of the second scanning signal GC at a high level. For example, the number of the first dummy driving stage circuits FDSTa may increase as the width of the second scanning signal GC increases.

[0213] The second dummy driving stage circuit SDSTa may generate the first scanning signal GW (ie, the first signal FS) while alternately receiving the first clock signal CLK1 and the second clock signal CLK2 .

[0214] The first scanning signal GW generated by the second dummy driving stage circuit SDSTa can be used as the first input signal FS_N of the generating unit 220 included in any one of the plurality of driving stage circuits STa. The number of the second dummy driving stage circuits SDSTa can be determined corresponding to the width of the high-level second scanning signal GC. As an example, the more the width of the high-level second scanning signal GC increases, the more the number of the second dummy driving stage circuits SDSTa can increase.

[0215] The driving stage circuit STa may generate a first scanning signal GW (ie, a first signal FS) and a second scanning signal GC (ie, a second signal SS) while alternately receiving the first clock signal CLK1 and the second clock signal CLK2.

[0216] Each driver stage circuit STa can use Figure 1 The driving unit 210 shown in the figure generates the first scanning signal GW, and the generating unit 220 generates the second scanning signal GC. The working process of each driving stage circuit STa as described above is the same as Figure 1 same.

[0217] Fig.14 It means Fig.13 The diagram shows the terminals of the driver stage circuit connections. Fig.15 It is separated by function Fig.14The driver stage circuit diagram is shown in Figure 1. Fig.14 and Fig.15 The i-th driving stage circuit STia is shown in FIG.

[0218] Reference Figure 1 , Fig.14 and Fig.15 The i-th driving stage circuit STia includes a driving section 210 and a generating section 220. As described above, the driving section 210 and the generating section 220 are configured similarly to the Figure 1 The driver stage circuit 200 shown is identical.

[0219] The i-th driving stage circuit STia can be connected to the first input terminal 211, the second input terminal 212, the third input terminal 213, the first signal input terminal 221, the second signal input terminal 222, the third signal input terminal 223, the first output terminal 214, the second output terminal 215, the output terminal 224, the first power input terminal 231 and the second power input terminal 232.

[0220] The first input terminal 211 receives the start signal FLM (or the scanning signal GWi-1 of the previous driving stage circuit), the second input terminal 212 receives the first clock signal CLK1, and the third input terminal 213 receives the second clock signal CLK2. The driving unit 210 can use the start signal FLM (or GWi-1), the first clock signal CLK1 and the second clock signal CLK2 to output the inverted scanning signal / GW to the first output terminal 214 and output the scanning signal GW to the second output terminal 215. The scanning signal GW output to the second output terminal 215 can be supplied to the i-th first scanning line SL1i.

[0221] The first signal input terminal 221 receives the first input signal FS_N (or GW_N), the second signal input terminal 222 receives the second input signal / FS_F (or / GW_F), and the third signal input terminal 223 receives the third input signal FS_F (or GW_F). The generator 220 may output a scan signal GC to the output terminal 224 corresponding to the first input signal FS_N (or GW_N), the second input signal / FS_F (or / GW_F), and the third input signal FS_F (or GW_F). The scan signal GC output to the output terminal 224 may be supplied to the i-th second scan line SL2i. Here, the width of the scan signal GC may be determined corresponding to the first input signal FS_N (or GW_N), the second input signal / FS_F (or / GW_F), and the third input signal FS_F (or GW_F).

[0222] Fig.16 Yes means Fig.12 A diagram of an embodiment of a light emitting driving unit is shown.

[0223] Reference Fig.16 The light emitting driving unit 134 according to one embodiment of the present invention includes a plurality of first dummy driving stage circuits FDST1b, FDST2b, ..., driving stage circuits ST1b, ..., STib, ..., STnb and second dummy driving stage circuits SDST1b, SDST2b, ...

[0224] The first dummy driving stage circuit FDSTb, the driving stage circuit STb, and the second dummy driving stage circuit SDSTb may have Figure 1 As an example, the first dummy driver stage circuit FDSTb, the driver stage circuit STb, and the second dummy driver stage circuit SDSTb may include a driving unit 210 and a generating unit 220, respectively.

[0225] The first dummy driving stage circuit FDSTb may alternately receive the first clock signal CLK1 and the second clock signal CLK2 while sequentially generating a first scanning signal GW (ie, a first signal FS) and an inverted first scanning signal / GW (ie, an inverted first signal / FS).

[0226] The inverted first scan signal / GW generated by the first dummy driver stage circuit FDSTb may be used as a second input signal / FS_F of the generation section 220 included in any one of the plurality of driver stage circuits STb. The first scan signal GW generated by the first dummy driver stage circuit FDSTb may be used as a third input signal FS_F of the generation section 220 included in any one of the plurality of driver stage circuits STb.

[0227] The number of the first dummy driving stage circuits FDSTb may be determined in accordance with the width of the high-level light emission control signal EM. As an example, the number of the first dummy driving stage circuits FDSTb may increase as the width of the light emission control signal EM increases.

[0228] The second dummy driving stage circuit SDSTb may generate the first scanning signal GW (ie, the first signal FS) while alternately receiving the first clock signal CLK1 and the second clock signal CLK2 .

[0229] The first scan signal GW generated by the second dummy drive stage circuit SDSTb can be used as the first input signal FS_N of the generating unit 220 included in any one of the plurality of drive stage circuits STb. The number of the second dummy drive stage circuits SDSTb can be determined corresponding to the width of the high-level light emission control signal EM. As an example, the number of the second dummy drive stage circuits SDSTb can increase as the width of the high-level light emission control signal EM increases.

[0230] The driving stage circuit STb can generate the first scanning signal GW (i.e., the first signal FS) and the light emitting control signal EM (i.e., the second signal SS) while alternately receiving the first clock signal CLK1 and the second clock signal CLK2. The first scanning signal GW (and the inverted first scanning signal / GW) generated by the driving stage circuit STb will not be supplied to the outside, but can be supplied to the driving stage circuit of the previous stage or the next stage.

[0231] The light emission control signal EM generated by the driving stage circuit STb can be supplied to the light emission control line EL. As an example, the light emission control signal EM generated by the i-th driving stage circuit STib can be supplied to the i-th light emission control line ELi. The operation process of each driving stage circuit STb is similar to Figure 1 same.

[0232] Fig.17 It means Fig.16 The diagram shows the terminals of the driver stage circuit connections. Fig.18 It is separated by function Fig.17 Diagram of the driver stage circuit.

[0233] Reference Figure 1 , Fig.17 and Fig.18 The driving stage circuit STib includes a driving unit 210 and a generating unit 220. As described above, the driving unit 210 and the generating unit 220 are configured similarly to the above. Figure 1 The driver stage circuit 200 shown is identical.

[0234] The driving stage circuit STib can be connected to the first input terminal 211, the second input terminal 212, the third input terminal 213, the first signal input terminal 221, the second signal input terminal 222, the third signal input terminal 223, the first output terminal 214, the second output terminal 215, the output terminal 224, the first power input terminal 231 and the second power input terminal 232.

[0235] The first input terminal 211 receives the start signal FLM (or the scan signal GWi-1 of the previous driver stage circuit), the second input terminal 212 receives the first clock signal CLK1, and the third input terminal 213 receives the second clock signal CLK2. The driver 210 can use the start signal FLM (or GWi-1), the first clock signal CLK1, and the second clock signal CLK2 to output the inverted scan signal / GW to the first output terminal 214 and the scan signal GW to the second output terminal 215. The scan signal GW and the inverted scan signal / GW output by the driver 210 can be supplied to the previous and / or subsequent driver stage circuits.

[0236] The first signal input terminal 221 receives a first input signal FS_N (or GW_N), the second signal input terminal 222 receives a second input signal / FS_F (or / GW_F), and the third signal input terminal 223 receives a third input signal FS_F (or GW_F). The generator 220 may output a light emission control signal EM to the output terminal 224 in correspondence with the first input signal FS_N (or GW_N), the second input signal / FS_F (or / GW_F), and the third input signal FS_F (or GW_F). The light emission control signal EM output to the output terminal 224 may be supplied to the i-th light emission control line ELi. Here, the width of the light emission control signal EM may be determined in correspondence with the first input signal FS_N (or GW_N), the second input signal / FS_F (or / GW_F), and the third input signal FS_F (or GW_F).

[0237] Fig.19 It is a diagram showing an electronic device according to an embodiment of the present invention.

[0238] Reference Fig.19 The electronic device 1000 according to the embodiment of the present invention outputs various information through the display module 1140. If the processor 1110 executes an application stored in the memory 1120, the display module 1140 provides the application information to the user through the display panel 1141.

[0239] The processor 1110 obtains external input through the input module 1130 or the sensor module 1161, and executes an application corresponding to the external input. For example, when the user selects the camera icon (or camera application icon) displayed in the display panel 1141, the processor 1110 obtains the user input through the input sensor 1161-2 and activates the camera module 1171. The processor 1110 transmits image data corresponding to the captured image obtained by the camera module 1171 to the display module 1140. The display module 1140 can display an image corresponding to the captured image through the display panel 1141.

[0240] As another example, in the case of performing personal information authentication in the display module 1140, the fingerprint sensor 1161-1 obtains the input fingerprint information as input data. The processor 1110 compares the input data obtained by the fingerprint sensor 1161-1 with the authentication data stored in the memory 1120, and executes the application according to the comparison result. The display module 1140 can display information executed according to the logic of the application through the display panel 1141. The fingerprint sensor 1161-1 can be configured to be able to obtain fingerprint information in the entire area of ​​the display module 1140 (or the display panel 1141).

[0241] As another example, when the music streaming icon displayed in the display module 1140 is selected, the processor 1110 obtains the user input through the input sensor 1161-2 and activates the music streaming application stored in the memory 1120. If a music execution command is input in the music streaming application, the processor 1110 activates the sound output module 1163 to provide the user with sound information corresponding to the music execution command.

[0242] The operation of the electronic device 1000 is briefly described above. The configuration of the electronic device 1000 is described in detail below. Some of the configurations of the electronic device 1000 described below may be integrated into one configuration, or one configuration may be separated into two or more configurations.

[0243] The electronic device 1000 can communicate with the external electronic device 2000 through a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, the electronic device 1000 may include a processor 1110, a memory 1120, an input module 1130, a display module 1140, a power module 1150, a built-in module 1160, and an external module 1170. According to one embodiment, the electronic device 1000 may omit at least one of the above-mentioned components or add one or more other components. According to one embodiment, a part of the above-mentioned components (e.g., a sensor module 1161, an antenna module 1162, or an audio output module 1163) may be combined into another component (e.g., a display module 1140).

[0244] The processor 1110 may execute software to control at least one other component (e.g., hardware or software component) of the electronic device 1000 connected to the processor 1110, and may perform various data processing or operations. According to one embodiment, as at least a part of the data processing or operation, the processor 1110 may store commands or data received from other components (e.g., the input module 1130, the sensor module 1161, or the communication module 1173) in the volatile memory 1121, process the commands or data stored in the volatile memory 1121, and store the result data in the non-volatile memory 1122.

[0245] The processor 1110 may include a main processor 1111 and an auxiliary processor 1112. The main processor 1111 may include one or more of a central processing unit (CPU) 1111-1 or an application processor (AP: application processor). The main processor 1111 may further include any one or more of a graphics processing unit (GPU) 1111-2, a communication processor (CP: communication processor) and an image signal processor (ISP: image signal processor). The main processor 1111 may further include a neural processing unit (neural processing unit) NPU 1111-3. The neural network processing unit NPU 1111-3 is a processor specialized for processing artificial intelligence models, which can be generated by machine learning. The artificial intelligence model may include multiple artificial neural network arrays. The artificial neural network can be a deep neural network (DNN), a CNN (convolutional neural network), an RNN (recurrent neural network), an RBM (restricted Boltzmann machine), a DBN (deep belief network), a BRDNN (bidirectional recurrent deep neural network), a deep Q-network or a combination of two or more of the above networks, and is not limited to the above examples. In addition to the hardware structure, the artificial intelligence model may additionally or alternatively include a software structure. At least two of the above-mentioned processing unit and processor can be implemented by a unified structure (for example, a single chip), and can be implemented by separate independent structures (for example, multiple chips).

[0246] The auxiliary processor 1112 may include a controller 1112-1. The controller 1112-1 may include an interface conversion circuit and a timing control circuit. As an example, the controller 1112-1 may include Figure 5 , Fig.11 and / or Fig.12The timing control unit 120 is shown. The controller 1112-1 receives the image signal from the main processor 1111, converts the data format of the image signal into an interface specification that conforms to the display module 1140, and outputs the image data. The controller 1112-1 can output various control signals required for driving the display module 1140.

[0247] The auxiliary processor 1112 may further include a data conversion circuit 1112-2, a gamma correction circuit 1112-3, a rendering circuit 1112-4, and a touch control circuit (not shown). The data conversion circuit 1112-2 may receive image data from the controller 1112-1, compensate the image data so as to display an image at a desired brightness according to the characteristics of the electronic device 1000 or the user's settings, or convert the image data in order to reduce power consumption or compensate for afterimages.

[0248] The gamma correction circuit 1112-3 may transform image data or gamma reference voltage so that an image displayed in the electronic device 1000 has a desired gamma characteristic. The rendering circuit 1112-4 may receive image data from the controller 1112-1 and render the image data in consideration of the pixel configuration of the display panel 1141 of the electronic device 1000.

[0249] The touch control circuit may supply a touch signal to the input sensor 1161 - 2 , and receive a sensing signal from the input sensor 1161 - 2 corresponding to the touch signal.

[0250] At least one of the data conversion circuit 1112-2, the gamma correction circuit 1112-3, the rendering circuit 1112-4, and the touch control circuit may be combined into other components (e.g., the main processor 1111 or the controller 1112-1). At least one of the data conversion circuit 1112-2, the gamma correction circuit 1112-3, and the rendering circuit 1112-4 may also be combined into the source driver 1143 described later.

[0251] The memory 1120 may store various data used by at least one component of the electronic device 1000 (e.g., the processor 1110 or the sensor module 1161) and input data or output data for commands related thereto. In addition, various setting data corresponding to user settings may be stored in the memory 1120. The memory 1120 may include at least one of a volatile memory 1121 and a nonvolatile memory 1122.

[0252] The input module 1130 may receive commands or data to be used in components of the electronic device 1000 (eg, the processor 1110 , the sensor module 1161 , or the audio output module 1163 ) from outside the electronic device 1000 (eg, a user or an external electronic device 2000 ).

[0253] The input module 1130 may include a first input module 1131 into which a user inputs a command or data and a second input module 1132 into which an external electronic device 2000 inputs a command or data. The first input module 1131 may include a microphone, a mouse, a keyboard, a button (e.g., a key) or a pen (e.g., a passive pen or an active pen). The second input module 1132 may support a specified protocol that can be connected to the external electronic device 2000 in a wired or wireless manner. According to one embodiment, the second input module 1132 may include an HDMI (high definition multimedia interface), a USB (universalserial bus) interface, an SD card interface, or an audio interface. The second input module 1132 may include a connector that can be physically connected to the external electronic device 2000 (e.g., an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector)).

[0254] The display module 1140 provides visual information to the user. The display module 1140 may include a display panel 1141, a gate driver 1142, and a source driver 1143. The display module 1140 may also include a window, a base, and a bracket for protecting the display panel 1141. The display module 1140 as described above may include Figure 5 , Fig.11 and / or Fig.12 The display devices 100, 100a, 100b are shown.

[0255] The display panel (or display) 1141 may include a liquid crystal display panel, an organic light emitting display panel, or an inorganic light emitting display panel, and the type of the display panel 1141 is not particularly limited. The display panel 1141 may be a rigid type, or may be a flexible type that is rollable or foldable. The display module 1140 may further include a support, a bracket, or a heat dissipation component that supports the display panel 1141.

[0256] The display panel 1141 may receive image data from the auxiliary processor 1112 and display an image while controlling the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the pixels PX in accordance with the image data.

[0257] The gate driver 1142 is a driving chip that can be installed in the display panel 1141. In addition, the gate driver 1142 can be integrated into the display panel 1141. For example, the gate driver 1142 may include an ASG (Amorphous Silicon TFT Gate driver circuit), an LTPS (Low Temperature Polycrystalline Silicon) TFT gate driver circuit, or an OSG (Oxide Semiconductor TFT Gate driver circuit) built into the display panel 1141. The gate driver 1142 receives a control signal from the controller 1112-1 and outputs a scan signal to the display panel 1141 in response to the control signal. The gate driver 1142 may include Figure 5 and Fig.11 The scanning / light-emitting driving units 130, 130a, 130b and Fig.12 The scan driving unit 132 is shown.

[0258] The display module 1140 may further include a light emitting driver. The light emitting driver outputs a light emitting control signal to the display panel 1141 in response to a control signal received from the controller 1112-1. The light emitting driver may be formed separately from the gate driver 1142 or may be combined into the gate driver 1142. The light emitting driver may include Fig.12 The light emitting driving unit 134 is shown.

[0259] The source driver 1143 receives a control signal from the controller 1112-1, converts the image data into an analog voltage (eg, a data signal) in response to the control signal, and then outputs the data signal to the display panel 1141. The source driver 1143 may include Figure 5 , Fig.11 and / or Fig.12 The data driving unit 140 is shown.

[0260] The source driver 1143 may be integrated into other components (eg, the controller 1112 - 1 ). The functions of the interface conversion circuit and the timing control circuit of the controller 1112 - 1 may also be integrated into the source driver 1143 .

[0261] The display module 1140 may further include a voltage generating circuit 1144. The voltage generating circuit 1144 may output various voltages required for driving the display panel 1141. As an example, the voltage generating circuit 1144 may include Figure 5 , Fig.11 and / or Fig.12The power supply unit 150 is shown.

[0262] In an embodiment, the display panel 1141 may include a plurality of pixel columns each including a plurality of pixels.

[0263] In an embodiment, the source driver 1143 may convert data corresponding to red (R), green (G), and blue (B) included in the image data received from the processor 1110 into red data signals (or data voltages), green data signals (or data voltages), and blue data signals (or data voltages), and provide them to a plurality of pixel columns included in the display panel 1141 within one horizontal period.

[0264] The power module 1150 supplies power to the components of the electronic device 1000. The power module 1150 may include a battery for charging the power supply voltage. The battery may include a primary battery that cannot be recharged, a secondary battery that can be recharged, or a fuel cell. The power module 1150 may include a PMIC (power management integrated circuit). The PMIC supplies optimized power to the above-mentioned modules and the modules described later, respectively. The power module 1150 may include a radio transceiver component electrically connected to the battery. The radio transceiver component may include a plurality of antenna radiators in the form of coils.

[0265] The electronic device 1000 may further include a built-in module 1160 and an external module 1170. The built-in module 1160 may include a sensor module 1161, an antenna module 1162, and an audio output module 1163. The external module 1170 may include a camera module 1171, a light module 1172, and a communication module 1173.

[0266] The sensor module 1161 can sense input caused by the user's body or input caused by the pen in the first input module 1131, and generate an electrical signal or data value corresponding to the input. The sensor module 1161 can include any one or more of a fingerprint sensor 1161-1, an input sensor 1161-2, and a digitizer 1161-3.

[0267] The fingerprint sensor 1161-1 may generate a data value corresponding to the fingerprint of the user. The fingerprint sensor 1161-1 may include an optical fingerprint sensor or a capacitive fingerprint sensor.

[0268] The input sensor 1161-2 may generate a data value corresponding to the coordinate information of the input caused by the user's body or the input caused by the pen. The input sensor 1161-2 generates the capacitance change caused by the input as a data value. The input sensor 1161-2 may sense the input caused by the passive pen or transmit and receive data with the active pen.

[0269] The input sensor 1161-2 may also measure biological signals such as blood pressure, water content, or body fat. For example, when a user places a part of the body in contact with the sensor layer or the sensing panel and does not move for a certain period of time, the input sensor 1161-2 may sense the biological signal based on the electric field change caused by the part of the body to output the information desired by the user to the display module 1140.

[0270] The digitizer 1161-3 may generate a data value corresponding to the coordinate information of the input caused by the pen. The digitizer 1161-3 generates the amount of electromagnetic change caused by the input as a data value. The digitizer 1161-3 may sense the input caused by the passive pen or transmit and receive data with the active pen.

[0271] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may also be implemented as a sensor layer formed on the display panel 1141 through a continuous process. At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be configured on the upper side of the display panel 1141, and any one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 (for example, the digitizer 1161-3) may be configured on the lower side of the display panel 1141.

[0272] Two or more of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be integrated into one sensing panel through the same process. When integrated into one sensing panel, the sensing panel may be disposed between the display panel 1141 and a window portion disposed on the upper side of the display panel 1141. According to one embodiment, the sensing panel may also be disposed on the window portion, and the position of the sensing panel is not particularly limited.

[0273] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be built in the display panel 1141. That is, at least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be simultaneously formed through the process of forming elements (e.g., light emitting elements, transistors, etc.) included in the display panel 1141.

[0274] In addition, the sensor module 1161 can generate an electrical signal or data value corresponding to the internal state or external state of the electronic device 1000. The sensor module 1161 may also include, for example, a gesture sensor, a gyro sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a grip force sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0275] The antenna module 1162 may include one or more antennas for transmitting signals or power to the outside or receiving signals or power from the outside. According to one embodiment, the communication module 1173 may transmit signals to the external electronic device 2000 or receive signals from the external electronic device 2000 through an antenna that complies with the communication method. The antenna pattern of the antenna module 1162 may also be integrated with a component of the display module 1140 (e.g., the display panel 1141) or the input sensor 1161-2, etc.

[0276] The audio output module 1163 is a device for outputting an audio signal to the outside of the electronic device 1000, and may include, for example, a speaker for general use such as multimedia playback or recording playback and a receiver for making and receiving calls. According to one embodiment, the receiver may be formed integrally with the speaker or formed separately. The audio output pattern of the audio output module 1163 may also be formed integrally with the display module 1140.

[0277] The camera module 1171 can capture still images or dynamic images. According to one embodiment, the camera module 1171 may include one or more lenses, image sensors, or image signal processors. The camera module 1171 may also include an infrared camera capable of measuring the presence of a user, the position of a user, the line of sight of a user, etc.

[0278] The light module 1172 may provide light. The light module 1172 may include a light emitting diode or a xenon lamp. The light module 1172 may operate in conjunction with the camera module 1171 or independently.

[0279] The communication module 1173 can support the establishment of a wired or wireless communication channel between the electronic device 1000 and the external electronic device 2000 and the execution of communication based on the established communication channel. The communication module 1173 may include any one or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module or a GNSS (global navigation satellite system) communication module and a wired communication module such as a LAN (local area network) communication module or a power line communication module. The communication module 1173 can communicate with the external electronic device 2000 through a short-range communication network such as Bluetooth, WiFi direct connection or IrDA (infrared data association) or a long-range communication network such as a cellular network, the Internet or a computer network (for example, LAN or WAN). The above-mentioned various types of communication modules 1173 can be implemented by one chip or by separate chips.

[0280] The input module 1130 , the sensor module 1161 , the camera module 1171 , and the like can be linked with the processor 1110 and effectively utilized in controlling the operation of the display module 1140 .

[0281] The processor 1110 outputs a command or data to the display module 1140, the audio output module 1163, the camera module 1171, or the light module 1172 based on the input data received from the input module 1130. For example, the processor 1110 may generate image data corresponding to input data applied through a mouse or an active pen, etc., and output it to the display module 1140, or generate command data corresponding to the input data and output it to the camera module 1171 or the light module 1172. The processor 1110 may convert the operation mode of the electronic device 1000 to a low power mode or a sleep mode when no input data is received from the input module 1130, thereby reducing the power consumed in the electronic device 1000.

[0282] The processor 1110 outputs a command or data to the display module 1140, the audio output module 1163, the camera module 1171, or the light module 1172 based on the sensing data received from the sensor module 1161. For example, the processor 1110 may execute an application according to the comparison result after comparing the authentication data applied by the fingerprint sensor 1161-1 with the authentication data stored in the memory 1120. The processor 1110 may execute a command or output corresponding image data to the display module 1140 based on the sensing data sensed by the input sensor 1161-2 or the digitizer 1161-3. In the case where the sensor module 1161 includes a temperature sensor, the processor 1110 may receive temperature data for the temperature measured by the sensor module 1161, and further implement brightness correction for the image data based on the temperature data.

[0283] The processor 1110 may receive measurement data on the presence or absence of a user, the position of the user, the line of sight of the user, etc. from the camera module 1171. The processor 1110 may further perform brightness correction on the image data based on the measurement data. For example, the processor 1110, which has determined the presence or absence of a user through the input from the camera module 1171, may output image data whose brightness has been corrected through the data conversion circuit 1112-2 or the gamma correction circuit 1112-3 to the display module 1140.

[0284] Some of the components described can be connected to each other through a communication method between peripheral devices (for example, a bus, GPIO (general purpose input / output), SPI (serial peripheral interface), MIPI (mobile industry processor interface) or UPI (Ultra path interconnect) link), so as to exchange signals (for example, commands or data) with each other. The processor 1110 can communicate with the display module 1140 through an interface agreed upon by each other, for example, any one of the above-mentioned communication methods can be used, but it is not limited to the above-mentioned communication methods.

[0285] Although the present invention has been described above with reference to the embodiments, it should be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as described in the claims.

Claims

1. A driving stage circuit, comprising: a driving unit that receives a start signal and generates a first signal and an inverted first signal using the first clock signal and the second clock signal; and The first generating unit generates a second signal using a preceding first signal supplied from a driving unit of a preceding driving circuit and an inverted preceding first signal and a succeeding first signal supplied from a driving unit of a succeeding driving circuit. The driving unit and the first generating unit are electrically connected to a first power input terminal to which a first power source is input and a second power input terminal to which a second power source is input.

2. The driving stage circuit according to claim 1, wherein: The first clock signal and the second clock signal have the same period and opposite phases.

3. The driving stage circuit according to claim 1, wherein: The driving unit comprises: an input unit, controlling a voltage of a first node using the start signal, the first clock signal, and the second clock signal; a first output unit connected to the first power input terminal and the second power input terminal, and controlling a voltage of a first output terminal corresponding to a voltage of the first node; as well as The second output unit is connected to the first power input terminal and the second power input terminal, and controls the voltage of the second output terminal according to the voltage of the first output terminal.

4. The driving stage circuit according to claim 3, wherein: The first output terminal outputs the inverted first signal, and the second output terminal outputs the first signal.

5. The driving stage circuit according to claim 3, wherein: The input unit includes: a first transistor and a second transistor connected in parallel between a first input terminal to which the start signal is input and the first node. The gate electrode of the first transistor is connected to a second input terminal for inputting the first clock signal. A gate electrode of the second transistor is connected to a third input terminal to which the second clock signal is input.

6. The driving stage circuit according to claim 5, wherein: The first transistor is an N-type transistor, and the second transistor is a P-type transistor.

7. The driving stage circuit according to claim 3, wherein: The first output unit and the second output unit are inverters, respectively.

8. The driving stage circuit according to claim 3, wherein: The first output unit includes: a P-type third transistor and an N-type fourth transistor, which are arranged in series between the first power input terminal and the second power input terminal. Gate electrodes of the third transistor and the fourth transistor are connected to the first node, and a common node between the third transistor and the fourth transistor is connected to the first output terminal.

9. The driving stage circuit according to claim 3, wherein: The second output unit includes: a P-type fifth transistor and an N-type sixth transistor, which are arranged in series between the first power input terminal and the second power input terminal. Gate electrodes of the fifth transistor and the sixth transistor are connected to the first output terminal, and a common node between the fifth transistor and the sixth transistor is connected to the second output terminal.

10. The driving stage circuit according to claim 3, wherein: The driving unit further includes a first capacitor connected between the first node and the second power input terminal.

11. The driving stage circuit according to claim 1, wherein: The first generating unit comprises: a control unit that controls a voltage of the first node using a first input signal supplied to the first signal input terminal and a second input signal supplied to the second signal input terminal; as well as The output unit outputs the second signal to the output terminal in response to the third input signal supplied to the third signal input terminal and the voltage of the first node.

12. The driving stage circuit according to claim 11, wherein: The first input signal is the second-stage first signal, the second input signal is the first signal inverted from the first-stage signal, and the third input signal is the first-stage signal.

13. The driving stage circuit according to claim 11, wherein: The control unit comprises: A first P-type transistor connected between the first power input terminal and the first node, with a gate electrode connected to the first signal input terminal; and The N-type second transistor is connected between the first node and the second power supply input terminal, and has a gate electrode connected to the second signal input terminal.

14. The driving stage circuit according to claim 11, wherein: The output unit comprises: A third P-type transistor connected between the first power input terminal and the output terminal, with a gate electrode connected to the third signal input terminal; and The fourth N-type transistor is connected between the output terminal and the second power input terminal, and has a gate electrode connected to the first node.

15. The driving stage circuit according to claim 11, wherein: The first generating unit further includes a second capacitor connected between the first node and the second power input terminal.

16. The driving stage circuit according to claim 1, wherein: The first power supply is set to a high-level voltage, and the second power supply is set to a low-level voltage which is a voltage lower than the first power supply.

17. The driving stage circuit according to claim 11, further comprising: The second generating unit includes the same circuit as the first generating unit, and outputs a third signal using a fourth input signal input to a fourth signal input terminal, a fifth input signal input to a fifth signal input terminal, and a sixth input signal input to a sixth signal input terminal.

18. The driving stage circuit according to claim 17, wherein: The fourth input signal is different from the first input signal, the fifth input signal is different from the second input signal, and the sixth input signal is different from the third input signal.

19. A display device comprising: A plurality of pixels are arranged to be connected to a plurality of scan lines, a plurality of light emitting control lines and a plurality of data lines; and a scanning / light-emitting driving unit, comprising a plurality of driving stage circuits for driving at least one of the plurality of scanning lines and the plurality of light-emitting control lines, a plurality of first dummy driving stage circuits located at the front stage of the plurality of driving stage circuits, and a plurality of second dummy driving stage circuits located at the rear stage of the plurality of driving stage circuits, The i-th driving stage circuit among the plurality of driving stage circuits comprises: a driving unit that receives a start signal and generates a first signal and an inverted first signal using the first clock signal and the second clock signal; and a generating section that generates a second signal using a preceding first signal supplied from a driving section of a preceding driving stage circuit and an inverted preceding first signal and a succeeding first signal supplied from a driving section of a succeeding driving stage circuit, The start signal is the first signal of the i-1th driving stage circuit, the first signal is the first scanning signal supplied to the i-th first scanning line, and the second signal is the second scanning signal supplied to the i-th second scanning line or the light-emitting control signal supplied to the i-th light-emitting control line.

20. An electronic device comprising: A display module, comprising a display panel for displaying a predetermined image; a processor, supplying data corresponding to the predetermined image to the display module; A gate driver, included in the display module, includes a plurality of drive stage circuits, a plurality of first dummy drive stage circuits located at the front stage of the plurality of drive stage circuits, and a plurality of second dummy drive stage circuits located at the rear stage of the plurality of drive stage circuits in order to supply at least one of a scan signal and a light emitting control signal to a plurality of pixels included in the display panel. The i-th driving stage circuit among the plurality of driving stage circuits comprises: A driving unit receives a start signal and generates a first signal and an inverted first signal using a first clock signal and a second clock signal; as well as a generating section that generates a second signal using a preceding first signal supplied from a driving section of a preceding driving stage circuit and an inverted preceding first signal and a succeeding first signal supplied from a driving section of a succeeding driving stage circuit, The start signal is the first signal of the i-1th driving stage circuit, the first signal is the first scanning signal supplied to the i-th first scanning line, and the second signal is the second scanning signal supplied to the i-th second scanning line or the light-emitting control signal supplied to the i-th light-emitting control line.

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