MIM capacitor test structure and preparation and test method thereof

Abstract

The invention discloses an MIM capacitor test structure and a preparation and test method thereof. The MIM capacitor test structure comprises a semiconductor substrate, a first dielectric layer, MIM structure lower layer metal, a second dielectric layer, a first isolation protection layer, a third dielectric layer, a second isolation protection layer and a passivation layer. A first conductive groove is formed in the first dielectric layer, the MIM structure lower-layer metal and the second dielectric layer, and a groove side wall dielectric layer, a first conductive groove barrier layer and the MIM structure upper-layer metal are arranged in the first conductive groove; the passivation layer wraps the MIM capacitor structure and protects the MIM capacitor structure from being eroded by environmental factors such as water vapor, an electrode detection position far away from a core research area is provided, and it is ensured that mechanical damage cannot be caused to the side wall of the groove.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and relates to a MIM capacitor test structure and a preparation and testing method thereof. Background Art

[0002] With the continuous development of the integrated circuit industry, the critical dimension (CD) of the back-end metal interconnection has gradually shrunk. When the CD is reduced to less than tens of nanometers, the electric field strength continues to increase, while the power supply voltage fails to decrease accordingly, resulting in increased pressure on materials and processes. At the same time, with the increase in the complexity and integration of IC design, the length and number of interconnects inside the chip continue to increase, which further increases the risk of breakdown and makes the interconnection reliability face increasingly severe challenges. Not only that, in the current advanced processes, the widespread application of three-dimensional structures such as 3D NAND and CFET has put forward higher requirements for manufacturing processes. In particular, for the films located on the sidewalls, whether it is dielectric materials or metal barrier layers, they need to be accurately characterized and optimized. The quality of these films directly affects the performance and reliability of the device. Therefore, careful analysis and optimization are key steps to ensure that the three-dimensional structure can smoothly achieve high performance and high density.

[0003] As a major passive device, capacitors are increasingly used in integrated circuit design. In the past, these capacitor devices usually adopted a polysilicon-insulator-polysilicon structure or a metal-oxide layer-silicon substrate structure. However, both structures have some problems, such as parasitic capacitance, and non-metallic electrodes also lead to large dissipation resistance. To solve these problems, metal-insulator-metal (MIM) structure capacitors came into being. By using metal as two electrodes, the MIM structure effectively reduces the parasitic capacitance and the contact resistance between the electrodes, thereby providing higher conductivity and lossless high capacitance density. Because of this, MIM capacitors have gradually become a new type of device to replace traditional integrated circuit capacitors, and have received more and more attention and application. Studies have shown that a series of reliability tests can be performed on MIM capacitor structures, including tests of parameters such as leakage current, dielectric loss, and time-dependent dielectric breakdown (TDDB). These tests help evaluate the performance and stability of MIM capacitors and ensure their reliable application in integrated circuits.

[0004] The traditional MIM capacitor test structure usually adopts the form of a flat plate capacitor, that is, a layer of dielectric material is sandwiched between the upper and lower metal electrodes. The main factors affecting the quality and reliability of the capacitor include pinholes in the dielectric layer, metal spikes on the metal plate, and defects generated during the deposition of the dielectric layer. These problems may cause capacitance attenuation caused by electron adsorption during use, and even cause the capacitor to fail through breakdown. A significant advantage of the grooved metal-insulator-metal (MIM) capacitor over the traditional flat plate capacitor is that it significantly increases the capacitance density, which can provide a larger effective electrode surface area within the same chip area, thereby greatly increasing the capacitance value without increasing the occupied area. It is an important technical means to improve the density and performance of integrated circuit components. In addition, when studying the sidewall performance of the capacitor, the presence of the sidewall sharp corners will cause the electric field to gather, which in turn causes a low breakdown electric field and rapid TDDB degradation, which is not conducive to our study of the inherent properties of the dielectric layer.

[0005] When the dielectric layer and the metal barrier layer are deposited on the sidewall of the trench, the dielectric layer may be damaged due to factors such as process parameters, thus affecting the reliability of the structural test results. For thin films that need to be grown on the sidewalls of three-dimensional structures such as vertical structures, traditional structures cannot qualitatively and quantitatively characterize their characteristics when deposited on the sidewalls of such three-dimensional structures. In addition, there is another potential problem with traditional capacitor structures: the probes usually directly contact the critical areas, and the dielectric layer is not properly encapsulated. For thin films with weak mechanical strength, the pressure applied by the probes may induce mechanical stress, leading to problems such as a decrease in TDDB performance. Therefore, it is urgent to design a special MIM capacitor structure to deeply study the reliability of the dielectric layer material on the trench sidewalls. Summary of the invention

[0006] The purpose of the present invention is to propose a MIM capacitor test structure and its preparation and testing method in view of the deficiencies in the prior art, which is specifically used to make up for the deficiencies in the sidewall reliability of the existing MIM capacitor structure, and is crucial for a deep understanding of the long-term stability of the device. The film grown on the plane may have different quality and characteristics from the film grown on the sidewall. For the film that needs to be grown on the sidewall of a three-dimensional structure such as a vertical structure, the structure in the present invention can qualitatively and quantitatively characterize the characteristics of the film when deposited on the sidewall of such a three-dimensional structure. In addition, the structure can also study the potential damage caused by the deposition of the barrier layer to the dielectric layer of the groove sidewall, helping us to control the process more accurately. At the same time, the dielectric layer of the groove sidewall will not be directly affected by mechanical stress, and the intrusion of water vapor is effectively avoided, thereby ensuring the accuracy and repeatability of the test results.

[0007] In order to solve the above technical problems, in the first aspect, the present invention provides a MIM capacitor test structure, which includes, from bottom to top, a semiconductor substrate, a first dielectric layer, a metal layer under the MIM structure, a second dielectric layer, a first isolation protection layer, a third dielectric layer, a second isolation protection layer, and a passivation layer; A first conductive trench is formed in the first dielectric layer, the lower metal layer of the MIM structure, and the second dielectric layer; the first conductive trench is provided with a trench sidewall dielectric layer, a first conductive trench barrier layer, and an upper metal layer of the MIM structure from the outside to the inside; the first conductive trench barrier layer wraps the upper metal layer of the MIM structure, and the trench sidewall dielectric layer wraps the first conductive trench barrier layer; the bottoms of the trench sidewall dielectric layer, the first conductive trench barrier layer, and the upper metal layer of the MIM structure are all located in the first dielectric layer, and the tops are flush with the top of the second dielectric layer; the middle section of the trench sidewall dielectric layer is located in the lower metal layer of the MIM structure; The lower metal layer and the second dielectric layer of the MIM structure are provided with conductive vias, and the conductive vias are provided with a first barrier layer and a first metal layer from the outside to the inside; the first barrier layer wraps the first metal layer; Two second conductive trenches are formed in the first isolation protection layer and the third dielectric layer, and each second conductive trench is provided with a second conductive trench barrier layer and a conductive metal layer from the outside to the inside; the second conductive trench barrier layer wraps the conductive metal layer; Preferably, two pad grooves are formed in the second isolation protection layer and the passivation layer, and each pad groove is provided with a second barrier layer and a second metal layer from the outside to the inside; the second barrier layer wraps the second metal layer; there is a distance between the two pad grooves; the two pad grooves are respectively located above the two second conductive grooves; Preferably, the top of the first conductive trench is flush with the top of the second dielectric layer, and the bottom of the first conductive trench is at a distance from the bottom of the first dielectric layer; Preferably, the top of the conductive through hole is flush with the top of the second dielectric layer, and the bottom of the conductive through hole is at a distance from the bottom of the metal layer under the MIM structure; Preferably, there is a distance between the first conductive groove and the conductive through hole; there is a distance between the two second conductive grooves; Preferably, the two second conductive trenches are respectively located above the first conductive trench and the conductive through hole, the bottom length of the second conductive trench located above the first conductive trench is shorter than the top length of the first conductive trench, and the bottom length of the second conductive trench located above the conductive through hole is longer than the top length of the conductive through hole; Preferably, the material of the upper metal layer and the conductive metal layer of the MIM structure is copper; the material of the second metal layer is aluminum; and the material of the first metal layer is tungsten.

[0008] In a second aspect, the present invention provides a preparation process of a MIM capacitor test structure, specifically: Providing a semiconductor substrate, and sequentially depositing a first dielectric layer, a lower metal layer of the MIM structure, and a second dielectric layer on the semiconductor substrate; A first conductive trench is etched out by an etching process, and then a trench sidewall dielectric layer and a first conductive trench barrier layer are deposited, and the upper metal layer of the MIM structure is filled and planarized by CMP; Etching a conductive via through an etching process, depositing a first barrier layer and a first metal layer in the conductive via and performing CMP planarization; A first isolation protection layer and a third dielectric layer are deposited on the structure, two second conductive trenches are formed by etching, and second conductive trench barrier layers are deposited respectively, and a conductive metal layer is filled and connected to the first conductive trench and the conductive through hole under the second conductive trench barrier layer respectively; Depositing a second isolation protection layer and a top passivation layer above the two second conductive trenches; Preferably, a pad groove is etched in the second isolation protection layer and the top passivation layer, and a second barrier layer and a second metal layer are deposited as two test pads, and the two test pads are located away from the test structure; In a third aspect, the present invention provides a reliability testing method for a MIM capacitor testing structure, specifically: Step S1, applying multiple groups of different test voltages to a group of MIM capacitor test structures at a fixed test temperature to obtain the failure time of the trench sidewall dielectric layer in the current MIM capacitor test structure; At the same time, applying multiple groups of different test temperatures to the above MIM capacitor test structure under a fixed test voltage to obtain the failure time of the trench sidewall dielectric layer in the current MIM capacitor test structure; Step S2: Use the reliability evaluation model to predict the failure time of the trench sidewall dielectric layer of the MIM capacitor test structure. According to formula (2), the linear fitting With E x The electric field acceleration factor can be extracted from the slope , through linear fitting The activation energy Ea is obtained by the relationship with 1 / T; according to the electric field acceleration factor , the activation energy Ea is inversely calculated to obtain the proportional constant τ; Step S3: Substitute the electric field acceleration factor calculated in step S2 into formula (1): , activation energy Ea, proportional constant τ, according to the actual test voltage and test temperature, the failure time of the trench sidewall dielectric layer of the MIM capacitor test structure in normal operation can be obtained; The reliability evaluation model is the E model, and the specific formula is: (1) After taking the logarithm of formula (1), it is: (2) Among them, t bd is the failure time of the trench sidewall dielectric layer, τ is the proportional constant, γ is the electric field acceleration factor, E x is the test voltage electric field, Ea is the activation energy, T is the test temperature, and k is the Boltzmann constant.

[0009] Preferably, the method comprises: Step S4: In order to further provide the failure behavior of the MIM capacitor test structure group, thereby predicting the TDDB life of the entire MIM capacitor test structure group, Weibull distribution fitting can be performed based on the failure time of the trench sidewall dielectric layer of the above-mentioned MIM capacitor test structure at different test voltages and test temperatures, and the shape parameter and scale parameter in the Weibull distribution fitting formula are extracted; the shape parameter and scale parameter are used to further predict the failure probability of the MIM capacitor test structure group, or the life under a given failure probability.

[0010] The beneficial effects are: The present invention does not require chemical mechanical grinding of the dielectric layer of the capacitor side wall, thus avoiding errors caused by the processing technology. In addition, the passivation layer covers the MIM capacitor structure to protect it from erosion by environmental factors such as water vapor, and provides an electrode detection position away from the core research area to ensure that no mechanical damage is caused to the groove side wall. When studying the performance of the capacitor side wall, since the middle section of the dielectric layer of the groove side wall is the part to be tested, it is located in the lower metal layer of the MIM structure to avoid the electric field concentration caused by the sharp corners of the groove, thereby causing low breakdown electric field and rapid TDDB degradation problems. This design optimization helps us study the inherent TDDB performance of the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a cross-sectional schematic diagram of the MIM capacitor test structure of the present invention; Figure 2 This is the process flow of the MIM capacitor test structure of the present invention.

[0012] Reference numerals: 101, semiconductor substrate; 102, first dielectric layer of silicon dioxide; 103, lower metal layer of MIM structure; 104, second dielectric layer; 105, trench sidewall dielectric layer; 106, first conductive trench barrier layer; 107, upper metal layer of MIM structure; 108, first metal layer; 109, first barrier layer; 110, first isolation protection layer; 111, third dielectric layer; 112, second conductive trench barrier layer; 113, conductive metal layer; 114, second isolation protection layer; 115, passivation layer; 116, second metal layer; 117, second barrier layer. DETAILED DESCRIPTION

[0013] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0014] See also Figure 1 to Figure 2 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation, the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0015] like Figure 1 As shown, this embodiment provides a test structure based on a MIM capacitor, which includes, from bottom to top: a semiconductor substrate 101, a first dielectric layer 102, a MIM structure lower metal 103, a second dielectric layer 104, a first isolation protection layer 110, a third dielectric layer 111, a second isolation protection layer 114, and a passivation layer 115; A first conductive trench is formed in the first dielectric layer 102, the MIM structure lower metal 103, and the second dielectric layer 104. The first conductive trench is provided with a trench sidewall dielectric layer 105, a first conductive trench barrier layer 106, and a MIM structure upper metal 107 from the outside to the inside. The first conductive trench barrier layer 106 wraps the MIM structure upper metal 107, and the trench sidewall dielectric layer 105 wraps the first conductive trench barrier layer 106. The bottoms of the trench sidewall dielectric layer 105, the first conductive trench barrier layer 106, and the MIM structure upper metal 107 are all located in the first dielectric layer 102, and the tops are flush with the top of the second dielectric layer 104. The middle section of the trench sidewall dielectric layer 105 is located in the MIM structure lower metal 103. Conductive vias are provided in the lower metal layer 103 and the second dielectric layer 104 of the MIM structure, and the conductive vias are provided with a first barrier layer 109 and a first metal layer 108 from the outside to the inside; the first barrier layer 109 wraps the first metal layer 108; Two second conductive trenches are formed in the first isolation protection layer 110 and the third dielectric layer 111, and each second conductive trench is provided with a second conductive trench barrier layer 112 and a conductive metal layer 113 from the outside to the inside; the second conductive trench barrier layer 112 wraps the conductive metal layer 113; Two pad grooves are formed in the second isolation protection layer 114 and the passivation layer 115, and each pad groove is provided with a second barrier layer 117 and a second metal layer 116 from the outside to the inside; the second barrier layer 117 wraps the second metal layer 116; The above structure is prepared by the following process: Figure 2 As shown: A silicon substrate is provided as the semiconductor substrate 101, and a silicon dioxide film is deposited on the semiconductor substrate 101 as the first dielectric layer 102 by using TEOS as a precursor gas through a thermal oxidation method, a physical vapor deposition method, or in a PECVD process, plasma excitation and chemical reaction with oxygen or an oxidizing gas (such as N2O). More specifically, the first dielectric layer 102 has a thickness of 300-600 nm.

[0016] By physical vapor deposition, a metal layer TiN is deposited in the MIM structure as the lower metal layer 103 of the MIM structure, and then a layer of silicon dioxide is deposited as the second dielectric layer 104. Since the lower metal layer 103 of the MIM structure is TiN, it has a mechanical clamping effect on the HfO2 film, so the interface contact between the two is good.

[0017] A first conductive trench or a conductive through hole needs to be etched, in no particular order.

[0018] Here, the first conductive trench (larger in area) is etched first, and the bottom of the trench is located in the first dielectric layer 102. The trench sidewall dielectric layer 105 is first deposited, and then metal TaN / Ta is sequentially deposited by physical vapor deposition as the first conductive trench barrier layer 106. A copper seed layer is first deposited by physical vapor deposition and then electroplated to generate a large area of ​​copper to fill the upper metal 107 of the MIM structure. Finally, the structure is flattened by CMP (chemical mechanical polishing). It should be noted that the copper seed layer is not in Figure 2 Therefore, the MIM structure upper metal 107 filled in the first conductive trench, the trench sidewall dielectric layer 105, and the MIM structure lower metal 103 constitute a MIM structure, which is convenient for studying the trench sidewall performance.

[0019] Specifically, when etching the first conductive groove, in order to ensure the accuracy of the etching endpoint, the bottom of the first conductive groove needs to be located in the first dielectric layer 102 to ensure that the designated layer is reached without damaging the underlying structure. Therefore, only a series of properties of the sidewall can be studied without including the bottom. Prior to this, photoresist is coated on the surface of the wafer through a photolithography process, and a photoresist mask with a groove pattern is formed through exposure and development steps.

[0020] Specifically, the material of the trench sidewall dielectric layer 105 is HfO2.

[0021] More specifically, before the first conductive trench is filled with metal copper, a first conductive trench barrier layer 106 is formed including the bottom and sidewalls of the trench.

[0022] Then, the conductive via is etched again, and the bottom of the conductive via is located in the lower metal layer 103 of the MIM structure, so that the electrical signal applied later can flow in the MIM structure, and the reliability of studying only the sidewalls of the conductive groove is guaranteed. Then, Ti / TiN is deposited in the conductive via as the first barrier layer 109 by physical vapor deposition, and then metal tungsten is filled in the via as the first metal layer 108 by chemical vapor deposition, and finally CMP flattening is performed again. When etching the conductive via, in order to ensure the accuracy of the etching end point, it is necessary to control the etching process so that the bottom of the conductive via is located in the lower metal layer 103 of the MIM structure made of TiN. In this way, the conductive via can form a good contact with the lower metal layer 103 of the MIM structure.

[0023] A layer of Si3N4 is deposited on the above structure as a first isolation protection layer 110 and a layer of BD (B x SiO2 serves as the third dielectric layer 111.

[0024] Two identical second conductive trenches are etched in the third dielectric layer 111 to respectively connect the first conductive trench and the conductive via in the lower layer, and TaN / Ta is sequentially deposited as the second conductive trench barrier layer 112 and filled with metal copper as the conductive metal layer 113 .

[0025] A second isolation protection layer 114 and a layer of TEOS (SiOC2H) are deposited on the third dielectric layer 111. 54 as a top passivation layer 115; Two pad grooves are etched in the second isolation protection layer 114 and the top passivation layer 115, and a layer of TaN / Ta is deposited in the pad groove as the second barrier layer 117 and filled with aluminum as the second metal layer 116; the test pad is connected to the second conductive groove. The part of the metal aluminum pad connected to the test probe needs to be away from the structure to avoid damage to the structure caused by the mechanical stress caused by the probe, which affects the reliability of the result.

[0026] This embodiment proposes a test structure based on a MIM capacitor, which is specifically used to make up for the shortcomings of the existing capacitor structure in terms of sidewall reliability, which is crucial for a deep understanding of the long-term stability of the device. In addition, the structure can also study the potential damage caused by the deposition of the barrier layer to the dielectric layer, helping to control the process more accurately. At the same time, the trench sidewall dielectric layer 105 will not be directly affected by mechanical stress, and effectively avoids the intrusion of water vapor, thereby ensuring the accuracy and repeatability of the test results.

[0027] This embodiment also provides a reliability testing method for the above-mentioned MIM capacitor testing structure, specifically: Step S1, applying multiple groups of different test voltages to a group of MIM capacitor test structures at a fixed test temperature to obtain the failure time of the trench sidewall dielectric layer 105 in the current MIM capacitor test structure; At the same time, a plurality of different test temperatures are applied to the MIM capacitor test structure under a fixed test voltage to obtain the failure time of the trench sidewall dielectric layer 105 in the current MIM capacitor test structure.

[0028] Step S2: Use the reliability evaluation model to predict the failure time of the trench sidewall dielectric layer 105 of the MIM capacitor test structure. According to formula (2), the linear fitting With E x The electric field acceleration factor can be extracted from the slope , through linear fitting The activation energy Ea is obtained by the relationship with 1 / T; according to the electric field acceleration factor , the activation energy Ea can be reversed to obtain the proportional constant τ.

[0029] Step S3: Substitute the electric field acceleration factor calculated in step S2 into formula (1): , activation energy Ea, proportional constant τ, and according to the actual test voltage and test temperature, the failure time of the trench sidewall dielectric layer 105 when the MIM capacitor test structure is in normal operation can be obtained.

[0030] The reliability evaluation model is the E model, and the specific formula is: (1) After taking the logarithm of formula (1), it is: (2) Among them, t bd is the failure time of the trench sidewall dielectric layer 105, τ is the proportionality constant, γ is the electric field acceleration factor, E x is the test voltage electric field, Ea is the activation energy, T is the test temperature, and k is the Boltzmann constant.

[0031] Step S4: In order to further provide the failure behavior of the MIM capacitor test structure group, thereby predicting the TDDB life of the entire MIM capacitor test structure group, Weibull distribution fitting can be performed based on the failure time of the trench sidewall dielectric layer 105 of the above-mentioned MIM capacitor test structure at different test voltages and test temperatures, and the shape parameter and scale parameter in the Weibull distribution fitting formula are extracted; the shape parameter and scale parameter are used to further predict the failure probability of the MIM capacitor test structure group, or the life under a given failure probability.

[0032] In addition to directly studying the TDDB performance of the MIM capacitor, the MIM capacitor test structure of the present invention can also be used to study factors that may cause damage to the trench sidewall dielectric layer. For example, the re-sputtering process is widely used in PVD deposition of the Ta-based first conductive trench barrier layer 106 to improve the sidewall coverage, but due to high-energy ion bombardment, damage to the trench sidewall dielectric layer 105 may be introduced. Therefore, for the application of high-porosity and low-k-value materials, special attention should be paid to the damage of the first conductive trench barrier layer 106 to the trench sidewall dielectric layer 105. The MIM capacitor of the present invention can minimize the damage to the trench sidewall dielectric layer 105 and reduce TDDB degradation by optimizing the re-sputtering process. In addition, when testing the inherent reliability of the trench sidewall dielectric layer 105, the probe does not need to directly contact the non-critical area, and the test trench sidewall dielectric layer 105 will not be damaged, so it will not affect the reliability of the structural test results.

[0033] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A MIM capacitor test structure, characterized in that The invention comprises, from bottom to top, a semiconductor substrate (101), a first dielectric layer (102), a metal layer below the MIM structure (103), a second dielectric layer (104), a first isolation protection layer (110), a third dielectric layer (111), a second isolation protection layer (114), and a passivation layer (115); A first conductive trench is formed in the first dielectric layer (102), the MIM structure lower metal layer (103), and the second dielectric layer (104); the first conductive trench is provided with a trench sidewall dielectric layer (105), a first conductive trench barrier layer (106), and a MIM structure upper metal layer (107) from the outside to the inside; the first conductive trench barrier layer (106) wraps the MIM structure upper metal layer (107), and the trench sidewall dielectric layer (105) wraps the first conductive trench barrier layer (106); the bottoms of the trench sidewall dielectric layer (105), the first conductive trench barrier layer (106), and the MIM structure upper metal layer (107) are all located in the first dielectric layer (102), and the tops are flush with the top of the second dielectric layer (104); the middle section of the trench sidewall dielectric layer 105 is located in the MIM structure lower metal layer 103; Conductive through holes are opened in the lower metal layer (103) and the second dielectric layer (104) of the MIM structure, and the conductive through holes are provided with a first barrier layer (109) and a first metal layer (108) from the outside to the inside; the first barrier layer (109) wraps the first metal layer (108); Two second conductive grooves are formed in the first isolation protection layer (110) and the third dielectric layer (111), and each second conductive groove is provided with a second conductive groove barrier layer (112) and a conductive metal layer (113) from the outside to the inside; the second conductive groove barrier layer (112) wraps the conductive metal layer (113).

2. A MIM capacitor test structure according to claim 1, characterized in that: Two pad grooves are formed in the second isolation protection layer (114) and the passivation layer (115), and each pad groove is provided with a second barrier layer (117) and a second metal layer (116) from the outside to the inside; the second barrier layer (117) wraps the second metal layer (116).

3. A MIM capacitor test structure according to claim 1, characterized in that: The top of the first conductive trench is flush with the top of the second dielectric layer (104), and the bottom of the first conductive trench is at a distance from the bottom of the first dielectric layer (102).

4. A MIM capacitor test structure according to claim 1, characterized in that: The top of the conductive through hole is flush with the top of the second dielectric layer (104), and the bottom of the conductive through hole is at a distance from the bottom of the lower metal layer (103) of the MIM structure.

5. A MIM capacitor test structure according to claim 1, characterized in that: There is a distance between the first conductive trench and the conductive through hole; there is a distance between the two second conductive trenches.

6. A MIM capacitor test structure according to claim 1, characterized in that: The two second conductive trenches are respectively located above the first conductive trench and the conductive through hole. The bottom length of the second conductive trench located above the first conductive trench is shorter than the top length of the first conductive trench, and the bottom length of the second conductive trench located above the conductive through hole is longer than the top length of the conductive through hole.

7. A MIM capacitor test structure according to claim 1, characterized in that: The material of the upper metal layer (107) and the conductive metal layer (113) of the MIM structure is copper; the material of the second metal layer (116) is aluminum; and the material of the first metal layer (108) is tungsten.

8. A process for preparing a MIM capacitor test structure according to any one of claims 1 to 7, characterized in that Specifically: A semiconductor substrate (101) is provided, and a first dielectric layer (102), a lower metal layer of the MIM structure (103), and a second dielectric layer (104) are sequentially deposited on the semiconductor substrate (101); Etching a first conductive trench through an etching process, then depositing a trench sidewall dielectric layer (105) and a first conductive trench barrier layer (106), filling the upper metal layer (107) of the MIM structure and performing CMP flattening; Etching a conductive through hole through an etching process, depositing a first barrier layer (109) and a first metal layer (108) in the conductive through hole and performing CMP planarization; A first isolation protection layer (110) and a third dielectric layer (111) are deposited on the structure, a second conductive trench is formed by etching, and a second conductive trench barrier layer (112) is deposited respectively, and a conductive metal layer (113) is filled and connected to the first conductive trench and the conductive through hole under the second conductive trench barrier layer (112); A second isolation protection layer (114) and a top passivation layer (115) are deposited above the two second conductive trenches.

9. A reliability testing method for a MIM capacitor testing structure according to any one of claims 1 to 7, characterized in that Specifically: Step S1, applying multiple groups of different test voltages to a group of MIM capacitor test structures at a fixed test temperature to obtain the failure time of the trench sidewall dielectric layer (105) in the current MIM capacitor test structure; At the same time, applying a plurality of different test temperatures to the MIM capacitor test structure under a fixed test voltage to obtain the failure time of the trench sidewall dielectric layer (105) in the current MIM capacitor test structure; Step S2: Use the reliability evaluation model to predict the failure time of the trench sidewall dielectric layer (105) of the MIM capacitor test structure. According to formula (2), the linear fitting With E x The electric field acceleration factor γ can be extracted from the slope by linear fitting The activation energy Ea is obtained from the relationship with 1 / T; the proportional constant τ is obtained by inverse calculation based on the electric field acceleration factor γ and the activation energy Ea; Step S3: Substitute the electric field acceleration factor calculated in step S2 into formula (1): , activation energy Ea, proportional constant τ, and according to the actual test voltage and test temperature, the failure time of the trench sidewall dielectric layer (105) of the MIM capacitor test structure during normal operation can be obtained; The reliability evaluation model is the E model, and the specific formula is: （1） After taking the logarithm of formula (1), it is: （2） Among them, t bd is the failure time of the trench sidewall dielectric layer (105), τ is the proportionality constant, γ is the electric field acceleration factor, E x is the test voltage electric field, Ea is the activation energy, T is the test temperature, and k is the Boltzmann constant.

10. The method according to claim 9, characterized in that: The method comprises: Step S4: In order to further provide the failure behavior of the MIM capacitor test structure group, thereby predicting the TDDB life of the MIM capacitor test structure group as a whole, a Weibull distribution fitting can be performed based on the failure time of the trench sidewall dielectric layer (105) of the above-mentioned MIM capacitor test structure at different test voltages and test temperatures, and the shape parameter and scale parameter in the Weibull distribution fitting formula are extracted; the shape parameter and scale parameter are used to further predict the failure probability of the MIM capacitor test structure group, or the life under a given failure probability.

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