Display device and manufacturing method thereof

Abstract

The invention provides a display device and a manufacturing method thereof. The display device may include a substrate including a display area and a non-display area, the non-display area including a pad area; a transistor and a conductive pattern on the substrate in the display area; a via layer on the transistor and the conductive pattern to cover the transistor and the conductive pattern; a first alignment electrode and a second alignment electrode on the via layer; a light emitting element between the first alignment electrode and the second alignment electrode; a first electrode and a second electrode spaced apart from each other and electrically connected to the light emitting element; a plurality of pads on the substrate in the pad region; and a dummy pattern on the substrate in the pad region and spaced apart from the plurality of pads. The via layer and the dummy pattern may include the same material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0088594 filed in the Korean Intellectual Property Office on July 7, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Various embodiments of the present disclosure are directed to a display device and a method of manufacturing the display device. Background Art

[0004] Recently, as interest in information display increases, research and development of display devices have been continuously conducted. Summary of the invention

[0005] Various embodiments of the present disclosure are directed to a display device having improved reliability and a method of manufacturing the display device.

[0006] One or more embodiments of the present disclosure may provide a display device, comprising: a substrate, comprising a display area and a non-display area, the non-display area comprising a pad area; a transistor and a conductive pattern, on the substrate in the display area; a through-hole layer, on the transistor and the conductive pattern, to cover the transistor and the conductive pattern; a first alignment electrode and a second alignment electrode, on the through-hole layer and spaced apart from each other; a light-emitting element, between the first alignment electrode and the second alignment electrode; a first electrode and a second electrode, spaced apart from each other and electrically connected to the light-emitting element; a plurality of pads, on the substrate in the pad area; and a dummy pattern, on the substrate in the pad area, and spaced apart from the plurality of pads. The through-hole layer and the dummy pattern may comprise the same material.

[0007] The via layer and the dummy pattern may be in the same layer.

[0008] The dummy pattern may be adjacent to an edge of each of the plurality of pads.

[0009] The dummy pattern may be between two adjacent pads among the plurality of pads.

[0010] The display device may further include: a passivation layer located between the substrate and the through-hole layer in the display area, and between the substrate and the dummy pattern in the pad area; a first insulating layer located on the through-hole layer in the display area; and a second insulating layer located on the first insulating layer in the display area, and on the dummy pattern and the passivation layer in the pad area.

[0011] A height of each of the plurality of pads in the thickness direction of the substrate may be different from a height of the dummy pattern in the thickness direction of the substrate.

[0012] A height of each of the plurality of pads may be greater than a height of the dummy pattern.

[0013] Each of the plurality of pads may include: a first pad electrode on the substrate; and a second pad electrode on the first pad electrode and electrically connected to the first pad electrode. The first pad electrode may be in the same layer as the conductive pattern. The second electrode may be in the same layer as at least one of the first electrode and the second electrode.

[0014] The conductive pattern may include a first conductive pattern, a second conductive pattern, and a third conductive pattern spaced apart from each other between the substrate and the passivation layer. The first conductive pattern may include an electrode of a storage capacitor electrically connected to the transistor. The second conductive pattern may include a second power line to which a voltage of a second driving power source is to be applied. The third conductive pattern may include a first power line to which a voltage of a first driving power source different from the second driving power source is to be applied.

[0015] The passivation layer may include a first opening exposing an area of ​​the first conductive pattern, a second opening exposing the first area of ​​the second conductive pattern, a third opening exposing the second area of ​​the second conductive pattern, a fourth opening exposing an area of ​​the third conductive pattern, and a fifth opening exposing a portion of the first pad electrode. The through-hole layer includes a first contact exposing the area of ​​the first conductive pattern, a second contact exposing the first area of ​​the second conductive pattern, a third contact exposing the second area of ​​the second conductive pattern, and a fourth contact exposing the area of ​​the third conductive pattern. The second insulating layer may include a first contact hole exposing the area of ​​the first conductive pattern, a second contact hole exposing the second area of ​​the second conductive pattern, and a third contact hole exposing the portion of the first pad electrode.

[0016] The first alignment electrode may contact the one region of the third conductive pattern through the fourth contactor and the fourth opening and may be electrically connected to the third conductive pattern. The second alignment electrode may contact the first region of the second conductive pattern through the second contactor and the second opening and may be electrically connected to the second conductive pattern.

[0017] The first electrode may directly contact the one region of the first conductive pattern through the first contact hole, the first contactor, and the first opening, and may be electrically connected to the first conductive pattern. The second electrode may directly contact the second region of the second conductive pattern through the second contact hole, the third contactor, and the third opening, and may be electrically connected to the second conductive pattern.

[0018] The light emitting element may include a first end electrically connected to the first electrode and a second end electrically connected to the second electrode. The light emitting element may also include a P-type semiconductor layer on the first end, an N-type semiconductor layer on the second end, and an active layer between the P-type semiconductor layer and the N-type semiconductor layer.

[0019] The display device may further include: a color conversion layer on the light emitting element and configured to change a wavelength of light emitted from the light emitting element; and a color filter on the color conversion layer.

[0020] One or more embodiments of the present disclosure may provide a display device, comprising: a substrate, comprising a display area and a non-display area, the non-display area comprising a pad area; a transistor and a conductive pattern, on the substrate in the display area; a through-hole layer, on the transistor and the conductive pattern, to cover the transistor and the conductive pattern; a first alignment electrode and a second alignment electrode, on the through-hole layer and spaced apart from each other; a light-emitting element, between the first alignment electrode and the second alignment electrode; a first electrode and a second electrode, spaced apart from each other and electrically connected to the light-emitting element; a plurality of pads, on the substrate in the pad area; and a dummy pattern, on the substrate in the pad area, and overlapping each of the plurality of pads. The dummy pattern may include a first layer, a second layer, and a third layer stacked in series. At least one of the first layer, the second layer, and the third layer may include the same material as the through-hole layer.

[0021] The display device may further include: an interlayer insulating layer located between the substrate and the conductive pattern in the display area, and between the substrate and the pad in the pad area; a passivation layer on the interlayer insulating layer; a first insulating layer located on the through-hole layer in the display area; and a second insulating layer located on the first insulating layer in the display area, and on the passivation layer in the pad area. The first layer may be in the same layer as the passivation layer, the second layer may be in the same layer as the through-hole layer, and the third layer may be in the same layer as the first insulating layer.

[0022] The first layer may include the same material as the passivation layer, the second layer may include the same material as the via layer, and the third layer may include the same material as the first insulating layer.

[0023] Each of the plurality of pads may include: a first pad electrode on the interlayer insulating layer; and a second pad electrode on the first pad electrode and the dummy pattern and electrically connected to the first pad electrode. The first pad electrode may be in the same layer as the conductive pattern. The second electrode may be in the same layer as at least one of the first electrode and the second electrode.

[0024] One or more embodiments of the present disclosure may provide a method for manufacturing a display device, comprising: forming a first conductive pattern, a second conductive pattern, a third conductive pattern, and a first pad electrode on a substrate including a display area and a non-display area, and forming a passivation layer on the first conductive pattern, the second conductive pattern, the third conductive pattern, and the first pad electrode, the non-display area including the pad area; forming a through-hole pattern by depositing a through-hole material layer on the passivation layer, setting a mask on the through-hole material layer, and performing a photolithography process, the through-hole pattern comprising a contact exposing an area of ​​the passivation layer on the third conductive pattern, a first step portion corresponding to the second conductive pattern, and a second step portion corresponding to the first pad electrode; exposing a portion of the third conductive pattern by removing an area of ​​the passivation layer through a dry etching process; forming each other on the through-hole pattern in the display area. The invention relates to a method for manufacturing a light emitting element according to the present invention, wherein the first alignment electrode and the second alignment electrode are separated by this interval; forming a first insulating layer patterned to expose the first step portion on the through hole pattern and the first alignment electrode and the second alignment electrode in the display area; forming a through hole layer by removing the first step portion in the display area through an ashing process to expose a portion of the passivation layer under the first step portion, and exposing a portion of the passivation layer under the second step portion and forming a dummy pattern by removing the second step portion in the pad area through an ashing process; aligning a light emitting element between the first alignment electrode and the second alignment electrode in the display area; forming a second insulating layer on the first insulating layer in the display area and the passivation layer in the non-display area; and forming a first electrode and a second electrode electrically connected to the light emitting element in the display area, and forming a second pad electrode electrically connected to the first pad electrode in the non-display area.

[0025] The mask may include a first portion, a second portion, a third portion, and a fourth portion. The first portion may include a transparent portion that allows light to pass completely. The second portion may include a blocking portion that completely blocks light. The third portion may include a translucent portion that allows light to pass partially. The fourth portion may include a slit pattern portion having at least one slit pattern.

[0026] The first portion may correspond to a contact of the through-hole pattern, the third portion may correspond to a first step portion of the through-hole pattern, the fourth portion may correspond to a second step portion of the through-hole pattern, and the second portion may correspond to another area of ​​the through-hole pattern other than the contact and the first and second step portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic perspective view showing a light emitting element according to one or more embodiments.

[0028] Figure 2 It is shown Figure 1 Schematic cross-sectional view of a light-emitting element.

[0029] Figure 3 is a schematic plan view illustrating a display device according to one or more embodiments.

[0030] Figure 4 It is shown that the Figure 3 Schematic circuit diagram of the electrical connection relationship of the components in a pixel.

[0031] Figure 5 It is shown Figure 3 Schematic plan view of the display element layers of a pixel in FIG.

[0032] Figure 6 It is along Figure 5 A schematic cross-sectional view taken along line II-II′.

[0033] Figure 7 and Figure 8 It is along Figure 5 A schematic cross-sectional view taken along line III-III′.

[0034] Fig. 9 It is along Figure 5 Schematic cross-sectional view taken along line IV-IV′ and line VV′.

[0035] Fig.10 A pixel according to one or more embodiments is shown and is along Figure 5 A schematic cross-sectional view taken along line III-III′.

[0036] Fig.11A It is along Figure 3 A schematic cross-sectional view taken along line II′.

[0037] Fig. 11B yes Fig.11A Schematic top view of the pad area.

[0038] Figures 12 to 18 It is used to describe the manufacturing Fig. 9 and Fig.11A A schematic cross-sectional view of a method of displaying a device as shown in FIG.

[0039] Fig.19A It is along Figure 3 A schematic cross-sectional view taken along line II′.

[0040] Fig.19B yes Fig.19A Schematic top view of the pad area.

[0041] Figure 20 to Figure 26 It is used to describe the manufacturing Fig. 9 and Fig.19AA schematic cross-sectional view of a method of displaying a device as shown in FIG. DETAILED DESCRIPTION

[0042] Since the present disclosure allows various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to a specific mode of practice, and it is to be understood that all changes, equivalents and substitutes that do not depart from the technical scope of the present disclosure are included in the present disclosure.

[0043] Throughout the present disclosure, the same reference numerals represent the same parts throughout the various drawings and embodiments of the present disclosure. For the clarity of illustration, the size of the elements in the drawings may be exaggerated. It will be understood that although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teaching of the present disclosure, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element.

[0044] It will also be understood that when used in this specification, the terms "comprising", "including", "having", etc. specify the presence of the stated features, wholes, steps, operations, elements, components and / or combinations thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. In addition, in the case of an expression such as a layer, film, region or plate that a first part is disposed on a second part, the first part may not only be directly on the second part, but also a third part may be between them. In addition, in the case of an expression such as a layer, film, region or plate that a first part is formed on a second part, the surface of the second part on which the first part is formed is not limited to the upper surface of the second part, but may include other surfaces such as the side surface or lower surface of the second part. Conversely, in the case of an expression such as a layer, film, region or plate that a first part is below the second part, the first part may not only be directly below the second part, but also a third part may be between them.

[0045] The embodiments of the present disclosure and required details are described with reference to the accompanying drawings in order to describe the present disclosure in detail so that those skilled in the art can easily practice the present disclosure. In addition, a singular form may include a plural form as long as it is not particularly mentioned in a sentence.

[0046] Figure 1 is a schematic perspective view showing a light emitting element LD according to one or more embodiments. Figure 2 It is shown Figure 1 Schematic cross-sectional view of a light emitting element LD.

[0047] refer to Figure 1 and Figure 2 , the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may be implemented as an emission stack (or referred to as a "light emitting stack pattern") formed by sequentially stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. The type and / or shape of the light emitting element LD is not limited to Figure 1 The type and / or shape of the embodiment shown in .

[0048] The light emitting element LD may be formed in a shape extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end EP1 and a second end EP2 opposite to each other along the longitudinal direction. For example, the second semiconductor layer 13 may be disposed on the first end EP1 of the light emitting element LD, and the first semiconductor layer 11 may be disposed on the second end EP2 of the light emitting element LD. However, the present disclosure is not limited to the foregoing examples.

[0049] The light emitting element LD can be arranged in various shapes. Figure 1 As shown in , the light emitting element LD may have a rod-like shape, a bar-like shape, or a column-like shape that is long in the longitudinal direction (e.g., having an aspect ratio greater than 1). The light emitting element LD may include a light emitting diode (LED) manufactured to have an ultra-small size, for example, having a diameter D and / or a length L corresponding to a range from nanometer level (or nanometer scale) to micrometer level (or micrometer scale).

[0050] In the case where the light emitting element LD is long relative to the longitudinal direction, the diameter D of the light emitting element LD may approximately range from 0.5 μm to 6 μm, and the length L thereof may approximately range from 1 μm to 10 μm. However, the diameter D and the length L of the light emitting element LD are not limited thereto. The size of the light emitting element LD may be changed to meet the requirements (or design conditions) of the lighting device or the self-emitting display device to which the light emitting element LD is applied.

[0051] The first semiconductor layer 11 may include, for example, at least one N-type semiconductor layer. For example, the first semiconductor layer 11 may include an N-type semiconductor layer including at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a first conductive dopant (or N-type dopant) such as, for example, Si, Ge, and / or Sn. However, the constituent material of the first semiconductor layer 11 is not limited thereto, and various other materials may be used to form the first semiconductor layer 11.

[0052] The active layer 12 (or emission layer) may be disposed on the first semiconductor layer 11 and may have a single quantum well structure or a multi-quantum well structure. For example, in the case where the active layer 12 has a multi-quantum well structure, the active layer 12 may be formed by periodically and repeatedly stacking a barrier layer, a strain enhancement layer, and a well layer as a unit. However, the structure of the active layer 12 is not limited to that of the aforementioned embodiment.

[0053] The active layer 12 may emit light having a wavelength ranging from 400 nm to 900 nm and have a double heterostructure. In one or more embodiments, a cladding layer doped with a conductive dopant may be formed on or below the active layer 12 along the longitudinal direction of the light emitting element LD. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In one or more embodiments, the active layer 12 may be formed using a material such as AlGaN or InAlGaN, and various other materials may be used to form the active layer 12.

[0054] If an electric field having a certain voltage or higher is applied to opposite ends of the light emitting element LD, the light emitting element LD can emit light by recombination of electron-hole pairs in the active layer 12. Since light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source (light emitting source) of various light emitting devices and pixels of a display device.

[0055] The second semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one P-type semiconductor layer. For example, the second semiconductor layer 13 may include a P-type semiconductor layer containing any semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN and / or InN and doped with a second conductive dopant (or P-type dopant) such as Mg, Zn, Ca, Sr and / or Ba. However, the material for forming the second semiconductor layer 13 is not limited thereto, and various other materials may be used to form the second semiconductor layer 13.

[0056] The first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses in the longitudinal direction of the light emitting element LD. For example, the first semiconductor layer 11 may have a thickness greater than that of the second semiconductor layer 13 in the longitudinal direction of the light emitting element LD, but the present disclosure is not limited thereto.

[0057] although Figure 1 and Figure 2It is shown that each of the first semiconductor layer 11 and the second semiconductor layer 13 is formed of a single layer, but the present disclosure is not limited thereto. In one or more embodiments, depending on the material of the active layer 12, each of the first semiconductor layer 11 and the second semiconductor layer 13 may also include one or more layers, such as a cladding layer and / or a tensile strain barrier reduction (TSBR) layer.

[0058] In one or more embodiments, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the light emitting element LD may further include a contact electrode (hereinafter referred to as a "first contact electrode") disposed on the second semiconductor layer 13. In addition, in one or more embodiments, the light emitting element LD may further include an additional contact electrode (hereinafter referred to as a "second contact electrode") disposed on one end of the first semiconductor layer 11.

[0059] Each of the first contact electrode and the second contact electrode may be an ohmic contact electrode, but the present disclosure is not limited thereto. In one or more embodiments, each of the first contact electrode and the second contact electrode may be a Schottky contact electrode.

[0060] Materials included in the first contact electrode and the second contact electrode may be the same as or different from each other.The first contact electrode and the second contact electrode may be substantially transparent or translucent.

[0061] In one or more embodiments, the light emitting element LD may further include an insulating layer 14. However, depending on the embodiment, the insulating layer 14 may be omitted or may be provided to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0062] The insulating layer 14 can prevent the active layer 12 from being short-circuited due to contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, the insulating layer 14 can reduce or minimize surface defects of the light-emitting element LD, thereby improving the life and emission efficiency of the light-emitting element LD. In the case where a plurality of light-emitting elements LD are arranged in close contact with each other, the insulating layer 14 can prevent an undesirable short circuit from occurring between the light-emitting elements LD. The presence or absence of the insulating layer 14 is not limited as long as the active layer 12 can be prevented from being short-circuited with an external conductive material.

[0063] The insulating layer 14 may be disposed around (eg, surround or enclose) the entire outer surface (eg, outer periphery or circumferential surface) of the emission stack including the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 , but is not limited thereto.

[0064] The insulating layer 14 may include a transparent insulating material. Various materials having insulating properties may be used as the material of the insulating layer 14. The insulating layer 14 may have a single-layer structure or a multi-layer structure including a double-layer structure.

[0065] In one or more embodiments, the light emitting element LD may be implemented as a light emitting pattern having a core-shell structure.

[0066] The light emitting element LD may be used as a light emitting source (or light source) for various display devices. The light emitting element LD may be manufactured through a surface treatment process.

[0067] Figure 3 is a schematic plan view illustrating a display device DD according to one or more embodiments.

[0068] exist Figure 3 , for the purpose of explanation, the structure of the display device DD, for example, the display panel DP provided in the display device DD is schematically illustrated with a display area DA in which an image is displayed as the center.

[0069] refer to Figures 1 to 3 The display device DD (or display panel DP) may include a substrate SUB, pixels PXL disposed on the substrate SUB and each including at least one light emitting element LD, a driver disposed on the substrate SUB and configured to drive the pixels PXL, and a line assembly disposed to electrically connect the pixels PXL to the driver.

[0070] The substrate SUB may include a transparent insulating material to allow light to be transmitted. The substrate SUB may be a rigid substrate or a flexible substrate.

[0071] For example, the rigid substrate may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate, but is not limited thereto.

[0072] The flexible substrate can be either a film substrate or a plastic substrate including a polymer organic material. For example, the flexible substrate can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0073] One area of ​​the substrate SUB may be set as a display area DA in which the pixel PXL is disposed, and another area of ​​the substrate SUB may be set as a non-display area NDA. For example, the substrate SUB may include a display area DA and a non-display area NDA disposed around an edge or periphery of the display area DA (or adjacent to the display area DA), in which there is a pixel area PXA in which the corresponding pixel PXL is disposed.

[0074] The non-display area NDA may be disposed on at least one side of the display area DA. The non-display area NDA may surround the periphery (or edge) of the display area DA. In the non-display area NDA, a line component and a driver are disposed. For example, the non-display area NDA may be an area in which a fan-out line LP, a pad PD, and / or an internal circuit component electrically connected to the pixel PXL to drive the pixel PXL are disposed.

[0075] The non-display area NDA may include a fan-out area FTA and a pad area PDA.

[0076] The pad area PDA may be an area of ​​the non-display area NDA in which the pad assembly PDP is positioned, and may be disposed to be closest to the periphery (or edge) of the non-display area NDA. The fan-out area FTA may be another area of ​​the non-display area NDA in which the fan-out line LP is positioned, and may be disposed adjacent to the display area DA in the non-display area NDA. For example, the fan-out area FTA may be an area of ​​the non-display area NDA disposed between the pad area PDA and the display area DA. In one or more embodiments, the non-display area NDA may include an antistatic circuit area in which an antistatic circuit electrically connected to a signal line disposed in the display area DA and configured to prevent static electricity from occurring is disposed.

[0077] The pad assembly PDP may be disposed in the pad area PDA. The fan-out line LP may be disposed in the fan-out area FTA.

[0078] The fan-out line LP may be electrically connected to the pixel PXL so that some signals applied from the driver may be transmitted to the pixel PXL. The fan-out line LP may be a connection component positioned in the fan-out area FTA to electrically connect the driver to the pixel PXL.

[0079] The pad assembly PDP may include a plurality of pads PD. The pads PD may provide a driving power voltage and a signal for driving an internal circuit assembly and / or a pixel PXL disposed in the display area DA. In one or more embodiments, in the case where a driver is mounted in a non-display area NDA of a substrate SUB, the pad assembly PDP may overlap with an output pad of the driver and receive a signal output from the driver. In one or more embodiments, the pads PD may be electrically connected to an external circuit substrate via a conductive adhesive assembly.

[0080] Each of the pixels PXL may be disposed in the pixel area PXA. The pixels PXL may be arranged in the display area DA in a stripe arrangement, etc., but the present disclosure is not limited thereto.

[0081] Each pixel PXL may include a pixel circuit layer (refer to Figure 6 "PCL") and a display element layer positioned on the pixel circuit layer PCL (reference Figure 6 “DPL”).

[0082] The pixel circuit layer PCL may include a pixel circuit disposed on the substrate SUB and including a plurality of transistors (see Figure 4 The pixel circuit layer PCL may include a semiconductor layer, a gate electrode, a first terminal, and a second terminal, and a signal line connected to the transistor. Each transistor has a structure in which, for example, a semiconductor layer, a gate electrode, a first terminal, and a second terminal are stacked in succession and an insulating layer is interposed therebetween. The semiconductor layer may include amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon, and / or an organic semiconductor and / or an oxide semiconductor. Although each of the gate electrode, the first terminal (or the drain electrode), and the second terminal (or the source electrode) may include one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo), the present disclosure is not limited thereto. In addition, the pixel circuit layer PCL may include one or more insulating layers.

[0083] In the display component layer DPL, you can set the emission component (refer to Figure 4 The emitting component includes a light emitting element LD electrically connected to a transistor to emit light.

[0084] Figure 4 It is shown that the Figure 3 Schematic circuit diagram of the electrical connection relationship of components in the pixel PXL.

[0085] For example, Figure 4 The electrical connection relationship of components included in a pixel PXL that can be used in an active matrix display device according to one or more embodiments is shown. Here, the connection relationship of the components of each pixel PXL is not limited thereto.

[0086] refer to Figures 1 to 4, the pixel PXL may include an emission component EMU configured to generate light having brightness corresponding to the data signal. In addition, the pixel PXL may include a pixel circuit PXC configured to drive the emission component EMU.

[0087] For example, the emission component EMU may include a first electrode PE1 (or a first pixel electrode) electrically connected to a first driving power source VDD by a pixel circuit PXC and a first power line PL1, a second electrode PE2 (or a second pixel electrode) electrically connected to a second driving power source VSS by a second power line PL2, and a plurality of light emitting elements LD electrically connected between the first electrode PE1 and the second electrode PE2. The first driving power source VDD and the second driving power source VSS may have different potentials to allow the light emitting element LD to emit light. For example, the first driving power source VDD may be set to a high potential power source, and the second driving power source VSS may be set to a low potential power source.

[0088] In one or more embodiments, the emission assembly EMU may include at least one series connection group. Each series connection group may include a pair of electrodes (e.g., two electrodes) and at least one light-emitting element LD electrically connected between the pair of electrodes in a forward direction. In one or more embodiments, the number of series connections forming the emission assembly EMU and the number of light-emitting elements LD forming each series connection group are not limited. For example, the number of light-emitting elements LD forming each series connection group may be the same or different from each other. The number of light-emitting elements LD in each series connection group is not particularly limited.

[0089] For example, the emission assembly EMU may include a first series set SET1 including at least one first light emitting element LD1 and a second series set SET2 including at least one second light emitting element LD2.

[0090] The first series group SET1 may include a first electrode PE1, an intermediate electrode CTE (or a bridging electrode), and at least one first light emitting element LD1 electrically connected between the first electrode PE1 and the intermediate electrode CTE. Each first light emitting element LD1 may be connected between the first electrode PE1 and the intermediate electrode CTE in a forward direction. For example, a first end EP1 of the first light emitting element LD1 may be electrically connected to the first electrode PE1. A second end EP2 of the first light emitting element LD1 may be electrically connected to the intermediate electrode CTE.

[0091] The second series group SET2 may include an intermediate electrode CTE, a second electrode PE2, and at least one second light emitting element LD2 electrically connected between the intermediate electrode CTE and the second electrode PE2. Each second light emitting element LD2 may be connected between the intermediate electrode CTE and the second electrode PE2 in a forward direction. For example, a first end EP1 of the second light emitting element LD2 may be electrically connected to the intermediate electrode CTE. A second end EP2 of the second light emitting element LD2 may be electrically connected to the second electrode PE2.

[0092] The first electrode (eg, the first electrode PE1 ) of the emission component EMU may be an anode of the emission component EMU, and the last electrode (eg, the second electrode PE2 ) of the emission component EMU may be a cathode of the emission component EMU.

[0093] In the case where the light-emitting elements LD are connected to have a series / parallel structure, the power efficiency can be improved compared to the case where the same number of light-emitting elements LD are only connected in parallel to each other. In addition, in the pixel PXL in which the light-emitting elements LD are connected to have a series / parallel structure, sufficient brightness can be presented by some series groups of light-emitting elements LD, so that the probability of black spot defects in the pixel PXL can be reduced. However, the present disclosure is not limited to this. The emission component EMU can be formed by connecting only the light-emitting elements LD in series. Alternatively, the emission component EMU can be formed by connecting only the light-emitting elements LD in parallel.

[0094] Each of the light emitting elements LD may include a first terminal EP1 (e.g., a P-type terminal) electrically connected to a first driving power source VDD via at least one electrode (e.g., a first electrode PE1), a pixel circuit PXC, a first power line PL1, etc., and a second terminal EP2 (e.g., an N-type terminal) electrically connected to a second driving power source VSS via at least one electrode (e.g., a second electrode PE2), a second power line PL2, etc. For example, the light emitting element LD may be electrically connected between the first driving power source VDD and the second driving power source VSS in the forward direction. The light emitting element LD electrically connected in the forward direction may form an effective light source of the emission component EMU.

[0095] In one or more embodiments, the emission assembly EMU may include at least one reverse light emitting element LDr in addition to the light emitting elements LD forming the corresponding effective light sources.

[0096] The light-emitting element LD of the emission component EMU can emit light having a brightness corresponding to the driving current provided thereto by the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC can provide a driving current corresponding to the grayscale value of the corresponding frame data to the emission component (also referred to as the light-emitting component) EMU. The driving current provided to the emission component EMU can be divided into a portion flowing into the corresponding light-emitting element LD. Therefore, each of the light-emitting elements LD can emit light having a brightness corresponding to the current applied thereto, so that the emission component EMU can emit light having a brightness corresponding to the driving current.

[0097] The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL, where i and j are natural numbers greater than 0. For example, if the pixel PXL is disposed on the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In addition, the pixel circuit PXC may be connected to the i-th control line CLi and the j-th sensing line SENj of the display area DA.

[0098] The pixel circuit PXC may include first, second and third transistors T1, T2 and T3 and a storage capacitor Cst.

[0099] The first transistor T1 may be a driving transistor configured to control a driving current to be applied to the emission component EMU, and may be electrically connected between the first driving power supply VDD and the emission component EMU. In detail, the first terminal of the first transistor T1 may be electrically connected to the first driving power supply VDD by the first power line PL1. The second terminal of the first transistor T1 may be electrically connected to the second node N2. The gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode.

[0100] The second transistor T2 may be a switching transistor that selects the pixel PXL in response to the scan signal and activates the pixel PXL, and may be electrically connected between the j-th data line Dj and the first node N1. The first terminal of the second transistor T2 may be electrically connected to the j-th data line Dj. The second terminal of the second transistor T2 may be electrically connected to the first node N1 (or the gate electrode of the first transistor T1). The gate electrode of the second transistor T2 may be electrically connected to the i-th scan line Si. The first terminal and the second terminal of the second transistor T2 are different terminals, and for example, if the first terminal is a drain electrode, the second terminal may be a source electrode.

[0101] When a scan signal of a gate-on voltage (e.g., a high level voltage) is provided from the i-th scan line Si, the second transistor T2 may be turned on to electrically connect the j-th data line Dj to the first node N1. The first node N1 may be a point at which the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are electrically connected to each other. The second transistor T2 may transmit a data signal to the gate electrode of the first transistor T1.

[0102] The third transistor T3 can obtain a sensing signal via the jth sensing line SENj by electrically connecting the first transistor T1 to the jth sensing line SENj, and use the sensing signal to detect the characteristics of the pixel PXL, such as the threshold voltage of the first transistor T1. Information about the characteristics of the pixel PXL can be used to convert image data, so that the deviation of the characteristics between the pixels PXL can be compensated. The second terminal of the third transistor T3 can be electrically connected to the second terminal of the first transistor T1 and the second node N2. The first terminal of the third transistor T3 can be electrically connected to the jth sensing line SENj. The gate electrode of the third transistor T3 can be electrically connected to the i-th control line CLi. The first terminal of the third transistor T3 can be a drain electrode, and the second terminal of the third transistor T3 can be a source electrode.

[0103] In addition, the first terminal of the third transistor T3 may be electrically connected to the initialization power supply. The third transistor T3 may be an initialization transistor configured to initialize the second node N2, and may be turned on when a sensing control signal is provided thereto from the i-th control line CLi, so that the voltage of the initialization power supply may be transmitted to the second node N2. Therefore, the upper electrode UE (or the second storage electrode) of the storage capacitor Cst electrically connected to the second node N2 may be initialized.

[0104] The storage capacitor Cst may include a lower electrode LE (or a first storage electrode) and an upper electrode UE (or a second storage electrode). The lower electrode LE may be electrically connected to the first node N1. The upper electrode UE may be electrically connected to the second node N2. The storage capacitor Cst may be charged with a gate voltage corresponding to a data signal to be provided to the first node N1 during one frame period. Therefore, the storage capacitor Cst may store a voltage corresponding to a difference between a voltage of the gate electrode of the first transistor T1 and a voltage of the second node N2.

[0105] although Figure 4 One or more embodiments in which all of the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors are shown, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 can be changed to a P-type transistor. In one or more embodiments, the emission component EMU can be connected between the first driving power supply VDD and the pixel circuit PXC.

[0106] The structure of the pixel circuit PXC may be changed in various ways.

[0107] In the following embodiments, for the purpose of explanation, the lateral direction (or X-axis direction) in the plan view will be represented by the first direction DR1, the longitudinal direction (or Y-axis direction) in the plan view will be represented by the second direction DR2, and the vertical direction in the cross-sectional view will be represented by the third direction DR3.

[0108] Figure 5 It is shown Figure 3 Schematic plan view of a display element layer DPL of a pixel PXL.

[0109] exist Figure 5 , for convenience of explanation, illustration of the pixel circuit PXC including the first to third transistors T1 to T3 electrically connected to the light emitting element LD is omitted.

[0110] exist Figure 5 In the present invention, not only components included in the pixel PXL but also a region in which the components are located may be included in the definition of the term “pixel PXL”.

[0111] refer to Figures 1 to 5 The pixel PXL may be disposed in a pixel area PXA provided on a substrate SUB. The pixel area PXA may include an emission area EMA and a non-emission area NEA.

[0112] The pixel PXL may include a first bank BNK1 positioned in the non-emission area NEA and a light emitting element LD located in the emission area EMA.

[0113] The first bank BNK1 may be a structure for defining respective emission areas EMA of the pixel PXL and the pixel PXL adjacent thereto, and may be, for example, a pixel defining layer. The first bank BNK1 may be a pixel defining layer or a dam structure for defining each emission area EMA to which the light emitting element LD is to be provided during a process of providing (or inputting) the light emitting element LD. The emission area EMA of the pixel PXL may be defined by the first bank BNK1, thereby enabling a mixed solution (e.g., ink) including a target amount and / or type of light emitting element LD to be provided (or inputted) to the emission area EMA.

[0114] The first bank BNK1 may include at least one light blocking material and / or reflective material (or scattering material), thereby preventing a light leakage defect in which light leaks between the pixel PXL and the pixel PXL adjacent thereto. In one or more embodiments, the first bank BNK1 may include a transparent material (or substance). The transparent material may include, for example, a polyamide resin, a polyimide resin, and / or the like, but the present disclosure is not limited thereto. In one or more embodiments, in order to improve the efficiency of light emitted from the pixel PXL, a separate reflective layer may be provided and / or formed on the first bank BNK1.

[0115] The first bank BNK1 may include at least one opening OP exposing components disposed thereunder in the pixel area PXA. The emission area EMA of the pixel PXL and the opening OP of the first bank BNK1 may correspond to each other.

[0116] The electrode separation area ESA may be provided in the non-emission area NEA of each pixel PXL. The electrode separation area ESA may be a region where the first alignment electrode ALE1 in each pixel PXL is separated from the first alignment electrodes ALE1 provided in the pixels PXL arranged in the same pixel column.

[0117] The pixel PXL may include an electrode PE (or pixel electrode) disposed in an emission area EMA, a light emitting element LD electrically connected to the electrode PE, and an alignment electrode ALE disposed at a position corresponding to the electrode PE. For example, a first electrode PE1 (or a first pixel electrode), a second electrode PE2 (or a second pixel electrode), a light emitting element LD, and a first alignment electrode ALE1 and a second alignment electrode ALE2 may be disposed in the emission area EMA. In addition, an intermediate electrode CTE (or a bridging electrode) may be disposed in the emission area EMA. The number, shape, size, arrangement structure, etc. of the electrode PE and / or the alignment electrode ALE may be changed in various ways depending on the structure of the pixel PXL (or the emission component EMU).

[0118] Based on one surface of the substrate SUB on which the pixel PXL is disposed, the alignment electrode ALE, the light emitting element LD, and the electrode PE may be disposed in the listed order, but the present disclosure is not limited thereto. Figures 6 to 9 The stack structure of the pixel PXL is described.

[0119] The alignment electrodes ALE may be disposed in at least the emission area EMA and may be spaced apart from each other in the first direction DR1 in the emission area EMA and each may extend in the second direction DR2. The alignment electrodes ALE may include a 2-2nd alignment electrode ALE2_2, a first alignment electrode ALE1, and a 2-1st alignment electrode ALE2_1 spaced apart from each other in the first direction DR1.

[0120] During the process of manufacturing the display device DD, after the light emitting element LD has been provided to the emission area EMA and aligned in the emission area EMA, at least one of the 2-2nd alignment electrode ALE2_2, the first alignment electrode ALE1, and the 2-1st alignment electrode ALE2_1 may be separated from other electrodes (e.g., the alignment electrode ALE provided in each of the pixels PXL arranged on the same pixel column). For example, during the process of manufacturing the display device DD, after the light emitting element LD has been provided to the emission area EMA and aligned in the emission area EMA, the first alignment electrode ALE1 may be separated from the first alignment electrode ALE1 provided in the adjacent pixel PXL arranged on the same pixel column as the corresponding pixel PXL.

[0121] During the process of manufacturing the display device DD, the first alignment electrodes ALE1 disposed in the display area DA may be formed to be connected to each other. For example, the first alignment electrodes ALE1 may be connected to each other without being partially removed, thereby forming a first alignment line. The first alignment line may be electrically connected to the pixel circuit through the fourth contact CNT4 and the fourth opening OPN4 (refer to Figure 4 The first power line (reference Figure 4 During the process of aligning the light emitting element LD, a first alignment signal may be provided to the first alignment line through the first power line PL1. After the process of aligning the light emitting element LD has been completed, a portion of the first alignment line positioned around the fourth contact CNT4 and the fourth opening OPN4 in the non-emission area NEA may be removed (or the first alignment line may be cut off), whereby the electrical connection between the first alignment electrode ALE1 and the first power line PL1 may be interrupted. In addition, the first alignment line may be cut off in the electrode separation area ESA between adjacent pixels PXL disposed on the same pixel column, so that the first alignment electrodes ALE1 of adjacent pixels PXL may be separated from each other. Therefore, the first alignment electrodes ALE1 of the pixels PXL disposed on the same pixel column may be electrically separated from each other, whereby the pixels PXL may be driven separately.

[0122] In one or more embodiments, the fourth contact CNT4 and the fourth opening OPN4 may be formed by removing portions of two or more insulating layers disposed between the first alignment electrode ALE1 and the first power line PL1 .

[0123] The 2-2nd alignment electrode ALE2_2 may be disposed adjacent to one side (e.g., the left side) of the first alignment electrode ALE1 in a plan view, and the 2-1st alignment electrode ALE2_1 may be disposed adjacent to the other side (e.g., the right side) of the first alignment electrode ALE1 in a plan view. The 2-1st alignment electrode ALE2_1 and the 2-2nd alignment electrode ALE2_2 may be integrally formed and electrically connected to each other, thereby forming the second alignment electrode ALE2.

[0124] The 2-1st alignment electrode ALE2_1 may be electrically connected to the second power line (refer to Figure 4 The second contact CNT2 and the second opening OPN2 may be formed by removing a portion of two or more insulating layers disposed between the 2-1 th alignment electrode ALE2_1 and the second power line PL2.

[0125] Each of the 2-2nd alignment electrode ALE2_2, the first alignment electrode ALE1 and the 2-1st alignment electrode ALE2_1 may serve as an alignment line provided for aligning the light emitting element LD and is configured to receive a signal (eg, an alignment signal) before the light emitting element LD is aligned in the emission area EMA of the pixel PXL.

[0126] Each of the 2-2nd alignment electrode ALE2_2, the first alignment electrode ALE1, and the 2-1st alignment electrode ALE2_1 may be provided in the form of a rod having a constant width in at least the emission area EMA, but the present disclosure is not limited thereto. Each of the 2-2nd alignment electrode ALE2_2, the first alignment electrode ALE1, and the 2-1st alignment electrode ALE2_1 may or may not have a bent portion in the non-emission area NEA, and the shape, size, and / or other characteristics of the electrodes in other areas except the emission area EMA may be changed in various ways without particular limitation.

[0127] Two or more light emitting elements LD may be aligned in the emission area EMA (or the pixel area PXA). The light emitting element LD may be disposed between the first alignment electrode ALE1 and the 2-1 alignment electrode ALE2_1 and between the first alignment electrode ALE1 and the 2-2 alignment electrode ALE2_2. In a plan view, each of the light emitting elements LD may include a first end EP1 and a second end EP2 positioned at respective opposite ends of the light emitting element LD in a longitudinal direction of the light emitting element LD (e.g., in a first direction DR1). The second semiconductor layer (refer to FIG. 1 ) including a P-type semiconductor layer Figure 1 13) can be disposed on the first end EP1 (or the P-type end), and includes a first semiconductor layer of an N-type semiconductor layer (reference Figure 1The light emitting elements LD may be electrically connected in parallel to each other between the 2-1st alignment electrode ALE2_1 and the first alignment electrode ALE1 and between the first alignment electrode ALE1 and the 2-2nd alignment electrode ALE2_2.

[0128] The light emitting elements LD may be disposed at positions spaced apart from each other and aligned substantially parallel to each other. The distance at which the light emitting elements LD are spaced apart from each other is not particularly limited. In one or more embodiments, a plurality of light emitting elements LD may be disposed adjacent to each other to form a group, and a plurality of additional light emitting elements LD may be spaced apart from each other at regular intervals to form another group. The light emitting elements LD may be aligned in one direction with uneven density.

[0129] The light emitting element LD may be input (or provided) to the pixel region PXA (or the emission region EMA) by an inkjet printing scheme, a slit coating scheme, or other various schemes. For example, the light emitting element LD may be mixed with a volatile solvent and then input (or provided) to the pixel region PXA by an inkjet printing scheme or a slit coating scheme.

[0130] In one or more embodiments, the light emitting element LD may include a first light emitting element LD1 and a second light emitting element LD2 .

[0131] The first light emitting element LD1 may be aligned between the right side of the first alignment electrode ALE1 and the 2-1st alignment electrode ALE2_1, and electrically connected to the first electrode PE1 and the intermediate electrode CTE. The second light emitting element LD2 may be aligned between the left side of the first alignment electrode ALE1 and the 2-2nd alignment electrode ALE2_2, and electrically connected to the intermediate electrode CTE and the second electrode PE2.

[0132] A plurality of first light emitting elements LD1 and a plurality of second light emitting elements LD2 may be provided. A first end EP1 of each of the first light emitting elements LD1 may be electrically connected to the first electrode PE1. A second end EP2 of each of the first light emitting elements LD1 may be electrically connected to the intermediate electrode CTE. A first end EP1 of each of the second light emitting elements LD2 may be electrically connected to the intermediate electrode CTE. A second end EP2 of each of the second light emitting elements LD2 may be electrically connected to the second electrode PE2.

[0133] The first light emitting elements LD1 may be connected in parallel to each other between the first electrode PE1 and the intermediate electrode CTE. The second light emitting elements LD2 may be connected in parallel to each other between the intermediate electrode CTE and the second electrode PE2.

[0134] The electrode PE and the intermediate electrode CTE may be disposed in at least the emission area EMA of the pixel PXL, and each may be disposed at a position corresponding to at least one alignment electrode ALE and at least one light emitting element LD.

[0135] The electrode PE may include a first electrode PE1 and a second electrode PE2 spaced apart from each other.

[0136] The first electrode PE1 (or the first pixel electrode) may be formed on the right side of the first alignment electrode ALE1 and the respective first ends EP1 of the first light emitting elements LD1, and thus be electrically connected to the respective first ends EP1 of the first light emitting elements LD1. The first electrode PE1 may have a rod shape having a constant width in its extending direction (e.g., the second direction DR2), but the present disclosure is not limited thereto.

[0137] The second electrode PE2 (or the second pixel electrode) may be formed on the respective second ends EP2 of the 2-2 alignment electrode ALE2_2 and the second light emitting element LD2, and thus be electrically connected to the respective second ends EP2 of the second light emitting element LD2. The second electrode PE2 may have a rod shape having a constant width in its extending direction (e.g., the second direction DR2), but the present disclosure is not limited thereto.

[0138] The intermediate electrode CTE may be formed on the 2-1st alignment electrode ALE2_1 and the respective second ends EP2 of the first light emitting element LD1, and thus may be electrically connected to the respective second ends EP2 of the first light emitting element LD1. In addition, the intermediate electrode CTE may be formed on the left side of the first alignment electrode ALE1 and the respective first ends EP1 of the second light emitting element LD2, and thus may be electrically connected to the respective first ends EP1 of the second light emitting element LD2. The intermediate electrode CTE may be bent one or more times to surround at least one side of the first electrode PE1.

[0139] The first light emitting element LD1 can be connected in series to the second light emitting element LD2 through the intermediate electrode CTE. The first electrode PE1 and the intermediate electrode CTE together with the first light emitting element LD1 connected in parallel therebetween can form a first series group of the emission assembly EMU (refer to Figure 4 The intermediate electrode CTE and the second electrode PE2 together with the second light emitting element LD2 connected in parallel therebetween can form a second series group of the emission assembly EMU (refer to Figure 4 The first electrode PE1 may be an anode of the emission component EMU. The second electrode PE2 may be a cathode of the emission component EMU.

[0140] In one or more embodiments, the first electrode PE1 may be electrically connected to some components of the pixel circuit PXC through the first contact hole CH1 and the first opening OPN1 that overlap each other in the non-emission area NEA. For example, the first electrode PE1 may be electrically connected to a storage capacitor of the pixel circuit PXC through the first contact hole CH1 and the first opening OPN1 (refer to Figure 4 The upper electrode (reference Figure 4 In one or more embodiments, the first contact hole CH1 and the first opening OPN1 may be formed by removing certain regions between the first electrode PE1 and the upper electrode UE of a plurality of insulating layers.

[0141] The second electrode PE2 may be electrically connected to the second power line PL2 through the second contact hole CH2 and the third opening OPN3 overlapping each other in the non-emission area NEA. The second contact hole CH2 and the third opening OPN3 may be formed by removing some regions of a plurality of insulating layers between the second electrode PE2 and the second power line PL2.

[0142] The first and second light emitting elements LD1 and LD2 may be connected in series to each other through the intermediate electrode CTE between the first and second electrodes PE1 and PE2. In this way, the light emitting elements LD aligned in the emission area EMA may be connected in a series / parallel combination structure to form an emission component EMU of the pixel PXL.

[0143] The upper electrode UE of the pixel circuit PXC and the first electrode PE1 of the emission component EMU are in direct contact with each other and connected to each other through the first contact hole CH1 and the first opening OPN1. The second power line PL2 and the second electrode PE2 of the emission component EMU are in direct contact with each other and connected to each other through the second contact hole CH2 and the third opening OPN3. Therefore, during each frame period, the driving current can flow from the first electrode PE1 to the second electrode PE2 via the first light emitting element LD1, the intermediate electrode CTE, and the second light emitting element LD2.

[0144] In one or more embodiments, the first electrode PE1 and the second electrode PE2 may function as driving electrodes configured to drive the light emitting element LD.

[0145] In the following, we will mainly refer to Figures 6 to 9 The stack structure of the pixel PXL according to the aforementioned embodiment will be described.

[0146] Figure 6 It is along Figure 5 A schematic cross-sectional view taken along line II-II′. Figure 7 and Figure 8 It is along Figure 5A schematic cross-sectional view taken along line III-III′. Fig. 9 It is along Figure 5 Schematic cross-sectional view taken along line IV-IV′ and line VV′.

[0147] Figure 8 One or more embodiments of the invention relate to Figure 7 The embodiment of the present invention is modified with respect to the step of forming the intermediate electrode CTE and whether or not the third insulating layer INS3 exists. Figure 8 , one or more embodiments of forming the first electrode PE1 and the second electrode PE2 after forming the intermediate electrode CTE and the third insulating layer INS3 are shown.

[0148] The following about Figures 6 to 9 The description of the embodiment of will focus on the differences from the above-mentioned embodiment in order to avoid redundant description.

[0149] refer to Figures 1 to 9 , the pixel PXL may include a substrate SUB, a pixel circuit layer PCL and a display element layer DPL.

[0150] The pixel circuit PXC including the circuit elements may be disposed in the pixel circuit layer PCL. The emission element EMU including the light emitting element LD electrically connected to the pixel circuit PXC may be disposed in the display element layer DPL.

[0151] The pixel circuit layer PCL and the display element layer DPL may be disposed on one surface of the substrate SUB and overlap each other. For example, in the pixel area PXA of the substrate SUB, the pixel circuit layer PCL may be disposed on one surface of the substrate SUB, and the display element layer DPL may be disposed on the pixel circuit layer PCL. However, the relative positions of the pixel circuit layer PCL and the display element layer DPL on the substrate SUB may vary depending on the implementation. In the case where the pixel circuit layer PCL and the display element layer DPL are separated from each other as separate layers and overlap each other, a layout space sufficient to form each of the pixel circuit PXC and the emission component EMU on a plane may be ensured. In one or more implementations, the pixel circuit layer PCL and the display element layer DPL may be disposed on the same plane without overlapping each other.

[0152] The substrate SUB may include a transparent insulating material. The substrate SUB may be a rigid substrate or a flexible substrate.

[0153] In each pixel region PXA of the pixel circuit layer PCL, a circuit element for forming a pixel circuit PXC of the corresponding pixel PXL and a signal line electrically connected to the circuit element may be provided. In addition, an alignment electrode ALE, a light emitting element LD and / or an electrode PE forming an emission element EMU of the corresponding pixel PXL may be provided in each pixel region PXA of the display element layer DPL.

[0154] In addition to circuit elements and signal lines, the pixel circuit layer PCL may also include one or more insulating layers. For example, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, a passivation layer PSV, and a via layer VIA that are continuously stacked on the substrate SUB in the third direction DR3.

[0155] The buffer layer BFL may be disposed on the entire surface of the substrate SUB. The buffer layer BFL may prevent impurities from diffusing into the transistor T included in the pixel circuit PXC. The buffer layer BFL may be an inorganic insulating layer including an inorganic material. For example, the buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ), but the present disclosure is not limited thereto. The buffer layer BFL may be provided in the form of a single layer structure, or in the form of a multilayer structure having two or more layers. In the case where the buffer layer BFL is provided in the form of a multilayer structure, each layer may be formed of the same material or different materials. The buffer layer BFL may be omitted depending on the material or process conditions of the substrate SUB.

[0156] The gate insulating layer GI may be disposed on the entire surface of the buffer layer BFL, but the present disclosure is not limited thereto. In one or more embodiments, the gate insulating layer GI may be partially disposed on the buffer layer BFL. The gate insulating layer GI may include the same material as that of the buffer layer BFL, or include a suitable (or selected) material among the materials provided as examples of constituent materials for the buffer layer BFL. The gate insulating layer GI may be an inorganic insulating layer including an inorganic material.

[0157] The interlayer insulating layer ILD may be disposed and / or formed on the entire surface of the gate insulating layer GI. The interlayer insulating layer ILD may include the same material as that of the buffer layer BFL, or include one or more suitable (or selected) materials among the materials provided as examples of constituent materials for the buffer layer BFL, but the present disclosure is not limited thereto.

[0158] The passivation layer PSV may be disposed and / or formed on the entire surface of the interlayer insulating layer ILD. The passivation layer PSV may include the same material as that of the buffer layer BFL, or include one or more suitable (or selected) materials among the materials provided as examples of constituent materials for the buffer layer BFL, but the present disclosure is not limited thereto. The passivation layer PSV may partially have an opening, through which some of the circuit elements disposed in the pixel circuit layer PCL are exposed. For example, the passivation layer PSV may partially have an opening, the opening including a first opening OPN1 through which certain areas of the upper electrode UE (or the first conductive pattern CP1) are exposed, a second opening OPN2 through which certain areas of the second power line PL2 are exposed, a third opening OPN3 through which certain areas of the second conductive pattern CP2 are exposed, and a fourth opening OPN4 through which certain areas of the third conductive pattern CP3 are exposed.

[0159] The through-hole layer VIA may be arranged and / or formed on the entire surface of the passivation layer PSV. The through-hole layer VIA may be formed by a single layer including an organic layer or a multilayer having two or more layers. In one or more embodiments, the through-hole layer VIA may be arranged in the form of an inorganic layer and an organic layer arranged on the inorganic layer. In the case where the through-hole layer VIA is formed by a multilayer having two or more layers, the organic layer included in the through-hole layer VIA may define the uppermost layer of the through-hole layer VIA. The through-hole layer VIA may include at least one of a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0160] In one or more embodiments, the through-hole layer VIA may partially have an opening, through which some of the circuit elements disposed in the pixel circuit layer PCL are exposed. For example, the through-hole layer VIA may partially have an opening, which includes a first contactor CNT1 through which some areas of the upper electrode UE (or the first conductive pattern CP1) are exposed, a second contactor CNT2 through which some areas of the second power line PL2 are exposed, a third contactor CNT3 through which some areas of the second conductive pattern CP2 are exposed, and a fourth contactor CNT4 through which some areas of the third conductive pattern CP3 are exposed. For example, the first contactor CNT1 of the through-hole layer VIA may correspond to the first opening OPN1 of the passivation layer PSV. The second contactor CNT2 of the through-hole layer VIA may correspond to the second opening OPN2 of the passivation layer PSV. The third contactor CNT3 of the through-hole layer VIA may correspond to the third opening OPN3 of the passivation layer PSV. The fourth contactor CNT4 of the through-hole layer VIA may correspond to the fourth opening OPN4 of the passivation layer PSV.

[0161] In one or more embodiments, the opposite side surfaces of the via layer VIA defining the first contact CNT1 therebetween are positioned outside the opposite side surfaces of the passivation layer PSV defining the first opening OPN1 therebetween, thereby allowing the opposite side surfaces of the passivation layer PSV to be exposed. In addition, the opposite side surfaces of the via layer VIA defining the third contact CNT3 therebetween are positioned outside the opposite side surfaces of the passivation layer PSV defining the third opening OPN3 therebetween, thereby allowing the opposite side surfaces of the passivation layer PSV to be exposed. The opposite side surfaces of the via layer VIA defining the second contact CNT2 therebetween may be positioned on the same line as the opposite side surfaces of the passivation layer PSV defining the second opening OPN2 therebetween. The opposite side surfaces of the via layer VIA defining the fourth contact CNT4 therebetween may be positioned on the same line as the opposite side surfaces of the passivation layer PSV defining the fourth opening OPN4 therebetween.

[0162] The via layer VIA may serve as a planarization layer formed to mitigate a step difference in the pixel circuit layer PCL generated by components of the pixel circuit PXC disposed below the via layer VIA.

[0163] The pixel circuit layer PCL may include one or more conductive layers disposed between the aforementioned insulating layers. For example, the pixel circuit layer PCL may include a first conductive layer disposed between the substrate SUB and the buffer layer BFL, a second conductive layer disposed on the gate insulating layer GI, and a third conductive layer disposed on the interlayer insulating layer ILD. However, the insulating layers and conductive layers included in the pixel circuit layer PCL are not limited to the aforementioned elements. In one or more embodiments, in addition to the aforementioned insulating layer and the aforementioned conductive layer, other insulating layers and other conductive layers may be disposed in the pixel circuit layer PCL.

[0164] The first conductive layer may be formed as a single layer made of a single material or a combination selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof. In addition, in order to reduce line resistance, the first conductive layer may have a double-layer or multi-layer structure formed of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and / or silver (Ag) as low-resistance materials. Each of the second conductive layer and the third conductive layer may include the same material as that of the first conductive layer, or include one or more suitable materials among the materials provided as examples of constituent materials for the first conductive layer, but the present disclosure is not limited thereto.

[0165] The pixel circuit PXC provided in the pixel circuit layer PCL may include at least one transistor T. The transistor T may be a reference Figure 4For example, the transistor T may be one of the first transistor T1, the second transistor T2, and the third transistor T3 described above. Figure 4 A first transistor T1 is described.

[0166] The transistor T may include a semiconductor pattern SCP, a gate electrode GE overlapping a portion of the semiconductor pattern SCP in the third direction DR3 , and a source electrode SE and a drain electrode DE connected to the semiconductor pattern SCP.

[0167] The gate electrode GE may be formed on the gate insulating layer GI. The gate electrode GE may be included in a second conductive layer disposed between the gate insulating layer GI and the interlayer insulating layer ILD. For example, the gate electrode GE may be the second conductive layer. The gate electrode GE may overlap a portion of the semiconductor pattern SCP. For example, the gate electrode GE may overlap an active pattern of the semiconductor pattern SCP.

[0168] The semiconductor pattern SCP may be disposed and / or formed on the buffer layer BFL. For example, the semiconductor pattern SCP may be disposed between the buffer layer BFL and the gate insulating layer GI. The semiconductor pattern SCP may be a semiconductor layer formed of polycrystalline silicon, amorphous silicon, an oxide semiconductor, and / or the like. The semiconductor pattern SCP may include an active pattern, a first contact region, and a second contact region. The active pattern, the first contact region, and the second contact region may each be formed of an undoped or impurity-doped semiconductor layer. For example, each of the first contact region and the second contact region may be formed of an impurity-doped semiconductor layer, and the active pattern may be formed of an undoped semiconductor layer.

[0169] The active pattern of the semiconductor pattern SCP may be a region overlapping with the gate electrode GE of the transistor T, and may form a channel region of the transistor T. The first contact region of the semiconductor pattern SCP may contact one end of the active pattern. In addition, the first contact region may be connected to the source electrode SE. The second contact region of the semiconductor pattern SCP may contact the remaining end of the active pattern. In addition, the second contact region may be connected to the drain electrode DE.

[0170] The source electrode SE may be positioned on the interlayer insulating layer ILD. The source electrode SE may contact the first contact region of the semiconductor pattern SCP through a contact hole passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0171] The drain electrode DE may be positioned on the interlayer insulating layer ILD. The drain electrode DE may be disposed on the interlayer insulating layer ILD at a position spaced apart from the source electrode SE. The drain electrode DE may contact the second contact region of the semiconductor pattern SCP through a contact hole passing through the gate insulating layer GI and the interlayer insulating layer ILD.

[0172] The first bottom metal pattern BML1 may be disposed under the transistor T. As shown in FIG.

[0173] The first bottom metal pattern BML1 may be formed of a first conductive layer disposed between the substrate SUB and the buffer layer BFL. The first bottom metal pattern BML1 may be electrically connected to the transistor T. The first bottom metal pattern BML1 may be electrically connected to the semiconductor pattern SCP of the transistor T and stabilize a channel region of the transistor T. In addition, the first bottom metal pattern BML1 is electrically connected to the transistor T, thereby preventing the first bottom metal pattern BML1 from floating.

[0174] The second bottom metal pattern BML2, the first and second power lines PL1 and PL2, and the conductive patterns CP1 to CP3 may be disposed in the pixel circuit layer PCL. The conductive patterns CP1 to CP3 may include the first, second, and third conductive patterns CP1, CP2, and CP3 disposed at locations spaced apart from each other.

[0175] The second bottom metal pattern BML2 may be formed of a first conductive layer disposed between the substrate SUB and the buffer layer BFL. The second bottom metal pattern BML2 may be disposed between the substrate SUB and the buffer layer BFL to overlap the second conductive pattern CP2 in the third direction DR3.

[0176] The first conductive pattern CP1 , the second power line PL2 , the second conductive pattern CP2 , and the third conductive pattern CP3 may be formed of a third conductive layer disposed between the interlayer insulating layer ILD and the passivation layer PSV.

[0177] In one or more embodiments, the first conductive pattern CP1 may be an upper electrode UE (of a capacitor (eg, Cst)) electrically connected to a source electrode SE of the transistor T. The third conductive pattern CP3 may be a first driving power source (reference Figure 4 The voltage of the second driving power source (reference voltage VDD) is applied to the first power line PL1. The second conductive pattern CP2 may be a voltage of the second driving power source (reference voltage VDD). Figure 4 The second power line PL2 to which the "VSS" of the voltage source is applied is provided, but the present disclosure is not limited thereto. In one or more embodiments, the second conductive pattern CP2 may be formed separately from the second power line PL2 and then electrically connected to the second power line PL2.

[0178] The upper electrode UE (or the first conductive pattern CP1 ) may be connected to the first electrode PE1 of the display element layer DPL in such a manner that the upper electrode UE directly contacts the first electrode PE1 through the first opening OPN1 of the passivation layer PSV and the first contact hole CH1 of the second insulating layer INS2 .

[0179] The second power line PL2 may be connected to the 2-1st alignment electrode ALE2_1 of the display element layer DPL in such a manner that the second power line PL2 directly contacts the 2-1st alignment electrode ALE2_1 through the second opening OPN2 of the passivation layer PSV and the second contact CNT2 of the via layer VIA.

[0180] The second conductive pattern CP2 may be connected to the second electrode PE2 of the display element layer DPL in such a manner that the second conductive pattern CP2 directly contacts the second electrode PE2 through the third opening OPN3 of the passivation layer PSV and the second contact hole CH2 of the second insulating layer INS2.

[0181] The second opening OPN2 of the passivation layer PSV and the second contact CNT2 of the through-hole layer VIA may expose a region of the second power line PL2. The third opening OPN3 of the passivation layer PSV, the third contact CNT3 of the through-hole layer VIA, and the second contact hole CH2 of the second insulating layer INS2 may expose a region of the second conductive pattern CP2 (or another region of the second power line PL2).

[0182] The third conductive pattern CP3 (or the first power line PL1 ) may be connected to the first alignment electrode ALE1 of the display element layer DPL in such a manner that the third conductive pattern CP3 directly contacts the first alignment electrode ALE1 through the fourth opening OPN4 of the passivation layer PSV and the fourth contact CNT4 of the via layer VIA.

[0183] The display element layer DPL may be located on the via layer VIA.

[0184] The display element layer DPL may include a first alignment electrode ALE1 and a second alignment electrode ALE2 disposed in the emission area EMA, a light emitting element LD, a first electrode PE1 and a second electrode PE2, and an intermediate electrode CTE. In addition, the display element layer DPL may also include an insulating pattern and / or an insulating layer continuously disposed on one surface of the pixel circuit layer PCL (or the through hole layer VIA). For example, the display element layer DPL may also include a bank pattern BNP, a first insulating layer INS1, a first bank BNK1, and a second insulating layer INS2.

[0185] The bank pattern BNP may be disposed on the through hole layer VIA of the pixel circuit layer PCL. Each of the bank patterns BNP may be formed by a separate pattern, which is respectively disposed under each of the first alignment electrode ALE1 and the second alignment electrode ALE2, so that the separate pattern overlaps a portion of a corresponding one of the first alignment electrode ALE1 and the second alignment electrode ALE2. For example, the bank pattern BNP may be formed by a separate pattern respectively disposed under each of the first alignment electrode ALE1, the 2-1st alignment electrode ALE2_1, and the 2-2nd alignment electrode ALE2_2, so that the separate pattern overlaps a portion of a corresponding one of the first alignment electrode ALE1, the 2-1st alignment electrode ALE2_1, and the 2-2nd alignment electrode ALE2_2.

[0186] The bank pattern BNP may protrude upward in the third direction DR3 on one surface of the via layer VIA of the pixel circuit layer PCL. Therefore, one area of ​​each of the first and second alignment electrodes ALE1 and ALE2 disposed on the bank pattern BNP may protrude in the third direction DR3 (or the thickness direction of the substrate SUB).

[0187] The embankment pattern BNP may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. In one or more embodiments, the embankment pattern BNP may include an organic layer having a single layer structure and / or an inorganic layer having a single layer structure, but the present disclosure is not limited thereto. In one or more embodiments, the embankment pattern BNP may be provided in the form of a multilayer structure formed by stacking at least one organic insulating layer and at least one inorganic insulating layer. However, the material of the embankment pattern BNP is not limited to the aforementioned embodiments. In one or more embodiments, the embankment pattern BNP may include a conductive material (or conductive substance). The shape of the embankment pattern BNP may be changed in various ways within the range that the efficiency of light emitted from the light emitting element LD can be improved.

[0188] The bank pattern BNP may function as a reflector. For example, the bank pattern BNP together with the first and second alignment electrodes ALE1 and ALE2 disposed thereon may function as a reflector to guide light emitted from the light emitting element LD in a desired direction, thereby improving light output efficiency of the pixel PXL.

[0189] The first alignment electrode ALE1 and the second alignment electrode ALE2 may be positioned on the bank pattern BNP.

[0190] The first and second alignment electrodes ALE1 and ALE2 may be positioned on the pixel circuit layer PCL (or the via layer VIA) and the bank pattern BNP.

[0191] The 2-2nd alignment electrode ALE2_2, the first alignment electrode ALE1, and the 2-1st alignment electrode ALE2_1 may be arranged in one direction (e.g., horizontal direction) intersecting the third direction DR3 in a cross-sectional view. The 2-2nd alignment electrode ALE2_2, the first alignment electrode ALE1, and the 2-1st alignment electrode ALE2_1 may be disposed on the same plane and have the same thickness in the third direction DR3. The 2-2nd alignment electrode ALE2_2, the first alignment electrode ALE1, and the 2-1st alignment electrode ALE2_1 may be formed concurrently (e.g., simultaneously) by the same process, or may be formed continuously.

[0192] The first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed of a material having reflectivity to allow light emitted from the light emitting element LD to travel in an image display direction (or a front direction, e.g., a third direction DR3) of the display device DD. For example, each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed of a conductive material (or substance). The conductive material may include an opaque metal suitable for reflecting light emitted from the light emitting element LD in the image display direction of the display device DD.

[0193] Each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may have a single-layer structure, but is not limited thereto. In one or more embodiments, each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be configured and / or formed as a multilayer structure formed by stacking two or more materials of metals, alloys, conductive oxides, and conductive polymers. Each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be in the form of a multilayer structure configured to include at least two layers to reduce or minimize distortion caused by signal delay when a signal is transmitted to the first end EP1 and the second end EP2 of each of the light emitting elements LD.

[0194] In the case where each of the first and second alignment electrodes ALE1 and ALE2 is formed of a conductive material having reflectivity, light emitted from each of the light emitting elements LD may more reliably travel in the image display direction (eg, third direction DR3 ) of the display device DD.

[0195] The first insulating layer INS1 may be positioned on the first and second alignment electrodes ALE1 and ALE2 .

[0196] The first insulating layer INS1 may be disposed on the first and second alignment electrodes ALE1 and ALE2, the bank pattern BNP, and the via layer VIA. The first insulating layer INS1 may partially have an opening in at least the non-emission area NEA, thereby allowing components disposed thereunder to be exposed. For example, the first insulating layer INS1 may have openings in certain areas corresponding to the first and third contacts CNT1 and CNT3 of the via layer VIA, respectively.

[0197] The first insulating layer INS1 may be formed of an inorganic insulating layer made of an inorganic material, but the present disclosure is not limited thereto. The first insulating layer INS1 may be provided to have a single-layer structure or a multi-layer structure. In the case where the first insulating layer INS1 is provided in the form of a multi-layer structure, the first insulating layer INS1 may have a distributed Bragg reflector structure formed by alternately stacking a first inorganic layer and a second inorganic layer having different refractive indices.

[0198] The first insulating layer INS1 may be disposed throughout the emission area EMA and the non-emission area NEA of each pixel PXL, but the present disclosure is not limited thereto. In one or more embodiments, the first insulating layer INS1 may be disposed in only a specific area of ​​each pixel PXL, for example, in only the emission area EMA.

[0199] The first bank BNK1 may be disposed on the first insulating layer INS1.

[0200] The first bank BNK1 may be disposed on the first insulating layer INS1 in the non-emission area NEA. The first bank BNK1 may be formed between adjacent pixels PXL to enclose the emission area EMA of each pixel PXL, thereby separating (or defining) the emission area EMA of the corresponding pixel PXL. The first bank BNK1 may be surface-treated so that at least one surface thereof has hydrophobicity. For example, the first bank BNK1 may be surface-treated by plasma to have hydrophobicity before the light emitting element LD is aligned, but the present disclosure is not limited thereto.

[0201] The first bank BNK1 and the bank pattern BNP may be formed by different processes and disposed in different layers, but the present disclosure is not limited thereto. In one or more embodiments, the first bank BNK1 and the bank pattern BNP may be formed by different processes and disposed in the same layer, or may be formed by the same process and disposed in the same layer.

[0202] The light emitting element LD may be provided to the emission area EMA of the pixel PXL between the adjacent first banks BNK1 in which the first insulating layer INS1 is formed, and aligned in the emission area EMA of the pixel PXL. For example, the light emitting element LD may be provided to the emission area EMA by an inkjet printing scheme or the like. The light emitting element LD may be aligned between the alignment electrodes ALE on the first insulating layer INS1 by an electric field formed by a signal (or alignment signal) applied to each of the alignment electrodes ALE. For example, the light emitting element LD provided to the emission area EMA may be arranged so that the first end EP1 faces the first alignment electrode ALE1, and the second end EP2 faces the second alignment electrode ALE2.

[0203] The light emitting element LD may include a first light emitting element LD1 and a second light emitting element LD2 .

[0204] The first light emitting element LD1 may be disposed between the right side of the first alignment electrode ALE1 and the 2-1th alignment electrode ALE2_1. The first light emitting element LD1 may include a first end EP1 overlapping the right side of the first alignment electrode ALE1 and a second end EP2 overlapping the 2-1th alignment electrode ALE2_1.

[0205] The second light emitting element LD2 may be disposed between the left side of the first alignment electrode ALE1 and the 2-2nd alignment electrode ALE2_2. The second light emitting element LD2 may include a first end EP1 overlapping the left side of the first alignment electrode ALE1 and a second end EP2 overlapping the 2-2nd alignment electrode ALE2_2.

[0206] The second insulating layer INS2 may be positioned on each of the first light emitting element LD1 and the second light emitting element LD2. The second insulating layer INS2 positioned on each of the first light emitting element LD1 and the second light emitting element LD2 allows the first end EP1 and the second end EP2 of each of the first light emitting element LD1 and the second light emitting element LD2 to be exposed to the outside. The second insulating layer INS2 may be formed on the first insulating layer INS1 in the non-emission area NEA and partially have an opening, thereby allowing some components disposed below to be exposed. For example, the second insulating layer INS2 may be partially opened to include a first contact hole CH1 corresponding to the first opening OPN1 of the passivation layer PSV so that a region of the upper electrode UE (or the first conductive pattern CP1) may be exposed, and may be partially opened to include a second contact hole CH2 corresponding to the third opening OPN3 of the passivation layer PSV so that a region of the second conductive pattern CP2 (or another region of the second power line PL2) may be exposed.

[0207] The second insulating layer INS2 may include an organic insulating layer or an inorganic insulating layer including an inorganic material. For example, the second insulating layer INS2 may include an active layer (refer to Figure 1 The second insulating layer INS2 may be an inorganic insulating layer that is protected from external oxygen, water, and / or the like (“12” in FIG. 1 ). However, the present disclosure is not limited thereto. Depending on the design conditions of the display device DD to which the first light emitting element LD1 and the second light emitting element LD2 are applied, etc., the second insulating layer INS2 may be formed of an organic insulating layer including an organic material. The second insulating layer INS2 may have a single-layer structure or a multi-layer structure.

[0208] The second insulating layer INS2 is formed on the first and second light emitting elements LD1 and LD2 that are completely aligned in the emission area EMA of each pixel PXL, thereby preventing the first and second light emitting elements LD1 and LD2 from being moved from the aligned position.

[0209] Different electrodes among the electrode PE and the intermediate electrode CTE may be formed on the first end EP1 and the second end EP2 of the first light emitting element LD1 and the second light emitting element LD2 that are not covered by the second insulating layer INS2. For example, the first electrode PE1 may be formed on the first end EP1 of the first light emitting element LD1. The intermediate electrode CTE may be formed on the second end EP2 of the first light emitting element LD1. The intermediate electrode CTE may be formed on the first end EP1 of the second light emitting element LD2. The second electrode PE2 may be formed on the second end EP2 of the second light emitting element LD2.

[0210] The first electrode PE1 may be disposed on the first alignment electrode ALE1 to overlap the right side of the first alignment electrode ALE1. The second electrode PE2 may be disposed on the 2-2nd alignment electrode ALE2_2 to overlap the 2-2nd alignment electrode ALE2_2. The intermediate electrode CTE may be disposed on the left side of the first alignment electrode ALE1 and each of the 2-1st alignment electrode ALE2_1.

[0211] In one or more embodiments, the first electrode PE1 may be directly contacted and connected to the upper electrode UE (or the first conductive pattern CP1) through the first contact hole CH1 of the second insulating layer INS2, the first contactor CNT1 of the through-hole layer VIA, and the first opening OPN1 of the passivation layer PSV. The second electrode PE2 may be directly contacted and connected to the second conductive pattern CP2 (or the second power line PL2) through the second contact hole CH2 of the second insulating layer INS2, the third contactor CNT3 of the through-hole layer VIA, and the third opening OPN3 of the passivation layer PSV.

[0212] In one or more embodiments, the first electrode PE1, the intermediate electrode CTE and the second electrode PE2 may be formed in the same layer or in different layers. For example, the relative positions and / or formation order of the first electrode PE1, the intermediate electrode CTE and the second electrode PE2 may be changed in various ways depending on the embodiment.

[0213] exist Figure 7 In one or more embodiments, the first electrode PE1, the intermediate electrode CTE, and the second electrode PE2 may be disposed on the same layer in the display element layer DPL, and may be formed concurrently (e.g., simultaneously) or sequentially. For example, the first electrode PE1 may be positioned adjacent to one side surface of the second insulating layer INS2 on the first light-emitting element LD1. The intermediate electrode CTE may be positioned adjacent to the other side surface of the second insulating layer INS2 on the first light-emitting element LD1. The intermediate electrode CTE may be positioned adjacent to one side surface of the second insulating layer INS2 on the second light-emitting element LD2. The second electrode PE2 may be positioned adjacent to the other side surface of the second insulating layer INS2 on the second light-emitting element LD2. In the case where the electrodes disposed on the first end EP1 and the second end EP2 of each light-emitting element LD are disposed on the same layer and are formed concurrently (e.g., simultaneously), the process of manufacturing the pixel PXL may be facilitated, and the process efficiency may be improved.

[0214] exist Figure 8 In one or more embodiments, an intermediate electrode CTE may be first formed on the second insulating layer INS2. The intermediate electrode CTE may directly contact each of the second end EP2 of the first light emitting element LD1 and the first end EP1 of the second light emitting element LD2, and thus may be connected between the first light emitting element LD1 and the second light emitting element LD2. Thereafter, a third insulating layer INS3 may be formed in the emission region EMA to cover the intermediate electrode CTE.

[0215] The third insulating layer INS3 may be disposed on the intermediate electrode CTE and thus cover the intermediate electrode CTE (or prevent the intermediate electrode CTE from being exposed to the outside), thereby preventing corrosion of the intermediate electrode CTE, etc. The third insulating layer INS3 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. For example, the third insulating layer INS3 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and aluminum oxide (AlO x ), but the present disclosure is not limited thereto. The third insulating layer INS3 may have a single-layer structure or a multi-layer structure.

[0216] A first electrode PE1 and a second electrode PE2 may be formed on the third insulating layer INS3. The first electrode PE1 may directly contact the first end EP1 of the first light emitting element LD1. The second electrode PE2 may directly contact the second end EP2 of the second light emitting element LD2.

[0217] like Figure 8 As shown in the embodiment, when the electrodes provided at the first end EP1 and the second end EP2 of each light emitting element LD are provided on different layers, the electrodes can be reliably electrically separated from each other, thereby preventing a short circuit defect from occurring between the electrodes.

[0218] The first electrode PE1, the second electrode PE2, and the intermediate electrode CTE may be formed of various transparent conductive materials to allow light emitted from each of the light emitting elements LD to travel in an image display direction of the display device DD (e.g., in the third direction DR3) without optical loss. For example, the first electrode PE1, the second electrode PE2, and the intermediate electrode CTE may include a material including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO), and may be substantially transparent or semi-transparent to meet a specific transmittance (or transmittance). The materials of the first electrode PE1, the second electrode PE2 and the intermediate electrode CTE are not limited to those of the aforementioned embodiments.

[0219] In one or more embodiments, at least one overcoat layer (eg, a layer for planarizing the upper surface of the display element layer DPL) may be further disposed throughout the first electrode PE1 , the intermediate electrode CTE, and the second electrode PE2 .

[0220] In one or more embodiments, the display element layer DPL of each pixel PXL may optionally include an optical layer including certain particles that convert light emitted from the light emitting element LD into light having excellent color reproducibility.

[0221] In the following, reference will be made to Fig.10 An example of a pixel PXL including an optical layer is described.

[0222] Fig.10 A pixel PXL according to one or more embodiments is shown and is shown along Figure 5 A schematic cross-sectional view taken along line III-III′.

[0223] about Fig.10 The following description will focus on the differences from the description of the preceding embodiments to avoid redundant explanations.

[0224] refer to Figures 1 to 5 as well as Fig.10 , each pixel PXL may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, a color filter layer CFL, and an encapsulation layer ENC.

[0225] The display element layer DPL may include a color conversion layer CCL positioned on the first electrode PE1, the intermediate electrode CTE, and the second electrode PE2 to correspond to the emission area EMA, and a second bank BNK2 positioned on the first bank BNK1 to correspond to the non-emission area NEA. In addition, the display element layer DPL may include a first capping layer CPL1 disposed on the second bank BNK2 and the color conversion layer CCL.

[0226] The second bank BNK2 may be a dam structure that surrounds the emission area EMA of the pixel PXL and defines the position where the color conversion layer CCL is provided, thereby ultimately defining the emission area EMA. The second bank BNK2 may include a light shielding material. For example, the second bank BNK2 may include at least one light blocking material and / or a reflective material, and allows light emitted from the color conversion layer CCL to reliably travel in the image display direction (e.g., the third direction DR3) of the display device DD, thereby improving the light output efficiency of the color conversion layer CCL.

[0227] The color conversion layer CCL may be formed on the first electrode PE1, the intermediate electrode CTE, and the second electrode PE2 of each pixel PXL in the emission area EMA surrounded by the second bank BNK2. The color conversion layer CCL may include color conversion particles QD corresponding to a specific color. For example, the color conversion layer CCL may include color conversion particles QD that convert light emitted from the light emitting element LD into light of a specific color (or light with excellent color reproducibility).

[0228] In the case where the pixel PXL is a red pixel, the color conversion layer CCL of the pixel PXL may include color conversion particles QD formed of red quantum dots that convert light emitted from the light emitting element LD into red light.

[0229] In the case where the pixel PXL is a green pixel, the color conversion layer CCL of the pixel PXL may include color conversion particles QD formed of green quantum dots that convert light emitted from the light emitting element LD into green light.

[0230] In the case where the pixel PXL is a blue pixel, the color conversion layer CCL of the pixel PXL may include color conversion particles QD formed by blue quantum dots that convert light emitted from the light emitting element LD into blue light. In the case where the pixel PXL is a blue pixel, in one or more embodiments, a light scattering layer having light scattering particles SCT may be provided instead of the color conversion layer CCL including the color conversion particles QD. For example, in the case where the light emitting element LD emits blue-based light, the pixel PXL may include a light scattering layer including light scattering particles SCT. The light scattering layer may be omitted depending on the embodiment. In the case where the pixel PXL is a blue pixel, a transparent polymer may be provided instead of the color conversion layer CCL.

[0231] The first capping layer CPL1 may be disposed in the display area (refer to Figure 3 The first capping layer CPL1 may be an inorganic insulating layer including an inorganic material. The first capping layer CPL1 may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and the like. The first capping layer CPL1 may cover the entirety of the second bank BNK2 and the color conversion layer CCL, and thus prevent external water, oxygen, and / or the like from being introduced into the color conversion layer CCL.

[0232] In one or more embodiments, the first capping layer CPL1 may alleviate a step difference formed by components disposed therebelow and have a flat surface. For example, the first capping layer CPL1 may include an organic insulating layer including an organic material, but the present disclosure is not limited thereto.

[0233] The color filter layer CFL may be disposed on the first capping layer CPL1.

[0234] The color filter layer CFL may include a color filter CF corresponding to the emission area EMA of each pixel PXL. For example, the color filter layer CFL may include a first color filter CF1 disposed on the color conversion layer CCL of one pixel PXL (hereinafter, referred to as a "first pixel"), a second color filter CF2 disposed on the color conversion layer CCL of an adjacent pixel adjacent to the first pixel PXL (hereinafter, referred to as a "second pixel"), and a third color filter CF3 disposed on the color conversion layer CCL of an adjacent pixel adjacent to the second pixel.

[0235] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed in the non-emission area NEA and overlap each other, thereby serving as a light blocking component for preventing optical interference between adjacent pixels PXL. Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a color filter material that allows light of a specific color converted by the corresponding color conversion layer CCL to selectively pass therethrough. For example, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter, but the present disclosure is not limited thereto.

[0236] The encapsulation layer ENC may be disposed on the color filter layer CFL.

[0237] The encapsulation layer ENC may include a second capping layer CPL2. The second capping layer CPL2 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The second capping layer CPL2 may cover the entirety of the components disposed therebelow and prevent external water, moisture, and / or the like from being introduced into the color filter layer CFL. In one or more embodiments, the encapsulation layer ENC may be used as a planarization layer for mitigating step differences caused by components of the color filter layer CFL positioned below the encapsulation layer ENC.

[0238] The second capping layer CPL2 may have a multilayer structure. For example, the second capping layer CPL2 may be formed by at least two inorganic insulating layers and at least one organic insulating layer interposed between the at least two inorganic insulating layers. Here, the constituent material and / or structure of the second capping layer CPL2 may be changed in various ways. In some embodiments, at least one outer coating layer, at least one filling layer and / or at least another substrate may be further disposed on the second capping layer CPL2.

[0239] In the pixel PXL according to the aforementioned embodiment, the color conversion layer CCL and the color filter layer CFL may be disposed on the light emitting element LD through a continuous process so that light having excellent color reproducibility may be emitted through the color conversion layer CCL and the color filter layer CFL, thereby improving light output efficiency.

[0240] In one or more embodiments, the color conversion layer CCL and the color filter layer CFL may be formed on one surface of a substrate (eg, upper substrate) disposed separately from the substrate SUB (eg, lower substrate) through a continuous process and then coupled to the substrate SUB by an adhesive or the like.

[0241] Fig.11A It is along Figure 3 A schematic cross-sectional view taken along line II′. Fig. 11B yes Fig.11ASchematic top view of the pad area PDA.

[0242] refer to Fig.11A and Fig. 11B The description will focus on the differences from the above-mentioned embodiments in order to avoid redundant description.

[0243] refer to Figure 3 , Fig.11A and Fig. 11B , a plurality of pads PD may be disposed in the pad area PDA (or the non-display area NDA).

[0244] Each of the pads PD may include a first pad electrode PDE1 and a second pad electrode PDE2 .

[0245] The first pad electrode PDE1 may be disposed on the interlayer insulating layer ILD. Figures 6 to 10 The first pad electrode PDE1, the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 may be formed by the same process or may be formed by a continuous process and may include the same material.

[0246] The second pad electrode PDE2 may be disposed on the second insulating layer INS2. Figures 6 to 10 The first electrode PE1 and the second electrode PE2 are described in the same layer. The second pad electrode PDE2, the first electrode PE1 and the second electrode PE2 may be formed by the same process or may be formed by a continuous process and may include the same material. The second pad electrode PDE2 may overlap the first pad electrode PDE1 with the passivation layer PSV and the second insulating layer INS2 interposed therebetween.

[0247] The second pad electrode PDE2 may be electrically connected to the first pad electrode PDE1 in such a manner that the second pad electrode PDE2 directly contacts the first pad electrode PDE1 through the fifth opening OPN5 of the passivation layer PSV and the third contact hole CH3 of the second insulating layer INS2. The fifth opening OPN5 of the passivation layer PSV may correspond to the third contact hole CH3 of the second insulating layer INS2. In this case, the opposite side surfaces of the passivation layer PSV between which the fifth opening OPN5 is defined may be positioned on the same line as the opposite side surfaces of the second insulating layer INS2 between which the third contact hole CH3 is defined.

[0248] In one or more embodiments, the dummy pattern DMP may be positioned in the pad area PDA. The dummy pattern DMP may be positioned in the pad area PDA without overlapping each of the pads PD. For example, the dummy pattern DMP may be positioned on the edge of each of the pads PD. In detail, the dummy pattern DMP may be positioned between two adjacent pads PD and disposed adjacent to the outermost pad PD among the pads PD. The dummy pattern DMP may be positioned in the same layer as the through-hole layer VIA in the display area DA and may include the same material as the through-hole layer VIA. The dummy pattern DMP may include a plurality of dummy patterns DMP. Each dummy pattern DMP may have a second height h2 in the third direction DR3. The second height h2 may be different from the first height h1 of each of the pads PD. For example, the second height h2 may be less than the first height h1. If the second height h2 of the dummy pattern DMP is greater than the first height h1 of each of the pads PD, the second pad electrode PDE2 may not adhere to the conductive adhesive assembly, thereby causing contact failure between the second pad electrode PDE2 and the conductive adhesive assembly.

[0249] The pad PD may be bonded to the conductive adhesive component by an external lead bonding (OLB) process. Therefore, the pad PD may be electrically connected to an external circuit substrate by the conductive adhesive component. The conductive adhesive component may be, for example, an anisotropic conductive film including conductive balls formed in an adhesive film having adhesive properties. In the OLB process, the conductive balls of the conductive adhesive component and the second pad electrode PDE2 of each of the pads PD may be bonded together under pressure applied thereto. Here, depending on factors such as the magnitude of the applied pressure and / or the material properties of the components positioned in the pad area PDA, crack defects may occur in the pad area PDA. The dummy pattern DMP may be provided to reduce or prevent the direct influence of the pressure applied during the OLB process on the components such as the second pad electrode PDE2 positioned in the pad area PDA and the inorganic insulating layer formed by the inorganic material. In one or more embodiments, the dummy pattern DMP may disperse or absorb some of the pressure applied during the OLB process, thereby reducing or minimizing the crack defects in the pad area PDA. If the crack defects are reduced or minimized, the reliability of the display device DD may be improved.

[0250] In the following, reference will be made to Figures 12 to 18 A method of manufacturing a display device DD according to one or more embodiments is described.

[0251] Figures 12 to 18 It is used to describe the manufacturing Fig. 9 and Fig.11A Schematic cross-sectional view of a method of displaying a display device DD shown in FIG.

[0252] exist Figures 12 to 18 In one or more embodiments, the steps of manufacturing the display device DD are shown to be performed sequentially according to the cross-sectional view, but without changing the technical scope of the present disclosure, some steps shown to be performed continuously may be performed concurrently (e.g., simultaneously), the order of the steps may be changed, some steps may be skipped, or additional steps may be included between the steps.

[0253] refer to Figures 12 to 18 The description will focus on the differences from the above-mentioned embodiments in order to avoid redundant description.

[0254] refer to Figures 1 to 12 In the display area DA (or pixel area PXA), first and second bottom metal patterns BML1 and BML2, transistors T, second power lines PL2, and first, second, and third conductive patterns CP1, CP2, and CP3 are formed on the substrate SUB. In the pad area PDA (or non-display area NDA), a first pad electrode PDE1 is formed on the substrate SUB.

[0255] A passivation layer PSV is formed on the transistor T, the first, second and third conductive patterns CP1, CP2 and CP3, and the first pad electrode PDE1. A via material layer VIAM is formed on the passivation layer PSV.

[0256] The via material layer VIAM may have a flat (or uniform) upper surface regardless of the region, but may have different thicknesses in different regions (eg, in the third direction DR3). Fig.12 As shown in, the thickness t1 of the via material layer VIAM on the second conductive pattern CP2 may be less than the thickness t2 of the via material layer VIAM on the first pad electrode PDE1 and the thickness t2 of the via material layer VIAM on the third conductive pattern CP3. This is because the second conductive pattern CP2 overlaps with the second bottom metal pattern BML2 positioned below, forming a step difference of the same thickness as the thickness of the second bottom metal pattern BML2, whereby the surface (or upper surface) of the second conductive pattern CP2 is positioned closer to the upper surface of the via material layer VIAM than the first pad electrode PDE1 and the third conductive pattern CP3.

[0257] A photoresist is deposited on the via material layer VIAM, and a mask M is placed thereon. The mask M may include a halftone mask capable of adjusting the light transmittance for each region. The mask M may include a first portion A, a second portion B, a third portion C, and a fourth portion D. The first portion A may be a transparent portion that completely transmits light. The second portion B may be a blocking portion that completely blocks light. The third portion C may be a semi-transparent portion with an adjusted light transmittance. The fourth portion D may be a slit pattern portion having a higher light transmittance than the third portion C. In one or more embodiments, the fourth portion D may include two or more slit patterns SLP.

[0258] refer to Figures 1 to 13 , a photolithography process using a mask M may be performed to form a second contact (reference Figure 6 ' CNT2 ' in the figure), the fourth contactor CNT4, the through hole pattern VIP of the first step portion HM1 and the second step portion HM2.

[0259] Each of the second and fourth contacts CNT2 and CNT4 may correspond to the first portion A of the mask M. The first step portion HM1 may correspond to the third portion C of the mask M. The second step portion HM2 may correspond to the fourth portion D of the mask M. The remaining area of ​​the via pattern VIP except for the second and fourth contacts CNT2 and CNT4, the first step portion HM1, and the second step portion HM2 may correspond to the second portion B of the mask M.

[0260] The second contactor CNT2 may expose the passivation layer PSV on the second power line PL2. The fourth contactor CNT4 may expose the passivation layer PSV on the third conductive pattern CP3. The first step portion HM1 may be placed on the passivation layer PSV on the second conductive pattern CP2, which is positioned above the second bottom metal pattern BML2 and overlaps the second bottom metal pattern BML2 in the third direction DR3. The second step portion HM2 may be placed on the passivation layer PSV on the first pad electrode PDE1.

[0261] The thickness d1 (hereinafter, referred to as the "first thickness") of the via pattern VIP in the first step portion HM1 may be the same as the thickness d2 (hereinafter, referred to as the "second thickness") of the via pattern VIP in the second step portion HM2. In other words, the remainder of the via material layer VIAM on the passivation layer PSV positioned on the second conductive pattern CP2 overlapping the second bottom metal pattern BML2 may be the same as the remainder of the via material layer VIAM on the passivation layer PSV positioned on the first pad electrode PDE1. By adjusting the distance between the slit patterns SLP provided in the fourth portion D of the mask M and the number of the slit patterns SLP, the first thickness d1 (or the thickness of the remainder of the via material layer VIAM on the second conductive pattern CP2) and the second thickness d2 (or the thickness of the remainder of the via material layer VIAM on the first pad electrode PDE1) may be made the same.

[0262] Although directly illustrated in the drawings, the first stepped portion HM1 of the via hole pattern VIP may be positioned on the passivation layer PSV on the first conductive pattern CP1 positioned on the first bottom metal pattern (refer to FIG. 1 ) in the display area DA. Figure 6 'BML1' in FIG. 1 and overlaps the first bottom metal pattern BML1.

[0263] refer to Figures 1 to 14 During the dry etching process, a fourth opening OPN4 corresponding to the fourth contact CNT4 is formed in the passivation layer PSV, thereby exposing a region of the third conductive pattern CP3 positioned below. In addition, during the dry etching process, a second opening OPN2 corresponding to the second contact CNT2 is formed in the passivation layer PSV, thereby exposing a region of the second power line PL2 positioned below.

[0264] During the dry etching process, the passivation layer PSV may be partially removed to include the second opening OPN2 and the fourth opening OPN4 .

[0265] After the dry etching process, a bank pattern is formed in the display area DA on the via hole pattern VIP (refer to Figure 6 The bank pattern BNP may be formed of an organic insulating substance including an organic material.

[0266] During the process of forming the bank pattern BNP, a portion of the via pattern VIP may be removed. Therefore, an upper surface of the first stepped portion HM1 may be located closer to the passivation layer PSV. An upper surface of the second stepped portion HM2 may be located closer to the passivation layer PSV.

[0267] refer to Figures 1 to 15, a first alignment electrode ALE1 and a second alignment electrode (reference Figure 6 2 in the .

[0268] The first alignment electrode ALE1 may contact the third conductive pattern CP3 exposed by the fourth contact CNT4 and the fourth opening OPN4 and thus may be electrically connected to the third conductive pattern CP3. The third conductive pattern CP3 may be the first power line PL1.

[0269] The second alignment electrode ALE2 may contact the second power line PL2 exposed through the second contact CNT2 and the second opening OPN2 , and thus may be electrically connected to the second power line PL2 .

[0270] refer to Figures 1 to 16 , after applying an insulating material layer to the entire surfaces of the first alignment electrode ALE1, the second alignment electrode ALE2, the bank pattern BNP, and the via pattern VIP, a photolithography process is performed to form a first insulating layer INS1 partially opened to expose some components positioned therebelow.

[0271] The first insulating layer INS1 may partially have an opening in the display area DA to expose the first step portion HM1. In addition, the first insulating layer INS1 may have an opening in the pad area PDA to expose the entirety of the via pattern VIP. In other words, the first insulating layer INS1 may not be provided (or may be omitted) in the pad area PDA.

[0272] refer to Figures 1 to 17 , an ashing process using oxygen plasma is performed to completely remove the first stepped portion HM1 from the display area DA, thereby forming a first contact including exposing the passivation layer PSV positioned under the first stepped portion HM1 (refer to Figure 6 “CNT1” in the figure) and the through-hole layer VIA of the third contactor CNT3.

[0273] During the ashing process, the second stepped portion HM2 is completely removed from the pad area PDA, thereby exposing the passivation layer PSV positioned thereunder. In addition, a portion of the via pattern VIP positioned between the first pad electrodes PDE1 in the pad area PDA is removed, thereby forming a dummy pattern DMP.

[0274] The via layer VIA in the pixel area PXA and the dummy pattern DMP in the pad area PDA may include the same material, and may be formed through the same process and disposed in the same layer.

[0275] If the thickness of the first step portion HM1 of the through hole pattern VIP (or the remainder of the through hole pattern VIP on the second conductive pattern CP2) and the thickness of the second step portion HM2 of the through hole pattern VIP (or the remainder of the through hole pattern VIP on the first pad electrode PDE1) are the same, the first step portion HM1 and the second step portion HM2 may be removed concurrently (e.g., simultaneously) by an ashing process. As a result, the passivation layer PSV on the second conductive pattern CP2 and the passivation layer PSV on the first pad electrode PDE1 may be exposed to the outside. If the thickness of the first step portion HM1 of the through hole pattern VIP and the thickness of the second step portion HM2 of the through hole pattern VIP are different from each other, the first step portion HM1 and the second step portion HM2 may not be removed concurrently (e.g., simultaneously) by an ashing process, and at least one of the first step portion HM1 and the second step portion HM2 may be maintained, preventing the passivation layer PSV positioned below from being exposed to the outside. For example, in the case where the second step portion HM2 of the via hole pattern VIP is not completely removed and remains so as to prevent the passivation layer PSV positioned thereunder from being exposed to the outside, when forming the second insulating layer (refer to Figure 6 During a subsequent process of the first pad electrode PDE1 (hereinafter referred to as "INS2"), there may be a contact failure in the pad area PDA because the first pad electrode PDE1 is not exposed to the outside. Taking this into account, in the aforementioned embodiment, a mask M as a halftone mask including a third portion C formed of a semi-transparent portion and a fourth portion D having a slit pattern SLP may be used to make the thickness of the first step portion HM1 of the through hole pattern VIP and the thickness of the second step portion HM2 of the through hole pattern VIP the same, so that the first step portion HM1 and the second step portion HM2 can be removed concurrently (e.g., simultaneously) during the ashing process.

[0276] After the ashing process, a first bank is formed in the display area DA (refer to Figure 6 ”BNK1” in the figure), and provide corresponding signals (for example, alignment signals) to the first alignment electrode ALE1 and the second alignment electrode ALE2, respectively, so as to form an electric field between the first alignment electrode ALE1 and the second alignment electrode ALE2. In the state where the electric field is formed, a method such as inkjet printing is used to print the light emitting element (reference Figure 5 The ink of the ink ("LD" in the figure) is input into the display area DA. The light emitting element LD is aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2. After the light emitting element LD is self-aligned, the solvent included in the ink may be removed by a volatilization scheme or other schemes.

[0277] refer to Figures 1 to 18After applying an insulating material layer to the entire surfaces of the light emitting element LD, the first bank BNK1, the first insulating layer INS1, the passivation layer PSV, and the dummy pattern DMP, a photolithography process is performed to form a second insulating layer INS2 partially opened to expose some components positioned therebelow.

[0278] The second insulating layer INS2 may partially have an opening to include a second contact hole CH2 exposing a region of the passivation layer PSV overlapping with and exposed through the third contact CNT3. The second insulating layer INS2 may partially have an opening to include a first contact hole CH1 exposing a region of the passivation layer PSV overlapping with and exposed through the first contact CNT1 of the via layer VIA. The second insulating layer INS2 may partially have an opening in the pixel region PXA to expose the emission region (refer to Figure 6 The second insulating layer INS2 may partially have an opening in the pad area PDA to include a third contact hole CH3 exposing a region of the passivation layer PSV on the first pad electrode PDE1.

[0279] During the process of forming the second insulating layer INS2, a first opening OPN1 of the passivation layer PSV is formed by removing a region of the passivation layer PSV exposed through the first contact hole CH1 of the second insulating layer INS2, a third opening OPN3 of the passivation layer PSV is formed by removing a region of the passivation layer PSV exposed through the second contact hole CH2 of the second insulating layer INS2, and a fifth opening OPN5 of the passivation layer PSV is formed by removing a region of the passivation layer PSV exposed through the third contact hole CH3 of the second insulating layer INS2.

[0280] In other words, during the process of forming the second insulating layer INS2, the passivation layer PSV may partially have openings to include the first opening OPN1, the third opening OPN3, and the fifth opening OPN5. A region of the first conductive pattern CP1 may be exposed to the outside through the first opening OPN1 of the passivation layer PSV. A region of the second conductive pattern CP2 may be exposed to the outside through the third opening OPN3 of the passivation layer PSV. A region of the first pad electrode PDE1 may be exposed to the outside through the fifth opening OPN5 of the passivation layer PSV.

[0281] After forming the second insulating layer INS2, a first electrode (refer to Figure 6 "PE1" in the figure), the second electrode (reference Figure 6"PE2" in the reference Figure 6 ” CTE” in the pad area PDA), and a second pad electrode PDE2 may be formed in the pad area PDA.

[0282] The first electrode PE1 may be electrically connected to the first conductive pattern CP1 (or the upper electrode UE) in such a manner that the first electrode PE1 contacts the first conductive pattern CP1 (or the upper electrode UE) through the first contact hole CH1 of the second insulating layer INS2 , the first contact CNT1 of the via layer VIA, and the first opening OPN1 of the passivation layer PSV.

[0283] The second electrode PE2 may be electrically connected to the second conductive pattern CP2 in such a manner that the second electrode PE2 contacts the second conductive pattern CP2 through the second contact hole CH2 of the second insulating layer INS2, the third contact CNT3 of the via layer VIA, and the third opening OPN3 of the passivation layer PSV.

[0284] The second pad electrode PDE2 may be electrically connected to the first pad electrode PDE1 in such a manner that the second pad electrode PDE2 contacts the first pad electrode PDE1 through the third contact hole CH3 of the second insulating layer INS2 and the fifth opening OPN5 of the passivation layer PSV.

[0285] Fig.19A It is along Figure 3 A schematic cross-sectional view taken along line II′. Fig.19B yes Fig.19A Schematic top view of the pad area PDA.

[0286] refer to Fig.19A and Fig.19B The description will focus on the differences from the above-mentioned embodiments in order to avoid redundant description.

[0287] refer to Figure 3 , Fig.19A and Fig.19B , a plurality of pads PD may be disposed in the pad area PDA (or the non-display area NDA).

[0288] Each of the pads PD may include a first pad electrode PDE1 and a second pad electrode PDE2. The first pad electrode PDE1 may be disposed on the interlayer insulating layer ILD. The second pad electrode PDE2 may be disposed on the second insulating layer INS2. The second pad electrode PDE2 may be electrically connected to the first pad electrode PDE1 in such a manner that the second pad electrode PDE2 directly contacts the first pad electrode PDE1 through the fifth opening OPN5 of the passivation layer PSV and the third contact hole CH3 of the second insulating layer INS2.

[0289] The dummy pattern DMP may be positioned in the pad area PDA.The dummy pattern DMP may be positioned on the first pad electrode PDE1 of each of the pads PD and overlap the first pad electrode PDE1 in the third direction DR3.

[0290] In one or more embodiments, the dummy pattern DMP may include a first layer FL, a second layer SL, and a third layer TL that are sequentially stacked in the third direction DR3 from one surface of the first pad electrode PDE1. The first layer FL may be positioned in the same layer as the passivation layer PSV and may include the same material as the passivation layer PSV. The second layer SL may be positioned in the same layer as the display area DA (or pixel area, refer to Figure 6 The third layer TL may be located in the same layer as the first insulating layer (referenced as “PXA” in FIG. 1 ) and may include the same material as the via layer VIA. Figure 6 ” INS1 ” in the same layer as the first insulating layer INS1 and may include the same material as the first insulating layer INS1.

[0291] The dummy pattern DMP may include a plurality of dummy patterns DMP. Each dummy pattern DMP may be positioned on the first pad electrode PDE1 and overlap the first pad electrode PDE1. The dummy pattern DMP may reduce or minimize arc defects that occur when charges are concentrated on the first pad electrode PDE1 that is mostly (e.g., widely) exposed to the outside during a process of forming the third contact hole CH3 in the second insulating layer INS2. If the arc defects on the first pad electrode PDE1 are reduced or minimized, the reliability of the display device DD may be enhanced.

[0292] In one or more embodiments, the second pad electrode PDE2 may be disposed on the dummy pattern DMP and a contact portion of the first pad electrode PDE1 that does not overlap the dummy pattern DMP, thereby being electrically connected to the first pad electrode PDE1.

[0293] In the following, reference will be made to Figure 20 to Figure 26 Describes a method for manufacturing a display device according to one or more embodiments (refer to Figure 3 The method of "DD" in .

[0294] Figure 20 to Figure 26 It is used to describe the manufacturing Fig. 9 and Fig.19A Schematic cross-sectional view of a method of displaying a display device DD shown in FIG.

[0295] refer to Figure 20 to Figure 26 The description will focus on the differences from the above-mentioned embodiments in order to avoid redundant description.

[0296] refer to Figures 1 to 9 as well as FIG. 19A to FIG. 20 In the display area DA (or pixel area PXA), first and second bottom metal patterns BML1 and BML2, transistors T, second power lines PL2, and first to third conductive patterns CP1 to CP3 are formed on the substrate SUB. In the pad area PDA (or non-display area NDA), a first pad electrode PDE1 is formed on the substrate SUB.

[0297] A passivation layer PSV and a via material layer VIAM are continuously formed on the transistor T, the first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3, and the first pad electrode PDE1. The via material layer VIAM may have a flat (or uniform) upper surface regardless of the region, but may have different thicknesses in different regions (for example, in the third direction DR3).

[0298] A photoresist is deposited on the via material layer VIAM, and a mask M is placed thereon. The mask M may include a halftone mask capable of adjusting the light transmittance for each region. The mask M may include a first portion A, a second portion B, a third portion C, and a fourth portion D. The first portion A may be a transparent portion that completely transmits light. The second portion B may be a blocking portion that completely blocks light. The third portion C may be a semi-transparent portion with an adjusted light transmittance. The fourth portion D may be a slit pattern portion having a higher light transmittance than the third portion C. In one or more embodiments, the fourth portion D may include two or more slit patterns SLP. The fourth portion D may be positioned in the pad area PDA to correspond to both the via material layer VIAM on the first pad electrode PDE1 and the via material layer VIAM in the region between the first pad electrode PDE1.

[0299] In one or more embodiments, the distance between the slit patterns SLP (hereinafter, referred to as "first slit patterns") corresponding to the via material layer VIAM on the first pad electrode PDE1 may be different from the distance between the slit patterns SLP (hereinafter, referred to as "second slit patterns") corresponding to the via material layer VIAM in the region between the first pad electrodes PDE1. For example, the distance between the first slit patterns SLP may be greater than the distance between the second slit patterns SLP. Because the distances between the slit patterns SLP of the mask M in the pad area PDA are different from each other, the via material layer VIAM positioned in the pad area PDA may have different thicknesses during subsequent processes.

[0300] refer to Figures 1 to 9 as well as FIG. 19A to FIG. 21 , a photolithography process using a mask M may be performed to form a second contact (reference Figure 6' CNT2 ' in ), the fourth contactor CNT4 , the first step portion HM1 , the second step portion HM2 , and the through hole pattern VIP of the protrusion pattern PRP.

[0301] Each of the second and fourth contacts CNT2 and CNT4 may correspond to the first portion A of the mask M. The first step portion HM1 may correspond to the third portion C of the mask M. The second step portion HM2 and the protrusion pattern PRP may correspond to the fourth portion D of the mask M. The remaining area of ​​the via pattern VIP except the second and fourth contacts CNT2 and CNT4, the first step portion HM1, the second step portion HM2, and the protrusion pattern PRP may correspond to the second portion B of the mask M.

[0302] The second contactor CNT2 may expose the passivation layer PSV on the second power line PL2. The fourth contactor CNT4 may expose the passivation layer PSV on the third conductive pattern CP3. The first step portion HM1 may be placed on the passivation layer PSV on the second conductive pattern CP2, which is positioned above and overlaps the second bottom metal pattern BML2. The protrusion pattern PRP may be positioned on the passivation layer PSV on a portion of the first pad electrode PDE1 in the pad area PDA. The second step portion HM2 may be positioned between the protrusion patterns PRP in the pad area PDA and positioned on the passivation layer PSV on the remaining portion of the first pad electrode PDE1.

[0303] The thickness d1 of the via pattern VIP in the first step portion HM1 may be the same as the thickness d2 of the via pattern VIP in the second step portion HM2. In other words, the thickness of the remainder of the via material layer VIAM on the passivation layer PSV positioned on the second conductive pattern CP2 overlapping the second bottom metal pattern BML2 may be the same as the thickness of the remainder of the via material layer VIAM on the passivation layer PSV positioned on the remainder of the first pad electrode PDE1 in the pad area PDA.

[0304] refer to Figures 1 to 9 as well as FIG. 19A to FIG. 22 During the dry etching process, a fourth opening OPN4 corresponding to the fourth contact CNT4 is formed in the passivation layer PSV, thereby exposing a region of the third conductive pattern CP3 positioned below. In addition, during the dry etching process, a second opening OPN2 corresponding to the second contact CNT2 is formed in the passivation layer PSV, thereby exposing a region of the second power line PL2 positioned below.

[0305] After the dry etching process, a bank pattern is formed on the via hole pattern VIP in the display area DA (refer to Figure 6in the literature).

[0306] During the process of forming the bank pattern BNP, a portion of the via pattern VIP may be removed. As a result, an upper surface of each of the first stepped portion HM1, the second stepped portion HM2, and the protrusion pattern PRP may be positioned closer to the passivation layer PSV.

[0307] refer to Figures 1 to 9 as well as FIG. 19A to FIG. 23 , a first alignment electrode ALE1 and a second alignment electrode (reference Figure 6 2 in the .

[0308] The first alignment electrode ALE1 may contact the third conductive pattern CP3 exposed by the fourth contact CNT4 and the fourth opening OPN4 and thus be electrically connected to the third conductive pattern CP3.

[0309] The second alignment electrode ALE2 may contact the second power line PL2 exposed through the second contact CNT2 and the second opening OPN2 , and thus be electrically connected to the second power line PL2 .

[0310] refer to Figures 1 to 9 as well as FIG. 19A to FIG. 24 , after applying an insulating material layer to the entire surfaces of the first alignment electrode ALE1, the second alignment electrode ALE2, the bank pattern BNP, and the via pattern VIP, a photolithography process is performed to form a first insulating layer INS1 and a third layer TL partially opened to expose some components positioned therebelow.

[0311] The first insulating layer INS1 may partially have an opening in the display area DA to expose the first stepped portion HM1. The third layer TL may be disposed on the protrusion pattern PRP in the pad area PDA. The first insulating layer INS1 and the third layer TL may include the same material and may be formed by the same process.

[0312] refer to Figures 1 to 9 as well as FIG. 19A to FIG. 25 , an ashing process using oxygen plasma is performed to completely remove the first stepped portion HM1 from the display area DA, thereby forming a first contact including exposing the passivation layer PSV positioned under the first stepped portion HM1 (refer to Figure 6 “CNT1” in the figure) and the through-hole layer VIA of the third contactor CNT3.

[0313] During the ashing process, a portion of the via pattern VIP in the pad area PDA that does not overlap the third layer TL is completely removed, thereby allowing the passivation layer PSV positioned below to be exposed. During the ashing process, a portion of the protrusion pattern PRP positioned below and overlapping the third layer TL may remain on the passivation layer PSV instead of being removed, thereby forming the second layer SL. The second layer SL may include the same material as the via layer VIA and may be formed in the same layer by the same process as the via layer VIA.

[0314] After the ashing process, a first bank is formed in the display area DA (refer to Figure 6 ”BNK1” in the figure), and provide corresponding signals (for example, alignment signals) to the first alignment electrode ALE1 and the second alignment electrode ALE2, respectively, so as to form an electric field between the first alignment electrode ALE1 and the second alignment electrode ALE2. In the state where the electric field is formed, the light emitting element (reference Figure 5 The ink of the ink ("LD" in the figure) is input into the display area DA. The light emitting element LD is aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2. After the light emitting element LD is self-aligned, the solvent included in the ink may be removed by a volatilization scheme or other schemes.

[0315] refer to Figures 1 to 9 as well as FIG. 19A to FIG. 26 After applying an insulating material layer to the entire surface of the light emitting element LD, the first bank BNK1, the first insulating layer INS1, the passivation layer PSV and the second layer SL, a photolithography process is performed to form a second insulating layer INS2 partially opened to expose some components positioned therebelow.

[0316] The second insulating layer INS2 may partially have an opening to include a second contact hole CH2 exposing a region of the passivation layer PSV overlapping with and exposed through the third contact CNT3. The second insulating layer INS2 may partially have an opening to include a first contact hole CH1 exposing a region of the passivation layer PSV overlapping with and exposed through the first contact CNT1. The second insulating layer INS2 may partially have an opening in the pixel area PXA to expose the emission area (refer to Figure 6 The second insulating layer INS2 may partially have an opening to include a third contact hole CH3 exposing a region of the passivation layer PSV on the first pad electrode PDE1 in the pad area PDA.

[0317] During the process of forming the second insulating layer INS2, a first opening OPN1 of the passivation layer PSV is formed by removing a region of the passivation layer PSV exposed by the first contact hole CH1 of the second insulating layer INS2, a third opening OPN3 of the passivation layer PSV is formed by removing a region of the passivation layer PSV exposed by the second contact hole CH2 of the second insulating layer INS2, and a fifth opening OPN5 of the passivation layer PSV is formed by removing a region of the passivation layer PSV exposed by the third contact hole CH3 of the second insulating layer INS2.

[0318] During the process of forming the second insulating layer INS2, the passivation layer PSV may partially have openings to include a first opening OPN1, a third opening OPN3, and a fifth opening OPN5. A region of the first conductive pattern CP1 (or the upper electrode UE) may be exposed to the outside through the first opening OPN1 of the passivation layer PSV. A region of the second conductive pattern CP2 may be exposed to the outside through the third opening OPN3 of the passivation layer PSV. A region of the first pad electrode PDE1 may be exposed to the outside through the fifth opening OPN5 of the passivation layer PSV.

[0319] In addition, during the process of forming the second insulating layer INS2, a region of the passivation layer PSV positioned below and overlapping the second layer SL may be retained to form the first layer FL. The first layer FL may be positioned on the first pad electrode PDE1 in the pad area PDA. The first layer FL may include the same material as the passivation layer PSV and may be disposed in the same layer as the passivation layer PSV.

[0320] In the pad area PDA, the first layer FL, the second layer SL, and the third layer TL continuously stacked in the third direction DR3 from one surface of the first pad electrode PDE1 may form a dummy pattern DMP. The dummy pattern DMP may partially overlap the first pad electrode PDE1, and reduce or minimize an arc defect occurring on the first pad electrode PDE1 that is mostly (widely) exposed to the outside during a process of forming the third contact hole CH3 in the second insulating layer INS2.

[0321] In one or more embodiments, a dummy pattern is disposed in a pad region, thereby reducing or minimizing crack defects occurring during an outer lead bonding (OLB) process of bonding a pad electrode and a conductive adhesive member (or anisotropic conductive film), thereby improving reliability of a display device.

[0322] In one or more embodiments, the dummy pattern is arranged to overlap with an area of ​​the pad electrode, thereby reducing the surface area of ​​the pad electrode exposed to the outside, thereby reducing or minimizing arc defects caused by charges concentrated on the exposed portion of the pad electrode. As a result, the reliability of the display device can be further improved.

[0323] In one or more embodiments, a method of manufacturing a display device may be provided.

[0324] The effects, aspects, and features of the present disclosure are not limited to the foregoing, and other various effects, aspects, and features are contemplated herein.

[0325] While various embodiments have been described above, those skilled in the art will appreciate that various modifications, additions, and substitutions are possible, without departing from the scope of the present disclosure.

[0326] Therefore, the embodiments disclosed in this specification are for illustrative purposes only, rather than limiting the scope of the present disclosure, which must be defined by the appended claims.

Claims

1. A display device, comprising: A substrate, comprising a display area and a non-display area, wherein the non-display area comprises a pad area; transistors and conductive patterns on the substrate in the display region; a through-hole layer on the transistor and the conductive pattern to cover the transistor and the conductive pattern; a first alignment electrode and a second alignment electrode on the via layer and spaced apart from each other; a light emitting element between the first alignment electrode and the second alignment electrode; a first electrode and a second electrode spaced apart from each other and electrically connected to the light emitting element; a plurality of pads on the substrate in the pad region; as well as a dummy pattern on the substrate in the pad region and spaced apart from the plurality of pads, Wherein, the through hole layer and the dummy pattern include the same material.

2. The display device according to claim 1, wherein: The via layer and the dummy pattern are in the same layer.

3. The display device according to claim 2, wherein: The dummy pattern is adjacent to an edge of each of the plurality of pads.

4. The display device according to claim 3, wherein: The dummy pattern is between two adjacent pads among the plurality of pads.

5. The display device according to claim 2, further comprising: a passivation layer located between the substrate and the through-hole layer in the display region, and between the substrate and the dummy pattern in the pad region; a first insulating layer, located on the through-hole layer in the display area; as well as A second insulating layer is located on the first insulating layer in the display region and on the dummy pattern and the passivation layer in the pad region.

6. The display device according to claim 5, wherein: A height of each of the plurality of pads in a thickness direction of the substrate is different from a height of the dummy pattern in the thickness direction of the substrate.

7. The display device according to claim 6, wherein: The height of each of the plurality of pads is greater than the height of the dummy pattern.

8. The display device according to claim 5, wherein: Each of the plurality of pads comprises: a first pad electrode on the substrate; and a second pad electrode on and electrically connected to the first pad electrode, wherein the first pad electrode is in the same layer as the conductive pattern, and The second pad electrode is in the same layer as at least one of the first electrode and the second electrode.

9. The display device according to claim 8, in, The conductive pattern includes a first conductive pattern, a second conductive pattern, and a third conductive pattern spaced apart from each other between the substrate and the passivation layer, wherein the first conductive pattern includes an electrode of a storage capacitor electrically connected to the transistor, wherein the second conductive pattern includes a second power line to which a voltage of a second driving power source is to be applied, and The third conductive pattern includes a first power line to which a voltage of a first driving power source different from the second driving power source is applied.

10. The display device according to claim 9, in, The passivation layer includes a first opening exposing a region of the first conductive pattern, a second opening exposing a first region of the second conductive pattern, a third opening exposing a second region of the second conductive pattern, a fourth opening exposing a region of the third conductive pattern, and a fifth opening exposing a portion of the first pad electrode, wherein the through-hole layer includes a first contact exposing the one region of the first conductive pattern, a second contact exposing the first region of the second conductive pattern, a third contact exposing the second region of the second conductive pattern, and a fourth contact exposing the one region of the third conductive pattern, and The second insulating layer includes a first contact hole exposing the one region of the first conductive pattern, a second contact hole exposing the second region of the second conductive pattern, and a third contact hole exposing the portion of the first pad electrode.

11. The display device according to claim 10, in, The first alignment electrode contacts the one region of the third conductive pattern through the fourth contactor and the fourth opening and is electrically connected to the third conductive pattern, and The second alignment electrode contacts the first region of the second conductive pattern through the second contactor and the second opening, and is electrically connected to the second conductive pattern.

12. The display device according to claim 11, in, The first electrode directly contacts the one region of the first conductive pattern through the first contact hole, the first contactor, and the first opening, and is electrically connected to the first conductive pattern, and The second electrode directly contacts the second region of the second conductive pattern through the second contact hole, the third contactor, and the third opening, and is electrically connected to the second conductive pattern.

13. The display device according to claim 12, in, The light emitting element includes a first end electrically connected to the first electrode and a second end electrically connected to the second electrode, and The light emitting element further includes a P-type semiconductor layer on the first end, an N-type semiconductor layer on the second end, and an active layer between the P-type semiconductor layer and the N-type semiconductor layer.

14. The display device according to claim 1, further comprising: a color conversion layer on the light emitting element and configured to change the wavelength of light emitted from the light emitting element; as well as A color filter is on the color conversion layer.

15. A display device, comprising: A substrate, comprising a display area and a non-display area, wherein the non-display area comprises a pad area; transistors and conductive patterns on the substrate in the display region; a through-hole layer on the transistor and the conductive pattern to cover the transistor and the conductive pattern; a first alignment electrode and a second alignment electrode on the via layer and spaced apart from each other; a light emitting element between the first alignment electrode and the second alignment electrode; a first electrode and a second electrode spaced apart from each other and electrically connected to the light emitting element; a plurality of pads on the substrate in the pad region; as well as a dummy pattern on the substrate in the pad region and overlapping each of the plurality of pads, The dummy pattern includes a first layer, a second layer and a third layer stacked continuously, and Wherein, at least one of the first layer, the second layer and the third layer includes the same material as the via layer.

16. The display device according to claim 15, further comprising: an interlayer insulating layer located between the substrate and the conductive pattern in the display area and between the substrate and the pad in the pad area; a passivation layer on the interlayer insulating layer; a first insulating layer, located on the through-hole layer in the display area; as well as a second insulating layer, located on the first insulating layer in the display area and on the passivation layer in the pad area, Wherein, the first layer is in the same layer as the passivation layer, the second layer is in the same layer as the via layer, and the third layer is in the same layer as the first insulating layer.

17. The display device according to claim 16, wherein: The first layer includes the same material as the passivation layer, the second layer includes the same material as the via layer, and the third layer includes the same material as the first insulating layer.

18. The display device according to claim 16, wherein: Each of the plurality of pads comprises: a first pad electrode on the interlayer insulating layer; and a second pad electrode on the first pad electrode and the dummy pattern and electrically connected to the first pad electrode, wherein the first pad electrode is in the same layer as the conductive pattern, and The second pad electrode is in the same layer as at least one of the first electrode and the second electrode.

19. A method for manufacturing a display device, comprising: forming a first conductive pattern, a second conductive pattern, a third conductive pattern and a first pad electrode on a substrate including a display area and a non-display area, and forming a passivation layer on the first conductive pattern, the second conductive pattern, the third conductive pattern and the first pad electrode, the non-display area including the pad area; forming a via pattern by depositing a via material layer on the passivation layer, setting a mask on the via material layer, and performing a photolithography process, the via pattern comprising a contact exposing an area of ​​the passivation layer on the third conductive pattern, a first step portion corresponding to the second conductive pattern, and a second step portion corresponding to the first pad electrode; exposing a portion of the third conductive pattern by removing the one region of the passivation layer through a dry etching process; forming a first alignment electrode and a second alignment electrode spaced apart from each other on the through hole pattern in the display region; forming a first insulating layer patterned to expose the first step portion on the through hole pattern and the first and second alignment electrodes in the display area; forming a through-hole layer by removing the first step portion in the display area through an ashing process to expose a portion of the passivation layer under the first step portion, and exposing a portion of the passivation layer under the second step portion and forming a dummy pattern by removing the second step portion in the pad area through the ashing process; aligning a light emitting element between the first alignment electrode and the second alignment electrode in the display area; forming a second insulating layer on the first insulating layer in the display area and the passivation layer in the non-display area; as well as A first electrode and a second electrode electrically connected to the light emitting element are formed in the display region, and a second pad electrode electrically connected to the first pad electrode is formed in the non-display region.

20. The method according to claim 19, in, The mask comprises a first portion, a second portion, a third portion and a fourth portion, wherein the first portion includes a transparent portion that allows light to pass completely through, wherein the second portion includes a blocking portion that completely blocks the light, wherein the third portion includes a translucent portion that allows the light to partially pass therethrough, wherein the fourth portion includes a slit pattern portion having at least one slit pattern, and wherein the first portion corresponds to the contactor of the through-hole pattern, the third portion corresponds to the first step portion of the through-hole pattern, the fourth portion corresponds to the second step portion of the through-hole pattern, and the second portion corresponds to another area of ​​the through-hole pattern excluding the contactor and the first step portion and the second step portion.

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