Display device

Abstract

The invention provides a display device. The display device includes a pixel electrode disposed on a substrate; an organic pattern layer disposed on the substrate and spaced apart from the pixel electrode; a light emitting element disposed on the organic pattern layer, the light emitting element including a contact electrode in contact with the organic pattern layer, and a first semiconductor layer, an active layer, and a second semiconductor layer disposed in this order on the contact electrode; and a connection electrode electrically connecting the pixel electrode to the contact electrode, and the connection electrode is disposed along an upper surface of the pixel electrode, a side surface of the organic pattern layer, and a side surface of the contact electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0089818 filed in the Korean Intellectual Property Office on July 11, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] As multimedia develops, display devices are becoming more and more important. In response to this, various types of display devices such as organic light emitting displays (OLEDs) and liquid crystal displays (LCDs) are being used.

[0005] The device for displaying an image of the display device may include a display panel such as an organic light-emitting display panel or a liquid crystal display panel. Among them, the light-emitting display panel may include a light-emitting element. For example, a light-emitting diode (LED) includes an organic light-emitting diode (OLED) using an organic material as a light-emitting material, an inorganic light-emitting diode using an inorganic material as a light-emitting material, and the like.

[0006] It is to be understood that this background section is intended, in part, to provide a useful background for understanding the present technology. However, this background section may also include ideas, concepts, or perceptions that were not known or understood by a person skilled in the relevant art prior to the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0007] Aspects and features of the embodiments provide a display device capable of low-temperature and low-pressure bonding of a light emitting element.

[0008] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to an embodiment, a display device may include: a pixel electrode disposed on a substrate; an organic pattern layer disposed on the substrate and spaced apart from the pixel electrode, a light-emitting element disposed on the organic pattern layer, the light-emitting element including a contact electrode contacting the organic pattern layer and a first semiconductor layer, an active layer, and a second semiconductor layer sequentially disposed on the contact electrode; and a connecting electrode electrically connecting the pixel electrode to the contact electrode, wherein the connecting electrode is disposed along an upper surface of the pixel electrode, a side surface of the organic pattern layer, and a side surface of the contact electrode.

[0010] The display device may include a light emitting region and a non-emitting region, wherein the organic pattern layer overlaps the light emitting region and does not overlap the non-emitting region.

[0011] The organic pattern layer may have a substantially island pattern shape.

[0012] The contact electrode may include a first portion disposed on and contacting the first semiconductor layer, and a second portion extending from the first portion and surrounding side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer.

[0013] The connection electrode may surround side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer on the contact electrode.

[0014] The display device may further include: a first through hole layer disposed on the connection electrode and the substrate on which the connection electrode is not disposed; a second through hole layer disposed on the first through hole layer; and a common electrode disposed on the light emitting element.

[0015] An upper surface of the first via layer may have the same height as an end portion of the connection electrode disposed along the second portion of the contact electrode.

[0016] The pixel electrode may overlap the non-emission region and not overlap the light emitting region.

[0017] The light emitting element may further include a first insulating layer surrounding the first semiconductor layer, the active layer, the side surface of the second semiconductor layer and the lower surface of the first semiconductor layer, the first insulating layer having a first opening on the first semiconductor layer, wherein the contact electrode directly contacts the first semiconductor layer through the first opening of the first insulating layer.

[0018] The light emitting element may further include: a second insulating layer surrounding the side surfaces of the first semiconductor layer, the active layer and the second semiconductor layer; and a reflective layer surrounding the side surfaces of the first semiconductor layer, the active layer and the second semiconductor layer on the second insulating layer, wherein the first insulating layer is disposed on the reflective layer and directly contacts the second portion of the contact electrode.

[0019] The reflective layer may be surrounded by the first insulating layer and the second insulating layer and not contact the contact electrode.

[0020] The display device may further include: a partition wall portion disposed on the common electrode and overlapping the non-emission region; a wavelength conversion layer disposed between the partition wall portions; and a color filter layer disposed on the wavelength conversion layer.

[0021] According to an embodiment, a display device may include: a pixel electrode, which is arranged on a substrate; an organic pattern layer, which is arranged on the pixel electrode; a light-emitting element, which is arranged on the organic pattern layer, the light-emitting element includes a contact electrode contacting the organic pattern layer and a first semiconductor layer, an active layer and a second semiconductor layer sequentially arranged on the contact electrode; and a connecting electrode, which electrically connects the pixel electrode to the contact electrode, wherein a portion of the upper surface of the pixel electrode does not overlap with the organic pattern layer, and the connecting electrode is arranged on the portion of the upper surface of the pixel electrode that does not overlap with the organic pattern layer, the side surface of the organic pattern layer and the side surface of the contact electrode.

[0022] The contact electrode may include a first portion disposed on and contacting the first semiconductor layer, and a second portion extending from the first portion and surrounding side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer.

[0023] The connection electrode may surround side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer on the contact electrode.

[0024] The display device may further include: a first through hole layer disposed on the connection electrode and the substrate on which the connection electrode is not disposed; a second through hole layer disposed on the first through hole layer; and a common electrode disposed on the light emitting element.

[0025] An upper surface of the first via layer may have the same height as an end portion of the connection electrode disposed along the second portion of the contact electrode.

[0026] The light emitting element may further include a first insulating layer surrounding the first semiconductor layer, the active layer, the side surface of the second semiconductor layer and the lower surface of the first semiconductor layer, the first insulating layer having a first opening on the first semiconductor layer, wherein the contact electrode directly contacts the first semiconductor layer through the first opening of the first insulating layer.

[0027] The light emitting element may further include: a second insulating layer surrounding the side surfaces of the first semiconductor layer, the active layer and the second semiconductor layer; and a reflective layer surrounding the side surfaces of the first semiconductor layer, the active layer and the second semiconductor layer on the second insulating layer, wherein the first insulating layer is disposed on the reflective layer and directly contacts the second portion of the contact electrode.

[0028] The display device may define a light emitting region and a non-emitting region. The display device may further include: a partition wall portion disposed on the common electrode and overlapping the non-emitting region; a wavelength conversion layer disposed between the partition wall portions; and a color filter layer disposed on the wavelength conversion layer.

[0029] Since the display device according to one embodiment performs bonding using an organic pattern layer, problems caused by eutectic bonding may be solved by omitting eutectic bonding.

[0030] However, the effects of the present disclosure are not limited to the above-mentioned effects, and various other effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0032] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0033] Figure 2 is a schematic plan view of a circuit of a display substrate of a display device according to an embodiment.

[0034] Figure 3 is a schematic diagram of an equivalent circuit of one pixel of a display device according to one embodiment.

[0035] Figure 4 is a schematic diagram of an equivalent circuit of one pixel of a display device according to an embodiment.

[0036] Figure 5 is a schematic diagram of an equivalent circuit of one pixel of a display device according to an embodiment.

[0037] Figure 6 is a schematic cross-sectional view of a display device according to an embodiment.

[0038] Figure 7 yes Figure 6 Magnified view of area A.

[0039] Figure 8 is a schematic plan view showing a light emitting area of ​​a display device.

[0040] Fig. 9 is an enlarged view of region A according to an embodiment.

[0041] Fig.10 is a schematic cross-sectional view of a display device according to an embodiment.

[0042] Fig.11 yes Fig.10 Magnified view of area B.

[0043] Fig.12 is a schematic plan view showing a light emitting area of ​​a display device.

[0044] Figures 13 to 33 is a schematic diagram for explaining a method of manufacturing a display device according to one embodiment. DETAILED DESCRIPTION

[0045] Embodiments will now be described more fully below with reference to the accompanying drawings. However, embodiments may be provided in different forms and should not be construed as limiting. Throughout the disclosure, the same reference numerals represent the same components. In the accompanying drawings, the thickness of a layer and the size of a region may be exaggerated for clarity.

[0046] In order to describe the embodiments of the present disclosure, some parts that are not related to the description may not be provided.

[0047] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being "directly on" another element, there may be no intervening elements present.

[0048] Furthermore, the phrase “in a plan view” means when the target portion is viewed from above, and the phrase “in a schematic cross-sectional view” means when a schematic cross-section obtained by vertically cutting the target portion is viewed from the side.

[0049] The term "overlap" or "overlapped" means that a first object can be above or below a second object, or on one side of the second object, and vice versa. Additionally, the term "overlap" may include layered, stacked, facing or facing, extending over, covering or partially covering, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art.

[0050] The expression "non-overlapping" may include meanings such as "spaced apart" or "offset" or "shifted" and any other suitable equivalents as would be appreciated and understood by one of ordinary skill in the art.

[0051] The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is interposed between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0052] For ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper" or the like may be used herein to describe the relationship between one element or component and another element or component as shown in the drawings. It will be understood that in addition to the orientation depicted in the drawings, the spatially relative terms are intended to also include different orientations of the device in use or operation. For example, in the case where the device shown in the drawings is flipped, a device positioned "below" or "below" another device can be placed "above" the other device. Therefore, the exemplary term "below" can include both lower and upper positions. The device may also be oriented in other directions, and therefore, the spatially relative terms may be interpreted differently depending on the orientation.

[0053] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element with one or more intervening elements interposed therebetween.

[0054] It will also be understood that when the terms "comprises," "comprising," "having," "having," "including," and / or "comprising" are used, they may specify the presence of stated features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of other features, integers, steps, operations, elements, parts, and / or any combinations thereof.

[0055] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or to facilitate description and explanation thereof. For example, when a "first element" is discussed in the description, it may be referred to as a "second element" or a "third element," and the "second element" and "third element" may be named in a similar manner without departing from the teachings herein.

[0056] In view of the measurements in question and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system), the terms "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0057] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or in a separate sense and may be understood to be equivalent to "and / or".

[0058] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0059] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formalized meaning unless explicitly defined in the specification.

[0060] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0061] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0062] refer to Figure 1 In the spirit and scope of the present disclosure, the display device 10 according to one embodiment may be applied to various consumer electronic products or IoT devices, such as smart phones, cellular phones, tablet PCs, personal digital assistants (PDAs), portable multimedia players (PMPs), televisions, game devices, watch-type electronic devices, head-mounted displays, displays of personal computers, laptop computers, car navigation devices, car dashboards, digital cameras, video cameras, exterior billboards, billboards, medical devices, inspection devices, refrigerators, washing machines, etc. A television is described herein as an example of the display device 10, and the television may have a high resolution or ultra-high resolution such as HD, UHD, 4K, 8K, etc.

[0063] The display device 10 according to some embodiments may be classified differently based on how it is displayed. For example, within the spirit and scope of the present disclosure, the classification of the display device 10 may include an organic light-emitting display device (OLED), an inorganic light-emitting display device (inorganic EL), a quantum dot light-emitting display device (QED), a micro-LED display device (micro-LED), a nano-LED display device (nano-LED), a plasma display device (PDP), a field emission display device (FED), a cathode ray tube display device (CRT), a liquid crystal display device (LCD), an electrophoretic display device (EPD), etc. In the following, an organic light-emitting display device will be described as an example of the display device 10, and unless otherwise indicated, the organic light-emitting display device applied in the embodiment will be abbreviated as a display device. However, the embodiment is not limited to an organic light-emitting display device, and the other display devices listed above can be used within the scope of their shared technical ideas.

[0064] In addition, in the following drawings, the first direction DR1 refers to the horizontal direction of the display device 10, the second direction DR2 refers to the vertical direction of the display device 10, and the third direction DR3 refers to the thickness direction of the display device 10. "Left", "right", "up", and "down" refer to directions when the display device 10 is observed from a plane. For example, "right" refers to one side or one side of the first direction DR1, "left" refers to the other side or the other side of the first direction DR1, "top" refers to one side or one side of the second direction DR2, and "bottom" refers to the other side or the other side of the second direction DR2. In addition, "up" refers to one side or one side of the third direction DR3, and "down" refers to the other side or the other side of the third direction DR3.

[0065] The display device 10 according to one embodiment may have a quadrilateral shape, such as a square shape, in a plan view. In addition, if the display device 10 is a TV, it may have a rectangular shape with the long side arranged in the lateral direction. However, it is not limited thereto, the long side may be arranged in the longitudinal direction, and it may be rotatably mounted so that the long side is variably arranged in the horizontal direction or the vertical direction. The display device 10 may also have a circular or elliptical shape.

[0066] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA may be an effective area for displaying a video. The display area DPA may have a square shape in a plan view similar to the overall shape of the display device 10, but is not limited thereto.

[0067] The display area DPA may include pixels PX. The pixels PX may be arranged (or set) in a matrix orientation. The shape of each pixel PX in a plan view may be a rectangle or a square, but is not limited thereto, and may also be a rhombus shape with each side tilted toward one side or one side of the display device 10. The pixels PX may include multi-color pixels PX. For example, the pixels PX may include a first color pixel PX of red, a second color pixel PX of green, and a third color pixel PX of blue, but is not limited thereto. The pixels PX of each color may be arranged in a stripe or pentile type. Arrange alternately.

[0068] The non-display area NDA may be disposed on the periphery of the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. The display area DPA may be in the shape of a square, and the non-display area NDA may be arranged adjacent to four sides of the display area DPA. The non-display area NDA may include a frame of the display device 10.

[0069] A driving circuit or a driving element for driving the display area DPA may be disposed in the non-display area NDA. Figure 1 The non-display area NDA disposed adjacent to the second side (the lower side of the display device 10) may have a pad portion disposed on the display substrate of the display device 10, and the external device EXD may be mounted on the pad electrode of the pad portion. Within the spirit and scope of the present disclosure, examples of the external device EXD include a connection film, a printed circuit board, a driver chip DIC, a connector, a wiring connection film, etc. Figure 1 In the non-display area NDA (the left side in the figure) adjacent to the display substrate 10, a scan driving unit SDR (or a scan driving part or a scan driver) directly formed on the display substrate of the display device 10 may be provided.

[0070] Figure 2 is a schematic plan view of a circuit of a display substrate of a display device according to an embodiment.

[0071] refer to Figure 2 , the lines are disposed on the substrate. Within the spirit and scope of the present disclosure, the lines may include a scan line SCL, a sensing signal line SSL, a data line DTL, a reference voltage line RVL, a first power line ELVDL, and the like.

[0072] The scan line SCL and the sensing signal line SSL may extend in the first direction DR1. The scan line SCL and the sensing signal line SSL may be connected to a scan drive unit SDR (or a scan drive portion or a scan driver). The scan drive unit SDR (or a scan drive portion or a scan driver) may include a drive circuit. The scan drive unit SDR (or a scan drive portion or a scan driver) may be disposed on one side or one side of the non-display area NDA on the display substrate, but may also be disposed on both sides of the non-display area NDA. The scan drive unit SDR (or a scan drive portion or a scan driver) may be connected to a signal connection line CWL, and at least one end of the signal connection line CWL may be connected to an external device ( Figure 1 in the .

[0073] The data line DTL and the reference voltage line RVL may extend in a second direction DR2 intersecting the first direction DR1. The first power line ELVDL may include a portion extending in the second direction DR2. The first power line ELVDL may also include a portion extending in the first direction DR1. The first power line ELVDL may have a mesh structure, but is not limited thereto.

[0074] The wiring pad WPD may be disposed at at least one end of the data line DTL, the reference voltage line RVL, and the first power line ELVDL. Each wiring pad WPD may be disposed in a pad area PDA of the non-display area NDA. In one embodiment, a wiring pad (hereinafter referred to as a "data pad") WPD_DT for the data line DTL, a wiring pad (hereinafter referred to as a "reference voltage pad") WPD_RV for the reference voltage line RVL, and a wiring pad (hereinafter referred to as a "first power pad") WPD_ELVD for the first power line ELVDL may be disposed in the pad area PDA of the non-display area NDA. In another example, the data pad WPD_DT, the reference voltage pad WPD_RV, and the first power pad WPD_ELVD may be disposed in different non-display areas NDA. External device ( Figure 1 The external device EXD may be mounted on the wiring pad WPD as described above. Within the spirit and scope of the present disclosure, the external device EXD may be mounted on the wiring pad WPD by an anisotropic conductive film, ultrasonic bonding, or the like.

[0075] Each pixel PX of the display device 10 may include a pixel driving circuit. The above wiring may pass through each pixel PX or around each pixel PX, and a driving signal is applied to each pixel driving circuit. The pixel driving circuit may include a transistor and a capacitor. The number of transistors and capacitors in each pixel driving circuit may vary. Hereinafter, the pixel driving circuit will be described by taking a 3T1C structure including three transistors and one capacitor as an example, but is not limited thereto, and various other modified pixel structures such as a 2T1C structure, a 7T1C structure, and a 6T1C structure may be applied.

[0076] Figure 3 is a schematic diagram of an equivalent circuit of one pixel of a display device according to one embodiment.

[0077] refer to Figure 3 In addition to the light emitting element LE, each pixel PX of the display device 10 according to one embodiment may include three transistors (ie, a driving transistor DTR, a first transistor STR1, and a second transistor STR2) and one capacitor for storage (ie, a capacitor CST).

[0078] The light emitting element LE emits light in response to the current provided by the driving transistor DTR. Within the spirit and scope of the present disclosure, the light emitting element LE may be implemented as an inorganic light emitting diode, an organic light emitting diode, a micro light emitting diode, a nano light emitting diode, or the like.

[0079] A first electrode (e.g., an anode electrode) of the light emitting element LE can be connected to a source electrode of the driving transistor DTR, and a second electrode (e.g., a cathode electrode) of the light emitting element LE can be connected to a second power line ELVSL, which is provided with a low potential voltage (second power supply voltage) lower than a high potential voltage (first power supply voltage) of the first power line ELVDL.

[0080] The driving transistor DTR adjusts the current flowing from the first power line ELVDL supplied with the first power voltage to the light emitting element LE according to the voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DTR may be connected to the first electrode of the first transistor STR1, the source electrode of the driving transistor DTR may be connected to the first electrode of the light emitting element LE, and the drain electrode of the driving transistor DTR may be connected to the first power line ELVDL supplied with the first power voltage.

[0081] The first transistor STR1 is turned on by a scan signal on the scan line SCL to connect the data line DTL to the gate electrode of the driving transistor DTR. The gate electrode of the first transistor STR1 may be connected to the scan line SCL, the first electrode of the first transistor STR1 may be connected to the gate electrode of the driving transistor DTR, and the second electrode of the first transistor STR1 may be connected to the data line DTL.

[0082] The second transistor STR2 is turned on by the sensing signal on the sensing signal line SSL to connect the initialization voltage line VIL to the source electrode of the driving transistor DTR. The gate electrode of the second transistor STR2 can be connected to the sensing signal line SSL, the first electrode can be connected to the initialization voltage line VIL, and the second electrode can be connected to the source electrode of the driving transistor DTR.

[0083] In one implementation, a first electrode of each of the first transistor STR1 and the second transistor STR2 may be a source electrode, and a second electrode thereof may be a drain electrode, but is not limited thereto, and may be vice versa.

[0084] The capacitor CST is formed between the gate electrode and the source electrode of the driving transistor DTR. The capacitor CST stores a voltage difference between a gate voltage of the driving transistor DTR and a source voltage of the driving transistor DTR.

[0085] The driving transistor DTR and the first and second transistors STR1 and STR2 may be formed as thin film transistors. Figure 3The driving transistor DTR and the first transistor STR1 and the second transistor STR2 as switching transistors are described as N-type MOSFETs (metal oxide semiconductor field effect transistors), but are not limited thereto. For example, the driving transistor DTR and the first transistor STR1 and the second transistor STR2 may be P-type MOSFETs; or some may be N-type MOSFETs and others may be P-type MOSFETs.

[0086] Figure 4 is a schematic diagram of an equivalent circuit of one pixel of a display device according to an embodiment.

[0087] refer to Figure 4 , the first electrode of the light emitting element LE may be connected to the first electrode of the fourth transistor STR4 and the second electrode of the sixth transistor STR6, and the second electrode of the light emitting element LE may be connected to the second power line ELVSL. A parasitic capacitor Cel may be formed between the first electrode of the light emitting element LE and the second electrode of the light emitting element LE. The gate electrode of the sixth transistor STR6 may be connected to the emission line EL.

[0088] Each pixel PX may include a driving transistor DTR, a switching element, and a capacitor CST. The switching element includes a first transistor STR1, a second transistor STR2, a third transistor STR3, a fourth transistor STR4, a fifth transistor STR5, and a sixth transistor STR6. The first transistor STR1 may include further transistors ST1-1 and ST1-2. The third transistor STR3 may include further transistors ST3-1 and ST3-2.

[0089] The driving transistor DTR may include a gate electrode, a first electrode, and a second electrode. The driving transistor DTR controls a drain-to-source current (hereinafter referred to as "driving current") Ids flowing between the first electrode of the driving transistor DTR and the second electrode of the driving transistor DTR based on a data voltage applied to the gate electrode.

[0090] The capacitor CST is formed between the gate electrode of the driving transistor DTR and the first power line ELVDL. One electrode of the capacitor CST may be connected to the gate electrode of the driving transistor DTR, and the other electrode of the capacitor CST may be connected to the first power line ELVDL.

[0091] In the case where the first electrode of each of the first transistor STR1, the second transistor STR2, the third transistor STR3, the fourth transistor STR4, the fifth transistor STR5, the sixth transistor STR6, and the driving transistor DTR is a source electrode, the second electrode thereof may be a drain electrode. For example, if the first electrode of each of the first transistor STR1, the second transistor STR2, the third transistor STR3, the fourth transistor STR4, the fifth transistor STR5, the sixth transistor STR6, and the driving transistor DTR is a drain electrode, the second electrode thereof may be a source electrode.

[0092] The active layer of each of the first transistor STR1, the second transistor STR2, the third transistor STR3, the fourth transistor STR4, the fifth transistor STR5, the sixth transistor STR6, and the driving transistor DTR may be formed of any one of polycrystalline silicon, amorphous silicon, and an oxide semiconductor. In the case where the semiconductor layer of each of the first transistor STR1, the second transistor STR2, the third transistor STR3, the fourth transistor STR4, the fifth transistor STR5, the sixth transistor STR6, and the driving transistor DTR is formed of polycrystalline silicon, the process for forming it may be a low temperature polycrystalline silicon (LTPS) process.

[0093] exist Figure 4 In the description, the first transistor STR1, the second transistor STR2, the third transistor STR3, the fourth transistor STR4, the fifth transistor STR5 and the sixth transistor STR6 and the driving transistor DTR are described with P-type MOSFET (metal oxide semiconductor field effect transistor) as the center, but are not limited to this and can be formed as N-type MOSFET.

[0094] In addition, within the spirit and scope of the present disclosure, the first power supply voltage of the first power line ELVDL, the second power supply voltage of the second power line ELVSL, and the third power supply voltage of the initialization voltage line VIL can be set by considering the characteristics of the driving transistor DTR, the characteristics of the light emitting element LE, etc.

[0095] Figure 5 is a schematic diagram of an equivalent circuit of one pixel of a display device according to an embodiment.

[0096] Figure 5 The implementation method and Figure 4 The embodiment of is different in that the driving transistor DTR, the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5 and the sixth transistor STR6 are formed as P-type MOSFETs, and the first transistor STR1 and the third transistor STR3 are formed as N-type MOSFETs.

[0097] refer to Figure 5 , the active layer of each of the driving transistor DTR, the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5 and the sixth transistor STR6 formed as a P-type MOSFET can be formed of polysilicon, and the active layer of each of the first transistor STR1 and the third transistor STR3 formed as an N-type MOSFET can be formed of an oxide semiconductor.

[0098] Figure 5 and Figure 4 The difference of the embodiment of is that the gate electrode of the second transistor STR2 and the gate electrode of the fourth transistor STR4 are connected to the write scan line GWL, and the gate electrode of the first transistor STR1 is connected to the control scan line GCL. Figure 5 In the embodiment, the first transistor STR1 and the third transistor STR3 are formed as N-type MOSFETs, so that a scan signal with a gate high voltage can be applied to the control scan line GCL and the initialization scan line GIL. On the other hand, since the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5, and the sixth transistor STR6 are formed as P-type MOSFETs, a scan signal with a gate low voltage can be applied to the write scan line GWL and the light emitting element LE.

[0099] It should be noted that the equivalent circuit diagram of the pixel PX according to the above embodiment is not limited to Figures 3 to 5 The equivalent circuit diagram of the pixel PX according to the embodiment of the present disclosure can be adopted by those skilled in the art, which is different from Figures 3 to 5 Other selected circuit structures of the embodiment shown in are formed.

[0100] Figure 6 is a schematic cross-sectional view of a display device according to an embodiment. Figure 7 yes Figure 6 Magnified view of area A. Figure 8 is a schematic plan view showing a light emitting area of ​​a display device. Fig. 9 is an enlarged view of region A according to an embodiment.

[0101] refer to Figure 6 , the display device 10 may include a display substrate 100 , and a wavelength control unit 200 (or controller) and a color filter layer CFL disposed on the display substrate 100 .

[0102] The display substrate 100 may include a substrate 110 and a light emitting element portion LEP disposed on the substrate 110. The substrate 110 may be an insulating substrate. The substrate 110 may include a transparent material. For example, within the spirit and scope of the present disclosure, the substrate 110 may include a transparent insulating material such as glass, quartz or the like. The substrate 110 may be a rigid substrate. However, the substrate 110 is not limited thereto, and within the spirit and scope of the present disclosure, may include a plastic such as polyimide. In addition, the substrate 110 may have flexible properties that allow it to be warped, bent, folded or rolled up. The light emitting areas (also referred to as emission areas) EA1, EA2 and EA3 and the non-emission area NEA may be defined on the substrate 110.

[0103] The switching elements T1, T2, and T3 may be disposed on the substrate 110. In one embodiment, the first switching element T1 may be disposed in the first light emitting area EA1 of the substrate 110, the second switching element T2 may be disposed in the second light emitting area EA2, and the third switching element T3 may be disposed in the third light emitting area EA3. However, it is not limited thereto, and in other embodiments, at least one of the first switching element T1, the second switching element T2, and the third switching element T3 may be disposed in the non-emission area NEA.

[0104] In one embodiment, the first switching element T1, the second switching element T2, and the third switching element T3 may each be a thin film transistor including amorphous silicon, polycrystalline silicon, or an oxide semiconductor. Although not shown, there may be a signal line (e.g., a gate line, a data line, a power line, etc.) further disposed on the substrate 110 to transmit a signal to each of the switching elements T1, T2, and T3.

[0105] Each of the switching elements T1, T2, and T3 may include a semiconductor layer 65, a gate electrode 75, a source electrode 85a, and a drain electrode 85b. For example, a buffer layer 60 may be provided on the substrate 110. The buffer layer 60 may be provided to cover the front side of the substrate 110. The buffer layer 60 may include silicon nitride, silicon oxide, or silicon oxynitride, and may be a single layer or a double layer thereof.

[0106] The semiconductor layer 65 may be disposed on the buffer layer 60. The semiconductor layer 65 may form a channel of each of the switching elements T1, T2, and T3. The semiconductor layer 65 may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor. In one example, within the spirit and scope of the present disclosure, the oxide semiconductor may include, for example, a binary compound (AB) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), or the like. x ), ternary compounds (AB x C y ) or quaternary compound (AB x Cy D z In one implementation, the semiconductor layer 65 may include indium tin zinc oxide (IGZO).

[0107] The gate insulating layer 70 may be disposed on the semiconductor layer 65. Within the spirit and scope of the present disclosure, the gate insulating layer 70 may include a silicon compound, a metal oxide, or the like. For example, within the spirit and scope of the present disclosure, the gate insulating layer 70 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. In one embodiment, the gate insulating layer 70 may include silicon oxide.

[0108] The gate electrode 75 may be disposed on the gate insulating layer 70. The gate electrode 75 may overlap the semiconductor layer 65. The gate electrode 75 may include a conductive material. The gate electrode 75 may include a conductive material such as ITO, IZO, ITZO, In 2 O 3 The gate electrode 75 may be formed of a metal oxide or a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg) or nickel (Ni). For example, the gate electrode 75 may be formed of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, but is not limited thereto.

[0109] The first interlayer insulating layer 80 and the second interlayer insulating layer 82 may be disposed on the gate electrode 75. The first interlayer insulating layer 80 may be disposed directly on the gate electrode 75, and the second interlayer insulating layer 82 may be disposed directly on the first interlayer insulating layer 80. Within the spirit and scope of the present disclosure, the first interlayer insulating layer 80 and the second interlayer insulating layer 82 may each include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, or the like. However, it is not limited thereto, and the second interlayer insulating layer 82 may include an organic insulating material capable of flattening the lower step.

[0110] The source electrode 85a and the drain electrode 85b may be disposed on the second interlayer insulating layer 82. The source electrode 85a and the drain electrode 85b may be connected to the semiconductor layer 65 through contact holes penetrating the first interlayer insulating layer 80, the second interlayer insulating layer 82, and the gate insulating layer 70, respectively. The source electrode 85a and the drain electrode 85b may include a semiconductor material such as ITO, IZO, ITZO, or In 2 O 3 The source electrode 85a and the drain electrode 85b may be formed of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, or a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), or nickel (Ni). For example, the source electrode 85a and the drain electrode 85b may be formed of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, but is not limited thereto.

[0111] The first planarization layer 120 may be disposed on the first switching element T1, the second switching element T2, and the third switching element T3. The first planarization layer 120 may include an organic material. For example, within the spirit and scope of the present disclosure, the first planarization layer 120 may include an acrylic resin, an epoxy resin, an imide resin, an ester resin, or the like. In one embodiment, the first planarization layer 120 may include a positive photosensitive material or a negative photosensitive material.

[0112] The pixel connection electrode 125 may be disposed on the first planarization layer 120. The pixel connection electrode 125 is disposed to correspond to each of the first switching element T1, the second switching element T2, and the third switching element T3, and may be electrically connected to them. The pixel connection electrode 125 may connect the pixel electrodes PE1, PE2, and PE3 described later to the above-mentioned switching elements T1, T2, and T3. The pixel connection electrode 125 may contact the switching elements T1, T2, and T3 through a contact hole penetrating the first planarization layer 120.

[0113] The second planarization layer 130 may be disposed on the first planarization layer 120 and the pixel connection electrode 125. The second planarization layer 130 planarizes the lower step, and may include the same material as the first planarization layer 120 described above.

[0114] The light emitting element portion LEP may be disposed on the second planarization layer 130. The light emitting element portion LEP may include pixel electrodes PE1, PE2, and PE3 (collectively referred to as pixel electrodes PE when not distinguished), an organic pattern layer OBL, light emitting elements LE1, LE2, and LE3 (collectively referred to as light emitting elements LE when not distinguished), and a common electrode CE. In addition, the light emitting element portion LEP may further include a first through hole layer VIA1 and a second through hole layer VIA2.

[0115] The pixel electrodes PE1, PE2 and PE3 may include a first pixel electrode PE1, a second pixel electrode PE2 and a third pixel electrode PE3. The first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may be electrically connected to the light emitting element LE through the connecting electrode 150. The first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may be used as a first electrode of the light emitting element LE and may be an anode electrode or a cathode electrode. The pixel electrodes PE1, PE2 and PE3 may be disposed in the non-emission area NEA. The pixel electrodes PE1, PE2 and PE3 may not overlap with the light emitting areas EA1, EA2 and EA3.

[0116] Each of the pixel electrodes PE1, PE2 and PE3 can be directly connected to the pixel connection electrode 125 through a contact hole penetrating the second planarization layer 130, and can be electrically connected to each of the switching elements T1, T2 and T3 through the pixel connection electrode 125. The first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may include a metal. The metal may include, for example, copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. In addition, the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may have a multilayer structure in which two or more metal layers may be stacked on each other. For example, the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may have a two-layer structure in which a copper layer is stacked on a titanium layer, but is not limited thereto.

[0117] The organic pattern layer OBL is disposed adjacent to the first pixel electrode PE1 and may be disposed in the emission regions EA1, EA2, and EA3. The organic pattern layer OBL may be formed to be thicker than the pixel electrode PE. The organic pattern layer OBL may be disposed in each of the emission regions EA1, EA2, and EA3 in a substantially island pattern shape. For example, the organic pattern layer OBL disposed in each of the emission regions EA1, EA2, and EA3 may be disposed separately from the organic pattern layer OBL disposed in the adjacent emission regions EA1, EA2, and EA3.

[0118] The thickness of the organic pattern layer OBL may be 2 μm or less, but is not limited thereto.

[0119] The organic pattern layer OBL may include an organic material. The organic material may be, for example, a photosensitive organic insulating material, but is not limited thereto. In addition, the organic material may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin.

[0120] The organic pattern layer OBL may be formed by various methods such as an organic imprint method, an inkjet printing method, an electrospray method, or a stamp method.

[0121] As in the display device 10 in one embodiment, it is difficult to replace the organic pattern layer OBL with an anisotropic conductive film (ACF) in a high-resolution display panel.

[0122] The light emitting element LE may be disposed on the organic pattern layer OBL.

[0123] like Figures 6 to 8As shown in , the light emitting element LE may be disposed in each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3. The light emitting element LE may be a vertical light emitting diode element that extends long in the third direction DR3. For example, the length of the light emitting element LE in the third direction DR3 may be longer than the length in the horizontal direction. The length in the horizontal direction refers to the length in the first direction DR1 or the length in the second direction DR2. For example, the length of the light emitting element LE in the third direction DR3 may be in the range of 1 μm to 5 μm. However, it is not limited thereto, and the length of the light emitting element LE in the third direction DR3 may be equal to or less than the length in the horizontal direction.

[0124] The light emitting element LE may be a micro light emitting diode element. The light emitting element LE may include a contact electrode RFM, a first semiconductor layer SEM1, an active layer MQW, and a second semiconductor layer SEM2 in the thickness direction of the substrate 110 (e.g., in the third direction DR3). The contact electrode RFM, the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 may be sequentially stacked on each other in the third direction DR3. The light emitting element LE may include a first insulating layer INS1, a reflective layer RFL, and a second insulating layer INS2 surrounding the outer surfaces of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2.

[0125] The light emitting element LE may have a cylindrical shape, a disk shape, or a rod shape in which the height is longer than the width. However, the light emitting element LE is not limited thereto, and may have a shape such as a rod, a wire, a tube, a polygonal column shape (such as a regular hexahedron, a rectangular parallelepiped, or a hexagonal column), or a shape extending in one direction or a certain direction but having a partially inclined outer surface.

[0126] The contact electrode RFM may be disposed on one end of the light emitting element LE and may be disposed on the organic pattern layer OBL. Hereinafter, the light emitting element LE of the first light emitting area EA1 will be described as an example, but is not limited thereto, and the light emitting elements LE disposed on the second pixel electrode PE2 and the third pixel electrode PE3 may have the same structure.

[0127] At least a portion of the contact electrode RFM is buried inside the organic pattern layer OBL, and at least a portion of the contact electrode RFM is exposed to the outside without being buried inside the organic pattern layer OBL.

[0128] In one embodiment, the contact electrode RFM may include a first portion RFM-1 disposed on one end surface or end surface of the light emitting element LE and a second portion RFM-2 extending from the first portion RFM-1 and disposed on at least a portion of the side surface of the light emitting element LE. The first portion RFM-1 is disposed on the first semiconductor layer SEM1 and may directly contact the first semiconductor layer SEM1. The first portion RFM-1 is buried inside the organic pattern layer OBL and is not visible from the outside of the organic pattern layer OBL. The second portion RFM-2 may surround at least one side or one side of the light emitting element LE. For example, the second portion RFM-2 may surround at least a portion of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2, but is not limited thereto. In another modification, the second portion RFM-2 surrounds the first semiconductor layer SEM1 and the active layer MQW, and one end of the second portion RFM-2 may be consistent with the height of the upper surface of the active layer MQW.

[0129] At least a portion of the second portion RFM-2 is exposed to the outside without being buried inside the organic pattern layer OBL. The second portion RFM-2 exposed to the outside without being buried inside the organic pattern layer OBL is electrically connected to the first pixel electrode PE1 through a connection electrode 150 as will be described later.

[0130] The contact electrode RFM may include a metal material having conductivity and high reflectivity, but is not limited thereto. The contact electrode RFM may include, for example, at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti).

[0131] The first semiconductor layer SEM1 may be disposed on the contact electrode RFM. The first semiconductor layer SEM1 may be disposed adjacent to the first pixel electrode PE1. The first semiconductor layer SEM1 may be a P-type semiconductor and may include a semiconductor having a chemical formula of Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) semiconductor material. For example, it can be any one or more of P-doped AlGaInN, GaN, AlGaN, InGaN, AlN and InN. The first semiconductor layer SEM1 can be doped with a P-type dopant, and within the spirit and scope of the present disclosure, the P-type dopant can be Mg, Zn, Ca, Se, Ba or the like. For example, the first semiconductor layer SEM1 can be P-GaN doped with P-type Mg. The thickness of the first semiconductor layer SEM1 can be in the range of 30nm to 200nm, but is not limited thereto.

[0132] The active layer MQW may be disposed on the first semiconductor layer SEM1. The active layer MQW may emit light by recombining electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2. The active layer MQW may emit first light having a central wavelength range of 450 nm to 495 nm, for example, light in a blue wavelength band.

[0133] The active layer MQW may include a single quantum well structure or a multi-quantum well structure. If the active layer MQW may include a material having a multi-quantum well structure, it may be a stacked structure having well layers and barrier layers alternating with each other. The well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. The thickness of the well layer may be in the range of 1 nm to 4 nm, and the thickness of the barrier layer may be in the range of 3 nm to 10 nm.

[0134] For example, the active layer MQW may have a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked with each other, and may include other III- to V-group semiconductor materials according to the wavelength band of the emitted light. The light emitted from the active layer MQW is not limited to the first light, and the second light (light in a green wavelength band) or the third light (light in a red wavelength band) may be emitted according to the situation. In one embodiment, in the case where indium is included among the semiconductor materials included in the active layer MQW, the color of the emitted light may vary according to the amount of indium. For example, in the case where the indium content is about 15%, light in a blue wavelength band may be emitted, in the case where the indium content is about 25%, light in a green wavelength band may be emitted, and in the case where the indium content is 35% or more, light in a red wavelength band may be emitted.

[0135] The second semiconductor layer SEM2 may be disposed on the active layer MQW. The second semiconductor layer SEM2 may be an N-type semiconductor. The second semiconductor layer SEM2 may include a semiconductor having a chemical formula of Al x Ga y In 1-x-y The second semiconductor layer SEM2 may be a semiconductor material of N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, it may be one or more of N-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second semiconductor layer SEM2 may be doped with an N-type dopant, and within the spirit and scope of the present disclosure, the N-type dopant may be Si, Ge, Sn, or the like. For example, the second semiconductor layer SEM2 may be N-GaN doped with N-type Si. The thickness of the second semiconductor layer SEM2 may be in the range from 2 μm to 4 μm, but is not limited thereto.

[0136] The first insulating layer INS1 may surround the side surfaces, for example, the outer circumferential surfaces, of the first semiconductor layer SEM1, the second semiconductor layer SEM2, and the active layer MQW of the light emitting element LE. The first insulating layer INS1 may insulate the first semiconductor layer SEM1, the second semiconductor layer SEM2, and the active layer MQW of the light emitting element LE from other layers. The first insulating layer INS1 may be directly disposed on the outer circumferential surfaces of the first semiconductor layer SEM1, the second semiconductor layer SEM2, and the active layer MQW to surround them. In one embodiment, the first insulating layer INS1 may surround the entire outer circumferential surfaces of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2.

[0137] like Figure 7 As shown in FIG. 1 , the first insulating layer INS1 may be disposed to surround the first semiconductor layer SEM1, the second semiconductor layer SEM2, and the active layer MQW of the light emitting element LE. Within the spirit and scope of the present disclosure, the first insulating layer INS1 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ), aluminum nitride (AlN), or the like. The thickness of the first insulating layer INS1 may be about 0.1 μm, but is not limited thereto.

[0138] The reflective layer RFL may be disposed on the first insulating layer INS1. The reflective layer RFL may directly contact one surface or surface of the first insulating layer INS1. The reflective layer RFL may be disposed to surround the side surface of the light emitting element LE. For example, the reflective layer RFL surrounds the outer circumferential surface of the first insulating layer INS1 on the first insulating layer INS1 of the light emitting element LE, and may surround the side surfaces of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 of the light emitting element LE. The reflective layer RFL may surround the side surfaces of the first semiconductor layer SEM1 and the active layer MQW of the light emitting element LE, and may surround at least a portion of the side surface of the second semiconductor layer SEM2. The height of the reflective layer RFL may be substantially the same as the height of the first insulating layer INS1. Here, the height of the reflective layer RFL and the height of the first insulating layer INS1 may mean the height from the upper surface of the contact electrode RFM to the highest point in the thickness direction.

[0139] In reference Fig. 9In an embodiment, the height of the reflective layer RFL may be lower than the height of the first insulating layer INS1. For example, the height of the reflective layer RFL may be lower than the height of the light emitting element LE. The reflective layer RFL may be completely surrounded by the first insulating layer INS1 and the second insulating layer INS2. For example, the reflective layer RFL may be insulated from the outside by the first insulating layer INS1 and the second insulating layer INS2.

[0140] The reflective layer RFL may reflect light emitted from the light emitting element LE. For example, the reflective layer RFL may reflect light emitted from the active layer MQW of the light emitting element LE upward (for example, in the third direction DR3) to the upper side. For example, the reflective layer RFL may improve the light emitting efficiency of the light emitting element LE. To this end, the reflective layer RFL may be disposed to at least surround the side surface of the active layer MQW of the light emitting element LE.

[0141] The reflective layer RFL may include a metal material having high reflectivity. For example, the reflective layer RFL may include aluminum or silver, or may be an alloy thereof.

[0142] The second insulating layer INS2 may be disposed on the reflective layer RFL. The second insulating layer INS2 may directly contact one surface or surface of the reflective layer RFL. The second insulating layer INS2 may be disposed to surround the side surface of the light emitting element LE. For example, the second insulating layer INS2 surrounds the outer circumferential surface of the reflective layer RFL on the reflective layer RFL of the light emitting element LE, and may surround the side surfaces of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 of the light emitting element LE.

[0143] The second insulating layer INS2 covers one end or one end of the reflective layer RFL and one end of the first insulating layer INS1 so that the reflective layer RFL and one end of the first insulating layer INS1 do not directly contact the contact electrode RFM. The reflective layer RFL may be disposed between the first insulating layer INS1 and the second insulating layer INS2 and may be insulated from the contact electrode RFM by the second insulating layer INS2.

[0144] The connection electrode 150 may cover the pixel electrode PE and may extend along the side surface and the upper surface of the organic pattern layer OBL on which the light emitting element LE is not disposed and along the side surface and the upper surface of the contact electrode RFM. The connection electrode 150 may cover all of the second portion RFM-2 exposed outside the organic pattern layer OBL. Therefore, the height of the connection electrode 150 may be higher than the height of the contact electrode RFM. The connection electrode 150 may be disposed to surround the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 on the second portion RFM-2.

[0145] The connection electrode 150 may overlap each of the light emitting areas EA1, EA2, and EA3 and the non-emission area NEA, but adjacent connection electrodes 150 may be spaced apart from each other. The connection electrode 150 may include a hole provided in a region corresponding to the light emitting element LE on a plane.

[0146] The connection electrode 150 electrically connects the pixel electrode PE (eg, the first pixel electrode PE1) and the light emitting element LE. Therefore, the light emitting element LE is not disposed on the pixel electrode PE and does not directly contact the pixel electrode PE. The light emitting element LE contacts the pixel electrode PE at the side through the connection electrode 150.

[0147] The connection electrode 150 may include a metal material having low resistance such as aluminum (Al), silver (Ag), or copper (Cu), or a metal oxide such as ITO, IZO, or ITZO.

[0148] The connection electrode 150 may be used to transfer a light emitting signal from the first pixel electrode PE1 to the light emitting element LE.

[0149] The first via layer VIA1 may be disposed on the connection electrode 150. The first via layer VIA1 may prevent the components below from being damaged in the etching process of the light emitting element LE, which will be described later. For example, the first via layer VIA1 may protect the connection electrode 150 below. The first via layer VIA1 may contact the upper surface of the connection electrode 150 and cover the connection electrode 150. The first via layer VIA1 covers the connection electrode 150 and may have an optional height. For example, the height of the first via layer VIA1 may be equal to or higher than the highest height of the connection electrode 150.

[0150] The first via layer VIA1 may include an organic material to planarize the lower step. For example, the first via layer VIA1 may include polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0151] The second via layer VIA2 may be disposed on the first via layer VIA1. The second via layer VIA2 may cover the first via layer VIA1 and may flatten the step at the bottom to allow the common electrode CE to be formed, as described later. The second via layer VIA2 may be formed at an optional height so that at least a portion of the light emitting element LE (e.g., the second semiconductor layer SEM2) may protrude above the second via layer VIA2. In other words, the height of the second via layer VIA2 may be smaller than the height of the light emitting element LE.

[0152] The second via layer VIA2 may cover the first via layer VIA1 to protect them.

[0153] The common electrode CE may be disposed on the second via layer VIA2 and the light emitting element LE. For example, the common electrode CE may be disposed on one surface or surfaces of the substrate 110 on which the light emitting element LE is formed. The common electrode CE is disposed to overlap each of the light emitting areas EA1, EA2, and EA3 and the non-emission area NEA, and may be made to have a thin thickness to allow light to be emitted.

[0154] The common electrode CE may be directly disposed on the top surface and the side surface of the light emitting element LE.

[0155] The common electrode CE may be directly disposed on the top surface and the side surface of the light emitting element LE. The common electrode CE may directly contact the second semiconductor layer SEM2 exposed on the upper surface of the light emitting element LE. Figure 6 As shown in , the common electrode CE may be a common layer covering the light emitting elements LE and arranged to be commonly connected to the light emitting elements LE. Since the conductive second semiconductor layer SEM2 has a patterned structure in each light emitting element LE, the common electrode CE may directly contact the second semiconductor layer SEM2 of each light emitting element LE, so that a common voltage may be applied to each light emitting element LE.

[0156] The common electrode CE may include a material having low resistance because it is provided throughout the entire substrate 110 to which a common voltage is applied. Also, the common electrode CE may be formed to have a thin thickness to easily transmit light. For example, within the spirit and scope of the present disclosure, the common electrode CE may include a low resistance metal material such as aluminum (Al), silver (Ag), copper (Cu), or the like, or a metal oxide such as ITO, IZO, ITZO, or the like. The common electrode CE may have a to The thickness is within the range of, but not limited to.

[0157] The above-mentioned light emitting element LE can be provided with a pixel voltage or an anode voltage from each of the pixel electrodes PE1, PE2 and PE3 and a common voltage through the common electrode CE. The light emitting element LE can emit light with a selectable brightness according to the voltage difference between the pixel voltage and the common voltage. In one embodiment, by providing a light emitting element LE (e.g., an inorganic light emitting diode) on the pixel electrodes PE1, PE2 and PE3, the disadvantage of the organic light emitting diode being susceptible to external moisture or oxygen can be eliminated, and the life span and reliability can be improved.

[0158] like Figure 8As shown in , the light emitting elements LE may be disposed on the organic pattern layer OBL. The light emitting elements LE are arranged in a regular pattern with a certain regularity. For example, the light emitting elements LE may be spaced apart from each other at regular intervals. In one embodiment, 2×4 light emitting elements LE are disposed on one organic pattern layer OBL, but are not limited thereto, and various modifications such as 2×3 and 1×4 may be considered.

[0159] The light emitting element part LEP may further include a first capping layer CPL1 covering the common electrode CE. The first capping layer CPL1 may be directly disposed on the common electrode CE. The first capping layer CPL1 serves to protect components disposed therebelow (eg, the light emitting element LE and the common electrode CE) from moisture or debris by covering them.

[0160] The first cap layer CPL1 may include an inorganic material. For example, the first cap layer CPL1 may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, and cerium oxide. Although the drawings show that the first cap layer CPL1 is formed of one layer, it is not limited thereto. For example, the first cap layer CPL1 may be formed as a multilayer alternately stacked with such an inorganic layer including at least one of the materials (for example, the materials that the first cap layer CPL1 may include). The thickness of the first cap layer CPL1 may be in the range from 0.05 μm to 2 μm, but is not limited thereto.

[0161] The wavelength control unit 200 (or controller) may be disposed on the light emitting element portion LEP. The wavelength control unit 200 (or controller) may include a first wavelength conversion layer WCL1, a second wavelength conversion layer WCL2, and a light transmission layer TPL, each serving as a wavelength control layer. In addition, the wavelength control unit 200 (or controller) may further include a bank layer (also referred to as a partition wall portion) BNL.

[0162] The bank layer BNL is disposed on the first cover layer CPL1 and may separate the light emitting areas EA1, EA2, and EA3. The bank layer BNL is disposed to extend in the first direction DR1 and the second direction DR2 and may be formed in a lattice pattern throughout the display area DPA. In addition, the bank layer BNL does not overlap with the light emitting areas EA1, EA2, and EA3 and may overlap with the non-emission area NEA.

[0163] The bank layer BNL may be used to provide a space in which the first wavelength conversion layer WCL1, the second wavelength conversion layer WCL2, and the light transmission layer TPL are formed. To this end, the bank layer BNL may have a thickness in the range of 1 μm to 10 μm. The bank layer BNL may include an organic insulating material formed to have a large thickness. The organic insulating material may include, for example, an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin.

[0164] In one embodiment, the bank layer BNL may also include a light blocking material, and may include a dye or pigment having a light blocking property. For example, the bank layer BNL may be a black matrix. External light incident from the outside of the display device 10 may cause a problem of distorting the color gamut of the wavelength control unit 200 (or controller). According to an embodiment, by providing a bank layer BNL including a light blocking material in the wavelength control unit 200 (or controller), color distortion due to reflection of external light can be reduced. The bank layer BNL including a light blocking material can prevent light from penetrating between adjacent light emitting areas and thus color mixing, thereby further improving color reproducibility.

[0165] The first wavelength conversion layer WCL1, the second wavelength conversion layer WCL2, and the light transmission layer TPL may be disposed in the light emitting areas EA1, EA2, and EA3. The first wavelength conversion layer WCL1 and the second wavelength conversion layer WCL2 may convert or shift the peak wavelength of the incident light to another specific peak wavelength and emit the light. The first wavelength conversion layer WCL1 converts the blue light emitted from the light emitting element LE into red light, and the second wavelength conversion layer WCL2 converts the blue light into green light. The light transmission layer TPL may transmit the blue light as it is.

[0166] The first wavelength conversion layer WCL1, the second wavelength conversion layer WCL2, and the light transmission layer TPL may be disposed in each of the light emitting areas EA1, EA2, and EA3 partitioned by the bank layer BNL, and may be arranged spaced apart from each other. For example, the first wavelength conversion layer WCL1, the second wavelength conversion layer WCL2, and the light transmission layer TPL may be formed in a dot-shaped island pattern spaced apart from each other.

[0167] The first wavelength conversion layer WCL1 may be disposed to overlap the first light emitting area EA1. The first wavelength conversion layer WCL1 may convert or shift the peak wavelength of the incident light into light having another specific peak wavelength and emit the light. In an embodiment, the first wavelength conversion layer WCL1 may convert the blue light emitted from the light emitting element LE of the first light emitting area EA1 into red light having a single peak wavelength in the range of 610nm to 650nm, and emit the red light.

[0168] The first wavelength conversion layer WCL1 may include a first base resin BRS1, first wavelength conversion particles WCP1, and scatterers SCP. The first base resin BRS1 may include a light-transmitting organic material. For example, the first base resin BRS1 may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin.

[0169] The first wavelength conversion particle WCP1 may convert the blue light emitted from the light emitting element LE into red light. For example, the first wavelength conversion particle WCP1 may convert the light in the blue wavelength band into the light in the red wavelength band. The first wavelength conversion particle WCP1 may be a quantum dot (QD), a quantum rod, a fluorescent material, or a phosphorescent material. For example, a quantum dot may be a particle material that emits a specific color when an electron transitions from a conduction band to a valence band.

[0170] Quantum dots can be semiconductor nanocrystal materials. Depending on their composition and size, quantum dots can have a specific band gap to absorb light and emit light with a unique wavelength. Examples of semiconductor nanocrystals of quantum dots include IV group nanocrystals, II-VI group compound nanocrystals, III-V group compound nanocrystals, IV-VI group compound nanocrystals, or a combination thereof.

[0171] The II-VI compounds are: binary compounds selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; binary compounds selected from the group consisting of InZnP, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZn Te, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; and a quaternary compound selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0172] The III-V compounds are: binary compounds selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof; ternary compounds selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, InPSb, GaAlNP and mixtures thereof; and quaternary compounds selected from the group consisting of GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof.

[0173] The IV-VI compound may be a binary compound selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; a ternary compound selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof; and a quaternary compound selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. The IV group element may be selected from the group consisting of Si, Ge, and mixtures thereof. The IV-IV compound may be a binary compound selected from the group consisting of SiC, SiGe, and mixtures thereof.

[0174] The binary, ternary or quaternary compound may be present in the particle at a uniform concentration, or may be present in the same particle at a partially different concentration distribution. The quantum dot may also have a core-shell structure in which one quantum dot surrounds another quantum dot. The interface of the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center.

[0175] In one embodiment, the quantum dot can have a core-shell structure including a core and a shell surrounding the core, the core including a nanocrystal as described above. The shell of the quantum dot can act as a protective layer to prevent the chemical denaturation of the core to maintain semiconductor properties and / or act as a charge layer to give the quantum dot electrophoretic properties. The shell can be a single layer or multiple layers. Examples of shells for quantum dots include metal or non-metal oxides, semiconductor compounds or combinations thereof.

[0176] For example, the metal or non-metal oxide may be SiO 2 、Al 2O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 or binary compounds such as NiO or MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 or CoMn 2 O 4 ternary compound, but the present disclosure is not limited thereto.

[0177] The semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, or the like, but is not limited thereto.

[0178] The scatterer SCP may scatter the light of the light emitting element LE in random directions. The scatterer SCP may have a refractive index different from that of the first base resin BRS1 and form an optical interface with the first base resin BRS1. For example, the scatterer SCP may be light scattering particles. The scatterer SCP is not particularly limited to any material capable of scattering at least a portion of the transmitted light, but may be, for example, metal oxide particles or organic particles. Examples of metal oxides include titanium oxide (TiO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 )、ZnO、SnO 2 ) or the like, and examples of the organic particulate material include acrylic resin or urethane resin. Regardless of the incident direction of the incident light, the scatterer SCP can scatter the light in random directions without substantially converting the wavelength of the light.

[0179] The second wavelength conversion layer WCL2 may be disposed to overlap with the second light emitting area EA2. The second wavelength conversion layer WCL2 may convert or shift the peak wavelength of the incident light into light having another specific peak wavelength and emit the light. In one embodiment, the second wavelength conversion layer WCL2 may convert the blue light emitted from the light emitting element LE of the second light emitting area EA2 into green light having a peak wavelength in the range of 510 nm to 550 nm and emit the green light.

[0180] The second wavelength conversion layer WCL2 may include a second base resin BRS2 and second wavelength conversion particles WCP2 and scatterers SCP dispersed in the second base resin BRS2.

[0181] The second base resin BRS2 may be made of a material having high light transmittance, and may be made of the same material as the first base resin BRS1, or may include at least one of the exemplary materials as a constituent material thereof.

[0182] The second wavelength conversion particles WCP2 may convert or shift the peak wavelength of the incident light into another specific peak wavelength. In one embodiment, the second wavelength conversion particles WCP2 may convert the blue light provided from the light emitting element LE into green light having a peak wavelength in the range of 510 nm to 550 nm and emit green light. Examples of the second wavelength conversion particles WCP2 include quantum dots, quantum rods, or phosphors. A more specific description of the second wavelength conversion particles WCP2 is substantially the same or similar to the above description in the description of the first wavelength conversion particles WCP1, and therefore will be omitted.

[0183] The light-transmitting layer TPL may be disposed to overlap the third light-emitting area EA3. The light-transmitting layer TPL may transmit incident light. The light-transmitting layer TPL may transmit blue light emitted from the light-emitting element LE disposed in the third light-emitting area EA3 as it is. The light-transmitting layer TPL may include a third base resin BRS3 and a scatterer SCP dispersed in the third base resin BRS3. Since the third base resin BRS3 is substantially the same as or similar to the above-described first base resin BRS1, a description thereof will be omitted.

[0184] The light transmitted through the wavelength control unit 200 (or controller) may realize full color by passing through a color filter layer CFL, which will be described later.

[0185] The wavelength control unit 200 (or controller) may further include a second cover layer CPL2. The second cover layer CPL2 covers the first wavelength conversion layer WCL1, the second wavelength conversion layer WCL2, the light transmission layer TPL, and the bank layer BNL disposed thereunder to protect them from moisture or foreign matter. The second cover layer CPL2 may include an inorganic material, and may include a material substantially the same as or similar to that of the first cover layer CPL1 described above.

[0186] First, second, and third color filters CF1, CF2, and CF3 may be disposed on the second cover layer CPL2. The first color filter CF1 is disposed in the first emission area EA1, the second color filter CF2 is disposed in the second emission area EA2, and the third color filter CF3 is disposed in the third emission area EA3.

[0187] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a colorant that absorbs wavelengths other than the corresponding color wavelengths, such as a dye or a pigment. The first color filter CF1 may selectively transmit red light and block or absorb blue light and green light. The second color filter CF2 may selectively transmit green light and block or absorb blue light and red light. The third color filter CF3 may selectively transmit blue light and block or absorb red light and green light. For example, the first color filter CF1 may be a red filter, the second color filter CF2 may be a green filter, and the third color filter CF3 may be a blue filter.

[0188] In one embodiment, the light incident on the first color filter CF1 may be light converted into red light by the first wavelength conversion layer WCL1, the light incident on the second color filter CF2 may be light converted into green light by the second wavelength conversion layer WCL2, and the light incident on the third color filter CF3 may be blue light transmitted through the light transmission layer TPL. As a result, the red light transmitted through the first color filter CF1, the green light transmitted through the second color filter CF2, and the blue light transmitted through the third color filter CF3 may be emitted onto the upper portion of the substrate 110 to achieve full color.

[0189] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can absorb some of the light introduced from the outside of the display device 10 to reduce the reflected light caused by the external light. Therefore, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can prevent color distortion caused by external light reflection.

[0190] The first color filter CF1 is disposed in the non-emission area NEA, and at least one of the second color filter CF2 and the third color filter CF3 may be further disposed overlapping each other. For example, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed in the non-emission area NEA.

[0191] Therefore, light emission from the display device 10 can be blocked in the non-emission area NEA, and reflection of external light can be suppressed. Each of the color filters CF1, CF2, and CF3 blocks emission of light of colors other than the corresponding color of each light emitting area EA1, EA2, and EA3, and therefore, red (R), green (G), and blue (B) light can all be blocked in the non-emission area NEA. However, the present disclosure is not limited thereto, and a light absorbing member including a light absorbing material that absorbs light of a visible light wavelength band can be provided in the non-emission area NEA.

[0192] The overcoat layer OC may be disposed on the color filter layer CFL. The overcoat layer OC may be disposed directly on the color filter layer CFL. The overcoat layer OC may be disposed as a whole in the display area DPA and may have a flat surface. The overcoat layer OC may flatten a step formed by the color filter layer CFL below. The overcoat layer OC may include a light-transmitting organic material.

[0193] In another modification, in one embodiment, the first light emitting element LE1 disposed in the first light emitting area EA1 may emit a blue first light, the second light emitting element LE2 disposed in the second light emitting area EA2 may emit a red second light, and the third light emitting element LE3 disposed in the third light emitting area EA3 may emit a green third light. In this way, in the case where the light emitting elements disposed in different light emitting areas may emit light of different wavelengths, the reference numeral 1 may be omitted. Figure 6 The wavelength control unit 200 (or controller) and the color filter layer CFL are described.

[0194] As described above, the display device 10 according to one embodiment can bond the light emitting elements LE to the substrate 110 by placing each light emitting element LE on the organic pattern layer OBL and forming the connection electrode 150. Therefore, for the light emitting elements LE in the display device 10, eutectic bonding requiring high heat and high pressure can be omitted.

[0195] Fig.10 is a schematic cross-sectional view of a display device according to an embodiment. Fig.11 yes Fig.10 Magnified view of area B. Fig.12 is a schematic plan view showing a light emitting area of ​​a display device.

[0196] Fig.11 and Fig.12 The implementation method is the same as above Figures 6 to 9The embodiment of the present invention is different in that the pixel electrodes PE1, PE2 and PE3 are disposed in the light emitting areas EA1, EA2 and EA3 and the organic pattern layer OBL is disposed on the pixel electrodes PE1, PE2 and PE3, and the common electrode CE is not disposed on the side of the light emitting element LE. Hereinafter, the description overlapping with the description of the above-mentioned embodiment will be omitted, and the differences will be described.

[0197] The pixel electrodes PE1, PE2, and PE3 may be disposed in the emission areas EA1, EA2, and EA3 and in the non-emission area NEA.

[0198] The organic pattern layer OBL may be disposed on the pixel electrodes PE1 , PE2 , and PE3 .

[0199] The organic pattern layer OBL may be disposed in an island pattern shape on the pixel electrodes PE1, PE2, and PE3. A planar shape of the organic pattern layer OBL may be similar to that of the pixel electrodes PE1, PE2, and PE3, but may be smaller than the pixel electrodes PE1, PE2, and PE3.

[0200] The light emitting element LE is disposed such that one end is buried in the organic pattern layer OBL. A portion of the contact electrode RFM of the light emitting element LE is disposed to be buried in the organic pattern layer OBL, and a portion of the contact electrode RFM of the light emitting element LE is exposed to the outside of the organic pattern layer OBL.

[0201] The connection electrode 150 may cover the pixel electrode PE and may extend along the side and upper surfaces of the organic pattern layer OBL on which the light emitting element LE is not disposed and along the side and upper surfaces of the contact electrode RFM.

[0202] Therefore, the connection electrode 150 electrically connects the pixel electrode PE and the light emitting element LE. The light emitting element LE contacts the pixel electrode PE at the side through the connection electrode 150.

[0203] The common electrode CE may be disposed on the light emitting element LE and the second via layer VIA2. For example, the common electrode CE is disposed on one surface or surfaces of the substrate 110 on which the light emitting element LE is formed, and may be formed to have a small thickness so that light can be emitted.

[0204] The common electrode CE may be directly disposed on the top surface and the side surface of the light emitting element LE. For example, the common electrode CE may contact the second semiconductor layer SEM2 as the upper surface of the light emitting element LE, and directly contact the reflective layer RFL as the side surface of the light emitting element LE. The common electrode CE may be a common layer disposed to cover the light emitting element LE and commonly connect the light emitting element LE.

[0205] Hereinafter, a manufacturing process of the display device 10 according to one embodiment will be described with reference to other drawings.

[0206] Figures 13 to 33 is a schematic diagram for explaining a method of manufacturing a display device according to one embodiment.

[0207] Figures 13 to 33 The structure according to the formation order of each layer of the display device 10 is shown as a schematic cross-sectional view. Figures 15 to 33 The manufacturing process of the light emitting element portion LEP is shown, and these processes can be roughly the same as Figure 7 In addition, the first light emitting area EA1 and the second light emitting area EA2 of the display device 10 are shown below. For ease of description, one light emitting element LE is disposed in one light emitting area (eg, the first light emitting area EA1), but is not limited thereto.

[0208] refer to Figures 13 to 22 , a light emitting element LE is formed on the base substrate BSUB.

[0209] For example, refer to Fig.13 , prepare a base substrate BSUB. The base substrate BSUB may include Al 2 O 3 However, it is not limited thereto, and in one embodiment, a case where the base substrate BSUB is a sapphire substrate will be described as an example.

[0210] Semiconductor material layers USEL, SEM2L, and SEM1L and an active material layer MQWL are formed on a base substrate BSUB. The semiconductor material layers USEL, SEM2L, and SEM1L and the active material layer MQWL grown by an epitaxial method may be formed by growing seed crystals. Methods for forming the semiconductor material layers USEL, SEM2L, and SEM1L and the active material layer MQWL include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), double thermal evaporation, sputtering, metal organic chemical vapor deposition (MOCVD), or the like, and are formed, for example, by metal organic chemical vapor deposition (MOCVD). However, it is not limited thereto.

[0211] The precursor material for forming the semiconductor material layers USEL, SEM2L and SEM1L and the active material layer MQWL is not particularly limited in the range that can be selected to form the main material. In one example, the precursor material may be a metal precursor including an alkyl group such as a methyl group or an ethyl group. For example, it may be a metal precursor such as trimethylgallium (Ga(CH 3 ) 3), trimethylaluminum (Al(CH 3 ) 3 ), triethyl phosphate ((C 2 H 5 ) 3 PO 4 ) compounds, but are not limited thereto.

[0212] For example, a third semiconductor material layer USEL is formed on the base substrate BSUB. Although the drawings show the third semiconductor material layer USEL being further stacked, it is not limited thereto and a layer may be formed. The third semiconductor material layer USEL may be provided to reduce the lattice constant difference between the second semiconductor material layer SEM2L and the base substrate BSUB. For example, the third semiconductor material layer USEL may include an undoped semiconductor that may be an N-type or P-type undoped material. In an embodiment, the third semiconductor material layer USEL may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0213] The second semiconductor material layer SEM2L, the active material layer MQWL, and the first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer USEL by using the above method.

[0214] The semiconductor material layers USEL, SEM2L, and SEM1L and the active material layer MQWL are etched to form first and second light emitting elements LE1 and LE2 (collectively referred to as light emitting elements LE).

[0215] For example, a first mask pattern MP1 is formed on the first semiconductor material layer SEM1L. The first mask pattern MP1 may be a hard mask including an inorganic material or a photoresist mask including an organic material. The first mask pattern MP1 prevents the underlying semiconductor material layers USEL, SEM2L, and SEM1L and the active material layer MQWL from being etched. The first mask pattern MP1 is used as a mask to etch (first etching) a portion of the semiconductor material layers USEL, SEM2L, and SEM1L and the active material layer MQWL to form a light emitting element LE.

[0216] like Fig.14 As shown in , on the base substrate BSUB, the semiconductor material layers USEL, SEM2L, and SEM1L and the active material layer MQWL not overlapping the first mask pattern MP1 are etched and removed, and the unetched portion overlapping the first mask pattern MP1 may be formed as a light emitting element LE.

[0217] The semiconductor material layers USEL, SEM2L, and SEM1L and the active material layer MQWL may be etched by a selected method. For example, within the spirit and scope of the present disclosure, the process of etching the semiconductor material layers USEL, SEM2L, and SEM1L and the active material layer MQWL may be dry etching, wet etching, reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma reactive ion etching (ICP-RIE), or the like. In the case of a dry etching method, anisotropic etching is possible, which may be suitable for vertical etching. In the case of utilizing the above etching method, the etchant may be Cl 2 or 2 However, it is not limited thereto.

[0218] The semiconductor material layers USEL, SEM2L and SEM1L and the active material layer MQWL overlapping the first mask pattern MP1 are not etched but formed into a light emitting element LE. Thus, the light emitting element LE is formed to include the third semiconductor layer USE, the second semiconductor layer SEM2, the active layer MQW and the first semiconductor layer SEM1.

[0219] refer to Fig.15 and Fig.16 A first insulating layer INS1 and a reflective layer RFL are formed on the base substrate BSUB on which the light emitting element LE is formed.

[0220] For example, an insulating material layer INSL is formed on the outer surface of the light emitting element LE. The insulating material layer INSL may be formed on the entire surface of the base substrate BSUB, and may be formed not only on the light emitting element LE but also on the upper surface of the base substrate BSUB exposed by the light emitting element LE. In addition, a reflective material layer RFLL is formed on the insulating material layer INSL. The reflective material layer RFLL is formed on the entire surface of the base substrate BSUB.

[0221] The second etching (second etching) is performed to partially remove the insulating material layer INSL to form the light emitting element LE including the first insulating layer INS1 and the reflective layer RFL.

[0222] For example, a second etching process may be performed in which a portion of the insulating material layer INSL and the reflective material layer RFLL are partially removed so that the insulating material layer INSL exposes the upper surface of the light emitting element LE but surrounds the side of the light emitting element LE. For example, in this process, a portion of the insulating material layer INSL may be removed to expose the upper surface of the first semiconductor layer SEM1 of the light emitting element LE. The process of partially removing the insulating material layer INSL may be performed by a process such as anisotropic dry etching or etch-back.

[0223] In another modification, an insulating material layer INSL is formed on the outer surface of the light emitting element LE, and the insulating material layer INSL is partially removed to form the first insulating layer INS1. Thereafter, a reflective material layer RFLL may be formed on the outer surface of the light emitting element LE, and the reflective material layer RFLL may be partially removed to form the reflective layer RFL.

[0224] refer to Fig.17 A second insulating layer INS2 having a first opening OP1 is formed around the light emitting element LE on which the first insulating layer INS1 and the reflective layer RFL are formed. The first opening OP1 is formed on an upper surface of the light emitting element LE.

[0225] The method of forming the second insulating layer INS2 is similar to that of the first insulating layer INS1. For example, an insulating material layer INSL is formed on the outer surface of the light emitting element LE. The insulating material layer INSL may be formed on the entire surface of the base substrate BSUB, and may be formed not only on the light emitting element LE but also on the upper surface of the base substrate BSUB exposed by the light emitting element LE. Subsequently, etching is performed to partially remove the insulating material layer INSL to form the second insulating layer INS2 having the first opening OP1 on the upper surface of the light emitting element LE. For example, an etching process may be performed to partially remove a portion of the insulating material layer INSL so that the insulating material layer INSL is exposed. Fig.16 At least a portion of the upper surface of the light emitting element LE manufactured in the process surrounds Fig.16 For example, in this process, a mask may be used to remove a portion of the insulating material layer INSL to form a first opening OP1 exposing the upper surface of the first semiconductor layer SEM1 of the light emitting element LE.

[0226] refer to Figures 18 to 22 , a contact electrode RFM covering one surface or the surface of the light emitting element LE is formed using a first photoresist PR1.

[0227] For example, refer to Fig.18 , a first photoresist PR1 is applied to cover the entire upper surface of the light emitting element LE to be planarized.

[0228] refer to Fig.19 The first photoresist PR1 is partially exposed to expose the top and side surfaces of the light emitting element LE. For example, a portion of the first photoresist PR1 may be removed to expose at least the first semiconductor layer SEM1 and the active layer MQW of the light emitting element LE, but is not limited thereto.

[0229] refer to Figure 20 to Figure 22, a contact electrode RFM is formed using a first photoresist PR1 that exposes a portion of the light emitting element LE. The contact electrode RFM may be formed similarly to the manufacturing process of the first insulating layer INS1. For example, at least one reflective material layer RFML is stacked on the base substrate BSUB. Thereafter, a second photoresist PR2 may be coated on the light emitting element LE, and the second photoresist PR2 may be etched by an etching process to form a contact electrode RFM surrounding the light emitting element LE. Therefore, a contact electrode RFM that surrounds at least the first semiconductor layer SEM1 and the active layer MQW of the light emitting element LE may be formed on the second insulating layer INS2. In addition, the contact electrode RFM contacts the first semiconductor layer SEM1 through the first opening OP1.

[0230] refer to Fig.23 Attach the first supporting film SPF1 to Fig. 22 A light emitting element LE is formed on a base substrate BSUB.

[0231] For example, the first supporting film SPF1 is attached to the light emitting element LE. The first supporting film SPF1 may be aligned on the light emitting element LE and attached to each of the contact electrodes RFM of the light emitting element LE. The light emitting elements LE may be arranged in large numbers so that they may be attached to the first supporting film SPF1 without detachment.

[0232] The first supporting film SPF1 may include a supporting layer and an adhesive layer disposed on the supporting layer. The supporting layer may be made of a transparent, mechanically stable material that allows light to penetrate. For example, within the spirit and scope of the present disclosure, the supporting layer may include a transparent polymer such as polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, or the like. The adhesive layer may include an adhesive material for bonding the light-emitting element LE. For example, within the spirit and scope of the present disclosure, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, or the like. The adhesive material may be a material whose adhesiveness changes as ultraviolet (UV) light or heat is applied, so that the adhesive layer can be easily separated from the light-emitting element LE.

[0233] refer to Fig.24 The base substrate BSUB is irradiated with the first laser to separate the light emitting elements LE (eg, the first light emitting element LE1 and the second light emitting element LE2) from the base substrate BSUB. The base substrate BSUB is separated from each third semiconductor layer USE of the light emitting elements LE.

[0234] The process for separating the base substrate BSUB may be a laser lift-off (LLO) process. The laser lift-off process utilizes a laser, and a KrF excimer laser (248 nm wavelength) may be used as a source. The energy density of the excimer laser is between 550 and 550 mJ / cm2 Up to 950550mJ / cm 2 The incident area can be 50×50μm 2 Up to 1×1cm 2 By irradiating the base substrate BSUB with laser, the base substrate BSUB can be separated from the light emitting element LE.

[0235] refer to Fig.25 , the first transfer film LFL1 is attached to the light emitting element LE separated from the base substrate BSUB.

[0236] For example, the first transfer film LFL1 is attached to each of the third semiconductor layers USE of the light emitting element LE. The first transfer film LFL1 may be aligned on the light emitting element LE and attached to each of the third semiconductor layers USE of the light emitting element LE.

[0237] The first transfer film LFL1 may include a stretchable material. Within the spirit and scope of the present disclosure, the stretchable material may include, for example, polyolefin, polyvinyl chloride (PVC), elastic silicone, elastic polyurethane, elastic polyisoprene, or the like. The first transfer film LFL1 may also include a supporting layer and an adhesive layer (such as the first supporting film SPF1 described above) to engage and support the light emitting element LE.

[0238] refer to Fig.26 , the first supporting film SPF1 is separated from the light emitting element LE, and the first transfer film LFL1 is stretched (first ORI). After applying ultraviolet light or heat to the first supporting film SPF1 to reduce the adhesive strength of the adhesive layer of the first supporting film SPF1, the first supporting film SPF1 may be physically or naturally separated. The light emitting elements LE may be arranged in a dot shape on the first transfer film LFL1 while being spaced apart from each other by an optional first distance D1.

[0239] The first transfer film LFL1 may be two-dimensionally stretched in the first direction DR1 and the second direction DR2. As the first transfer film LFL1 is stretched, the distance between the light emitting elements LE attached to the first transfer film LFL1 may be greater than Fig.25 The first distance D1 is greater than the second distance D2. The tensile strength (or tensile strength) of the first transfer film LFL1 may be adjusted according to the desired interval between the light emitting elements LE, and may be, for example, about 120 gf / inch. However, it is not limited thereto.

[0240] In this embodiment, it has been described as an example that the stretching process is performed once, but is not limited thereto. The stretching process may be performed a plurality of times.

[0241] refer to Fig. 27, the first transfer film LFL1 is bonded on the substrate 110 , and the light emitting element LE is electrically connected to the first pixel electrode PE1 and the second pixel electrode PE2 through the connection electrode 150 .

[0242] The first transfer film LFL1 is aligned on the substrate 110. At this time, the contact electrode RFM of the light emitting element LE formed on the first transfer film LFL1 is aligned to face the substrate 110. Figure 6 As shown in FIG. 1 , the substrate 110 may have pixel electrodes PE1 and PE2 and an organic pattern layer OBL formed thereon. The contact electrode RFM of the light emitting element LE is aligned to be disposed on the organic pattern layer OBL. The height h1 of the organic pattern layer OBL may be about 2 μm, but is not limited thereto.

[0243] The substrate 110 and the first transfer film LFL1 are bonded. For example, the contact electrode RFM of the light emitting element LE formed on the first transfer film LFL1 is aligned on the organic pattern layer OBL of the substrate 110. At this time, the contact electrode RFM of the light emitting element LE is in contact with the organic pattern layer OBL. Subsequently, heat and pressure are applied to the organic pattern layer OBL to cure the organic pattern layer OBL. As a result, the light emitting element LE and the organic pattern layer OBL are preliminarily bonded. The heat and pressure at this time are lower than the heat and pressure of the eutectic bonding process. For example, the eutectic bonding process is a relatively high temperature process of 200 to 400 degrees, while the organic material curing process is a relatively low temperature process of 80 to 200 degrees. Therefore, compared with the eutectic bonding process, the light emitting element LE can be bonded to the organic pattern layer OBL at a relatively low temperature and pressure.

[0244] The eutectic bonding process requires different heat and pressure conditions depending on the length and diameter of the light emitting element. In addition, it is difficult to uniformly achieve the state of the bonding metal in the eutectic bonding process, and the uneven state of the bonding metal may appear as brightness scattering. In one embodiment, since the bonding is performed using the organic pattern layer OBL, the problems caused by the eutectic bonding can be solved by omitting the eutectic bonding.

[0245] The first transfer film LFL1 is removed. The first transfer film LFL1 is separated from the light emitting element LE. After the adhesive strength of the adhesive layer of the first transfer film LFL1 is reduced by applying ultraviolet light or heat to the first transfer film LFL1, the first transfer film LFL1 may be physically or naturally separated. After the first transfer film LFL1 is separated, refer to Fig.28 , attaching the second supporting film SPF2 to the light emitting element LE.

[0246] refer to Figure 29 to Figure 31 , forming a connection electrode 150 and a first through hole layer VIA1 that electrically connect the pixel electrodes PE1 and PE2 and the light emitting element LE.

[0247] The connection electrode 150 may be formed by stacking an electrode material layer 150L to cover both the pixel electrodes PE1 and PE2 and the light emitting element LE, and etching the electrode material layer 150L through an etching process using the first via layer VIA1 as a mask to form the connection electrode 150 .

[0248] For example, refer to Fig.29 , the electrode material layer 150L is laminated to cover both the pixel electrodes PE1 and PE2 and the light emitting element LE. The electrode material layer 150L may be stacked along the top and side surfaces of the pixel electrodes PE1 and PE2 and extend along the top and side surfaces of the light emitting element LE. The electrode material layers 150L corresponding to different light emitting regions are spaced apart from each other.

[0249] refer to Fig.30 , a first via layer VIA1 is formed on the substrate 110 on which the light emitting element LE surrounded by the electrode material layer 150L is formed.

[0250] The first via layer VIA1 may be formed on the electrode material layer 150L. The first via layer VIA1 is formed on the electrode material layer 150L. The first via layer VIA1 may be formed at a height higher than that of the active layer MQW of the light emitting element LE.

[0251] refer to Fig.31 , the electrode material layer 150L is etched to form the connection electrode 150. The electrode material layer 150L may be etched using the first via layer VIA1 as a mask. Therefore, the height of the upper surface of the first via layer VIA1 is equal to one end portion of the connection electrode 150 disposed along the side of the light emitting element LE. The electrode material layer 150L may be etched using, for example, a wet etching process, but is not limited thereto.

[0252] Then, refer to Fig.32 , the first insulating layer INS1 of the light emitting element LE, portions of the reflective layer RFL and the second insulating layer INS2, and the third semiconductor layer USE are etched and removed.

[0253] For example, the first insulating layer INS1, the reflective layer RFL, and the second insulating layer INS2 surrounding the light emitting element LE are removed using a dry etching process. Only the portion of the first insulating layer INS1, the reflective layer RFL, and the second insulating layer INS2 surrounding the third semiconductor layer USE is removed to expose the third semiconductor layer USE. When the third semiconductor layer USE is exposed, the third semiconductor layer USE is removed using a dry etching process. Since the third semiconductor layer USE does not exhibit conductivity, it is removed in order to connect the common electrode CE. At this time, the first via layer VIA1 may be partially etched by the above-mentioned dry etching process and formed to be arranged inward from the side of the first insulating layer INS1, the reflective layer RFL, and the second insulating layer INS2.

[0254] refer to Fig.33 , a second via layer VIA2 and a common electrode CE are formed on the first via layer VIA1.

[0255] For example, the second via layer VIA2 may be formed on the first via layer VIA1. The second via layer VIA2 may be manufactured in the same manner as the first via layer VIA1 described above. The second via layer VIA2 may be formed to a height lower than that of the second semiconductor layer SEM2 of the light emitting element LE.

[0256] A common electrode CE may be formed on the light emitting element LE and the second through hole layer VIA2. The common electrode CE is continuously formed throughout the entire display area DPA. The common electrode CE covers the second through hole layer VIA2 and the light emitting element LE and directly contacts them. The common electrode CE is formed to directly contact the upper surface of the second semiconductor layer SEM2 of the light emitting element LE.

[0257] It is within the spirit and scope of this disclosure that Figure 6 As shown in , a display device 10 according to one embodiment is manufactured by forming a partition wall portion, a wavelength control layer, a color filter layer, and the like.

[0258] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the claims and their equivalents to be included therein.

Claims

1. A display device, comprising: A pixel electrode is disposed on the substrate; an organic pattern layer, disposed on the substrate and spaced apart from the pixel electrode; A light emitting element is disposed on the organic pattern layer, wherein the light emitting element comprises a contact electrode contacting the organic pattern layer and a first semiconductor layer, an active layer and a second semiconductor layer sequentially disposed on the contact electrode; as well as connecting electrodes to electrically connect the pixel electrodes to the contact electrodes, Wherein, the connecting electrode is arranged along the upper surface of the pixel electrode, the side surface of the organic pattern layer and the side surface of the contact electrode.

2. The display device according to claim 1, wherein: The display device defines a light emitting area and a non-emitting area, and The organic pattern layer overlaps the light emitting area and does not overlap the non-emitting area.

3. The display device according to claim 2, wherein: The organic pattern layer has an island pattern shape.

4. The display device according to claim 2, wherein: The contact electrode comprises: a first portion disposed on and contacting the first semiconductor layer; and The second portion extends from the first portion and surrounds side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer.

5. The display device according to claim 4, wherein: The connection electrode surrounds the side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer on the contact electrode.

6. The display device according to claim 4, further comprising: A first through-hole layer is provided on the connecting electrode and the substrate on which the connecting electrode is not provided; A second through-hole layer, disposed on the first through-hole layer; as well as The common electrode is arranged on the light emitting element.

7. The display device according to claim 6, wherein: An upper surface of the first via layer has the same height as an end portion of the connection electrode disposed along the second portion of the contact electrode.

8. The display device according to claim 2, wherein: The pixel electrode overlaps the non-emitting area and does not overlap the light emitting area.

9. The display device according to claim 4, wherein: The light emitting element further includes a first insulating layer surrounding the first semiconductor layer, the active layer, the side surfaces of the second semiconductor layer and the lower surface of the first semiconductor layer, the first insulating layer having a first opening on the first semiconductor layer, and The contact electrode directly contacts the first semiconductor layer through the first opening of the first insulating layer.

10. The display device according to claim 9, wherein: The light emitting element further comprises: a second insulating layer surrounding the side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer; and a reflective layer surrounding the first semiconductor layer, the active layer and the side surface of the second semiconductor layer on the second insulating layer, and The first insulating layer is disposed on the reflective layer and directly contacts the second portion of the contact electrode.

11. The display device according to claim 10, wherein: The reflective layer is surrounded by the first insulating layer and the second insulating layer and does not contact the contact electrode.

12. The display device according to claim 6, further comprising: a partition wall portion disposed on the common electrode and overlapping the non-emitting region; a wavelength conversion layer disposed between the partition walls; as well as The color filter layer is disposed on the wavelength conversion layer.

13. A display device, comprising: A pixel electrode is disposed on the substrate; An organic pattern layer, disposed on the pixel electrode; A light emitting element is disposed on the organic pattern layer, wherein the light emitting element comprises a contact electrode contacting the organic pattern layer and a first semiconductor layer, an active layer and a second semiconductor layer sequentially disposed on the contact electrode; as well as connecting electrodes to electrically connect the pixel electrodes to the contact electrodes, in, A portion of the upper surface of the pixel electrode does not overlap with the organic pattern layer, and The connection electrode is disposed on the portion of the upper surface of the pixel electrode that does not overlap the organic pattern layer, a side surface of the organic pattern layer, and a side surface of the contact electrode.

14. The display device according to claim 13, wherein: The contact electrode comprises: a first portion disposed on and contacting the first semiconductor layer; and The second portion extends from the first portion and surrounds side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer.

15. The display device according to claim 14, wherein: The connection electrode surrounds side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer on the contact electrode.

16. The display device according to claim 14, further comprising: A first through-hole layer is provided on the connecting electrode and the substrate on which the connecting electrode is not provided; A second through-hole layer, disposed on the first through-hole layer; as well as The common electrode is arranged on the light emitting element.

17. The display device according to claim 16, wherein: An upper surface of the first via layer has the same height as an end portion of the connection electrode disposed along the second portion of the contact electrode.

18. The display device according to claim 15, wherein: The light emitting element further includes a first insulating layer surrounding the first semiconductor layer, the active layer, the side surfaces of the second semiconductor layer and the lower surface of the first semiconductor layer, the first insulating layer having a first opening on the first semiconductor layer, and The contact electrode directly contacts the first semiconductor layer through the first opening of the first insulating layer.

19. The display device according to claim 18, wherein: The light emitting element further comprises: a second insulating layer surrounding the side surfaces of the first semiconductor layer, the active layer, and the second semiconductor layer; and a reflective layer surrounding the first semiconductor layer, the active layer and the side surface of the second semiconductor layer on the second insulating layer, and The first insulating layer is disposed on the reflective layer and directly contacts the second portion of the contact electrode.

20. The display device according to claim 16, wherein: The display device defines a light emitting area and a non-emitting area, and The display device further includes: a partition wall portion disposed on the common electrode and overlapping the non-emitting region; a wavelength conversion layer disposed between the partition wall portions; and The color filter layer is disposed on the wavelength conversion layer.

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