Display device and manufacturing method thereof

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a display area including a plurality of pixels and spacers extending around the pixels, and a peripheral area positioned around the display area and including a scan driver and an electrostatic element unit. Each pixel includes a pixel electrode, a light-emitting auxiliary layer, and a common electrode. The light-emitting auxiliary layer is broken at a spacer between adjacent pixels. The electrostatic element unit includes a first voltage line electrically connected to the scan driver and a plurality of electrostatic elements electrically connected to the first voltage line. A plurality of contact holes overlaps a first voltage line positioned in the electrostatic element unit, and an insulating layer is positioned in the contact holes.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0091014 filed in the Korean Intellectual Property Office on July 13, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device and a method for manufacturing the same. Background Art

[0003] The display device is a device that displays an image and may include a liquid crystal display (LCD) and an organic light emitting display (OLED), etc. Such a display device may be used in various electronic devices such as mobile phones, navigation devices, digital cameras, e-books, portable game consoles, and various terminals.

[0004] A type of display device includes a plurality of pixels, the plurality of pixels include light emitting diodes, which are self-luminous elements, and each pixel may also include a plurality of transistors and at least one capacitor for driving the light emitting diode or the plurality of light emitting diodes in the pixel. The plurality of pixels may include pixels capable of emitting light of different colors.

[0005] A light emitting diode may include two electrodes and a light emitting layer and / or a light emitting auxiliary layer located between the two electrodes. During operation, electrons injected from one electrode and holes injected from the other electrode may recombine in the light emitting layer and release energy which may be in the form of emitted light.

[0006] The manufacture of a display device generally includes processes of stacking and patterning several layers on a substrate, and the substrate needs to be transferred between processes. Summary of the invention

[0007] The embodiments disclosed herein may prevent spots from occurring on a display device by preventing display defects due to leakage current between pixels of the display device or by preventing changes in transistor characteristics due to charging during a manufacturing process.

[0008] The display device according to the embodiment includes a display area and a peripheral area, the display area includes a plurality of pixels and a partition extending around the pixels, and the peripheral area is located around the display area and includes a scan driver and an electrostatic element unit. Each pixel in the pixel includes: a pixel electrode; a portion of a light-emitting auxiliary layer, located on the pixel electrode; and a portion of a common electrode, located on the auxiliary light-emitting layer. Between adjacent pixels, the partition disconnects the portion of the light-emitting auxiliary layer. The electrostatic element unit includes a first voltage line electrically connected to the scan driver and a plurality of electrostatic elements electrically connected to the first voltage line. A plurality of contact holes overlapping the first voltage line are positioned in the electrostatic element unit, and an insulating layer is in the contact holes.

[0009] A passivation layer located on the first voltage line and having a contact hole formed therein may further be included, and the insulating layer may contact a side surface of the passivation layer defining the contact hole and an upper surface of the first voltage line.

[0010] The insulating layer may include a portion positioned on an upper surface of the passivation layer.

[0011] A pixel insulating layer on the passivation layer and the pixel electrode may further be included, and the spacer may be formed in a concave shape on an upper surface of the pixel insulating layer.

[0012] The display device may further include a substrate and a transistor disposed between the substrate and the passivation layer, and the pixel electrode may be electrically connected to the transistor.

[0013] A plurality of data lines connected to the plurality of electrostatic elements may also be included, the plurality of data lines intersecting the first voltage line, and the plurality of contact holes may be positioned between adjacent data lines on a plane.

[0014] The electrostatic element unit may further include an electrostatic semiconductor layer forming the plurality of electrostatic elements, and the plurality of contact holes may not overlap the electrostatic semiconductor layer in a plane.

[0015] The residue including the metal oxide may also be included in a partial region within the contact hole.

[0016] A light emitting layer may be provided between the pixel electrode and the common electrode or between the light emitting auxiliary layer and the pixel electrode.

[0017] According to an embodiment, a display device includes: a substrate including a display area and a peripheral area outside the display area; a transistor located above the display area; an electrostatic element and a first voltage line and a second voltage line, the electrostatic element being located above the peripheral area, the first voltage line and the second voltage line being electrically connected to the electrostatic element; a passivation layer located on the transistor, the first voltage line and the second voltage line; a plurality of pixel electrodes located on the passivation layer and located in the display area; and a pixel insulating layer located on the passivation layer and the pixel electrode; and a light-emitting auxiliary layer and a light-emitting layer located on the pixel electrode and the pixel insulating layer, wherein the pixel insulating layer is located between adjacent pixel electrodes among the plurality of pixel electrodes and includes a concave-shaped partition, and the passivation layer has a contact hole located on the first voltage line in the peripheral area.

[0018] The passivation layer may cover all of the second voltage lines in the peripheral region.

[0019] The display device may further include a plurality of data lines connected to the plurality of electrostatic elements, the data lines crossing the first voltage line and the second voltage line, and the plurality of contact holes may be positioned between adjacent data lines on a plane.

[0020] The display device may further include an electrostatic semiconductor layer forming the plurality of electrostatic elements, and the plurality of contact holes may not overlap the electrostatic semiconductor layer in a plane.

[0021] The residue including the metal oxide may also be included in a partial region within the contact hole.

[0022] An insulating layer may further be included, the insulating layer including a portion located within the contact hole and contacting the passivation layer defining a side surface of the contact hole and an upper surface of the first voltage line.

[0023] The insulating layer may include a portion positioned on an upper surface of the passivation layer.

[0024] The light emitting auxiliary layer may be disconnected from the partition.

[0025] According to an embodiment, a method for manufacturing a display device includes: forming a plurality of transistors on a substrate, the plurality of transistors being located on a display area; forming a plurality of electrostatic elements and voltage lines, the plurality of electrostatic elements and voltage lines being located in a peripheral area, the peripheral area being around the display area; stacking a passivation layer on the voltage lines; forming contact holes in the passivation layer to expose the voltage lines, the contact holes being positioned in the peripheral area; forming a plurality of pixel electrodes in the display area; forming a pixel insulating layer on the pixel electrodes and patterning the pixel insulating layer to form a first opening located on the pixel electrodes; depositing a mask layer on the entire surface of the substrate and patterning the mask layer to form a second opening located between adjacent pixel electrodes; using the second opening as a mask to remove a portion of the upper surface of the pixel insulating layer corresponding to the second opening to form a partition in the shape of a recessed hole on the upper surface of the pixel insulating layer; and removing the mask layer on the entire surface of the substrate, wherein the stacked mask layer is electrically connected to the voltage lines through the contact holes.

[0026] The mask layer may include metal oxide.

[0027] The process may also include the following steps: stacking a light-emitting auxiliary layer on the pixel electrode and the pixel insulating layer; forming a common electrode on the light-emitting auxiliary layer; and forming an insulating layer on the substrate, the light-emitting auxiliary layer may include a portion blocked by the partition, and the insulating layer may include a portion positioned inside the contact hole.

[0028] According to the embodiments, display defects due to leakage current between a plurality of pixels of a display device may be prevented, and characteristic variations of transistors due to charging during a manufacturing process may be prevented to prevent spots from occurring. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a plan view of a display device according to an embodiment.

[0030] Figure 2is a plan view of a portion of a display area of ​​a display device according to an embodiment.

[0031] Figure 3 is a cross-sectional view of one pixel in a display area of ​​a display device according to an embodiment.

[0032] Figure 4 is a plan view of an electrostatic element unit in a peripheral area of ​​a display device according to an embodiment.

[0033] Figure 5 is a circuit diagram of an electrostatic element unit in a peripheral area of ​​a display device according to an embodiment.

[0034] Figure 6 , Figure 7 and Figure 8 yes Figure 4 0 is a cross-sectional view of the display device shown in taken along line A1 - A2 .

[0035] Fig. 9 is a circuit diagram of an electrostatic element unit in a peripheral area of ​​a display device according to an embodiment.

[0036] Fig.10 , Fig.11 and Fig.12 yes Fig. 9 0 is a cross-sectional view of the display device shown in taken along line B1 - B2 .

[0037] Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 and Fig. 20 is a cross-sectional view of a structure formed during a method of manufacturing a display device according to an embodiment.

[0038] Fig.21 , Fig. 22 , Fig.23 and Fig.24 is a cross-sectional view of a display device in a manufacturing process of the display device according to the embodiment.

[0039] Fig.25 is a cross-sectional view of a display device in a manufacturing process of the display device according to a comparative example.

[0040] Fig.26 and Fig. 27 A manufacturing process of a display device according to a comparative example and smudges displayed on an image of the display device are shown. DETAILED DESCRIPTION

[0041] Various embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can make or use the embodiments. The disclosed embodiments may take many different forms, and the disclosure is not limited to the specific embodiments set forth herein. In order to provide a clear description, parts or elements that are known or irrelevant to the description may be omitted.

[0042] In the drawings, the same reference numerals are assigned to the same or similar components throughout the specification. In addition, for ease of explanation, the shape, size or thickness of each component in the drawings may be changed, and the present disclosure is not necessarily limited to the shapes, sizes or thicknesses shown. For example, in the drawings, the thickness may be enlarged or exaggerated in order to clearly indicate various layers and regions or for ease of explanation.

[0043] In the specification, when a component such as a layer, film, region, or plate is referred to as being “on” or “over” another component, this includes not only a case where the component is “directly on” the other component but also a case where another component is between the two components. Conversely, a component referred to as being “directly on” another component means that there are no other components therebetween.

[0044] Furthermore, “above” or “on” a reference component means positioned above or below the reference component, and does not necessarily mean positioned “above” or “on” the reference component in an opposite direction of gravity.

[0045] Furthermore, throughout the specification, unless explicitly stated otherwise, a component referred to as “comprising” a component means that the component may further include other components without excluding the other components.

[0046] Furthermore, throughout the specification, reference to a “planar image” means a view of a target component viewed from above a main surface of the component, and reference to a “cross-sectional image” means cutting the target component along a section line and viewing the target component from a direction perpendicular to the cut.

[0047] Will refer to Figures 1 to 12 A display device according to an embodiment will be described.

[0048] Figure 1 is a top plan view of the display device 1000 according to the embodiment. A view viewing a surface extending in the first direction DR1 and the second direction DR2 may be referred to herein as a plan view, and a view viewing a section perpendicular to the plan view may be referred to herein as a cross-sectional view.

[0049] Reference Figure 1The display device 1000 includes a substrate 110, the substrate 110 includes a display area DA and a peripheral area PA, the display area DA is an area capable of displaying an image, and the peripheral area PA is around the display area DA. The display area DA may include a plurality of pixels PX that may be used to display an image. The peripheral area PA may or may not display an image, and may or may not include pixels PX capable of displaying an image.

[0050] The substrate 110 has a major surface parallel to the first direction DR1 and a second direction DR2 perpendicular to the first direction DR1 , and a direction perpendicular to the major surface of the substrate 110 may be referred to herein as upward or as a third direction DR3 .

[0051] The display area DA may include a plurality of pixels PX, which are units capable of displaying an image. Each pixel PX may include at least one transistor, a light emitting device, and a capacitor.

[0052] The display area DA may further include a plurality of signal lines or voltage lines electrically connected to the pixels PX to apply signals or voltages. The plurality of signal lines or voltage lines may include a plurality of scan lines SL capable of transmitting scan signals to the pixels PX and a plurality of data lines DL capable of transmitting data signals to the pixels PX. In a plan view, the data lines DL may extend substantially in the second direction DR2, but are not limited thereto. In a plan view, the scan lines SL may extend substantially in the first direction DR1, but are not limited thereto.

[0053] The peripheral area PA may include a scan driver 700 that is connected to the plurality of scan lines SL and may supply a scan signal, an electrostatic element unit 710 , a wiring extension 730 , and a pad (also referred to as a “pad”) unit 720 .

[0054] The scan driver 700 may include transistors directly formed on the substrate 110 together with transistors located in the display area DA. Portions of the scan driver 700 may be located in the left and right portions of the peripheral area PA relative to the display area DA, but the scan driver 700 is not limited thereto and may be located only in one portion of the peripheral area PA. The scan lines SL may extend to the peripheral area PA and be connected to the scan driver 700.

[0055] The electrostatic element unit 710 may be located in the peripheral area PA below and / or above the display area DA, and may include a plurality of electrostatic diodes or a plurality of electrostatic transistors on the substrate 110, which may release static electricity charged therein. The data line DL may extend to the peripheral area PA and be connected to the electrostatic element unit 710.

[0056] The pad unit 720 may be located close to an edge of the substrate 110 adjacent to the peripheral area PA where the electrostatic element unit 710 is located. That is, the electrostatic element unit 710 may be located between the pad unit 720 and the display area DA.

[0057] The data line DL passing through the electrostatic element unit 710 may extend to the pad unit 720 and be electrically connected to a plurality of pads positioned on the pad unit 720. The data line DL extending to the peripheral area PA may include a wiring extension 730. The wiring extension 730 may be positioned between the electrostatic element unit 710 and the pad unit 720, and may include a plurality of wirings connecting the electrostatic element unit 710 and the pad unit 720. The wiring extension 730 may form a fan-out shape in which a gap or interval between wirings in the wiring extension 730 may be wider at the electrostatic element unit 710 and may be narrowed toward the pad unit 720.

[0058] The substrate 110 may be bent in the region where the wiring extension 730 is located, and the peripheral region PA where the pad unit 720 is located may be folded toward the rear surface of the substrate 110. A data driver supplying a data signal and / or a driving voltage may be mounted on the pad unit 720 in the form of an integrated circuit chip or a circuit board.

[0059] The voltage line 800 electrically connected to the scan driver 700 and the electrostatic element unit 710 may be positioned in the peripheral area PA. The voltage line 800 may include a portion extending substantially in the second direction DR2 along an edge of the substrate 110 adjacent to the peripheral area PA where the scan driver 700 is positioned. The voltage line 800 may transmit a specific voltage to the scan driver 700 and the electrostatic element unit 710. The voltage line 800 may include two or more voltage lines that transmit two or more voltages.

[0060] Figure 2 is a plan view of a portion of a display area of ​​a display device according to an embodiment.

[0061] Reference Figure 2 , a plurality of pixel electrodes 191 corresponding to each pixel PX are located in the display area DA. Each pixel electrode 191 may be an anode electrode of a light-emitting device, but is not limited thereto. A group of pixel electrodes 191 adjacent to each other may include a plurality of pixel electrodes 191a, 191b, and 191c having different planar sizes. The light-emitting regions LEAa, LEAb, and LEAc, which are regions emitting light from each pixel PX, may be positioned to overlap with the corresponding pixel electrodes 191a, 191b, and 191c. A group of light-emitting regions LEAa, LEAb, and LEAc adjacent to each other may emit light of different colors. For example, the light-emitting region LEAa may emit red light, the light-emitting region LEAb may emit green light, and the light-emitting region LEAc may emit blue light.

[0062] The display area DA may include a partition 357 extending around each of the pixel electrodes 191a, 191b, and 191c. Each partition 357 may be a structure that disconnects and separates at least one layer or region constituting the light emitting device (i.e., an anode electrode layer, a cathode electrode layer, a light emitting layer, a light emitting auxiliary layer) from at least one layer or region of an adjacent light emitting region LEAa, LEAb, LEAc or an adjacent pixel. Each partition 357 may protrude in the third direction DR3, or may have a concave shape.

[0063] A plurality of partitions 357 located around one pixel electrode 191a, 191b, or 191c and extending in different directions may be separated from each other without being connected to each other. That is, a plurality of partitions 357 located around one pixel electrode 191a, 191b, or 191c and extending in different directions may not form a closed curve shape, and the spacing region 357s may be positioned between adjacent partitions 357.

[0064] Figure 3 is a cross-sectional view of one pixel in a display area of ​​a display device according to an embodiment.

[0065] Reference Figure 3 , the first insulating layer 120 may be located on the substrate 110. The substrate 110 may include a rigid material that does not bend (such as glass), or may include a flexible material that can bend (such as plastic or polyimide). The first insulating layer 120 may also be referred to as a buffer layer. The first insulating layer 120 may include an inorganic insulating material or an organic insulating material, such as silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y ).

[0066] The first semiconductor layer 130a of the first transistor DQ may be located on the first insulating layer 120, and the first transistor DQ may be a driving transistor. The first semiconductor layer 130a may include a channel region 132a and a first electrode 131a and a second electrode 133a connected to opposite sides of the channel region 132a. The first semiconductor layer 130a may include, for example, a polycrystalline semiconductor material.

[0067] The lower layer 121 may be further located between the first semiconductor layer 130a and the substrate 110. The lower layer 121 may block light that may otherwise be incident on the first semiconductor layer 130a, and may include a metal or a metal alloy such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti). Alternatively, the lower layer 121 may include amorphous silicon, and the lower layer 121 may be composed of a single layer or multiple layers.

[0068] The first gate insulating layer 141 may be located on the first semiconductor layer 130a. The first gate insulating layer 141 may have a single layer or a multi-layer structure. The first gate insulating layer 141 may include an inorganic insulating material such as silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ).

[0069] The first gate conductive layer including the gate electrode 151 of the first transistor DQ may be located on the first gate insulating layer 141. The first gate conductive layer may have a single layer or a multilayer structure. The first gate conductive layer may include a metal material such as molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti). The gate electrode 151 of the first transistor DQ may overlap with the channel region 132a of the first transistor DQ.

[0070] The second gate insulating layer 142 may be located on the first gate conductive layer and the first gate insulating layer 141. The second gate insulating layer 142 may have a single layer or a multi-layer structure. The second gate insulating layer 142 may include an inorganic insulating material such as silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ).

[0071] The second gate conductive layer including the storage electrode 152 may be located on the second gate insulating layer 142. The second gate conductive layer may have a single layer or a multilayer structure. The second gate conductive layer may include a metal material such as molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti). The storage electrode 152 may overlap with the gate electrode 151 of the first transistor DQ and the second gate insulating layer 142 is between the storage electrode 152 and the gate electrode 151 to form a capacitor. The driving voltage may be transmitted to the storage electrode 152.

[0072] The first interlayer insulating layer 161 may be located on the second gate conductive layer and the second gate insulating layer 142. The first interlayer insulating layer 161 may have a single layer or a multi-layer structure. The first interlayer insulating layer 161 may include an inorganic insulating material such as silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ).

[0073] The second semiconductor layer 130b of the second transistor SQ may be located on the first interlayer insulating layer 161, and the second transistor SQ may be a switching transistor. The second semiconductor layer 130b may include a channel region 132b and a first electrode 131b and a second electrode 133b connected to opposite sides of the channel region 132b. The second semiconductor layer 130b may include, for example, an oxide semiconductor material. For example, the second semiconductor layer 130b may include a monometallic oxide (such as indium oxide (In 2 O 3 ), tin oxide (SnO 2 ) or zinc oxide (ZnO)), binary metal oxides (such as In-Zn oxides, Sn-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides or In-Ga oxides), ternary metal oxides (such as In-Ga-Zn oxides, In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides The second semiconductor layer 130b may include at least one of the Sn-Hf-Zn oxide and the In-Hf-Al-Zn oxide. For example, the second semiconductor layer 130b may include indium gallium zinc oxide (IGZO) among the In-Ga-Zn oxides.

[0074] The second gate conductive layer may further include a light blocking layer overlapping with or under the second semiconductor layer 130 b .

[0075] The third gate insulating layer 143 may be located on the second semiconductor layer 130b. The third gate insulating layer 143 may be formed on the entire surface of the substrate 110, and may be formed on the second semiconductor layer 130b. Figure 3As shown in FIG. 1 , the third gate insulating layer 143 overlaps the channel region 132 b of the second semiconductor layer 130 b, and the third gate insulating layer 143 may be patterned so as not to overlap the remaining portion of the second semiconductor layer 130 b. The third gate insulating layer 143 may have a single layer or a multilayer structure. The third gate insulating layer 143 may include an inorganic insulating material such as silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ).

[0076] The third gate conductive layer including the gate electrode 153 of the second transistor SQ may be located on the third gate insulating layer 143. The third gate conductive layer may have a single layer or a multilayer structure. The third gate conductive layer may include a metal material such as molybdenum (Mo), aluminum (Al), copper (C) and / or titanium (Ti). The gate electrode 153 of the second transistor SQ may overlap with the channel region 132b of the second transistor SQ.

[0077] The second interlayer insulating layer 162 may be located on the third gate conductive layer. The second interlayer insulating layer 162 may have a single layer or a multilayer structure. The second interlayer insulating layer 162 may include an inorganic insulating material such as silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ).

[0078] A first data conductive layer including a plurality of connection electrodes 171 a , 171 b , 173 a , and 173 b may be positioned on the second interlayer insulating layer 162 .

[0079] The connection electrode 171a is connected to the first transistor DQ through a contact hole formed in the first gate insulating layer 141, the second gate insulating layer 142, the first interlayer insulating layer 161, and the second interlayer insulating layer 162. The connection electrode 171a may be electrically connected to the first electrode 131a of the first transistor DQ.

[0080] The connection electrode 173a is connected to the first transistor DQ through a contact hole formed in the first gate insulating layer 141, the second gate insulating layer 142, the first interlayer insulating layer 161 and the second interlayer insulating layer 162, and the connection electrode 173a may be electrically connected to the second electrode 133a of the first transistor DQ.

[0081] The connection electrode 171 b may be electrically connected to the first electrode 131 b of the second transistor SQ through a contact hole formed in the second interlayer insulating layer 162 .

[0082] The connection electrode 173 b may be electrically connected to the second electrode 133 b of the second transistor SQ through a contact hole formed in the second interlayer insulating layer 162 .

[0083] The first passivation layer 180 may be located on the first data conductive layer.

[0084] The second data conductive layer including the connection electrode 175 may be located on the first passivation layer 180. The second data conductive layer may include a data line. The connection electrode 175 is electrically connected to the connection electrode 173a of the first data conductive layer through the contact hole 183 in the first passivation layer 180, and through this, the connection electrode 175 is electrically connected to the second electrode 133a of the first transistor DQ.

[0085] Each of the first data conductive layer and the second data conductive layer may have a single layer or multi-layer structure. The first data conductive layer and the second data conductive layer may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and / or copper (Cu).

[0086] The second passivation layer 181 may be located on the second data conductive layer.

[0087] Each of the first passivation layer 180 and the second passivation layer 181 may have a single layer or a multi-layer structure. The first passivation layer 180 and the second passivation layer 181 may include a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, polyimide, an acrylic polymer, an organic insulating material such as a siloxane-based polymer, or an inorganic insulating material.

[0088] The pixel electrode 191 may be located on the second passivation layer 181. The pixel electrode 191 is electrically connected to the connection electrode 175 of the second data conductive layer through a contact hole 185 in the second passivation layer 181, and through this, the pixel electrode 191 is connected to the second electrode 133a of the first transistor DQ.

[0089] The pixel insulating layer 350 may be located on the pixel electrode 191. The pixel insulating layer 350 may also be referred to as a wall, and may have an opening 355 located above the pixel electrode 191. The pixel insulating layer 350 may include an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin. The pixel insulating layer 350 may include one or more partitions 357.

[0090] Figure 3An example is shown in which a partition 357 is formed on the top surface of the pixel insulating layer 350 and has a concave hole shape extending in the third direction DR3. The depth of the partition 357 in the third direction DR3 may be smaller than the thickness of the pixel insulating layer 350 in the third direction DR3. That is, the pixel insulating layer 350 may remain without being completely removed where the partition 357 is formed. Figure 2 As shown in , each of the spacers 357 may have a shape extending along the periphery of each pixel electrode 191 in a plan view.

[0091] At least one light emitting auxiliary layer 371 and light emitting layer 372 may be positioned on the pixel insulating layer 350 and the pixel electrode 191. The light emitting auxiliary layer 371 may include at least one of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.

[0092] The light emitting layer 372 may include a light emitting material that emits light of a color expressed by each pixel PX. Most of the light emitting layer 372 may be located within the opening 355 in the pixel insulating layer 350. In the opening 355, a portion of the light emitting auxiliary layer 371 may be located between the light emitting layer 372 and the pixel electrode 191, and a portion of the light emitting auxiliary layer 371 may be located on the light emitting layer 372.

[0093] exist Figure 3 , only the light-emitting auxiliary layer 371 between the pixel electrode 191 and the light-emitting layer 372 is shown, but at least one light-emitting auxiliary layer may also be located on the pixel electrode 191. For example, when the pixel electrode 191 is used as an anode electrode, the light-emitting auxiliary layer 371 between the pixel electrode 191 and the light-emitting layer 372 may include at least one of a hole injection layer and a hole transport layer, and another light-emitting auxiliary layer located on the light-emitting layer 372 may include at least one of an electron injection layer and an electron transport layer.

[0094] The light-emitting auxiliary layer 371 may also include a portion located on the pixel insulating layer 350. The light-emitting auxiliary layer 371 may be blocked by a partition 357 located around the pixel electrode 191. Therefore, the light-emitting auxiliary layer 371 is not continuous between adjacent pixels PX and may be interrupted and separated by the partition 357 to prevent display defects caused by lateral leakage between pixels PX. The light-emitting auxiliary layer 371 may have a side end surface 375 overlapping the partition 357 or located around the partition 357. The side end surface 375 of the light-emitting auxiliary layer 371 may be aligned with the edge of the partition 357 or may not be aligned with the edge of the partition 357.

[0095] The common electrode 270 may be located on the light-emitting auxiliary layer 371 and the light-emitting layer 372. The common electrode 270 may be used as a cathode electrode of the light-emitting device. That is, the pixel electrode 191, the light-emitting layer 372 and the common electrode 270 may together constitute a light-emitting diode ED. The light-emitting diode ED may include the light-emitting auxiliary layer 371.

[0096] The common electrode 270 may be formed throughout a plurality of pixels PX and thus may also include a portion located on the pixel insulating layer 350. Portions of the common electrode 270 may be blocked or separated by the partition 357 located around the pixel electrode 191. Thus, the common electrode 270 between adjacent pixels PX may include a discontinuous disconnected portion. Figure 2 As shown in FIG. 1 , the spacers 357 positioned around each pixel electrode 191 are spaced apart from each other, so that Figure 2 In the spacing area 357s shown in FIG. 3 , the common electrodes 270 of adjacent pixels PX are electrically connected to each other, and the common voltage transmitted by the common electrode 270 can be transmitted to the entire display area DA. The common electrode 270 may have a side end surface 275 overlapping the partition 357 or located around the partition 357. The side end surface 275 of the common electrode 270 may be aligned with the edge of the partition 357 or may not be aligned with the edge of the partition 357.

[0097] Figure 4 is a top plan view of an electrostatic element unit in a peripheral area of ​​a display device according to an embodiment.

[0098] Reference Figure 4 , the electrostatic element unit 710 according to one embodiment may include a voltage line 800 , a data line DL, and a plurality of electrostatic elements 850 a , 850 b , 850 c , and 850 d electrically connected to the voltage line 800 and the data line DL.

[0099] The voltage line 800 may include a low voltage line 810 transmitting a low voltage and a high voltage line 820 transmitting a voltage higher than the low voltage line 810. In the electrostatic element unit 710, the low voltage line 810 and the high voltage line 820 may extend in a direction crossing the data line DL.

[0100] The electrostatic elements 850a, 850b, 850c, and 850d may include various elements capable of discharging static electricity. For example, the electrostatic element may include an electrostatic diode or an electrostatic transistor. Figure 4 An example is shown in which the electrostatic element includes a plurality of electrostatic diodes. The plurality of electrostatic diodes may be connected in series, and may include an electrostatic semiconductor layer 830 that may extend parallel to the data line DL.

[0101] Figure 5 is a circuit diagram of an electrostatic element unit in a peripheral area of ​​a display device according to an embodiment. Figure 5 , each data line DL may be electrically connected to the low voltage line 810 through two or more electrostatic elements 850 a and 850 b connected in series, and two or more electrostatic elements 850 c and 850 d may electrically connect the data line DL to the high voltage line 820 .

[0102] Reference Figure 4 , the plurality of contact holes 187 may be positioned at positions overlapping the low voltage lines 810 located in the electrostatic element unit 710. Figure 4 In the plan view shown in , a plurality of contact holes 187 may be arranged along each low voltage line 810, and the spacing and arrangement density between the plurality of contact holes 187 may be adjusted differently. For example, the plurality of contact holes 187 may be located at positions where the data line DL crosses the low voltage line 810. Figure 4 As shown in , one contact hole 187 may be provided for every two data lines DL. Alternatively, one contact hole 187 may also be provided for every three or more data lines DL. The contact hole 187 may be positioned between adjacent data lines DL in the electrostatic element unit 710, and the contact hole 187 may not overlap with the data line DL and may not overlap with the electrostatic semiconductor layer 830. In the case where a plurality of low voltage lines 810 are positioned in the electrostatic element unit 710, a plurality of contact holes 187 may overlap with each low voltage line 810, and may also overlap with only some of the low voltage lines 810.

[0103] Figure 6 , Figure 7 and Figure 8 It is along Figure 4 sectional views taken along line A1 - A2 of various embodiments of the display device shown in FIG.

[0104] Reference Figure 4 and Figure 6 , the low voltage line 810 on the substrate 110 may be located in or formed by the first data conductive layer, which is located on the second interlayer insulating layer 162. The contact hole 187 may be formed in the first passivation layer 180 and the second passivation layer 181 located on the low voltage line 810. The encapsulation layer 390 may be located on the second passivation layer 181 and the exposed low voltage line 810. The encapsulation layer 390 may include a plurality of insulating layers, and in particular, may include an inorganic insulating layer and an organic insulating layer alternately stacked. The encapsulation layer 390 may contact the side surfaces of the first passivation layer 180 and the second passivation layer 181 defining the contact hole 187 and the top surface of the low voltage line 810.

[0105] Reference Figure 4 and Figure 7, the low voltage line 810 on the substrate 110 may be positioned in or formed by the second data conductive layer located on the first passivation layer 180. The contact hole 187 may be formed in the second passivation layer 181 located on the low voltage line 810. The encapsulation layer 390 may be located on the second passivation layer 181 and the exposed low voltage line 810. The encapsulation layer 390 may include a plurality of insulating layers, and in particular, may include an inorganic insulating layer and an organic insulating layer alternately stacked. The encapsulation layer 390 may contact the side surface of the second passivation layer 181 defining the contact hole 187 and the top surface of the low voltage line 810.

[0106] Reference Figure 4 and Figure 8 ,according to Figure 8 The structure around the contact hole 187 of the embodiment is Figure 6 The structure depicted in is largely identical, but residue 360r can be positioned as Figure 8 The residue 360r may include a material different from that of the first passivation layer 180 and the second passivation layer 181. For example, the residue 360r may include a metal oxide such as IGZO. Figure 8 An example is shown in which the low voltage line 810 is positioned in the first data conductive layer, but the embodiment is not limited thereto, and the low voltage line 810 may alternatively be positioned in the second data conductive layer, wherein the residue 360r may exist in some areas inside the contact hole 187 passing through the second passivation layer 181 .

[0107] In the case where the contact hole 187 is positioned on the low voltage line 810 in the electrostatic element unit 710 , the contact hole 187 may not be positioned on the high voltage line 820 in the electrostatic element unit 710 , so that the high voltage line 820 may be completely covered by the second passivation layer 181 .

[0108] Fig. 9 The layout of the electrostatic element unit in the peripheral area of ​​the display device according to the embodiment is shown.

[0109] Reference Fig. 9 , a plurality of contact holes 189 may be positioned in the electrostatic element unit 710 at a position overlapping with the high voltage line 820. Fig. 9 In the plan view shown in , a plurality of contact holes 189 may be arranged along each high voltage line 820. The spacing and arrangement density between the contact holes 189 may be adjusted differently. For example, a plurality of contact holes 189 may be regularly arranged at positions corresponding to intersections of the data lines DL and the high voltage lines 820, and as shown in FIG. Fig. 9As shown in , one contact hole 189 may be provided for every two data lines DL. Alternatively, only one contact hole 189 may be provided for every three or more data lines DL. Each contact hole 189 may be positioned between adjacent data lines DL in the electrostatic element unit 710, and the contact hole 189 may not overlap with the data line DL and may not overlap with the electrostatic semiconductor layer 830. In the case where a plurality of high voltage lines 820 are positioned in the electrostatic element unit 710, a plurality of contact holes 189 may overlap with each high voltage line 820, and they may also overlap with a plurality of contact holes 187 only on some of the high voltage lines 820.

[0110] Fig.10 , Fig.11 and Fig.12 It is along Fig. 9 0 is a cross-sectional view taken along line B1 - B2 of various embodiments of the display device shown in FIG.

[0111] Reference Fig. 9 and Fig.10 , the high voltage line 820 may be located on the substrate 110 in the first data conductive layer on the second interlayer insulating layer 162. The contact hole 189 may be formed in the first passivation layer 180 and the second passivation layer 181 on the high voltage line 820. The encapsulation layer 390 may be on the second passivation layer 181 and extend into the contact hole 189 and onto the exposed portion of the high voltage line 820. The encapsulation layer 390 may include a plurality of insulating layers, and in particular, may include an inorganic insulating layer and an organic insulating layer alternately stacked. The encapsulation layer 390 may contact the side surfaces of the first passivation layer 180 and the second passivation layer 181 defining the contact hole 189, and may contact the top surface of the high voltage line 820.

[0112] Reference Fig. 9 and Fig.11 , the high voltage line 820 is located on the substrate 110, and may be a region of the second data conductive layer located on the first passivation layer 180. The contact hole 189 may be formed in the second passivation layer 181 located on the high voltage line 820. The encapsulation layer 390 may be located on the second passivation layer 181, and may extend into the contact hole 189 and onto the exposed high voltage line 820. The encapsulation layer 390 may include a plurality of insulating layers, and in particular, may include an inorganic insulating layer and an organic insulating layer alternately stacked. The encapsulation layer 390 may contact the side surface of the second passivation layer 181 defining the contact hole 189 and the top surface of the high voltage line 820.

[0113] Reference Fig. 9 and Fig.12 ,according to Fig.12 The structure around the contact hole 189 of the embodiment shown in FIG. Fig.10, but a residue 360r including a material different from that of the second passivation layer 181 may be positioned on the first passivation layer 180 and / or the second passivation layer 181. For example, the residue 360r may include a metal oxide such as IGZO. Fig.12 An example is shown where the high voltage line 820 is positioned in the first data conductive layer on the second interlayer insulating layer 162 , but the embodiment is not limited thereto. For example, the high voltage line 820 may be positioned in the second data conductive layer on the first passivation layer 180 , and the residue 360 ​​r may exist in some areas inside the contact hole 189 .

[0114] In the case where the contact hole 189 is positioned on the high voltage line 820 in the electrostatic element unit 710 , the contact hole 189 may not be positioned on the low voltage line 810 in the electrostatic element unit 710 , and the low voltage line 810 may be completely covered by the second passivation layer 181 .

[0115] Will refer to Figures 13 to 24 With the previously described Figure 1 Next, a method for manufacturing a display device according to an embodiment will be described. Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 and Fig. 20 is a cross-sectional view of a structure in the region of a partition that may be formed during the manufacture of a display device using a manufacturing method according to an embodiment, Fig.21 , Fig. 22 , Fig.23 and Fig.24 is a cross-sectional view in a region of a contact hole in an electrostatic element unit of a display device manufactured in a method of manufacturing a display device according to an embodiment.

[0116] Reference Fig.13 With the above Figure 3 Together, the manufacturing method of the display device according to the embodiment can be as follows Figure 3 As shown in FIG. 1 , a first insulating layer 120 to a second passivation layer 181 are sequentially stacked on a substrate 110, and after necessary patterning, a plurality of pixel electrodes 191 are formed on the second passivation layer 181. Subsequently, as shown in FIG. Fig.13 As shown in , a pixel insulating layer 350 is stacked on a plurality of pixel electrodes 191 , and the pixel insulating layer 350 is patterned to form an opening 355 located on the pixel electrode 191 .

[0117] Reference Figure 3 and Fig.14, a mask layer 360 is stacked on the entire surface of the substrate 110. The mask layer 360 on the pixel insulating layer 350 includes a portion located in the display area DA and a portion located in the peripheral area PA including the electrostatic element unit 710, and may be connected as a whole as one layer. The mask layer 360 may include a material different from that of the pixel insulating layer 350, and may include a material having an etching rate different from that of the pixel insulating layer 350. For example, the mask layer 360 may include a metal oxide such as IGZO. The mask layer 360 may contact the pixel electrode 191 and the top surface of the pixel insulating layer 350.

[0118] Reference Fig.15 , a photoresist 380 is deposited on the mask layer 360, and a photomask 400 is placed on the photoresist 380. Light such as ultraviolet (UV) light is irradiated through the opening 405 of the photomask 400. The photoresist 380 may have positive photosensitivity so that the portion 381 irradiated by the light is removed, but the embodiment is not limited thereto. The opening 405 of the photomask 400 or the portion 381 of the photoresist 380 may be located between the pixel electrodes 191 adjacent to each other on a plane, and may not overlap with the pixel electrode 191.

[0119] Reference Fig.16 , a portion 381 of the photoresist 380 exposed to light is removed to form an opening 382 in the photoresist 380 and expose a corresponding portion of the mask layer 360 .

[0120] Reference Fig.17 By etching and removing (patterning) the mask layer 360 exposed by the opening 382 of the photoresist 380, an opening 362 is formed in the mask layer 360. The mask layer 360 may be etched using wet etching. The opening 362 may be between adjacent pixel electrodes 191.

[0121] Reference Fig.17 and Fig.18 , the photoresist 380 may be removed by a stripping process or the like.

[0122] Reference Fig.19 , a portion of the upper surface of the pixel insulating layer 350 corresponding to the opening 362 is removed by a method such as ashing using the mask layer 360 having the opening 362 as a mask on the pixel insulating layer 340. This removal process applied to the pixel insulating layer 350 forms a partition 357 having a concave hole shape on the upper surface of the pixel insulating layer 350. The partition 357 may have a greater width than the opening 362 of the mask layer 360.

[0123] Reference Fig.19 and Fig. 20 , the mask layer 360 is removed from the entire surface of the substrate 110. In this case, wet etching may be used.

[0124] Reference Figure 3 , after removing the mask layer 360, a light emitting auxiliary layer 371 may be stacked on the pixel electrode 191 and the pixel insulating layer 350. At this time, regions of the light emitting auxiliary layer 371 may be separated or blocked from each other due to the steps of the partition 357. Subsequently, even in the step of forming the common electrode 270 on the light emitting auxiliary layer 371, the partition 357 may cause blocking in the common electrode 270.

[0125] Reference Fig.21 In the process of manufacturing the display device according to the above-mentioned method, the first insulating layer 120 to the second passivation layer 181 are sequentially stacked on the substrate 110, and then the second passivation layer 181 and the first passivation layer 180 are patterned to form the contact hole 187 on the low voltage line 810 in the electrostatic element unit 710. Thereafter, in reference to Fig.14 During the process described above, when the mask layer 360 is stacked, the mask layer 360 can be electrically connected via the contact low voltage line 810 through the contact hole 187 passing through the first passivation layer 180 and the second passivation layer 181 in the electrostatic element unit 710. Fig. 20 When the mask layer 360 is removed in the process of removing the mask layer 360, the mask layer 360 connected to the low voltage line 810 can be removed. Therefore, the mask layer 360 connected to the low voltage line 810 can be removed as shown in FIG. Figure 6 , or the residue 360r of the mask layer 360 may be removed as shown in FIG. Figure 8 As shown in FIG. 1 , the ions remain inside the contact hole 187 .

[0126] Reference Fig. 22 In the process of manufacturing the display device according to the above-mentioned method, the first insulating layer 120 to the first passivation layer 180 are sequentially stacked on the substrate 110, and then the second passivation layer 181 is formed. Patterning the second passivation layer 181 can form a contact hole 187 on the low voltage line 810 located in the electrostatic element unit 710. Afterwards, in the above-explained Fig.14 In the process described in the above, when the mask layer 360 is stacked, the mask layer 360 can be electrically connected via the contact hole 187 in the electrostatic element unit 710 via the contact low voltage line 810. Fig. 20 When the mask layer 360 is removed in the process of removing the mask layer 360, the mask layer 360 connected to the low voltage line 810 can be removed. Therefore, the mask layer 360 connected to the low voltage line 810 can be removed as described above. Figure 7 As shown in FIG. 1 , the mask layer 360 may be completely removed from the contact hole 187 , or a residue 360 ​​r of the mask layer 360 may remain inside the contact hole 187 .

[0127] Reference Fig.23 In the process of manufacturing the display device according to the above method, the first insulating layer 120 to the second passivation layer 181 are sequentially stacked on the substrate 110, and then the contact hole 189 in the first passivation layer 180 and the second passivation layer 181 can be formed on the high voltage line 820 located in the electrostatic element unit 710 by patterning the first passivation layer 180 and the second passivation layer 181. Then, when the above Fig.14 When the mask layer 360 is stacked in the process shown in FIG. 1 , the mask layer 360 electrically contacts the high voltage line 820 through the contact hole 189 in the electrostatic element unit 710. Fig. 20 When the mask layer 360 is removed in the process of removing the mask layer 360, the mask layer 360 connected to the high voltage line 820 may be removed. Therefore, as described above, the mask layer 360 connected to the high voltage line 820 may be removed as described above. Fig.10 , or the residue 360r of the mask layer 360 may be removed as shown in FIG. Fig.12 As shown in FIG. 1 , the ions remain inside the contact hole 189 .

[0128] Reference Fig.24 In the process of manufacturing the display device according to the above-mentioned method, after sequentially stacking the first insulating layer 120 to the second passivation layer 181 on the substrate 110, and patterning the second passivation layer 181, a contact hole 189 may be formed in the second passivation layer 181 on the high voltage line 820 located in the electrostatic element unit 710. Afterwards, Fig.14 In the process described in the above, when the mask layer 360 is stacked, the mask layer 360 can be electrically connected via the contact hole 189 in the electrostatic element unit 710 via the contact high voltage line 820. Fig. 20 When the mask layer 360 is removed in the process of removing the mask layer 360, the mask layer 360 connected to the high voltage line 820 can be removed. Therefore, the mask layer 360 connected to the high voltage line 820 can be removed as described above. Fig.11 As shown in FIG. 18A , the mask layer 360 may be completely removed, or a residue 360 ​​r of the mask layer 360 may remain inside the contact hole 189 .

[0129] exist Figures 13 to 24 In the process of forming the partition 357 on the upper surface of the pixel insulating layer 350, the mask layer 360 is also in the peripheral area PA or the low voltage line 810. Since the mask layer 360 is electrically connected to the low voltage line 810 or the high voltage line 820, the electrostatic charge generated during the process can flow from the mask layer 360 to the low voltage line 810 or the high voltage line 820 and escape. Therefore, the mask layer 360 can prevent the first transistor DQ (such as the low voltage line 810 or the high voltage line 820) from being blocked by the static electricity by contacting the pixel electrode 191 and transmitting the static electricity to the low voltage line 810 or the high voltage line 820 through the pixel electrode 191. Figure 3 The following is the characteristic change of Figure 25 to Figure 27 The comparative example shown in describes these effects in comparison.

[0130] Fig.25 is a cross-sectional view of a display device in a manufacturing process according to a comparative example, Fig.26 and Fig. 27 : is a graph showing stains displayed in an image of a display device in a manufacturing process according to each comparative example.

[0131] Reference Fig.25 ,exist Figures 13 to 20 In various stages of the process described in (e.g., pre-cleaning before exposure after depositing the mask layer 360, a stripping process for removing the photoresist, removing the mask layer 360, etc.), the roller 500 used for equipment transportation may cause electrostatic discharge due to static electricity generated by contact with the substrate 110, and a portion of the substrate 110 adjacent to the roller 500 may be charged. The charge charged to the substrate 110 may be transferred to the dielectric of the layer stacked on the substrate 110, so that the upper mask layer 360 may also be charged, and the charge of the mask layer 360 may be transferred to the first transistor DQ through the pixel electrode 191, the connection electrode 175, and the connection electrode 173a. Therefore, due to the change in the characteristics of the first transistor DQ, smudges may appear on the image displayed by the display device.

[0132] Fig.26 The substrate 110 is shown being transferred or moved on a roller 500 during the manufacture of the display device 1000. Fig.26 , for each roller 500, a discharge or additional charge compared to the surrounding environment may be generated at a position corresponding to the roller 500, thereby causing the substrate 110 to be charged by friction with the roller 500 under the substrate 110 of the display device 1000. The accumulation of the charge may generate a potential difference VD. Then, the characteristics of the transistor (for example, the first transistor DQ) of the pixel at the position corresponding to the roller 500 may be changed compared to the surrounding environment, and as shown in FIG. Fig.26 As shown in , spots ST may occur on an image displayed by the display device 1000 .

[0133] Refer to Fig.26 and Fig. 27 In the manufacturing process of the display device 1000, when an air knife 600 is used to remove the solution after cleaning or wet etching, the air pressure from the air knife 600 may cause the substrate 110 to be Fig. 27 The slight vibration in the oblique direction is shown in FIG. This may cause a change in the characteristics of the transistor of the corresponding pixel, which may also cause an oblique stain OST to appear on the image of the display device 1000.

[0134] However, according to the present embodiment, during the manufacturing process of the display device, the mask layer 360 is formed in the peripheral area PA and is electrically connected to the low voltage line 810 or the high voltage line 820, and the mask layer 360 affects the characteristics by causing the current to flow due to charging the transistor of the pixel (e.g., the first transistor DQ). Therefore, the electrostatic charge generated during the process can flow from the mask layer 360 to the low voltage line 810 or the high voltage line 820 and escape. Therefore, the mask layer 360 can contact the pixel electrode 191 to prevent the electrostatic charge from being transferred to the first transistor DQ through the pixel electrode 191 and changing the characteristics of the first transistor DQ. Therefore, it is possible to prevent the occurrence of Fig.26 and Fig. 27 Display defects such as spots ST or diagonal stains OST shown in .

[0135] Although some specific embodiments have been described in detail above, the scope of the present disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present disclosure are also included in the scope defined in the claims.

[0136] <Description of the tag>

[0137] 110: Base

[0138] 120: Insulation layer

[0139] 121: Lower level

[0140] 130a, 130b, 830: semiconductor layer

[0141] 141, 142, 143: Gate insulation layer

[0142] 151, 153: Gate electrode

[0143] 152: Storage electrode

[0144] 161, 162: Interlayer insulation layer

[0145] 171a, 171b, 173a, 173b, 175: connecting electrodes

[0146] 180, 181: Passivation layer

[0147] 183, 185, 187, 189: Contact holes

[0148] 191, 191a, 191b, 191c: pixel electrodes

[0149] 270: Common electrode

[0150] 350: Pixel insulation layer

[0151] 355, 362, 382, ​​405: Open

[0152] 357: Separator

[0153] 360: Mask layer

[0154] 371: Luminous auxiliary layer

[0155] 372: Luminous layer

[0156] 380: Photoresist

[0157] 390: Encapsulation layer

[0158] 400: Photomask

[0159] 500: Roller

[0160] 600: Air Knife

[0161] 700: Scan drive

[0162] 710: Electrostatic Component Unit

[0163] 720: Pad unit

[0164] 800, 810, 820: voltage line

[0165] 850a, 850b, 850c, 850d: Electrostatic components

[0166] 1000: Display device.

Claims

1. A display device, comprising: a display area including a plurality of pixels and a partition extending along a periphery of the pixels; as well as a peripheral area, positioned around the display area and including a scan driver and an electrostatic element unit, Each of the pixels includes: a pixel electrode; a portion of a light-emitting auxiliary layer positioned on the pixel electrode; and a portion of a common electrode positioned on the light-emitting auxiliary layer. Between adjacent pixels, the partition disconnects the portion of the light-emitting auxiliary layer. The electrostatic element unit includes a first voltage line electrically connected to the scan driver and a plurality of electrostatic elements electrically connected to the first voltage line. A plurality of contact holes overlapping the first voltage line are positioned in the electrostatic element unit, and An insulating layer is positioned in the contact hole.

2. The display device according to claim 1, further comprising: a passivation layer located on the first voltage line and having the contact hole formed therein, and The insulating layer contacts a side surface of the passivation layer defining the contact hole and an upper surface of the first voltage line.

3. The display device according to claim 2, wherein: The insulating layer includes a portion located on an upper surface of the passivation layer.

4. The display device according to claim 2, further comprising: a pixel insulating layer, located on the passivation layer and the pixel electrode, The partition is formed in a concave shape on an upper surface of the pixel insulating layer.

5. The display device according to claim 4, further comprising: Base, Each of the pixels further includes a transistor located between the substrate and the passivation layer, and the transistor is electrically connected to the pixel electrode.

6. The display device according to claim 5, further comprising: A plurality of data lines connected to the electrostatic element unit, Wherein, the data line crosses the first voltage line, and The contact hole is positioned between adjacent data lines among the plurality of data lines.

7. The display device according to claim 6, wherein: The electrostatic element unit further includes an electrostatic semiconductor layer forming the plurality of electrostatic elements, and The contact hole does not overlap with the electrostatic semiconductor layer in a plane.

8. The display device according to claim 2, further comprising: Residues, in a partial region within the contact hole, the residues include metal oxides.

9. The display device according to claim 1, further comprising: The light-emitting layer is located between the pixel electrode and the common electrode or between the light-emitting auxiliary layer and the pixel electrode.

10. A display device, comprising: A substrate including a display area and a peripheral area outside the display area; A transistor positioned on the display area; an electrostatic element and a first voltage line and a second voltage line, the electrostatic element being located on the peripheral area, the first voltage line and the second voltage line being electrically connected to the electrostatic element; a passivation layer, located on the transistor, the first voltage line and the second voltage line; A plurality of pixel electrodes, located on the passivation layer and in the display area; A pixel insulating layer, located on the passivation layer and the pixel electrode; as well as The light-emitting auxiliary layer and the light-emitting layer are located on the pixel electrode and the pixel insulating layer. The pixel insulating layer is located between adjacent pixel electrodes among the plurality of pixel electrodes and includes a concave-shaped partition, and The passivation layer has a contact hole located on the first voltage line in the peripheral region.

11. The display device according to claim 10, wherein: The passivation layer covers all of the second voltage lines in the peripheral region.

12. The display device according to claim 10, further comprising: a plurality of data lines connected to the plurality of electrostatic elements, wherein the data line crosses the first voltage line and the second voltage line, and The contact hole is located between adjacent data lines among the plurality of data lines on a plane.

13. The display device according to claim 12, further comprising: an electrostatic semiconductor layer, forming the plurality of electrostatic elements, The contact hole does not overlap with the electrostatic semiconductor layer in a plane. 14 . The display device according to claim 10 , further comprising a residue in a partial region within the contact hole, the residue comprising a metal oxide.

15. The display device according to claim 10, further comprising: The insulating layer includes a portion located in the contact hole and contacting the passivation layer, defining a side surface of the contact hole and an upper surface of the first voltage line.

16. The display device according to claim 15, wherein: The insulating layer also includes a portion positioned on an upper surface of the passivation layer.

17. The display device according to claim 10, wherein: The partition separates a portion of the light emitting auxiliary layer.

18. A method for manufacturing a display device, the method comprising: forming a plurality of transistors on a substrate, wherein the plurality of transistors are located in a display area; forming a plurality of electrostatic elements and voltage lines, the plurality of electrostatic elements and the voltage lines being positioned in a peripheral area, the peripheral area being positioned around the display area; stacking a passivation layer on the voltage line; forming a contact hole in the passivation layer to expose the voltage line, the contact hole being positioned in the peripheral region; forming a plurality of pixel electrodes in the display area; forming a pixel insulating layer on the pixel electrode and patterning the pixel insulating layer to form a first opening located on the pixel electrode; depositing a mask layer over the entire surface of the substrate, the mask layer being electrically connected to the voltage line through the contact hole; patterning the mask layer to form a second opening, wherein the second opening is located between adjacent pixel electrodes among the plurality of pixel electrodes; forming a concave hole-shaped partition on the upper surface of the pixel insulating layer by removing a portion of the upper surface of the pixel insulating layer corresponding to the second opening using the second opening as a mask, and The mask layer is removed over the entire surface of the substrate.

19. The method for manufacturing a display device according to claim 18, wherein: The mask layer includes metal oxide.

20. The method for manufacturing a display device according to claim 18, further comprising: stacking a light-emitting auxiliary layer on the pixel electrode and the pixel insulating layer; forming a common electrode on the light-emitting auxiliary layer; as well as forming an insulating layer on the substrate, The light emitting auxiliary layer includes a portion blocked by the partition, and the insulating layer includes a portion positioned in the contact hole.

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