Display device

Abstract

The invention discloses a display device. The display device includes a 1-1 line extending in a first direction, a 1-2 line extending in a second direction crossing the first direction and connected to the 1-1 line, a data line extending in the first direction and connected to the 1-2 line, a pixel connected to the data line, a receiving line extending in the first direction, a sensor connected to the receiving line; and a shield electrode overlapping the first-second line and the receiving line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0089580 filed in the Korean Intellectual Property Office on July 11, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a display device. Background Art

[0004] Electronic devices such as smart phones, digital cameras, notebook computers, car navigation units, smart TVs, or the like generally include a display device for displaying images. The display device includes a display panel for generating images, an input device such as an input sensing unit, a camera for capturing external images, and various sensors.

[0005] The input sensing unit is arranged on the display panel and senses input from the user. The sensor may include a fingerprint sensor, a proximity sensor, and an illumination sensor. Among the multiple sensors, the fingerprint sensor senses the fingerprint on the display panel. The fingerprint sensor is prepared as a separate module and arranged in the display device. Summary of the invention

[0006] Embodiments of the present disclosure provide a display device for improving the sensing sensitivity of a sensor.

[0007] According to an embodiment, a display device includes a 1-1 line extending in a first direction, a 1-2 line extending in a second direction crossing the first direction and connected to the 1-1 line, a data line extending in the first direction and connected to the 1-2 line, a pixel connected to the data line, a receiving line extending in the first direction, a sensor connected to the receiving line, and a shielding electrode arranged above the 1-2 line and overlapping the 1-2 line and the receiving line.

[0008] According to an embodiment, a display device includes a 1-1 line extending in a first direction, a 1-2 line extending in a second direction crossing the first direction and arranged below the 1-1 line and connected to the 1-1 line, a data line extending in the first direction and arranged in the same layer as the 1-1 line and connected to the 1-2 line, a pixel connected to the data line, a receiving line extending in the first direction and arranged in a layer different from a layer in which the data line is arranged, a sensor connected to the receiving line, and a shielding electrode arranged above the 1-2 line and overlapping with the 1-2 line.

[0009] According to an embodiment, a display device includes a 1-1 line, a 1-2 line crossing the 1-1 line and connected to the 1-1 line, a data line crossing the 1-2 line and connected to the 1-2 line, a pixel connected to the data line, a receiving line arranged in a layer different from a layer in which the 1-2 line is arranged, a sensor connected to the receiving line, and a plurality of shielding electrodes arranged in a layer between the 1-2 line and the receiving line and overlapping the 1-2 line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0011] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0012] Figure 2 yes Figure 1 A cross-sectional view of a display device shown in FIG.

[0013] Figure 3 yes Figure 2 A cross-sectional view of a display panel shown in FIG.

[0014] Figure 4 yes Figure 2 A plan view of the display panel shown in FIG.

[0015] Figure 5 It is shown Figure 4 0 is a view of an equivalent circuit diagram of one pixel among the pixels shown in 0 and a sensor adjacent to the pixel.

[0016] Figure 6 It is shown Figure 5 0 is a cross-sectional view of a light emitting element, a first transistor, a fourth transistor and a sixth transistor of a pixel shown in FIG.

[0017] Figure 7 It is shown Figure 5 0 is a cross-sectional view of a light receiving element, a first transistor, and a second transistor of a sensor shown in FIG.

[0018] Figure 8 It is shown that the arrangement Figure 4 0 is a view of a planar arrangement state of light emitting elements and light receiving elements in a partial area of ​​a display area shown in .

[0019] Fig. 9 It is shown Figure 5 and Figure 7 : View of the fingerprint sensing state of the sensor shown in .

[0020] Fig.10 It shows that Figure 4FIG. 1 is a plan view of a data line at a boundary of a display panel and a connection state of longitudinal lines and transverse lines.

[0021] Fig.11 It shows that Figure 4 0 is a plan view of a receiving line of a boundary of a display panel and a connection state of longitudinal lines and transverse lines shown in .

[0022] FIG. 12A to FIG. 12I is a view showing a planar structure of a pixel circuit and a sensor circuit step by step.

[0023] Fig.13 It is shown Fig.12I 0026] Figure 2 is a view of a cross-sectional configuration of a first transverse line and an electrode connected to the first transverse line shown in FIG.

[0024] FIG. 14A to FIG. 14D is a view showing a planar structure of a pixel circuit and a sensor circuit step by step.

[0025] Fig.15 It is shown Fig.14D 0047] Figure 2 is a view of a cross-sectional configuration of a second transverse line and an electrode connected to the second transverse line shown in FIG.

[0026] FIG. 16A to FIG. 16D It is shown FIG. 12A to FIG. 12I A view of a modified embodiment of the layout shown in FIG.

[0027] Fig.17 It is shown Fig.16D 0026] Figure 2 is a view of a cross-sectional configuration of a first transverse line and an electrode connected to the first transverse line shown in FIG.

[0028] 18A to 18C It is shown FIG. 12A to FIG. 12I A view of a modified embodiment of the layout shown in FIG.

[0029] Fig.19 It is shown Fig. 18C 0026] Figure 2 is a view of a cross-sectional configuration of a first transverse line and an electrode connected to the first transverse line shown in FIG.

[0030] FIG. 20A to FIG. 20D It is shown FIG. 14A to FIG. 14D A view of a modified embodiment of the layout shown in FIG.

[0031] Fig.21 It is shown Fig.20D 0047] Figure 2 is a view of a cross-sectional configuration of a second transverse line and an electrode connected to the second transverse line shown in FIG.

[0032] FIG. 22A to FIG. 22C It is shown FIG. 14A to FIG. 14D A view of a modified embodiment of the layout shown in FIG.

[0033] Fig.23It is shown Fig. 22C 0047] Figure 2 is a view of a cross-sectional configuration of a second transverse line and an electrode connected to the second transverse line shown in FIG. DETAILED DESCRIPTION

[0034] In this specification, when a component (or region, layer, part, etc.) is referred to as being “on,” “connected to” or “coupled to” another component, this means that the component may be directly on, directly connected to or directly coupled to the other component, or a third component may be present therebetween.

[0035] The same reference numerals refer to the same components. Additionally, in the drawings, the thickness, ratio, and size of components are exaggerated for efficient description.

[0036] As used herein, the term "and / or" includes all of one or more combinations defined by the relevant components.

[0037] Terms such as first, second and similar words can be used to describe various components, but components should not be limited by the terms. Terms can only be used to distinguish one component from other components. For example, without departing from the scope of the present disclosure, a first component can be referred to as a second component, and similarly, a second component can also be referred to as a first component. Unless otherwise specified, terms in the singular may include plural forms.

[0038] In addition, terms such as "below", "below", "above", and "on" are used to describe the relationship of components shown in the drawings. The terms are relative concepts and are described based on orientation and directions in the drawings.

[0039] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those generally understood by ordinary technicians in the field to which the present disclosure belongs. Such terms as defined in commonly used dictionaries should be interpreted as having the same meaning as the contextual meaning in the relevant technical field, and unless clearly defined as having such meaning in this application, should not be interpreted as having an idealized or excessive form of meaning.

[0040] It should be understood that terms such as “includes,” “comprising,” and “having,” when used herein, specify the presence of stated features, numbers, steps, operations, components, parts, or a combination thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or a combination thereof.

[0041] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0042] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure.

[0043] Reference Figure 1 , the display device DD according to an embodiment of the present disclosure may have a rectangular shape with long sides extending in a first direction DR1 and short sides extending in a second direction DR2 crossing the first direction DR1. However, not limited thereto, the display device DD may have various shapes such as a circular shape, another polygonal shape, and the like.

[0044] Hereinafter, a direction substantially perpendicularly crossing a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. As used herein, the expression "when viewed from above a plane" may mean viewed in the third direction DR3.

[0045] An upper surface of the display device DD may be defined as a display surface DS and may have a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the display device DD may be provided to a user through the display surface DS.

[0046] The display surface DS may include a display area DA and a non-display area NDA around the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and may define a border of the display device DD printed in a predetermined color.

[0047] The display device DD may be used in large electronic devices such as televisions, monitors, or billboards. In addition, the display device DD may be used in small and medium-sized electronic devices such as personal computers, notebook computers, personal digital terminals, car navigation units, game consoles, smart phones, tablet computers, and cameras. However, these electronic devices are merely illustrative, and the display device DD may be used in other electronic devices without departing from the spirit and scope of the present disclosure.

[0048] Figure 2 yes Figure 1 A cross-sectional view of a display device shown in FIG.

[0049] exist Figure 2 , a cross section of the display device DD viewed in the first direction DR1 is shown.

[0050] Reference Figure 2 , the display device DD may include a display panel DP, an input sensing unit ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first and second adhesive layers AL1 and AL2.

[0051] The display panel DP may be a flexible display panel. The display panel DP according to an embodiment of the present disclosure may be an emissive display panel, but is not particularly limited. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material. The emission layer of the inorganic light-emitting display panel may include quantum dots, quantum rods, and the like. Hereinafter, the description will be based on an exemplary embodiment in which the display panel DP is an organic light-emitting display panel.

[0052] The input sensing unit ISP may be arranged on the display panel DP. The input sensing unit ISP may include a plurality of sensing units (not shown) for sensing external input in a capacitive type. When the display device DD is prepared, the input sensing unit ISP may be directly prepared on the display panel DP. However, not limited thereto, the input sensing unit ISP may be prepared as a panel separated from the display panel DP and may be attached to the display panel DP by an adhesive layer.

[0053] The anti-reflection layer RPL may be disposed on the input sensing unit ISP. When the display device DD is prepared, the anti-reflection layer RPL may be directly prepared on the input sensing unit ISP. However, not limited thereto, the anti-reflection layer RPL may be prepared as a separate panel and may be attached to the input sensing unit ISP through an adhesive layer.

[0054] The anti-reflection layer RPL may be defined as a film for preventing reflection of external light. The anti-reflection layer RPL may reduce reflectivity of external light incident from above the display device DD toward the display panel DP. Due to the anti-reflection layer RPL, the external light may not be visible to the user.

[0055] When external light traveling toward the display panel DP is reflected from the display panel DP and provided back to the user, the user can visually recognize the external light as in a mirror. To prevent such a phenomenon, the anti-reflection layer RPL may include a plurality of color filters displaying the same color as the color of the pixels of the display panel DP.

[0056] The color filter may filter the external light into the same color as the color of the pixel. In this case, the external light may not be visible to the user. However, not limited thereto, the anti-reflection layer RPL may include a phase retarder and / or a polarizer to reduce the reflectivity of the external light.

[0057] The window WIN may be disposed on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensing unit ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0058] The panel protection film PPF may be disposed under the display panel DP. The panel protection film PPF may protect a lower portion of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).

[0059] The first adhesive layer AL1 may be disposed between the display panel DP and the panel protection film PPF, and the display panel DP and the panel protection film PPF may be bonded to each other through the first adhesive layer AL1. The second adhesive layer AL2 may be disposed between the window WIN and the anti-reflection layer RPL, and the window WIN and the anti-reflection layer RPL may be bonded to each other through the second adhesive layer AL2.

[0060] Figure 3 yes Figure 2 A cross-sectional view of a display panel shown in FIG.

[0061] exist Figure 3 Schematic diagram of a cross section of the display panel DP viewed in the first direction DR1 is shown in FIG.

[0062] Reference Figure 3 The display panel DP may include a substrate SUB, a circuit element layer DP-CL arranged on the substrate SUB, a display element layer DP-OLED arranged on the circuit element layer DP-CL, and a thin film encapsulation layer TFE arranged on the display element layer DP-OLED.

[0063] The substrate SUB may include a display area DA and a non-display area NDA around the display area DA. The substrate SUB may include glass or a flexible plastic material such as polyimide (PI). The display element layer DP-OLED may be arranged on the display area DA.

[0064] A plurality of pixels may be arranged in the circuit element layer DP-CL and the display element layer DP-OLED. Each of the pixels may include a transistor arranged in the circuit element layer DP-CL and a light emitting element arranged in the display element layer DP-OLED and connected to the transistor.

[0065] The thin film encapsulation layer TFE may be arranged on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the pixels from moisture, oxygen, and external foreign matter.

[0066] Figure 4 yes Figure 2 A plan view of the display panel shown in FIG.

[0067] Reference Figure 4 , the display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, a light emitting driver EDV, and a plurality of pads PD.

[0068] The display panel DP may include a first portion PT1 and a second portion PT2 extending from the first portion PT1. The second portion PT2 may have a smaller width in the second direction DR2 than the first portion PT1. The first portion PT1 may include a display area DA and a non-display area NDA surrounding the display area DA. The second portion PT2 may be defined as the non-display area NDA.

[0069] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, and first and second control lines CSL1 and CSL2.

[0070] Although not shown, the display panel DP may include a sensing unit for sensing a fingerprint. That is, the sensing unit for sensing a fingerprint may not be prepared as a separate module and may be embedded in the display panel DP. The sensing unit may include a plurality of sensors arranged between the pixels PX. The configuration of the sensor will be described in detail below.

[0071] The pixels PX may be arranged in the display area DA. The scan driver SDV and the light emitting driver EDV may be arranged in the non-display area NDA adjacent to opposite sides of the display panel DP extending in the first direction DR1 and facing each other in the second direction DR2.

[0072] The data driver DDV and the pad PD may be disposed on the second portion PT2. The pad PD may be closer to one side of the second portion PT2 than the data driver DDV. The one side of the second portion PT2 may extend in the second direction DR2.

[0073] The scan lines SL1 to SLm may extend in the second direction DR2 and may be connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend in the first direction DR1 and may be connected to the pixels PX and the data driver DDV. The emission lines EL1 to ELm may extend in the second direction DR2 and may be connected to the pixels PX and the emission driver EDV.

[0074] Although not shown, the display panel DP may include a first power line receiving a first voltage and a second power line receiving a second voltage having a level lower than the first voltage. The first power line and the second power line may extend to the display area DA and may be connected to the pixels PX.

[0075] The first control line CSL1 may be connected to the scan driver SDV and may extend toward the second portion PT2. The second control line CSL2 may be connected to the light emitting driver EDV and may extend toward the second portion PT2. The data driver DDV may be disposed between the first control line CSL1 and the second control line CSL2.

[0076] The data driver DDV and the first and second control lines CSL1 and CSL2 may be connected to the pads PD. The data lines DL1 to DLn may be connected to the data driver DDV, and the data driver DDV may be connected to the pads PD corresponding to the data lines DL1 to DLn.

[0077] Although not shown, the display device DD may further include a timing controller for controlling operations of the scan driver SDV, the data driver DDV, and the light emitting driver EDV. The timing controller may be mounted on the printed circuit board and may be connected to the pad PD through the printed circuit board.

[0078] The scan driver SDV may generate a plurality of scan signals, and the scan signals may be applied to the pixels PX through the scan lines SL1 to SLm. The data driver DDV may generate a plurality of data voltages, and the data voltages may be applied to the pixels PX through the data lines DL1 to DLn. The light emitting driver EDV may generate a plurality of light emitting signals, and the light emitting signals may be applied to the pixels PX through the light emitting lines EL1 to ELm.

[0079] The pixel PX may receive a data voltage in response to the scan signal, and may display an image by emitting light having brightness corresponding to the data voltage in response to the light emission signal.

[0080] Figure 5 Shows Figure 4 An equivalent circuit diagram of one pixel among the pixels shown in and a sensor adjacent to the pixel.

[0081] exist Figure 5 FIG. 1 shows a pixel PXij connected to the i-th scan line SLi, the i-th emission line ELi and the j-th data line DLj as an example. Figure 5 1 shows a sensor SNij connected to an i-th reset scanning line GRi and a j-th receiving line RXj. “i” and “j” are natural numbers greater than 0.

[0082] Reference Figure 5 , the pixel PXij may include a pixel circuit PC and a light emitting element OLED connected to the pixel circuit PC. The pixel circuit PC may drive the light emitting element OLED.

[0083] The pixel circuit PC may include a plurality of transistors T1 to T8 and a capacitor CST. The transistors T1 to T8 and the capacitor CST may control the amount of current flowing through the light emitting element OLED. The light emitting element OLED may generate light having a predetermined brightness according to the amount of current supplied to the light emitting element OLED.

[0084] The i-th scan line SLi may include an i-th write scan line GWi, an i-th compensation scan line GCi, an i-th initialization scan line GIi, an i-th bias scan line GBi, and an i-th reset scan line GRi.

[0085] The i-th write scan line GWi may receive the i-th write scan signal GWSi, and the i-th compensation scan line GCi may receive the i-th compensation scan signal GCSi. The i-th initialization scan line GIi may receive the i-th initialization scan signal GISi, and the i-th bias scan line GBi may receive the i-th bias scan signal GBSi. The i-th reset scan line GRi may receive the i-th reset scan signal GRSi. The i-th emission line ELi may receive the i-th emission signal ELSi.

[0086] Pixel PXij can be connected to the jth data line DLj, the ith write scan line GWi, the ith compensation scan line GCi, the ith initialization scan line GIi, the ith bias scan line GBi, the ith emission line ELi, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL, and the first power line PL1 and the second power line PL2.

[0087] The pixel circuit PC may be connected to the jth data line DLj, the ith writing scan line GWi, the ith compensation scan line GCi, the ith initialization scan line GIi, the ith bias scan line GBi, the ith light emitting line ELi, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL and the first power line PL1. The light emitting element OLED may be connected to the second power line PL2.

[0088] The first initialization line VIL1 may receive a first initialization voltage VINT, and the second initialization line VIL2 may receive a second initialization voltage AINT. The bias line VBL may receive a bias voltage VBIAS. The first power line PL1 may receive a first voltage ELVDD, and the second power line PL2 may receive a second voltage ELVSS.

[0089] Each of the transistors T1 to T8 may include a source electrode, a drain electrode, and a gate electrode. Figure 5 In the embodiment of the present invention, for convenience, one of the source electrode and the drain electrode is defined as a first electrode, and the other is defined as a second electrode. In addition, the gate electrode is defined as a control electrode.

[0090] The transistors T1 to T8 may include first to eighth transistors T1 to T8. The first transistor T1, the second transistor T2, the fifth transistor T5, and the eighth transistor T8 may be PMOS transistors. The third transistor T3 and the fourth transistor T4 may be NMOS transistors. In addition, the sixth transistor T6 and the seventh transistor T7 may also be PMOS transistors.

[0091] The first transistor T1 may be defined as a driving transistor, and the second transistor T2 may be defined as a switching transistor. The third transistor T3 may be defined as a compensation transistor. The fourth transistor T4 and the seventh transistor T7 may be defined as initialization transistors. The fifth transistor T5 and the sixth transistor T6 may be defined as light emitting control transistors. The eighth transistor T8 may be defined as a bias transistor.

[0092] The light emitting element OLED may be defined as an organic light emitting element. The light emitting element OLED may include an anode AE ​​and a cathode CE. The anode AE ​​may receive a first voltage ELVDD through a sixth transistor T6, a first transistor T1, and a fifth transistor T5. The first voltage ELVDD may be applied to the pixel circuit PC through a first power line PL1. The cathode CE may receive a second voltage ELVSS having a level lower than the first voltage ELVDD. The second voltage ELVSS may be applied to the pixel circuit PC through a second power line PL2.

[0093] The first transistor T1 may be disposed between the fifth transistor T5 and the sixth transistor T6 and may be connected to the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may be connected to the first power line PL1 through the fifth transistor T5 and may be connected to the anode AE ​​through the sixth transistor T6.

[0094] The first transistor T1 may include a first electrode connected to the first power line PL1 through a fifth transistor T5 , a second electrode connected to the anode AE ​​through a sixth transistor T6 , and a control electrode connected to the first node N1 .

[0095] The first electrode of the first transistor T1 may be connected to the fifth transistor T5, and the second electrode of the first transistor T1 may be connected to the sixth transistor T6. The first transistor T1 may control the amount of current flowing through the light emitting element OLED according to the voltage of the first node N1 applied to the control electrode of the first transistor T1.

[0096] The second transistor T2 may be disposed between the first transistor T1 and the jth data line DLj and may be connected to the first transistor T1 and the jth data line DLj. The second transistor T2 may include a first electrode connected to the jth data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the ith write scan line GWi.

[0097] The second transistor T2 may be turned on by the i-th write scan signal GWSi applied through the i-th write scan line GWi and may electrically connect the j-th data line DLj and the first electrode of the first transistor T1. The second transistor T2 may perform a switching operation of providing the data voltage VD applied through the j-th data line DLj to the first electrode of the first transistor T1.

[0098] The third transistor T3 may be connected to the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the i-th compensation scan line GCi.

[0099] The third transistor T3 may be turned on by the i-th compensation scan signal GCSi applied through the i-th compensation scan line GCi and may electrically connect the second electrode of the first transistor T1 and the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 may be connected in a diode form.

[0100] The fourth transistor T4 may be connected to the first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the first initialization line VIL1, and a control electrode connected to the i-th initialization scan line GIi. The fourth transistor T4 may be turned on by the i-th initialization scan signal GISi applied through the i-th initialization scan line GIi, and may provide the first initialization voltage VINT applied through the first initialization line VIL1 to the first node N1.

[0101] The fifth transistor T5 may include a first electrode connected to the first power line PL1 , a second electrode connected to the first electrode of the first transistor T1 , and a control electrode connected to the i th light emitting line ELi.

[0102] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE, and a control electrode connected to the i-th light emitting line ELi.

[0103] The fifth transistor T5 and the sixth transistor T6 may be turned on by the i-th light emitting signal ELSi applied through the i-th light emitting line ELi. The first voltage ELVDD may be provided to the light emitting element OLED through the turned-on fifth transistor T5 and the turned-on sixth transistor T6, and a driving current may flow through the light emitting element OLED. Accordingly, the light emitting element OLED may emit light.

[0104] The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line GBi. The seventh transistor T7 may be turned on by the i-th bias scan signal GBSi applied through the i-th bias scan line GBi, and may provide the second initialization voltage AINT applied through the second initialization line VIL2 to the anode AE ​​of the light emitting element OLED.

[0105] In an embodiment of the present disclosure, the seventh transistor T7 may be omitted. In an embodiment of the present disclosure, the second initialization voltage AINT may have a level different from that of the first initialization voltage VINT. However, not limited thereto, the second initialization voltage AINT may have the same level as the first initialization voltage VINT.

[0106] The seventh transistor T7 can improve the ability of the pixel PXij to express black. When the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the light emitting element OLED can be discharged. Accordingly, when black brightness is achieved, the light emitting element OLED does not emit light due to the leakage current of the first transistor T1, and thus the ability to express black can be improved.

[0107] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth and sixth transistors T5 and T6 are turned on, the amount of current flowing through the first transistor T1 may be determined according to the voltage stored in the capacitor CST.

[0108] The eighth transistor T8 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th bias scan line GBi. In an embodiment of the present disclosure, the eighth transistor T8 may be omitted.

[0109] The eighth transistor T8 may be turned on by the i-th bias scan signal GBSi and may provide the bias voltage VBIAS to the first electrode of the first transistor T1. When the bias voltage VBIAS is applied to the first transistor T1, movement of the hysteresis curve of the first transistor T1 may be suppressed.

[0110] The sensor SNij may include a sensing circuit SNC and a light receiving element LRE connected to the sensing circuit SNC. The sensing circuit SNC may drive the light receiving element LRE.

[0111] The sensing circuit SNC may include a first transistor T1 ′, a second transistor T2 ′, and a third transistor T3 ′. The first transistor T1 ′ and the third transistor T3 ′ may be PMOS transistors, and the second transistor T2 ′ may be an NMOS transistor.

[0112] The light receiving element LRE may be defined as a photodiode. The light receiving element LRE may convert light energy incident from the outside into electrical energy. The light receiving element LRE may include an anode AE' and a cathode CE'. The anode AE' may be connected to the second node N2, and the cathode CE' may be connected to the second power line PL2.

[0113] The first transistor T1' may be connected to the light receiving element LRE, the second transistor T2', and the third transistor T3'. The first transistor T1' may include a first electrode receiving a second initialization voltage AINT, a control electrode connected to a second node N2, and a second electrode connected to the third transistor T3'. The first electrode of the first transistor T1' may be connected to a second initialization line VIL2 to receive the second initialization voltage AINT.

[0114] The second transistor T2 ′ may include a first electrode connected to the second node N2 , a control electrode connected to the i th reset scan line GRi, and a second electrode connected to a reset line VRL receiving a reset voltage VRST.

[0115] The third transistor T3' may include a first electrode connected to the second electrode of the first transistor T1', a control electrode connected to the i-th write scan line GWi, and a second electrode connected to the j-th receiving line RXj. The third transistor T3' may be turned on by the i-th write scan signal GWSi received through the i-th write scan line GWi.

[0116] The second transistor T2' may be turned on by the i-th reset scan signal GRSi received through the i-th reset scan line GRi. The turned-on second transistor T2' may receive the reset voltage VRST and may provide the reset voltage VRST to the second node N2. The second node N2 may be reset by the reset voltage VRST.

[0117] The i-th write scan signal GWSi may be applied to the control electrode of the third transistor T3', and the third transistor T3' may be turned on accordingly. The first transistor T1' may be connected to the j-th receiving line RXj through the turned-on third transistor T3'.

[0118] The light receiving element LRE may receive light and may convert the light into an electrical signal. At this time, the voltage of the second node N2 may change. When the first transistor T1' is turned on, the second initialization voltage AINT provided to the first transistor T1' may be controlled according to the change of the voltage of the second node N2, and may be provided to the j-th receiving line RXj through the third transistor T3'. Accordingly, the signal sensed by the light receiving element LRE may be output as a sensing signal RS through the j-th receiving line RXj.

[0119] Figure 6 It is shown Figure 5 0 is a cross-sectional view of a light emitting element, a first transistor, a fourth transistor and a sixth transistor of a pixel shown in FIG.

[0120] Reference Figure 6 The light emitting element OLED may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL and an emission layer EML. The first electrode AE ​​may be Figure 5The anode AE ​​shown in FIG. 1 and the second electrode CE may be Figure 5 The cathode CE shown in FIG. The second electrode CE may be disposed on the first electrode AE, and the hole control layer HCL, the electron control layer ECL, and the emission layer EML may be disposed between the first electrode AE ​​and the second electrode CE.

[0121] The first transistor T1, the fourth transistor T4 and the sixth transistor T6 and the light emitting element OLED may be arranged on the substrate SUB. The display area DA may include an emission area LEA corresponding to the pixel PXij and a non-emission area NLEA adjacent to the emission area LEA. The light emitting element OLED may be arranged in the emission area LEA.

[0122] The lower metal layer BML may be disposed on the substrate SUB. The lower metal layer BML may overlap with the first transistor T1. Although not shown, a constant voltage may be applied to the lower metal layer BML. When the constant voltage is applied to the lower metal layer BML, the threshold voltage (Vth) of the first transistor T1 disposed above the lower metal layer BML may remain unchanged.

[0123] In addition, the lower metal layer BML may block light incident to the first transistor T1 from below the lower metal layer BML. For example, the lower metal layer BML may include a reflective metal. The lower metal layer BML may be omitted.

[0124] The buffer layer BFL may be disposed on the substrate SUB. The buffer layer BFL may be an inorganic layer. The buffer layer BFL may cover the lower metal layer BML. The semiconductor layers S1, A1, and D1 of the first transistor T1 and the semiconductor layers S6, A6, and D6 of the sixth transistor T6 may be disposed on the buffer layer BFL. The semiconductor layers S1, A1, D1, S6, A6, and D6 may include polycrystalline silicon. However, not limited thereto, the semiconductor layers S1, A1, D1, S6, A6, and D6 may include amorphous silicon.

[0125] The semiconductor layers S1, A1, D1, S6, A6, and D6 may be doped with an N-type dopant or a P-type dopant. The semiconductor layers S1, A1, D1, S6, A6, and D6 may include a heavily doped region and a lightly doped region. The heavily doped region may have a higher conductivity than the lightly doped region and may be substantially used as a source electrode and a drain electrode of the first transistor T1 and the sixth transistor T6. The lightly doped region may substantially correspond to an active (or channel) region of the first transistor T1 and the sixth transistor T6.

[0126] The first source region S1, the first channel region A1, and the first drain region D1 of the first transistor T1 may be formed by semiconductor layers S1, A1, and D1. The sixth source region S6, the sixth channel region A6, and the sixth drain region D6 of the sixth transistor T6 may be formed by semiconductor layers S6, A6, and D6. The first channel region A1 may be disposed between the first source region S1 and the first drain region D1. The sixth channel region A6 may be disposed between the sixth source region S6 and the sixth drain region D6.

[0127] The first insulating layer INS1 may be disposed on the buffer layer BFL to cover the semiconductor layers S1, A1, D1, S6, A6, and D6. The first gate electrodes G1 and G6 (or control electrodes) of the first and sixth transistors T1 and T6 may be disposed on the first insulating layer INS1.

[0128] Although not explicitly shown, the structure of the source region, channel region, drain region and gate electrode of each of the second transistor T2, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 may be substantially the same as the structure of the source region, channel region, drain region and gate electrode of each of the first transistor T1 and the sixth transistor T6.

[0129] The second insulating layer INS2 may be arranged on the first insulating layer INS1 to cover the first gate electrode G1 and the sixth gate electrode G6. The dummy electrode DME may be arranged on the second insulating layer INS2. The dummy electrode DME may be arranged above the first gate electrode G1 and may overlap the first gate electrode G1 when viewed from a plane defined by the first direction DR1 and the second direction DR2. The dummy electrode DME may form the above-mentioned capacitor CST together with the first gate electrode G1.

[0130] The third insulating layer INS3 may be arranged on the second insulating layer INS2 to cover the dummy electrode DME. The semiconductor layers S4, A4, and D4 of the fourth transistor T4 may be arranged on the third insulating layer INS3. The semiconductor layers S4, A4, and D4 may include an oxide semiconductor formed of a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0131] The semiconductor layers S4, A4 and D4 may include a plurality of regions that are distinguished from each other according to whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter referred to as the reduction region) has a higher conductivity than the region where the metal oxide is not reduced (hereinafter referred to as the non-reduction region). The reduction region may be substantially used as a source electrode or a drain electrode of the fourth transistor T4. The non-reduction region may substantially correspond to the active (or channel) region of the fourth transistor T4.

[0132] The fourth source region S4, the fourth channel region A4, and the fourth drain region D4 of the fourth transistor T4 may be formed of the semiconductor layers S4, A4, and D4. The fourth channel region A4 may be disposed between the fourth source region S4 and the fourth drain region D4.

[0133] The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the semiconductor layers S4, A4, and D4. The fourth gate electrode G4 of the fourth transistor T4 may be disposed on the fourth insulating layer INS4.

[0134] The fifth insulating layer INS5 may be arranged on the fourth insulating layer INS4 to cover the fourth gate electrode G4. The buffer layer BFL and the first to fifth insulating layers INS1 to INS5 may include an inorganic layer. Although not shown, the structure of the source region, channel region, drain region, and gate electrode of the third transistor T3 may be substantially the same as the structure of the source region, channel region, drain region, and gate electrode of the fourth transistor T4.

[0135] The connection electrode CNE may be disposed between the sixth transistor T6 and the light emitting element OLED. The connection electrode CNE may electrically connect the sixth transistor T6 and the light emitting element OLED. The connection electrode CNE may include a first connection electrode CNE1, a second connection electrode CNE2 disposed on the first connection electrode CNE1, and a third connection electrode CNE3 disposed on the second connection electrode CNE2.

[0136] The first connection electrode CNE1 may be disposed on the fifth insulating layer INS5 and may be connected to the sixth drain region D6 through a first contact hole CH1 defined in the first to fifth insulating layers INS1 to INS5. The sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 to cover the first connection electrode CNE1.

[0137] The second connection electrode CNE2 may be disposed on the sixth insulating layer INS6. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CH2 defined in the sixth insulating layer INS6. The seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 to cover the second connection electrode CNE2.

[0138] The third connection electrode CNE3 may be disposed on the seventh insulating layer INS7. The third connection electrode CNE3 may be connected to the second connection electrode CNE2 through a third contact hole CH3 defined in the seventh insulating layer INS7. The eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7 to cover the third connection electrode CNE3. The sixth to eighth insulating layers INS6 to INS8 may include an inorganic layer or an organic layer.

[0139] The first electrode AE ​​may be disposed on the eighth insulating layer INS8. The first electrode AE ​​may be electrically connected to the third connection electrode CNE3 through a fourth contact hole CH4 defined in the eighth insulating layer INS8.

[0140] A pixel defining layer PDL exposing a predetermined portion of the first electrode AE ​​may be disposed on the first electrode AE ​​and the eighth insulating layer INS8. An opening PX_OP for exposing the predetermined portion of the first electrode AE ​​may be defined in the pixel defining layer PDL.

[0141] The hole control layer HCL may be disposed on the first electrode AE ​​and the pixel defining layer PDL. The hole control layer HCL may be commonly disposed in the emission area LEA and the non-emission area NLEA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0142] The emission layer EML may be disposed on the hole control layer HCL. The emission layer EML may be disposed in a region corresponding to the opening PX_OP. The emission layer EML may include an organic material and / or an inorganic material. The emission layer EML may generate one of red light, green light, and blue light.

[0143] The electron control layer ECL may be disposed on the emission layer EML and the hole control layer HCL. The electron control layer ECL may be commonly disposed in the emission area LEA and the non-emission area NLEA. The electron control layer ECL may include an electron transport layer and an electron injection layer.

[0144] The second electrode CE may be disposed on the electron control layer ECL. The second electrode CE may be commonly disposed in the plurality of pixels PX. That is, the second electrode CE may be commonly disposed on the emission layer EML of the plurality of pixels PX.

[0145] The layer from the buffer layer BFL to the eighth insulating layer INS8 may be defined as a circuit element layer DP-CL. The layer where the light emitting element OLED is arranged may be defined as a display element layer DP-OLED.

[0146] The thin film encapsulation layer TFE may be arranged on the light emitting element OLED. The thin film encapsulation layer TFE may include an inorganic layer, an organic layer, and an organic layer sequentially stacked on top of each other. The inorganic layer may include an inorganic material and may protect the pixel PX from moisture / oxygen. The organic layer may include an organic material and may protect the pixel PX from foreign matter such as dust particles.

[0147] A first voltage ELVDD may be applied to the first electrode AE, and a second voltage ELVSS may be applied to the second electrode CE. Holes and electrons injected into the emission layer EML may be combined to form excitons, and as the excitons transition to a ground state, the light emitting element OLED may emit light. As the light emitting element OLED emits light, an image may be displayed.

[0148] Figure 7 It is shown Figure 5 0 is a cross-sectional view of a light receiving element, a first transistor, and a second transistor of a sensor shown in FIG.

[0149] Figure 7 The following description of the configuration shown in will focus on Figure 6 The structural differences in the stacking structure shown in .

[0150] Reference Figure 7 , the display area DA may include a light receiving area LRA corresponding to the sensor SNij and a non-emitting area NLEA adjacent to the light receiving area LRA. The non-emitting area NLEA may be Figure 6 The non-emitting area NLEA shown in .

[0151] The light receiving element LRE may include a first electrode AE', a second electrode CE', a hole control layer HCL', an electron control layer ECL' and a light receiving layer OPD. The first electrode AE' may be Figure 5 The anode AE' shown in FIG. 1 and the second electrode CE' may be Figure 5 The cathode CE' shown in FIG.

[0152] The light receiving layer OPD may be defined as an organic photodiode. The first electrode AE', the second electrode CE', the hole control layer HCL' and the electron control layer ECL' may be Figure 6 The first electrode AE, the second electrode CE, the hole control layer HCL and the electron control layer ECL shown in FIG. 1 are substantially the same components.

[0153] exist Figure 7 The position where the light receiving layer OPD is arranged may correspond to Figure 6 The position where the emission layer EML is arranged is arranged in the middle. That is, the second electrode CE' may be arranged on the first electrode AE', and the hole control layer HCL', the electron control layer ECL' and the light receiving layer OPD may be arranged between the first electrode AE' and the second electrode CE'. The second electrode CE' may be arranged on the light receiving layer OPD of the light receiving element LRE. The second electrode CE' may be arranged on the light receiving layer OPD of the light receiving element LRE. Figure 6 The second electrode CE shown in FIG. 1 is formed integrally. The opening PX_OP' may be connected to Figure 6 The opening PX_OP shown in FIG.

[0154] The first transistor T1' may include a first source region S1', a first drain region D1', a first channel region A1', and a first gate electrode G1'. The second transistor T2' may include a second source region S2', a second drain region D2', a second channel region A2', and a second gate electrode G2'.

[0155] The stack structure of the first transistor T1' can be Figure 6 The stack structure of the first transistor T1 shown in FIG. 1 is substantially the same as that of the second transistor T2′. Figure 6The stack structure of the fourth transistor T4 shown in FIG. 1 is substantially the same as that of the first transistor T1 ′. Although not explicitly shown, the stack structure of the third transistor T3 ′ may be substantially the same as that of the first transistor T1 ′.

[0156] The connection electrode CNE' may include a first connection electrode CNE1', a second connection electrode CNE2', and a third connection electrode CNE3'. The first connection electrode CNE1' may be disposed at Figure 6 The second connection electrode CNE2′ may be arranged in the same layer as the first connection electrode CNE1 shown in FIG. Figure 6 The second connection electrode CNE2 shown in FIG. 1 is in the same layer, and the third connection electrode CNE3′ may be arranged at the same layer as the second connection electrode CNE2. Figure 6 In the same layer as the third connection electrode CNE3 shown in FIG.

[0157] The first connection electrode CNE1' may be connected to the first gate electrode G1' of the first transistor T1' through a first contact hole CH1' defined in the second to fifth insulating layers INS2 to INS5. The second connection electrode CNE2' may be connected to the first connection electrode CNE1' through a second contact hole CH2' defined in the sixth insulating layer INS6. The third connection electrode CNE3' may be connected to the second connection electrode CNE2' through a third contact hole CH3' defined in the seventh insulating layer INS7. The first electrode AE' may be connected to the third connection electrode CNE3' through a fourth contact hole CH4' defined in the eighth insulating layer INS8.

[0158] Figure 8 It is shown that the arrangement Figure 4 0 is a view of a planar arrangement state of light emitting elements and light receiving elements in a partial area of ​​a display area shown in .

[0159] Reference Figure 8 , each of the first light emitting element OLED1, the second light emitting element OLED2 and the third light emitting element OLED3 may correspond to Figure 5 and Figure 6 Each of the light receiving elements LRE may correspond to Figure 5 and Figure 7 The light receiving element LRE shown in FIG. 1 can display red. The second light emitting element OLED2 can display green. The third light emitting element OLED3 can display blue.

[0160] The display panel DP may include a plurality of first pixel units PU1 and a plurality of second pixel units PU2. The first pixel units PU1 may be arranged in the second direction DR2. The second pixel units PU2 may be adjacent to the first pixel units PU1 in the first direction DR1 and may be arranged in the second direction DR2.

[0161] Each of the first pixel units PU1 may include one first light emitting element OLED1, two second light emitting elements OLED2, one third light emitting element OLED3 and one light receiving element LRE. In each of the first pixel units PU1, the first light emitting element OLED1, the second light emitting element OLED2 and the third light emitting element OLED3 may be arranged in the second direction DR2 in the order of the first light emitting element OLED1, the second light emitting element OLED2, the third light emitting element OLED3 and the second light emitting element OLED2.

[0162] In each of the first pixel units PU1, the light receiving element LRE may be adjacent to the third light emitting element OLED3 and the second left second light emitting element OLED2. In each of the first pixel units PU1, the light receiving element LRE may be adjacent to the second left second light emitting element OLED2 in the first direction DR1.

[0163] Each of the second pixel units PU2 may include one first light emitting element OLED1, two second light emitting elements OLED2, one third light emitting element OLED3 and one light receiving element LRE. In each of the second pixel units PU2, the first light emitting element OLED1, the second light emitting element OLED2 and the third light emitting element OLED3 may be arranged in the second direction DR2 in the order of the third light emitting element OLED3, the second light emitting element OLED2, the first light emitting element OLED1 and the second light emitting element OLED2.

[0164] In each of the second pixel units PU2, the light receiving element LRE may be adjacent to the third light emitting element OLED3 and the first left second light emitting element OLED2. In each of the second pixel units PU2, the light receiving element LRE may be adjacent to the first left second light emitting element OLED2 in the first direction DR1.

[0165] In each of the first pixel unit PU1 and the second pixel unit PU2, when viewed from above the plane, the first light emitting element OLED1 may have a larger area than the second light emitting element OLED2, and the third light emitting element OLED3 may have a larger area than the first light emitting element OLED1. In addition, in each of the first pixel unit PU1 and the second pixel unit PU2, when viewed from above the plane, the second light emitting element OLED2 may have a larger area than the light receiving element LRE.

[0166] When viewed from above a plane, the first light emitting element OLED1, the second light emitting element OLED2, the third light emitting element OLED3, and the light receiving element LRE may have a quadrilateral shape. However, not limited thereto, the first light emitting element OLED1, the second light emitting element OLED2, the third light emitting element OLED3, and the light receiving element LRE may have various shapes, such as a rhombus shape, a circular shape, and the like.

[0167] Fig. 9 It is shown Figure 5 and Figure 7 : View of the fingerprint sensing state of the sensor shown in .

[0168] Reference Fig. 9 , the display device DD may include a sensing unit SNP embedded in the display panel DP, and the sensing unit SNP may include a plurality of sensors SN. Each of the sensors SN may have Figure 5 and Figure 7 The same configuration of the sensor SNij as shown in FIG. Fig. 9 However, more sensors SN may be arranged in the display panel DP and may constitute the sensing unit SNP.

[0169] The sensor SN may sense the fingerprint FNT of the finger FN on the display panel DP. Light generated from the light emitting element OLED of the pixel PX may be provided to the fingerprint FNT and may be reflected from the fingerprint FNT.

[0170] The light reflected from the fingerprint FNT may be sensed by the light receiving element LRE of the sensor SN. The sensor SN may sense the fingerprint FNT by the light reflected from the fingerprint FNT. The control module (not shown) of the display device DD may receive the fingerprint information sensed by the sensor SN, and may perform a user authentication mode using the received fingerprint information.

[0171] Fig.10 It shows that Figure 4 FIG. 1 is a plan view of a data line at a boundary of a display panel and a connection state of longitudinal lines and transverse lines. Fig.11 It shows that Figure 4 0 is a plan view of a receiving line of a boundary of a display panel and a connection state of longitudinal lines and transverse lines shown in .

[0172] For example, in Fig.10 and Fig.11 Only some data lines DL, some reception lines RX, some longitudinal lines VBRS, and some transverse lines HBRS required for description are shown, and the remaining lines are omitted. In addition, the order of the lines is not shown with separate symbols.

[0173] Reference Fig.10 and Fig.11 , the display panel DP may include a plurality of longitudinal lines VBRS and a plurality of transverse lines HBRS. The longitudinal lines VBRS may include a first longitudinal line VBRS1, a second longitudinal line VBRS2, ​​and a dummy longitudinal line DVBRS. The transverse lines HBRS may include a first transverse line HBRS1, a second transverse line HBRS2, ​​and a dummy transverse line DHBRS.

[0174] The first longitudinal line VBRS1 may be defined as line 1-1, and the first transverse line HBRS1 may be defined as line 1-2. The second longitudinal line VBRS2 may be defined as line 2-1, and the second transverse line HBRS2 may be defined as line 2-2.

[0175] Reference Fig.10 , the first longitudinal lines VBRS1 and the dummy longitudinal lines DVBRS may extend in the first direction DR1 and may be arranged in the second direction DR2. The first transverse lines HBRS1 and the dummy transverse lines DHBRS may extend in the second direction DR2 and may be arranged in the first direction DR1.

[0176] When viewed from above a plane, the first longitudinal line VBRS1 , the dummy longitudinal line DVBRS, and the data line DL may extend to cross the first transverse line HBRS1 and the dummy transverse line DHBRS.

[0177] Based on the second direction DR2, the width of the second portion PT2 having the data driver DDV disposed thereon may be smaller than the width of the first portion PT1 having the pixels PX disposed thereon. In this case, it may be difficult to directly connect some data lines DL extending in the first direction DR1 and adjacent to the boundary of the first portion PT1 to the data driver DDV.

[0178] The data lines DL adjacent to the boundary of the first portion PT1 may be connected to the data driver DDV through some of the longitudinal lines VBRS and some of the transverse lines HBRS.

[0179] Specifically, a plurality of first longitudinal lines VBRS1 may be connected to the data driver DDV, and a plurality of first transverse lines HBRS1 may be respectively connected to the plurality of first longitudinal lines VBRS1. In addition, the first transverse lines HBRS1 may be connected to the data lines DL adjacent to the boundary of the first portion PT1. The data lines DL adjacent to the boundary of the first portion PT1 may be connected to the data driver DDV through the first transverse lines HBRS1 and the first longitudinal lines VBRS1.

[0180] The longitudinal line VBRS and the transverse line HBRS not used to connect the data line DL to the data driver DDV may be defined as a dummy longitudinal line DVBRS and a dummy transverse line DHBRS. The dummy longitudinal line DVBRS may not be connected to the data driver DDV. The dummy transverse line DHBRS may not be connected to the data line DL and the first longitudinal line VBRS1.

[0181] Reference Fig.11 , the second longitudinal line VBRS2 and the dummy longitudinal line DVBRS may extend in the first direction DR1 and may be arranged in the second direction DR2. The second transverse line HBRS2 and the dummy transverse line DHBRS may extend in the second direction DR2 and may be arranged in the first direction DR1. The receiving line RX may extend in the first direction DR1 and may be arranged in the second direction DR2.

[0182] When viewed from above a plane, the second longitudinal line VBRS2 , the dummy longitudinal line DVBRS, and the receiving line RX may extend to cross the second transverse line HBRS2 and the dummy transverse line DHBRS.

[0183] The receiving lines RX may be connected to the data driver DDV, and the sensing signals RS may be outputted through the data driver DDV. For similar reasons to the data lines DL, it may be difficult to directly connect some receiving lines RX extending in the first direction DR1 and adjacent to the boundary of the first portion PT1 to the data driver DDV.

[0184] Similar to the data lines DL, the reception lines RX adjacent to the boundary of the first portion PT1 may be connected to the data driver DDV through some of the longitudinal lines VBRS and some of the transverse lines HBRS.

[0185] Specifically, a plurality of second longitudinal lines VBRS2 may be connected to the data driver DDV, and a plurality of second transverse lines HBRS2 may be respectively connected to the plurality of second longitudinal lines VBRS2. The second transverse lines HBRS2 may be connected to the receiving lines RX adjacent to the boundary of the first portion PT1. The receiving lines RX adjacent to the boundary of the first portion PT1 may be connected to the data driver DDV through the second transverse lines HBRS2 and the second longitudinal lines VBRS2.

[0186] The longitudinal line VBRS and the transverse line HBRS not used to connect the reception line RX to the data driver DDV may be defined as a dummy longitudinal line DVBRS and a dummy transverse line DHBRS. The dummy transverse line DHBRS may not be connected to the reception line RX and the second longitudinal line VBRS2.

[0187] FIG. 12A to FIG. 12I is a view showing a planar structure of a pixel circuit and a sensor circuit step by step.

[0188] FIG. 12A to FIG. 12I The pixel circuit PC and the sensor circuit SNC are shown in FIG. Fig.10 , a data line DL, a first longitudinal line VBRS1, and a first transverse line HBRS1 are connected to each other. Each of the pixel circuits PC may correspond to Figure 5 The pixel circuit PC shown in FIG. 1 and each of the sensor circuits SNC may correspond to Figure 5 The sensor circuit SNC shown in FIG.

[0189] For example, FIG. 12A to FIG. 12I Shown with Figure 8 , a circuit in which the light emitting elements OLED1, OLED2, and OLED3 and the light receiving element LRE of the first pixel unit PU1 and the second pixel unit PU2 adjacent to each other in the first direction DR1 are connected.

[0190] The pixel circuit PC and the sensor circuit SNC arranged above in the first direction DR1 may be connected to Figure 8 The pixel circuit PC and the sensor circuit SNC arranged below in the first direction DR1 may be connected to the circuit of the light emitting elements OLED1, OLED2 and OLED3 and the light receiving element LRE of the first pixel unit PU1 shown in FIG. Figure 8 The circuit of the light emitting elements OLED1, OLED2 and OLED3 and the light receiving element LRE of the second pixel unit PU2 is shown in FIG.

[0191] exist FIG. 12A to FIG. 12I The boundary between the pixel circuit PC and the sensor circuit SNC is shown by a dotted line in FIG. Fig. 12A Only the reference numerals of the pixel circuit PC and the sensor circuit SNC are shown. FIG. 12A to FIG. 12I The configuration of one pixel circuit PC among a plurality of pixel circuits PC, the configuration of one sensor circuit SNC among a plurality of sensor circuits SNC, and the configuration for lines connected to the pixel circuit PC and the sensor circuit SNC are described.

[0192] FIG. 12A to FIG. 12I The layout of the pixel circuit PC and the sensor circuit SNC is depicted. FIG. 12A to FIG. 12I In the description of FIG. 1 , the term “overlap” indicates a state in which components cover each other when viewed on a plane.

[0193] Reference Fig. 12A , the lower conductive pattern BMP can be arranged on Figure 6 and Figure 7 On the substrate SUB shown in FIG. Fig. 12A The lower metal layer BML shown in FIG. 1 may be formed of a lower conductive pattern BMP. The lower conductive pattern BMP may have various shapes, without limitation. Fig. 12A The shapes shown in . Figure 6 The lower metal layer BML shown in FIG. 5 may be formed of the lower conductive pattern BMP.

[0194] Reference Fig. 12A and Fig. 12B , the first semiconductor pattern SMP1 may be disposed on the lower conductive pattern BMP. The first semiconductor pattern SMP1 may have various shapes without limitation. Fig. 12B The shapes shown in .

[0195] The first source region S1, the second source region S2, the fifth source region S5, the sixth source region S6, the seventh source region S7 and the eighth source region S8, the first drain region D1, the second drain region D2, the fifth drain region D5, the sixth drain region D6, the seventh drain region D7 and the eighth drain region D8 and the first channel region A1, the second channel region A2, the fifth channel region A5, the sixth channel region A6, the seventh channel region A7 and the eighth channel region A8 of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may be formed by the first semiconductor pattern SMP1.

[0196] The first channel region A1, the second channel region A2, the fifth channel region A5, the sixth channel region A6, the seventh channel region A7 and the eighth channel region A8 may be respectively arranged between the first source region S1 and the first drain region D1, between the second source region S2 and the second drain region D2, between the fifth source region S5 and the fifth drain region D5, between the sixth source region S6 and the sixth drain region D6, between the seventh source region S7 and the seventh drain region D7, and between the eighth source region S8 and the eighth drain region D8.

[0197] The second drain region D2 of the second transistor T2 and the fifth drain region D5 of the fifth transistor T5 may extend from the first source region S1 of the first transistor T1. The sixth source region S6 of the sixth transistor T6 may extend from the first drain region D1 of the first transistor T1. The seventh source region S7 of the seventh transistor T7 may extend from the sixth drain region D6 of the sixth transistor T6.

[0198] According to this structure, the first transistor T1 may be connected to the second transistor T2 , the fifth transistor T5 , and the sixth transistor T6 , and the sixth transistor T6 may be connected to the seventh transistor T7 .

[0199] The first semiconductor pattern SMP1 of the eighth transistor T8 may be adjacent to the first semiconductor pattern SMP1 of the fifth transistor T5. The first semiconductor pattern SMP1 of the eighth transistor T8 may be formed in an island shape.

[0200] The first source region S1' and the third source region S3', the first drain region D1' and the third drain region D3', and the first channel region A1' and the third channel region A3' of the first transistor T1' and the third transistor T3' may be formed by the first semiconductor pattern SMP1. The first channel region A1' and the third channel region A3' may be arranged between the first source region S1' and the first drain region D1' and between the third source region S3' and the third drain region D3', respectively. The third channel region A3' of the third transistor T3' may be formed by two channel regions.

[0201] The third source region S3' of the third transistor T3' may extend from the first drain region D1' of the first transistor T1'. According to this structure, the first transistor T1' may be connected to the third transistor T3'.

[0202] The first semiconductor pattern SMP1 of the first transistor T1 ′ and the third transistor T3 ′ may be adjacent to the first semiconductor pattern SMP1 of the second transistor T2 in the second direction DR2 .

[0203] In the following drawings, the serial numbers i-th and j-th indicating the order of the above-mentioned lines are omitted. That is, the layout will be described without limiting the lines to a specific order.

[0204] Reference FIG. 12A to FIG. 12C , the first gate pattern GPT1 may be disposed on the first semiconductor pattern SMP1. The first gate pattern GPT1 may include a write scan line GW, a light emitting line EL, a bias scan line GB, a first gate electrode G1, and a first gate electrode G1'.

[0205] The write scan line GW, the light emitting line EL, and the bias scan line GB may extend in the second direction DR2 and may be arranged in the first direction DR1. The light emitting line EL may be arranged between the write scan line GW and the bias scan line GB. The first gate electrode G1 and the first gate electrode G1' may be arranged between the write scan line GW and the light emitting line EL.

[0206] The first gate electrode G1 of the first transistor T1 may be formed of the first gate pattern GPT1. The first gate electrode G1 may overlap the first channel region A1.

[0207] The write scan line GW may extend to cross the first semiconductor pattern SMP1. The second gate electrode G2 of the second transistor T2 may be formed by the write scan line GW. When viewed from above a plane, a portion of the write scan line GW overlapping the first semiconductor pattern SMP1 may be defined as the second gate electrode G2. When viewed from above a plane, the second gate electrode G2 may overlap the second channel region A2.

[0208] The light emitting line EL may extend to cross the first semiconductor pattern SMP1. A fifth gate electrode G5 of the fifth transistor T5 and a sixth gate electrode G6 of the sixth transistor T6 may be formed of the light emitting line EL.

[0209] When viewed from above, a portion of the emission line EL overlapping the first semiconductor pattern SMP1 may be defined as fifth and sixth gate electrodes G5 and G6. When viewed from above, the fifth gate electrode G5 may overlap the fifth channel region A5, and the sixth gate electrode G6 may overlap the sixth channel region A6.

[0210] The bias scan line GB may extend to cross the first semiconductor pattern SMP1. The seventh gate electrode G7 of the seventh transistor T7 and the eighth gate electrode G8 of the eighth transistor T8 may be formed by the bias scan line GB. A portion of the bias scan line GB overlapping the first semiconductor pattern SMP1 may be defined as the seventh gate electrode G7 and the eighth gate electrode G8. The seventh gate electrode G7 and the eighth gate electrode G8 may overlap the seventh channel region A7 and the eighth channel region A8, respectively.

[0211] The first gate electrode G1' of the first transistor T1' may be formed of the first gate pattern GPT1. The first gate electrode G1' may overlap the first channel region A1'.

[0212] The third gate electrode G3' of the third transistor T3' may be formed by the write scan line GW. When viewed from above the plane, a portion of the write scan line GW overlapping the first semiconductor pattern SMP1 may be defined as the third gate electrode G3'. When viewed from above the plane, the third gate electrode G3' may overlap the third channel region A3'. The third gate electrode G3' may be formed of two gate electrodes.

[0213] In the following, FIG. 12D to FIG. 12I In the figure, for the convenience of description and simplification of reference numerals, the reference numerals of the first source region S1, the second source region S2, the fifth source region S5 to the eighth source region S8, the first drain region D1, the second drain region D2, the fifth drain region D5 to the eighth drain region D8, the first channel region A1, the second channel region A2, the fifth channel region A5 to the eighth channel region A8, and the first gate electrode G1, the second gate electrode G2, and the fifth gate electrode G5 to the eighth gate electrode G8 will be omitted. In addition, the reference numerals of the first source region S1' and the third source region S3', the first drain region D1' and the third drain region D3', the first channel region A1' and the third channel region A3', and the first gate electrode G1' and the third gate electrode G3' will also be omitted.

[0214] exist FIG. 12D to FIG. 12I 2 , reference numerals of the first transistor T1 , the second transistor T2 , the fifth transistor T5 to the eighth transistor T8 , and the first transistor T1 ′ and the third transistor T3 ′ are shown.

[0215] Reference FIG. 12A to FIG. 12D , the second gate pattern GPT2 may be disposed on the first gate pattern GPT1. The second gate pattern GPT2 may include a dummy electrode DME, a plurality of sub-dummy electrodes SDE, and a first transverse line HBRS1.

[0216] The dummy electrode DME may overlap the above-described first gate electrode G1 when viewed from a plane formed by the first direction DR1 and the second direction DR2. The dummy electrode DME may form a capacitor CST together with the first gate electrode G1. An opening OP may be defined in the dummy electrode DME.

[0217] The sub-dummy electrode SDE may extend in the second direction DR2 and may be arranged in the first direction DR1. When viewed from a plane defined by the first direction DR1 and the second direction DR2, the sub-dummy electrode SDE may be aligned with the first direction DR1. Fig.12F The reset scan line GR, the compensation scan line GC, and the initialization scan line GI shown in FIG. 1 overlap.

[0218] The first transverse line HBRS1 may correspond to the connection to Fig.10 The first transverse line HBRS1 may extend in the second direction DR2. The first transverse line HBRS1 may be adjacent to the lower side of the pixel circuit PC and the sensing circuit SNC. A plurality of protrusions PRT may be defined on the first transverse line HBRS1. The protrusions PRT may be connected to Figure 12G The first connection electrode CNE1-9 shown in FIG.

[0219] Reference FIG. 12A to FIG. 12E The second semiconductor pattern SMP2 may be disposed on the second gate pattern GPT2. The third and fourth source regions S3 and S4, the third and fourth drain regions D3 and D4, and the third and fourth channel regions A3 and A4 of the third and fourth transistors T3 and T4 may be formed by the second semiconductor pattern SMP2.

[0220] The third channel region A3 and the fourth channel region A4 may be disposed between the third source region S3 and the third drain region D3 and between the fourth source region S4 and the fourth drain region D4, respectively. The fourth drain region D4 of the fourth transistor T4 may extend from the third source region S3 of the third transistor T3. According to this structure, the fourth transistor T4 may be connected to the third transistor T3.

[0221] The second source region S2', the second drain region D2', and the second channel region A2' of the second transistor T2' may be formed by the second semiconductor pattern SMP2. The second channel region A2' may be disposed between the second source region S2' and the second drain region D2'.

[0222] In the following, FIG. 12F to FIG. 12I In the figure, the reference numeral of the sub-dummy electrode SDE will be omitted.

[0223] Reference FIG. 12A to FIG. 12F , the third gate pattern GPT3 may be disposed on the second semiconductor pattern SMP2. The third gate pattern GPT3 may include a reset scan line GR, a compensation scan line GC, an initialization scan line GI, and a second initialization line VIL2.

[0224] The reset scan line GR, the compensation scan line GC, the initialization scan line GI, and the second initialization scan line VIL2 may extend in the second direction DR2 and may be arranged in the first direction DR1. The reset scan line GR, the compensation scan line GC, and the initialization scan line GI may be arranged to be respectively aligned with Fig.12D The multiple sub-dummy electrodes SDE shown in FIG. 8 overlap.

[0225] The compensation scan line GC may be disposed between the initialization scan line GI and the reset scan line GR. The second initialization line VIL2 may be disposed between the compensation scan line GC and the reset scan line GR. The second initialization line VIL2 may be adjacent to the seventh and eighth transistors T7 and T8 and the first and second transistors T1' and T2'.

[0226] The compensation scan line GC may extend to cross the second semiconductor pattern SMP2. The third gate electrode G3 of the third transistor T3 may be formed by the compensation scan line GC. When viewed from above a plane, a portion of the compensation scan line GC overlapping the second semiconductor pattern SMP2 may be defined as the third gate electrode G3.

[0227] The initialization scan line GI may extend to cross the second semiconductor pattern SMP2. A fourth gate electrode G4 of the fourth transistor T4 may be formed by the initialization scan line GI. When viewed from above a plane, a portion of the initialization scan line GI overlapping the second semiconductor pattern SMP2 may be defined as the fourth gate electrode G4.

[0228] The reset scan line GR may extend to cross the second semiconductor pattern SMP2. The second gate electrode G2' of the second transistor T2' may be formed by the reset scan line GR. When viewed from above a plane, a portion of the reset scan line GR overlapping the second semiconductor pattern SMP2 may be defined as the second gate electrode G2'.

[0229] In the following, FIG. 12G to FIG. 12I In the figure, for the convenience of description and simplification of reference numerals, the reference numerals of the third source region S3 and the fourth source region S4, the third drain region D3 and the fourth drain region D4, the third channel region A3 and the fourth channel region A4, and the third gate electrode G3 and the fourth gate electrode G4 will be omitted. In addition, the reference numerals of the second source region S2', the second drain region D2', the second channel region A2' and the second gate electrode G2' will also be omitted. In addition, in FIG. 12G to FIG. 12IIn the figure, the reference numerals of the writing scanning line GW, the compensation scanning line GC, the initialization scanning line GI, the bias scanning line GB and the reset scanning line GR will also be omitted. FIG. 12G to FIG. 12I 2 shows reference numerals of the first to eighth transistors T1 to T8 and the first to third transistors T1 ′ to T3 ′.

[0230] Reference Figure 12G , the first connection pattern CNP1 may be arranged on the third gate pattern GPT3. The first connection pattern CNP1 may include first connection electrodes CNE1, CNE1', and CNE1-1 to CNE1-9, a first initialization line VIL1, a reset line VRL, and a bias line VBL. The first connection electrode CNE1 may be Figure 6 The first connection electrode CNE1 ′ may be Figure 7 The first connection electrode CNE1 ′ is shown in FIG.

[0231] The first initialization line VIL1, the reset line VRL, and the bias line VBL may extend in the second direction DR2 and may be arranged in the first direction DR1. The first initialization line VIL1 may be adjacent to the fourth transistor T4. The reset line VRL may be adjacent to the second transistor T2'. The bias line VBL may be adjacent to the eighth transistor T8.

[0232] The first connection electrodes CNE1, CNE1' and CNE1-1 to CNE1-9, the first initialization line VIL1, the reset line VRL and the bias line VBL may be arranged in the same layer. The first connection electrodes CNE1, CNE1' and CNE1-1 to CNE1-9, the first initialization line VIL1, the reset line VRL and the bias line VBL may be subjected to patterning at the same time and may be formed of the same material.

[0233] A plurality of first contact holes CH1, CH1', and CH1-1 to CH1-12 may be defined. The first contact hole CH1 may be Figure 6 The first contact hole CH1 shown in FIG. Among the plurality of first contact holes CH1′, the first contact hole CH1′ overlapping the first gate electrode G1′ may be Figure 7 The first contact holes CH1-1 to CH1-12 may be formed to be Figure 6 and Figure 7 The first contact hole CH1 shown in FIG. 1 is similar to the first contact hole CH1 ′.

[0234] The first connection electrode CNE1 may be connected to the sixth drain region D6 of the sixth transistor T6 through the first contact hole CH1.

[0235] The first connection electrode CNE1' may be connected to the first gate electrode G1' of the first transistor T1' and the second source region S2' of the second transistor T2' through the first contact hole CH1'. The first transistor T1' and the second transistor T2' may be connected to each other through the first connection electrode CNE1'.

[0236] The first connection electrode CNE1-1 may be connected to the third transistor T3 and the first and sixth transistors T1 and T6 through the first contact hole CH1-1. The first connection electrode CNE1-1 may be connected to the first drain region D1 of the first transistor T1, the sixth source region S6 of the sixth transistor T6, and the third drain region D3 of the third transistor T3. The third transistor T3 may be connected to the first transistor T1 and the sixth transistor T6 through the first connection electrode CNE1-3.

[0237] The first connection electrode CNE1-2 may be connected to the fifth transistor T5 and the dummy electrode DME of the capacitor CST through the first contact hole CH1-2. The first connection electrode CNE1-2 may be connected to the fifth source region S5 of the fifth transistor T5.

[0238] The first connection electrode CNE1-3 may be connected to the third and fourth transistors T3 and T4 and the first gate electrode G1 of the first transistor T1 through the first contact hole CH1-3. The first connection electrode CNE1-3 may be connected to the third source region S3 of the third transistor T3 and the fourth drain region D4 of the fourth transistor T4. The third and fourth transistors T3 and T4 may be connected to the first transistor T1 through the first connection electrode CNE1-3.

[0239] A portion of the first gate electrode G1 may be exposed by the opening OP formed in the dummy electrode DME. The first contact hole CH1-3 may be formed to overlap the opening OP, and accordingly, the first connection electrode CNE1-3 may be easily connected to the first gate electrode G1.

[0240] The first connection electrode CNE1-4 may be connected to the second transistor T2 through the first contact hole CH1-4. The first connection electrode CNE1-4 may be connected to the second source region S2 of the second transistor T2.

[0241] The first connection electrode CNE1-5 may be connected to the seventh transistor T7 and a second initialization line VIL2 through the first contact hole CH1-5. The first connection electrode CNE1-5 may be connected to the seventh drain region D7 of the seventh transistor T7 through the first contact hole CH1-5. The seventh transistor T7 may be connected to the second initialization line VIL2 through the first connection electrode CNE1-5.

[0242] The first connection electrode CNE1-6 may be connected to the fifth transistor T5 and the eighth transistor T8 through the first contact hole CH1-6. The first connection electrode CNE1-6 may be connected to the fifth drain region D5 of the fifth transistor T5 and the eighth drain region D8 of the eighth transistor T8 through the first contact hole CH1-6. The fifth transistor T5 may be connected to the eighth transistor T8 through the first connection electrode CNE1-6.

[0243] The first connection electrode CNE1-7 may be connected to the first transistor T1' and a second initialization line VIL2 through the first contact hole CH1-7. The first connection electrode CNE1-7 may be connected to the first source region S1' of the first transistor T1' through the first contact hole CH1-7. The first transistor T1' may be connected to the second initialization line VIL2 through the first connection electrode CNE1-7.

[0244] The first connection electrode CNE1-8 may be connected to the third transistor T3' through the first contact hole CH1-8. The first connection electrode CNE1-8 may be connected to the third drain region D3' of the third transistor T3'.

[0245] Hereinafter, a configuration in which a plurality of first connection electrodes CNE1-9 and a plurality of shielding electrodes SHE are provided will be described. For example, a configuration in which a plurality of first connection electrodes CNE1-9 and a plurality of shielding electrodes SHE overlap with the first transverse line HBRS1 will be described.

[0246] The plurality of first link electrodes CNE1-9 may be arranged in the second direction DR2 and may overlap the first transverse line HBRS1. The first link electrode CNE1-9 may overlap the pixel circuit PC and may not overlap the sensing circuit SNC.

[0247] The first connection electrode CNE1-9 may be connected to the first transverse line HBRS1 through the first contact hole CH1-9. For example, the first connection electrode CNE1-9 may be connected to the protrusion PRT of the first transverse line HBRS1 through the first contact hole CH1-9.

[0248] The first initialization line VIL1 may be connected to the fourth transistor T4. The first initialization line VIL1 may be connected to the fourth source region S4 of the fourth transistor T4 through the first contact hole CH1-10.

[0249] A plurality of shielding electrodes SHE may protrude from the first initialization line VIL1. The shielding electrodes SHE may be arranged in the second direction DR2. The shielding electrode SHE may be arranged on the first transverse line HBRS1, and when viewed from above a plane, the shielding electrode SHE may overlap a portion of the first transverse line HBRS1. When viewed from above a plane, the shielding electrode SHE may be arranged between the plurality of first connection electrodes CNE1-9. A first initialization voltage VINT that is a constant voltage may be applied to the shielding electrode SHE protruding from the first initialization line VIL1.

[0250] The bias line VBL may be connected to the eighth transistor T8. The bias line VBL may be connected to the eighth source region S8 of the eighth transistor T8 through the first contact hole CH1-11.

[0251] The reset line VRL may be connected to the second transistor T2'. The reset line VRL may be connected to the second drain region D2' of the second transistor T2' through the first contact hole CH1-12.

[0252] In the following, Fig.12H and Fig.12I , for simplification of reference numerals, reference numerals of the first connection electrodes CNE1, CNE1', and CNE1-1 to CNE1-9, the first contact holes CH1, CH1', and CH1-1 to CH1-12, and the dummy electrodes DME will be omitted.

[0253] Reference FIG. 12A to FIG. 12H , the second connection pattern CNP2 may be arranged on the first connection pattern CNP1. The second connection pattern CNP2 may include second connection electrodes CNE2, CNE2', and CNE2-1 to CNE2-3, a first power line PL1, a receiving line RX, and a reset line VRL'. The second connection electrode CNE2 may be connected to Figure 6 The second connection electrode CNE2′ may be the same as the second connection electrode CNE2 shown in FIG. Figure 7 The second connection electrode CNE2 ′ shown in FIG.

[0254] The first power line PL1 may extend in the first direction DR1 and may overlap the pixel circuit PC. The receiving line RX and the reset line VRL' may extend in the first direction DR1. The receiving line RX and the reset line VRL' may be spaced apart from each other in the second direction DR2 and may overlap the sensing circuit SNC.

[0255] The second connection electrodes CNE2, CNE2' and CNE2-1 to CNE2-3, the first power line PL1, the receiving line RX and the reset line VRL' may be arranged in the same layer. The second connection electrodes CNE2, CNE2' and CNE2-1 to CNE2-3, the first power line PL1, the receiving line RX and the reset line VRL' may be subjected to patterning at the same time and may be formed of the same material.

[0256] A plurality of second contact holes CH2, CH2', and CH2-1 to CH2-6 may be defined. The second contact hole CH2 may be connected to Figure 6 The second contact hole CH2' may be the same as the second contact hole CH2 shown in FIG. Figure 7 The second contact holes CH2-1 to CH2-6 may be formed similar to the second contact holes CH2' shown in FIG. Figure 6 and Figure 7 The second contact holes CH2 and CH2' shown in FIG. 5 are similar.

[0257] The second link electrode CNE2 may be connected to the first link electrode CNE1 through the second contact hole CH2. Accordingly, the second link electrode CNE2 may be connected to the sixth transistor T6 through the first link electrode CNE1.

[0258] The second connection electrode CNE2' may be connected to the first connection electrode CNE1' through the second contact hole CH2'. Accordingly, the second connection electrode CNE2' may be connected to the second transistor T2' through the first connection electrode CNE1'.

[0259] The second connection electrode CNE2-1 may be connected to the first connection electrode CNE1-4 through the second contact hole CH2-1. Accordingly, the second connection electrode CNE2-1 may be connected to the second transistor T2 through the first connection electrode CNE1-4.

[0260] Hereinafter, similar to the first link electrode CNE1-9 and the shielding electrode SHE, a plurality of second link electrodes CNE2-2 are provided. For example, a configuration of a plurality of second link electrodes CNE2-2 overlapping the first transverse line HBRS1 will be described.

[0261] The plurality of second connection electrodes CNE2-2 may overlap with some of the first connection electrodes CNE1-9. The plurality of second connection electrodes CNE2-2 may be connected to some of the first connection electrodes CNE1-9 through the plurality of second contact holes CH2-2. Accordingly, the plurality of second connection electrodes CNE2-2 may be connected to the first transverse line HBRS1 through some of the first connection electrodes CNE1-9.

[0262] The second link electrode CNE2-3 may be connected to the first initialization line VIL1 through the second contact hole CH2-3. Fig.12H , the second connection electrode CNE2-3 may be arranged on the left and right sides. The second connection electrode CNE2-3 on the left side may be connected to the first initialization line VIL1, while the second connection electrode CNE2-3 on the right side may not be connected to the first initialization line VIL1. Accordingly, the second contact hole CH2-3 may not be defined in the second connection electrode CNE2-3 on the right side.

[0263] The first power line PL1 may be connected to the first connection electrode CNE1-2 through the second contact hole CH2-4. Accordingly, the first power line PL1 may be connected to the fifth transistor T5 and the dummy electrode DME through the first connection electrode CNE1-2.

[0264] The receiving line RX may be connected to the first connection electrode CNE1-8 through the second contact hole CH2-5. Accordingly, the receiving line RX may be connected to the third transistor T3' through the first connection electrode CNE1-8.

[0265] The reset line VRL' may be connected to the reset line VRL through the second contact hole CH2-6. The reset line VRL' may be connected to the second transistor T2' through the reset line VRL.

[0266] In the following, Fig.12I , for simplification of reference numerals, reference numerals of the second connection electrodes CNE2, CNE2', and CNE2-1 to CNE2-3 and the second contact holes CH2, CH2', and CH2-1 to CH2-6 will be omitted.

[0267] Reference FIG. 12A to FIG. 12I The third connection pattern CNP3 may be disposed on the second connection pattern CNP2. The third connection pattern CNP3 may include a plurality of third connection electrodes CNE3, CNE3' and CNE3-1, a data line DL, a reset line VRL", a first initialization line VIL1' and a longitudinal line VBRS.

[0268] The third connection electrode CNE3 can be connected to Figure 6 The third connection electrode CNE3′ may be the same as the third connection electrode CNE3 shown in FIG. Figure 7 The third connection electrode CNE3 ′ shown in FIG.

[0269] The data line DL, the reset line VRL″, the first initialization line VIL1′ and the longitudinal line VBRS may extend in the first direction DR1 and may be arranged in the second direction DR2. The data line DL, the first initialization line VIL1′ and the longitudinal line VBRS may overlap the pixel circuit PC, and the reset line VRL″ may overlap the sensing circuit SNC.

[0270] The third link electrode CNE3 may be disposed between the first initialization line VIL1 ′ and the longitudinal line VBRS. The data line DL may be disposed between the longitudinal line VBRS and the reset line VRL″.

[0271] The third connection electrodes CNE3, CNE3' and CNE3-1, the data line DL, the reset line VRL", the first initialization line VIL1' and the longitudinal line VBRS may be arranged in the same layer. The third connection electrodes CNE3, CNE3' and CNE3-1, the data line DL, the reset line VRL", the first initialization line VIL1' and the longitudinal line VBRS may be subjected to patterning at the same time and may be formed of the same material.

[0272] A plurality of third contact holes CH3, CH3', and CH3-1 to CH3-4 may be defined. The third contact hole CH3 may be Figure 6 The third contact hole CH3 'may be Figure 7 The third contact holes CH3-1 to CH3-4 may be formed to be Figure 6 and Figure 7 The third contact holes CH3 and CH3' shown in FIG.

[0273] A plurality of fourth contact holes CH4 and CH4' may be defined. The fourth contact hole CH4 may be Figure 6 The fourth contact hole CH4 shown in FIG. The fourth contact hole CH4′ may be Figure 7 The fourth contact hole CH4' is shown in FIG.

[0274] The third link electrode CNE3 may be connected to the second link electrode CNE2 through the third contact hole CH3. The third link electrode CNE3 may be connected to the second link electrode CNE2 through the fourth contact hole CH4. Figure 6 Accordingly, the first electrode AE ​​may be connected to the sixth transistor T6 through the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3.

[0275] The third connection electrode CNE3' may be connected to the second connection electrode CNE2' through the third contact hole CH3'. The third connection electrode CNE3' may be connected to the second connection electrode CNE2' through the fourth contact hole CH4'. Figure 7 . Accordingly, the first electrode AE' may be connected to the second transistor T2' through the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3'.

[0276] The data line DL may be connected to the second link electrode CNE2-1 through the third contact hole CH3-1. Accordingly, the data line DL may be connected to the second transistor T2 through the first link electrode CNE1-4 and the second link electrode CNE2-1.

[0277] The first initialization line VIL1' may be connected to the second connection electrode CNE2-3 through the third contact hole CH3-2. Accordingly, the first initialization line VIL1' may be connected to the first initialization line VIL1 through the second connection electrode CNE2-3. The first initialization voltage VINT may be provided to the fourth transistor T4 through the first initialization line VIL1' and the first initialization line VIL1.

[0278] The reset line VRL" may be connected to the reset line VRL' through the third contact hole CH3-3. The reset line VRL" may be connected to the reset line VRL through the reset line VRL'. The reset voltage VRST may be provided to the second transistor T2' through the reset line VRL, the reset line VRL' and the reset line VRL". The reset line VRL" may overlap with the receiving line RX.

[0279] The data lines DL may be arranged on the left and right sides of the reset line VRL”. The reset line VRL” may be arranged between the data lines DL. The data voltage applied to the data line DL may be a pulse signal. The pulse signal may affect the sensing signal RS output through the receiving line RX. When viewed from above a plane, the reset line VRL” may be arranged between the data lines DL, may overlap with the receiving line RX, and may block the influence of the pulse data voltage on the sensing signal RS. That is, the reset line VRL” may be used as a shielding electrode.

[0280] In the following, Fig.12I A plurality of third link electrodes CNE3 - 1 and a plurality of longitudinal lines VBRS are provided will be described in detail.

[0281] The plurality of third connection electrodes CNE3-1 may overlap with the plurality of second connection electrodes CNE2-2, respectively. The plurality of third connection electrodes CNE3-1 may be connected to the plurality of second connection electrodes CNE2-2 through the plurality of third contact holes CH3-4, respectively. The plurality of third connection electrodes CNE3-1 may be connected to the first transverse line HBRS1 through some of the plurality of second connection electrodes CNE2-2 and the first connection electrode CNE1-9.

[0282] The data line DL may be connected to a corresponding third connection electrode CNE3-1 among a plurality of third connection electrodes CNE3-1. For example, the data line DL may be integrally formed with the corresponding third connection electrode CNE3-1. The third connection electrode CNE3-1 corresponding to the data line DL may extend from the data line DL. The data line DL may be connected to the first transverse line HBRS1 through the corresponding third connection electrode CNE3-1.

[0283] The plurality of longitudinal lines VBRS may extend in the first direction DR1 and may be arranged in the second direction DR2. Among the plurality of longitudinal lines VBRS, the rightmost first longitudinal line VBRS1 may be connected to a corresponding third connection electrode CNE3-1 among the plurality of third connection electrodes CNE3-1. For example, the first longitudinal line VBRS1 may be integrally formed with the corresponding third connection electrode CNE3-1. The third connection electrode CNE3-1 corresponding to the first longitudinal line VBRS1 may extend from the first longitudinal line VBRS1. The first longitudinal line VBRS1 may be connected to the first transverse line HBRS1 through the corresponding third connection electrode CNE3-1.

[0284] According to this structure, as referenced Fig.10 As described, the first longitudinal line VBRS1 may be connected to the first transverse line HBRS1, and the first transverse line HBRS1 may be connected to the data line DL.

[0285] Fig.13 It is shown Fig.12I 0026] Figure 2 is a view of a cross-sectional configuration of a first transverse line and an electrode connected to the first transverse line shown in FIG.

[0286] Fig.13 FIG. 2 shows a cross section formed in the extension direction of the first transverse line HBRS1. Fig.13 , together with the cross section of the first transverse line HBRS1, a cross section of a connection electrode connected to the first transverse line HBRS1 and a cross section of a line around the first transverse line HBRS1 are shown. For convenience of description, components below the first transverse line HBRS1 are omitted.

[0287] Reference Fig.12I and Fig.13 , the first transverse line HBRS1 may be disposed on the second insulating layer INS2 , and the third insulating layer INS3 , the fourth insulating layer INS4 , and the fifth insulating layer INS5 may be disposed on the first transverse line HBRS1 .

[0288] The first connection electrode CNE1-9 may be disposed on the fifth insulating layer INS5. The first connection electrode CNE1-9 may be connected to the first transverse line HBRS1 through a first contact hole CH1-9 defined in the third insulating layer INS3, the fourth insulating layer INS4, and the fifth insulating layer INS5. The sixth insulating layer INS6 may be disposed on the first connection electrode CNE1-9.

[0289] The second connection electrode CNE2-2 may be disposed on the sixth insulating layer INS6. The second connection electrode CNE2-2 may be connected to the first connection electrode CNE1-9 through a second contact hole CH2-2 defined in the sixth insulating layer INS6.

[0290] The seventh insulating layer INS7 may be disposed on the second connection electrode CNE2-2. The third connection electrode CNE3-1 may be disposed on the seventh insulating layer INS7. The third connection electrode CNE3-1 may be connected to the second connection electrode CNE2-2 through a third contact hole CH3-4 defined in the seventh insulating layer INS7. The eighth insulating layer INS8 may be disposed on the third connection electrode CNE3-1.

[0291] In the above stacked structure, the first longitudinal line VBRS1 and the data line DL may be arranged in the same layer. The receiving line RX may be arranged in a layer different from the layer where the first longitudinal line VBRS1 and the data line DL are arranged. The receiving line RX may be arranged below the first longitudinal line VBRS1 and the data line DL.

[0292] The first transverse line HBRS1 may be disposed under the first longitudinal line VBRS1, the data line DL, and the receiving line RX. The shielding electrode SHE may be disposed in a layer between the receiving line RX and the first transverse line HBRS1.

[0293] The plurality of first connection electrodes CNE1-9 may include a plurality of 1-1th connection electrodes CN1-1, a plurality of 1-2th connection electrodes CN1-2, and a plurality of 1-3th connection electrodes CN1-3. The 1-1th connection electrode CN1-1, the 1-2nd connection electrode CN1-2, and the 1-3rd connection electrode CN1-3 may be arranged on the first transverse line HBRS1 and may be connected to the first transverse line HBRS1.

[0294] The shielding electrode SHE may be arranged in the same layer as the 1-1th connection electrode CN1-1, the 1-2th connection electrode CN1-2, and the 1-3th connection electrode CN1-3. The shielding electrode SHE may include a plurality of first shielding electrodes SHE1 arranged between the plurality of 1-1th connection electrodes CN1-1, the plurality of 1-2th connection electrodes CN1-2, and the plurality of 1-3rd connection electrodes CN1-3.

[0295] When viewed from a plane defined by the first direction DR1 and the second direction DR2, the shielding electrode SHE may overlap the first transverse line HBRS1. In addition, among the plurality of shielding electrodes SHE, the shielding electrode SHE arranged in the sensing circuit SNC may overlap the receiving line RX when viewed from a plane defined by the first direction DR1 and the second direction DR2.

[0296] When viewed from a plane defined by the first direction DR1 and the second direction DR2, a plurality of 1-1 connection electrodes CN1-1 may overlap the data line DL and the first longitudinal line VBRS1. The connection electrodes may be arranged above the 1-2 connection electrodes CN1-2, and the connection electrodes may not be arranged above the 1-3 connection electrodes CN1-3. This configuration will be described in detail below.

[0297] Each of the 1-3rd connection electrodes CN1-3 may be disposed between a corresponding 1-1th connection electrode CN1-1 among the plurality of 1-1th connection electrodes CN1-1 and a corresponding 1-2nd connection electrode CN1-2 among the plurality of 1-2nd connection electrodes CN1-2.

[0298] The plurality of second connection electrodes CNE2-2 may include a plurality of 2-1st connection electrodes CN2-1 and a plurality of 2-2nd connection electrodes CN2-2. The reception line RX may be disposed in the same layer as the 2-1st connection electrode CN2-1 and the 2-2nd connection electrode CN2-2.

[0299] The plurality of 2-1st connection electrodes CN2-1 may be disposed above the plurality of 1-1st connection electrodes CN1-1 and may be respectively connected to the plurality of 1-1st connection electrodes CN1-1. The plurality of 2-2nd connection electrodes CN2-2 may be disposed above the plurality of 1-2nd connection electrodes CN1-2 and may be respectively connected to the plurality of 1-2nd connection electrodes CN1-2.

[0300] The plurality of third link electrodes CNE3-1 may include a plurality of 3-1st link electrodes CN3-1 and a plurality of 3-2nd link electrodes CN3-2. The data line DL and the first longitudinal line VBRS1 may be arranged in the same layer as the 3-1st link electrode CN3-1 and the 3-2nd link electrode CN3-2.

[0301] The plurality of 3-1st connection electrodes CN3-1 may be formed integrally with the data lines DL and the first longitudinal lines VBRS1, respectively. For example, the plurality of 3-1st connection electrodes CN3-1 may extend from the data lines DL and the first longitudinal lines VBRS1, respectively.

[0302] The data line DL and the first longitudinal line VBRS1 may be connected to the plurality of 2-1 connection electrodes CN2-1, respectively. For example, the plurality of 3-1 connection electrodes CN3-1 extending from the data line DL and the first longitudinal line VBRS1 may be arranged above the plurality of 2-1 connection electrodes CN2-1 and may be connected to the plurality of 2-1 connection electrodes CN2-1, respectively. The plurality of 3-2 connection electrodes CN3-2 may be arranged above the plurality of 2-2 connection electrodes CN2-2 and may be connected to the plurality of 2-2 connection electrodes CN2-2, respectively.

[0303] According to this structure, the first longitudinal line VBRS1 may be connected to the first transverse line HBRS1 through the corresponding 1-1th and 2-1th connection electrodes CN1-1 and CN2-1, and the first transverse line HBRS1 may be connected to the data line DL through the corresponding 1-1th and 2-1th connection electrodes CN1-1 and CN2-1.

[0304] The 2-1st and 2-2nd connection electrodes CN2-1 and CN2-2 and the 3-1st and 3-2nd connection electrodes CN3-1 and CN3-2 may not be arranged above the 1-3rd connection electrode CN1-3. For example, when viewed from a plane defined by the first direction DR1 and the second direction DR2, the 2-1st and 2-2nd connection electrodes CN2-2 and the 3-1st and 3-2nd connection electrodes CN3-1 and CN3-2 may not overlap with the 1-3rd connection electrode CN1-3. When viewed from a plane defined by the first direction DR1 and the second direction DR2, the 2-2nd and 3-2nd connection electrodes CN2-2 and CN3-2 may not overlap with the data line DL and the reception line RX.

[0305] The reset line VRL" may be disposed above the reception line RX and may overlap the reception line RX. The reset line VRL" may be adjacent to the data line DL.

[0306] The above-mentioned data voltage VD may be applied to the data line DL through the first longitudinal line VBRS1 and the first transverse line HBRS1.

[0307] The data voltage VD applied to the first longitudinal line VBRS1, the first transverse line HBRS1, and the data line DL may be a pulse signal. The pulse signal may affect the sensing signal RS output through the receiving line RX. In this case, the noise of the sensing signal RS may increase, and thus the sensing sensitivity may decrease. That is, the signal-to-noise ratio (SNR) of the sensing signal RS may deteriorate.

[0308] In the layer structure, the shielding electrode SHE may be arranged between the first horizontal line HBRS1 applied with the data voltage VD and the receiving line RX. In an embodiment of the present disclosure, the shielding electrode SHE applied with a constant voltage may block the influence of the pulse data voltage VD applied to the first horizontal line HBRS1 on the sensing signal RS of the receiving line RX.

[0309] If the reception line RX is arranged in a dotted box marked on the reset line VRL” in the same layer as the data line DL, the reception line RX may be closer to the data line DL than when the reception line RX is arranged in a layer different from the layer in which the data line DL is arranged. When the reception line RX is arranged in a dotted box marked on the reset line VRL”, the reset line VRL” may be arranged in another position.

[0310] When the receiving line RX is close to the data line DL, the capacitance of the parasitic capacitor (shown by the dotted line connected to the data line DL) formed by the receiving line RX and the data line DL may increase. As the capacitance of the parasitic capacitor increases, the noise of the sensing signal RS may increase according to the influence of the pulse data voltage VD. This phenomenon can be defined as a coupling phenomenon.

[0311] In an embodiment of the present disclosure, the receiving line RX may be arranged below the data line DL, but not arranged in the same layer as the data line DL. In this case, the receiving line RX may be spaced farther from the data line DL than when the receiving line RX is arranged in the same layer as the data line DL. The capacitance of the parasitic capacitor (shown by the dotted line) formed by the receiving line RX and the data line DL may be reduced. Accordingly, the coupling phenomenon may be reduced, and thus the noise of the sensing signal RS may be reduced.

[0312] In an embodiment of the present disclosure, a reset line VRL" applied with a constant voltage may be adjacent to the data line DL and may be arranged above the receiving line RX to overlap with the receiving line RX. The reset line VRL" may additionally block the influence of the pulse data voltage VD applied to the data line DL on the sensing signal RS of the receiving line RX.

[0313] FIG. 14A to FIG. 14D is a view showing a planar structure of a pixel circuit and a sensor circuit.

[0314] FIG. 14A to FIG. 14D The pixel circuit PC and the sensor circuit SNC are shown in FIG. Fig.11 0 is a view of a configuration in which the reception line RX, the second longitudinal line VBRS2, ​​and the second transverse line HBRS2 are connected to each other.

[0315] In addition to some parts, FIG. 14A to FIG. 14D The parts shown in FIG. 12A to FIG. 12I Accordingly, the following description will focus on the components shown in FIG. FIG. 12A to FIG. 12I The components shown in the figure are different components.

[0316] Fig.14A Corresponds to Fig.12D , but for another embodiment. The lower conductive pattern BMP, the first semiconductor pattern SMP1, the first gate pattern GPT1 and the second gate pattern GPT2 may be connected to FIG. 12A to FIG. 12D Those shown in are essentially the same.

[0317] However, the second gate pattern GPT2 may include a second transverse line HBRS2. Like the first transverse line HBRS1, the second transverse line HBRS2 may have a plurality of protrusions PRT defined thereon. The second transverse line HBRS2 may correspond to the first transverse line HBRS1 connected to the Fig.11 Any one of the second transverse lines HBRS2 of the receiving line RX shown in FIG.

[0318] Fig. 14B Corresponds to Figure 12G The second semiconductor pattern SMP2, the third gate pattern GPT3 and the first connection pattern CNP1 may be connected to FIG. 12E to FIG. 12GThe first connection electrode CNE1-9 may be arranged in the second direction DR2 and may overlap the second transverse line HBRS2. The first connection electrode CNE1-9 may be connected to the second transverse line HBRS2 through the first contact hole CH1-9.

[0319] The shielding electrode SHE may protrude from the first initialization line VIL1 and may overlap a portion of the second transverse line HBRS2. When viewed from above a plane, the shielding electrode SHE may be disposed between the plurality of first connection electrodes CNE1-9.

[0320] Fig. 14C Corresponds to Fig.12H In addition to the configuration of the receiving line RX, Fig. 14C The second connection pattern CNP2 shown in FIG. Fig.12H The second connection pattern CNP2 shown in FIG.

[0321] The plurality of second link electrodes CNE2-2 may be connected to some of the first link electrodes CNE1-9 through the plurality of second contact holes CH2-2. Accordingly, the plurality of second link electrodes CNE2-2 may be connected to the second transverse line HBRS2 through some of the first link electrodes CNE1-9.

[0322] The receiving line RX may be connected to a corresponding second connection electrode CNE2-2 among the plurality of second connection electrodes CNE2-2. Basically, the receiving line RX may be integrally formed with the corresponding second connection electrode CNE2-2. The receiving line RX may be connected to the second transverse line HBRS2 through the corresponding second connection electrode CNE2-2.

[0323] Reference Fig.14D , Fig.14D Corresponds to Fig.12I In addition to the configuration of the data line DL and the second longitudinal line VBRS2, Fig.14D The third connection pattern CNP3 shown in FIG. Fig.12I The third connection pattern CNP3 shown in FIG.

[0324] The plurality of third connection electrodes CNE3-1 may be connected to the plurality of second connection electrodes CNE2-2 through the plurality of third contact holes CH3-4, respectively. The data line DL may not be connected to the third connection electrode CNE3-1. The reception line RX may be connected to the corresponding third connection electrode CNE3-1 through the corresponding second connection electrode CNE2-2.

[0325] Among the plurality of longitudinal lines VBRS, the second longitudinal line VBRS2 from the right may be connected to a corresponding third connection electrode CNE3-1 among the plurality of third connection electrodes CNE3-1. For example, the second longitudinal line VBRS2 may be integrally formed with the corresponding third connection electrode CNE3-1. The second longitudinal line VBRS2 may be connected to the second transverse line HBRS2 through the corresponding third connection electrode CNE3-1.

[0326] According to this structure, as referenced Fig.11 As described, the second longitudinal line VBRS2 may be connected to the second transverse line HBRS2, ​​and the second transverse line HBRS2 may be connected to the receiving line RX.

[0327] Fig.15 It is shown Fig.14D 0047] Figure 2 is a view of a cross-sectional configuration of a second transverse line and an electrode connected to the second transverse line shown in FIG.

[0328] Fig.15 Can be with Fig.13 The following description will focus on the cross-sectional view corresponding to the embodiment of the present invention. Fig.13 The components shown in the figure are different components.

[0329] Reference Fig.13 , Fig.14D and Fig.15 , the second transverse lines HBRS2 may be arranged in the same layer as the first transverse lines HBRS1, and the second longitudinal lines VBRS2 may be arranged in the same layer as the first longitudinal lines VBRS1.

[0330] The plurality of first connection electrodes CNE1-9 may include a plurality of 1st-4th connection electrodes CN1-4, a plurality of 1st-5th connection electrodes CN1-5, and a plurality of 1st-6th connection electrodes CN1-6. The 1st-4th connection electrodes CN1-4, the 1st-5th connection electrodes CN1-5, and the 1st-6th connection electrodes CN1-6 may be arranged above the second transverse line HBRS2 and may be connected to the second transverse line HBRS2.

[0331] The 1-4th connection electrode CN1-4, the 1-5th connection electrode CN1-5, and the 1-6th connection electrode CN1-6 may be substantially the same as the 1-1st connection electrode CN1-1, the 1-2nd connection electrode CN1-2, and the 1-3rd connection electrode CN1-3, respectively.

[0332] The shielding electrode SHE may be arranged in the same layer as the 1st-4th connection electrode CN1-4, the 1st-5th connection electrode CN1-5, and the 1st-6th connection electrode CN1-6. The shielding electrode SHE may include a plurality of second shielding electrodes SHE2 arranged between the plurality of 1st-4th connection electrodes CN1-4, the plurality of 1st-5th connection electrodes CN1-5, and the plurality of 1st-6th connection electrodes CN1-6.

[0333] The plurality of second connection electrodes CNE2-2 may include a plurality of 2nd-3rd connection electrodes CN2-3 and a plurality of 2nd-4th connection electrodes CN2-4. The reception line RX may be arranged in the same layer as the 2nd-3rd connection electrode CN2-3 and the 2nd-4th connection electrode CN2-4.

[0334] The plurality of 2nd-3rd connection electrodes CN2-3 may be disposed above the plurality of 1st-4th connection electrodes CN1-4 and may be respectively connected to the plurality of 1st-4th connection electrodes CN1-4. The plurality of 2nd-4th connection electrodes CN2-4 may be disposed above the plurality of 1st-5th connection electrodes CN1-5 and may be respectively connected to the plurality of 1st-5th connection electrodes CN1-5.

[0335] The receiving line RX may be integrally formed with a corresponding 2nd-3rd connection electrode CN2-3 among a plurality of 2nd-3rd connection electrodes CN2-3. For example, the 2nd-3rd connection electrode CN2-3 corresponding to the receiving line RX may extend from the receiving line RX. The receiving line RX may be connected to the corresponding 1st-4th connection electrode CN1-4 through the corresponding 2nd-3rd connection electrode CN2-3.

[0336] The plurality of third connection electrodes CNE3-1 may include a plurality of 3rd-3rd connection electrodes CN3-3 and a plurality of 3rd-4th connection electrodes CN3-4. The plurality of 3rd-3rd connection electrodes CN3-3 may be arranged above the plurality of 2nd-3rd connection electrodes CN2-3 and may be respectively connected to the plurality of 2nd-3rd connection electrodes CN2-3. The plurality of 3rd-4th connection electrodes CN3-4 may be arranged above the plurality of 2nd-4th connection electrodes CN2-4 and may be respectively connected to the plurality of 2nd-4th connection electrodes CN2-4.

[0337] The second longitudinal line VBRS2 may be arranged in the same layer as the 3-3rd connection electrode CN3-3 and the 3-4th connection electrode CN3-4. The second longitudinal line VBRS2 may be connected to the 2-3rd connection electrode CN2-3 that does not extend from the receiving line RX among the plurality of 2-3rd connection electrodes CN2-3. Among the plurality of 3-3rd connection electrodes CN3-3, the 3-3rd connection electrode CN3-3 connected to the 2-3rd connection electrode CN2-3 that does not extend from the receiving line RX may be defined as the 3-3rd connection electrode CN3-3 corresponding to the second longitudinal line VBRS2.

[0338] The second longitudinal line VBRS2 may be integrally formed with the 3-3rd connection electrode CN3-3 corresponding to the second longitudinal line VBRS2. For example, the 3-3rd connection electrode CN3-3 corresponding to the second longitudinal line VBRS2 may extend from the second longitudinal line VBRS2. The second longitudinal line VBRS2 may be connected to the corresponding 2-3rd connection electrode CN2-3 through the corresponding 3-3rd connection electrode CN3-3.

[0339] According to this structure, the second longitudinal line VBRS2 can be connected to the second transverse line HBRS2 through the corresponding 1-4 connection electrodes CN1-4 and 2-3 connection electrodes CN2-3, and the second transverse line HBRS2 can be connected to the receiving line RX through the corresponding 1-4 connection electrodes CN1-4 and 2-3 connection electrodes CN2-3. The above-mentioned sensing signal RS can be output through the receiving line RX, the second transverse line HBRS2 and the second longitudinal line VBRS2.

[0340] In an embodiment of the present disclosure, the shielding electrode SHE may be arranged between the plurality of data lines DL and the second transverse line HBRS2 along the third direction DR3 and may block the influence of the data voltage VD applied to the data line DL on the sensing signal RS output through the second transverse line HBRS2.

[0341] In addition, similar to the above description, the reset line VRL″ adjacent to the data line DL and arranged above the receiving line RX to overlap the receiving line RX may block the influence of the data voltage VD on the sensing signal RS of the receiving line RX.

[0342] FIG. 16A to FIG. 16D It is shown FIG. 12A to FIG. 12I A view of a modified embodiment of the layout shown in FIG.

[0343] In the following, the FIG. 16A to FIG. 16D The following description will focus on the components related to FIG. 12A to FIG. 12I The components shown in the figure are different components.

[0344] Fig.16A Corresponds to Fig.12D In this embodiment, the configuration of the first transverse line HBRS1' can be the same as Fig.12D A plurality of protrusions PRT may be defined on the first transverse line HBRS1'. For example, Fig.12D Among the plurality of protrusions PRT of the first transverse line HBRS1 shown in FIG. 1 , the protrusions PRT of the first transverse line HBRS1′ may be omitted from the first transverse line HBRS1′. Fig.13 The 1st-2nd connection electrode CN1-2 shown in FIG. overlaps the protrusion PRT. For example, in Fig.16A In the figure, the portion where the protrusion PRT is omitted is shown by a circular broken line.

[0345] Fig. 16B Corresponds to Figure 12G , but for another embodiment. Fig. 16B In the embodiment of FIG. 1 , some of the first connection electrodes CNE1-9 may be omitted. Figure 12G Among the plurality of first connection electrodes CNE1-9 shown in Fig. 16B Can be omitted Fig.13 The 1st-2nd connecting electrode CN1-2 shown in FIG.

[0346] Fig. 16C Corresponds to Fig.12H , but for another embodiment. Fig. 16C In the embodiment of FIG. 1 , some of the second connection electrodes CNE2-2 may be omitted. Fig.12H Among the plurality of second connection electrodes CNE2-2 shown in Fig. 16C Can be omitted Fig.13 The 2-2nd connecting electrode CN2-2 shown in FIG.

[0347] Fig.16D Corresponds to Fig.12I , but for another embodiment. Fig.16D In the embodiment of FIG. 1 , some of the third connection electrodes CNE3-1 may be omitted. Fig.12I Among the plurality of third connection electrodes CNE3-1 shown in Fig.16D Can be omitted Fig.13 The 3-2nd connecting electrode CN3-2 shown in FIG.

[0348] Fig.17 It is shown Fig.16D 0026] Figure 2 is a view of a cross-sectional configuration of a first transverse line and an electrode connected to the first transverse line shown in FIG.

[0349] Fig.17 Can be with Fig.13 The following description will focus on Fig.13 The components shown in the figure are different components.

[0350] Reference Fig.13 , Fig.16D and Fig.17 ,exist Fig.17 Can be omitted Fig.13 In this case, a parasitic capacitor formed by the 1-2, 2-2, and 3-2 connection electrodes CN1-2, CN2-2, and CN3-2 and the adjacent data line DL' can be removed.

[0351] For example, assuming that there are 1-2nd connection electrode CN1-2, 2-2nd connection electrode CN2-2 and 3-2nd connection electrode CN3-2, the reference numeral of the data line adjacent to the 1-2nd connection electrode CN1-2, 2-2nd connection electrode CN2-2 and 3-2nd connection electrode CN3-2 is shown as DL'.

[0352] When the 1-2nd connection electrode CN1-2, the 2-2nd connection electrode CN2-2, and the 3-2nd connection electrode CN3-2 are used, a parasitic capacitor formed by the 1-2nd connection electrode CN1-2, the 2-2nd connection electrode CN2-2, the 3-2nd connection electrode CN3-2, and the data line DL' may affect the sensing signal RS of the reception line RX. However, in an embodiment of the present disclosure, the 1-2nd connection electrode CN1-2, the 2-2nd connection electrode CN2-2, and the 3-2nd connection electrode CN3-2 may be omitted, and thus the above-mentioned parasitic capacitor may be removed.

[0353] 18A to 18C It is shown FIG. 12A to FIG. 12I A view of a modified embodiment of the layout shown in FIG.

[0354] In the following, the 18A to 18C The following description will focus on the components related to FIG. 12A to FIG. 12I The components shown in the figure are different components.

[0355] Fig.18A Corresponds to Figure 12G , but for another embodiment. The first transverse line HBRS1 may have Fig.12D The same configuration as the first transverse line HBRS1 shown in FIG. Fig.12D The same protrusion PRT of the first transverse line HBRS1 shown in FIG. 1 may be defined on the first transverse line HBRS1 .

[0356] However, the configuration of the first connection electrode CNE1-9 may be different. The first contact hole CH1-9 may not be defined in some of the first connection electrodes CNE1-9. For example, the first contact hole CH1-9 may not be defined in Figure 12G Among the plurality of first connection electrodes CNE1-9 shown in Fig.13 In the first link electrode CNE1-9 corresponding to the 1-2nd link electrode CN1-2 shown in FIG. Accordingly, the first link electrode CNE1-9 corresponding to the 1-2nd link electrode CN1-2 may not be connected to the first transverse line HBRS1.

[0357] For example, a portion where the first contact hole CH1 - 9 is omitted is indicated by a dotted arrow.

[0358] Fig.18BCorresponds to Fig.12H However, some of the second connection electrodes CNE2-2 may be formed integrally with the first power line PL1. Fig.12H Among the plurality of second connection electrodes CNE2-2 shown in Fig.13 The second connection electrode CNE2 - 2 corresponding to the 2-2nd connection electrode CN2 - 2 shown in FIG. 1 may be formed integrally with the first power line PL1 .

[0359] Reference Fig. 18C , Fig. 18C Corresponds to Fig.12I Plan view of the. Fig. 18C Can be used with Fig.12I same.

[0360] Fig.19 It is shown Fig. 18C 0026] Figure 2 is a view of a cross-sectional configuration of a first transverse line and an electrode connected to the first transverse line shown in FIG.

[0361] Fig.19 Can be with Fig.13 The following description will focus on Fig.13 The components shown in the figure are different components.

[0362] Reference Fig.13 , Fig. 18C and Fig.19 , Fig.19 The 1-2nd connection electrode CN1-2 shown in FIG. 1 may not be connected to the first transverse line HBRS1. The plurality of 2-2nd connection electrodes CN2-2 may be connected to the plurality of 1-2nd connection electrodes CN1-2, respectively, and the plurality of 3-2nd connection electrodes CN3-2 may be connected to the plurality of 2-2nd connection electrodes CN2-2, respectively.

[0363] The first power line PL1 may be adjacent to the 2-2nd connection electrode CN2-2 and may be integrally formed with the 2-2nd connection electrode CN2-2. For example, the 2-2nd connection electrode CN2-2 may extend from the first power line PL1. The 2-2nd connection electrode CN2-2 may be defined as the first power line PL1.

[0364] The first power line PL1 may be arranged to overlap the data line DL'. The first voltage ELVDD applied to the first power line PL1 may be a constant voltage. The first power line PL1 may be arranged to overlap the data line DL' and may perform a function similar to that of the shielding electrode SHE. The first power line PL1 adjacent to the receiving line RX may be arranged to overlap the data line DL' and may block the influence of the data voltage VD of the data line DL' on the receiving line RX.

[0365] FIG. 20A to FIG. 20D It is shown FIG. 14A to FIG. 14D A view of a modified embodiment of the layout shown in FIG.

[0366] In the following, the FIG. 20A to FIG. 20D The following description will focus on the components related to FIG. 14A to FIG. 14D The components shown in the figure are different components.

[0367] Fig. 20A Corresponds to Fig.14A , but for another embodiment. Fig. 20A In the embodiment, the second transverse line HBRS2' may be configured with Fig.14A A plurality of protrusions PRT may be defined on the second transverse line HBRS2'. Fig.14A Among the plurality of protrusions PRT of the second transverse line HBRS2 shown in FIG. 1 , the protrusions PRT of the second transverse line HBRS2′ may be omitted from the second transverse line HBRS2′. Fig.15 The 1st to 5th connection electrodes CN1-5 shown in FIG. overlap the protrusion PRT. The portion where the protrusion PRT is omitted is shown by a circular broken line.

[0368] Fig. 20B Corresponds to Fig. 14B However, some of the first connection electrodes CNE1-9 may be omitted. For example, Fig. 14B Among the plurality of first connection electrodes CNE1-9 shown in Fig. 20B Can be omitted Fig.15 The 1st to 5th connecting electrodes CN1-5 are shown in FIG.

[0369] Fig. 20C Corresponds to Fig. 14C , but for another embodiment. Fig. 20C In the embodiment of FIG. 1 , some of the second connection electrodes CNE2-2 may be omitted. Fig. 14C Among the plurality of second connection electrodes CNE2-2 shown in Fig. 20C Can be omitted Fig.15 The 2nd to 4th connecting electrodes CN2-4 are shown in FIG.

[0370] Reference Fig.20D , Fig.20D Corresponds to Fig.14D However, some of the third connection electrodes CNE3-1 may be omitted. For example, Fig.14D Among the plurality of third connection electrodes CNE3-1 shown in Fig.20D Can be omitted Fig.15 The 3rd-4th connecting electrode CN3-4 is shown in FIG.

[0371] Fig.21 It is shown Fig.20D 0047] Figure 2 is a view of a cross-sectional configuration of a second transverse line and an electrode connected to the second transverse line shown in FIG.

[0372] Fig.21 Can be with Fig.15 The following description will focus on Fig.15 The components shown in the figure are different components.

[0373] Reference Fig.15 , Fig.20D and Fig.21 ,exist Fig.21 Can be omitted Fig.15 In this case, a parasitic capacitor formed by the 1-5, 2-4, and 3-4 connection electrodes CN1-5, CN2-4, and CN3-4 and the adjacent data line DL' can be removed.

[0374] When the 1-5th, 2-4th, and 3-4th connecting electrodes CN1-5, CN2-4, and CN3-4 are used, a coupling phenomenon according to a parasitic capacitor formed by the 1-5th, 2-4th, and 3-4th connecting electrodes CN1-5 and CN2-4 and CN3-4 and the data line DL' may affect the sensing signal RS output through the second horizontal line HBRS2'.

[0375] However, in the embodiment of the present disclosure, the 1-5th connection electrode CN1-5, the 2-4th connection electrode CN2-4, and the 3-4th connection electrode CN3-4 may be omitted, and thus the above-described coupling phenomenon according to the parasitic capacitor may be prevented.

[0376] FIG. 22A to FIG. 22C It is shown FIG. 14A to FIG. 14D A view of a modified embodiment of the layout shown in FIG.

[0377] In the following, the FIG. 22A to FIG. 22C The following description will focus on the components related to FIG. 14A to FIG. 14D The components shown in the figure are different components.

[0378] Fig.22A Corresponds to Fig. 14B , but for another embodiment. The second transverse line HBRS2 may have Fig.14A The same configuration as the second transverse line HBRS2 shown in FIG. Accordingly, the protrusion PRT may be defined on the second transverse line HBRS2.

[0379] However, the configuration of the first connection electrode CNE1-9 may be different. The first contact hole CH1-9 may not be defined in some of the first connection electrodes CNE1-9. For example, the first contact hole CH1-9 may not be defined in Fig. 14B Among the plurality of first connection electrodes CNE1-9 shown in Fig.15 In the first link electrode CNE1-9 corresponding to the 1-5th link electrode CN1-5 shown in FIG. 1 , accordingly, the first link electrode CNE1-9 corresponding to the 1-5th link electrode CN1-5 may not be connected to the second transverse line HBRS2.

[0380] For example, a portion where the first contact hole CH1 - 9 is omitted is indicated by a dotted arrow.

[0381] Reference Fig. 22B , Fig. 22B Corresponds to Fig. 14C However, some of the second connection electrodes CNE2-2 may be formed integrally with the first power line PL1. Fig. 14C Among the plurality of second connection electrodes CNE2-2 shown in Fig.15 The second connection electrode CNE2 - 2 corresponding to the 2 - 4 connection electrode CN2 - 4 shown in FIG. 1 may be formed integrally with the first power line PL1 .

[0382] Fig. 22C Corresponds to Fig.14D , but for another embodiment. Fig. 22C The third connection pattern CNP3 of the embodiment depicted in FIG. Fig.14D The third connection pattern CNP3 of the embodiment is the same.

[0383] Fig.23 It is shown Fig. 22C 0047] Figure 2 is a view of a cross-sectional configuration of a second transverse line and an electrode connected to the second transverse line shown in FIG.

[0384] Fig.23 Can be with Fig.15 The following description will focus on Fig.15 The components shown in the figure are different components.

[0385] Reference Fig.15 , Fig. 22C and Fig.23 , Fig.23 The 1st-5th connection electrodes CN1-5 shown in FIG. 1 may not be connected to the second transverse line HBRS2. The plurality of 2nd-4th connection electrodes CN2-4 may be connected to the plurality of 1st-5th connection electrodes CN1-5, respectively, and the plurality of 3rd-4th connection electrodes CN3-4 may be connected to the plurality of 2nd-4th connection electrodes CN2-4, respectively.

[0386] The first power line PL1 may be adjacent to the 2-4th connection electrode CN2-4 and may be integrally formed with the 2-4th connection electrode CN2-4. For example, the 2-4th connection electrode CN2-4 may extend from the first power line PL1. The 2-4th connection electrode CN2-4 may be defined as the first power line PL1.

[0387] The first power line PL1 may be arranged to overlap the data line DL′. The first power line PL1 applied with a constant voltage may block the influence of the data voltage VD of the data line DL′ on the sensing signal RS of the second transverse line HBRS2.

[0388] According to an embodiment of the present disclosure, a shielding electrode to which a constant voltage is applied may be arranged between a transverse line connected to a data line and a receiving line. Accordingly, a signal-to-noise ratio of a sensing signal output through the receiving line may be improved. As a result, the sensing sensitivity of the sensor may be improved.

[0389] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: A 1-1 line, wherein the 1-1 line extends in a first direction; a 1-2 line extending in a second direction crossing the first direction and connected to the 1-1 line; a data line extending in the first direction and connected to the 1-2 line; a pixel connected to the data line; a receiving line extending in the first direction; a sensor connected to the receiving line; as well as A shielding electrode is disposed above the 1-2 line and overlaps the 1-2 line and the receiving line.

2. The display device according to claim 1, wherein: The 1-1th line and the data line are arranged in the same layer, and the receiving line is arranged on one layer below the 1-1th line and the data line.

3. The display device according to claim 2, wherein: The 1-2nd line is arranged below the receiving line.

4. The display device according to claim 3, wherein: The shielding electrode is arranged in a layer between the receiving line and the 1-2th line.

5. The display device according to claim 1, further comprising: a plurality of 1-1 connection electrodes, the plurality of 1-1 connection electrodes being arranged on the 1-2 line and connected to the 1-2 line; as well as a plurality of 2-1 connection electrodes, the plurality of 2-1 connection electrodes being arranged above the plurality of 1-1 connection electrodes and connected to the plurality of 1-1 connection electrodes, Wherein, the data line and the 1-1 line are connected to the plurality of 2-1 connection electrodes.

6. The display device according to claim 5, further comprising: a plurality of 1-2 connection electrodes, the plurality of 1-2 connection electrodes being arranged above the 1-2 line and connected to the 1-2 line; a plurality of 2-2 connection electrodes, the plurality of 2-2 connection electrodes being arranged above the plurality of 1-2 connection electrodes and connected to the plurality of 1-2 connection electrodes; a plurality of 3-1 connection electrodes extending from the data line and the 1-1 line, the plurality of 3-1 connection electrodes being arranged above the plurality of 2-1 connection electrodes and connected to the plurality of 2-1 connection electrodes; as well as A plurality of 3-2 connection electrodes are arranged above the plurality of 2-2 connection electrodes and connected to the plurality of 2-2 connection electrodes.

7. The display device according to claim 6, further comprising: a plurality of 1st-3rd connection electrodes, the plurality of 1st-3rd connection electrodes being arranged above the 1st-2nd line and connected to the 1st-2nd line, The plurality of 2-1 connection electrodes and the plurality of 2-2 connection electrodes and the plurality of 3-1 connection electrodes and the plurality of 3-2 connection electrodes are not arranged above the plurality of 1-3 connection electrodes.

8. The display device according to claim 7, wherein: The shielding electrode is arranged in the same layer as the multiple 1-1 connecting electrodes, the multiple 1-2 connecting electrodes and the multiple 1-3 connecting electrodes, the receiving line is arranged in the same layer as the multiple 2-1 connecting electrodes and the multiple 2-2 connecting electrodes, and the data line and the 1-1 line are arranged in the same layer as the multiple 3-1 connecting electrodes and the multiple 3-2 connecting electrodes.

9. The display device according to claim 7, wherein: The shielding electrode includes a plurality of first shielding electrodes disposed between the plurality of 1-1th connection electrodes, the plurality of 1-2th connection electrodes, and the plurality of 1-3th connection electrodes.

10. The display device according to claim 1, further comprising: an initialization line connected to the pixel, Wherein, the shielding electrode protrudes from the initialization line.

11. The display device according to claim 1, further comprising: A reset line is disposed above the receive line and adjacent to the data line.

12. The display device according to claim 1, further comprising: a plurality of 1-1 connection electrodes, the plurality of 1-1 connection electrodes being arranged above the 1-2 line and connected to the 1-2 line; A plurality of 1-2 connection electrodes, wherein the plurality of 1-2 connection electrodes are arranged above the 1-2 line; a plurality of 2-1 connection electrodes, the plurality of 2-1 connection electrodes being arranged above the plurality of 1-1 connection electrodes and connected to the plurality of 1-1 connection electrodes; a plurality of 2-2 connection electrodes, the plurality of 2-2 connection electrodes being arranged above the plurality of 1-2 connection electrodes and connected to the plurality of 1-2 connection electrodes; as well as a first power line, the first power line being adjacent to the plurality of 2-2 connection electrodes, the first power line being integrally formed with the plurality of 2-2 connection electrodes, Wherein, the data line and the 1-1 line are connected to the plurality of 2-1 connection electrodes.

13. The display device according to claim 12, wherein: The plurality of 1-2 connection electrodes are spaced apart from the 1-2 line spaces.

14. The display device according to claim 1, further comprising: a line 2-1, wherein the line 2-1 extends in the first direction; as well as a 2-2 line extending in the second direction and connected to the 2-1 line, Wherein, the 2-2 line is connected to the receiving line.

15. The display device according to claim 14, further comprising: a plurality of 1st to 4th connection electrodes, the plurality of 1st to 4th connection electrodes being arranged above the 2-2 line and connected to the 2-2 line; as well as a plurality of 2nd-3rd connection electrodes, the plurality of 2nd-3rd connection electrodes being arranged above the plurality of 1st-4th connection electrodes and connected to the plurality of 1st-4th connection electrodes, wherein the receiving line is arranged in the same layer as the plurality of second-third connection electrodes, and Among the plurality of 2nd-3rd connection electrodes, the 2nd-3rd connection electrode corresponding to the receiving line extends from the receiving line.

16. The display device according to claim 15, further comprising: a plurality of 1st to 5th connection electrodes, the plurality of 1st to 5th connection electrodes being arranged above the 2-2 line and connected to the 2-2 line; a plurality of 1st to 6th connection electrodes, the plurality of 1st to 6th connection electrodes being arranged above the 2-2 line and connected to the 2-2 line; a plurality of 2nd to 4th connection electrodes, the plurality of 2nd to 4th connection electrodes being arranged above the plurality of 1st to 5th connection electrodes and connected to the plurality of 1st to 5th connection electrodes; a plurality of 3rd-3rd connection electrodes, the plurality of 3rd-3rd connection electrodes being arranged above the plurality of 2nd-3rd connection electrodes and connected to the plurality of 2nd-3rd connection electrodes; as well as a plurality of 3rd-4th connection electrodes, the plurality of 3rd-4th connection electrodes being arranged above the plurality of 2nd-4th connection electrodes and connected to the plurality of 2nd-4th connection electrodes, wherein the 2-1st line is arranged in the same layer as the plurality of 3-3rd connecting electrodes, and Among the plurality of 3-3 connection electrodes, the 3-3 connection electrode connected to the 2-3 connection electrode not extending from the receiving line extends from the 2-1 line.

17. The display device according to claim 16, wherein: The shielding electrode includes a plurality of second shielding electrodes arranged between the plurality of 1st to 4th connecting electrodes, the plurality of 1st to 5th connecting electrodes, and the plurality of 1st to 6th connecting electrodes.

18. The display device according to claim 14, further comprising: a plurality of 1st to 4th connection electrodes, the plurality of 1st to 4th connection electrodes being arranged above the 2-2 line and connected to the 2-2 line; a plurality of 1st to 5th connection electrodes, the plurality of 1st to 5th connection electrodes being arranged above the 2-2 line and spaced apart from the 2-2 line; a plurality of 2nd-3rd connection electrodes, the plurality of 2nd-3rd connection electrodes being arranged above the plurality of 1st-4th connection electrodes and connected to the plurality of 1st-4th connection electrodes; a plurality of 2nd to 4th connection electrodes, the plurality of 2nd to 4th connection electrodes being arranged above the plurality of 1st to 5th connection electrodes and connected to the plurality of 1st to 5th connection electrodes; as well as a first power line, the first power line being adjacent to the plurality of second to fourth connection electrodes, the first power line being integrally formed with the plurality of second to fourth connection electrodes, wherein the receiving line is arranged in the same layer as the plurality of second-third connection electrodes, Among the plurality of second-third connection electrodes, the second-third connection electrode corresponding to the receiving line extends from the receiving line, and The 2-1st line is connected to a 2-3rd connection electrode spaced apart from the receiving line.

19. A display device comprising: A 1-1 line, wherein the 1-1 line extends in a first direction; a 1-2 line extending in a second direction crossing the first direction, the 1-2 line being arranged below the 1-1 line and connected to the 1-1 line; a data line extending in the first direction, arranged in the same layer as the 1-1 line and connected to the 1-2 line; a pixel connected to the data line; a receiving line extending in the first direction and arranged in a layer different from the layer in which the data line is arranged; a sensor connected to the receiving line; as well as A shielding electrode is disposed above the 1-2 line and overlaps the 1-2 line.

20. A display device, comprising: Line 1-1; a 1-2 line, the 1-2 line crossing the 1-1 line and connected to the 1-1 line; a data line, the data line crossing the 1-2 line and connected to the 1-2 line; a pixel connected to the data line; a receiving line arranged in a layer different from the layer in which the 1-2nd line is arranged; a sensor connected to the receiving line; as well as A plurality of shielding electrodes are arranged in a layer between the 1-2 line and the receiving line and overlap the 1-2 line.

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