Display panel and display device

Abstract

The invention discloses a display panel and a display device. A gate driving unit of the display panel comprises an output circuit, a receiving circuit and a storage capacitor which are connected, each of the output circuit and the receiving circuit comprises a gate transistor, an active part of the gate transistor is located on a first active layer, and a polar plate of the storage capacitor is located on a second active layer. The gate of the gate transistor and the other polar plate of the storage capacitor are located on a first gate layer, and the first gate layer, the first active layer and the second active layer are arranged in different layers; the active part of the gate transistor is arranged by using the material of the first active layer, and the polar plate of the storage capacitor is arranged by using the material of the second active layer, so that the polar plate of the storage capacitor is replaced by the material of the active layer from a metal material, a metal layer for preparing the polar plate of the storage capacitor originally is removed, and the number of film layers of the display panel is reduced; and the preparation process of the display panel is simplified.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The existing OLED (Organic Light-Emitting Diode) display devices have increasingly higher requirements for power consumption and screen-to-body ratio. In order to reduce power consumption and increase screen-to-body ratio, low-temperature polysilicon oxide (LTPO) technology is used. LTPO technology refers to the simultaneous use of low-temperature polysilicon thin-film transistors and oxide thin-film transistors, so that the driving circuit takes into account the advantages of low-temperature polysilicon thin-film transistors and oxide thin-film transistors, thereby reducing power consumption and leakage current.

[0003] Currently, display devices using LTPO technology have a large number of film layers, and a correspondingly large number of mask plates are required, resulting in a more complicated process and higher cost. Summary of the invention

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem of complex process of existing display devices using LTPO technology.

[0005] To solve the above-mentioned problems, the technical solutions provided by this application are as follows:

[0006] The present application proposes a display panel, which includes a plurality of gate driving units, wherein the gate driving units include an output circuit, a receiving circuit and a storage capacitor connected to each other, wherein the output circuit includes a first output transistor and a second output transistor connected to each other, wherein the drain of the first output transistor is connected to a clock line, the drain of the second output transistor is connected to a high potential line, and the area of ​​the first output transistor is larger than the area of ​​the second output transistor;

[0007] Among them, the output circuit and the receiving circuit both include a gate transistor, the active part of the gate transistor is located in the first active layer, one plate of the storage capacitor is located in the second active layer, the gate of the gate transistor and the other plate of the storage capacitor are located in the first gate layer, and the first gate layer, the first active layer, and the second active layer are all arranged in different layers.

[0008] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0010] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0011] Figure 1 This is a schematic diagram of the first structure of the display panel of this application.

[0012] Figure 2 This is an equivalent circuit diagram of a pixel driving circuit in a display panel of the present application.

[0013] Figure 3 This is a schematic diagram of the second structure of the display panel of this application.

[0014] Figure 4 This is a third structural diagram of the display panel of this application.

[0015] Figure 5 FIG. 4 is an equivalent circuit diagram of a gate driving circuit in a display panel of the present application.

[0016] Figure 6 This is a schematic diagram of the film layer in the display panel of this application.

[0017] Figure 7 This is a film layer diagram of the first gate layer in the display panel of this application.

[0018] Figure 8 This is a film layer diagram of the first active layer in the display panel of this application.

[0019] Fig. 9 This is a film layer stacking diagram of the first active layer and the first gate layer in the display panel of the present application.

[0020] Fig.10 This is a film layer diagram of the second active layer in the display panel of this application.

[0021] Fig.11 This is a film layer stacking diagram of the first active layer, the second active layer and the first gate layer in the display panel of the present application.

[0022] Fig.12 This is a film layer diagram of the second gate layer in the display panel of this application.

[0023] Fig.13 It is a film layer stacking diagram of the first active layer, the second active layer, the first gate layer and the second gate layer in the display panel of the present application.

[0024] Fig.14 This is a film layer diagram of the first source and drain layer in the display panel of the present application.

[0025] Fig.15 It is a film layer stacking diagram of the first active layer, the second active layer, the first gate layer, the second gate layer and the first source and drain layer in the display panel of the present application.

[0026] Fig.16 This is a film layer diagram of the second source and drain layer in the display panel of the present application.

[0027] Fig.17 It is a film layer stacking diagram of the first active layer, the second active layer, the first gate layer, the second gate layer, the first source and drain layer, and the second source and drain layer in the display panel of the present application.

[0028] Fig.18 This is a connection diagram of four consecutive gate driving units and clock lines in the display panel of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0030] See also Figures 1 to 17 The present application provides a display panel 100, which includes a display area AA and a non-display area NA arranged on one side of the display area AA.

[0031] In this embodiment, the display area AA includes a pixel driving circuit 300 having multiple pixel transistors, the multiple pixel transistors include silicon semiconductor transistors and oxide semiconductor transistors, the active part of the silicon semiconductor transistor is located in the first active layer 123, and the active part of the oxide semiconductor transistor is located in the second active layer 127.

[0032] In this embodiment, the non-display area NA is disposed on one side of the display area AA, and the non-display area NA includes a gate driving circuit 200 having a plurality of cascaded gate driving units 200a, each of which includes a plurality of gate transistors and a storage capacitor connected to the gate transistor;

[0033] In this embodiment, the active portion of the gate transistor is located in the first active layer 123 , and one plate of the storage capacitor is located in the second active layer 127 .

[0034] In some embodiments of the present application, the storage capacitor of the gate driving unit 200a is generally composed of two layers of metal material, so that the number of film layers of the display panel 100 is large, thereby increasing the number of mask plates, resulting in a more complicated process and higher cost; while the present application uses the material of the first active layer 123 to set the active part of the gate transistor, and the material of the second active layer 127 to set a plate of the storage capacitor, so that the plate of the storage capacitor is replaced by the metal material with the active layer material, the metal layer of the original plate of the storage capacitor is removed, the number of film layers of the display panel 100 is reduced, and the preparation process of the display panel 100 is simplified.

[0035] In this embodiment, the gate driving unit 200a also includes an output circuit 222 and a receiving circuit 221 connected to each other. The area of ​​the gate transistor in the output circuit 222 is larger than the area of ​​the gate transistor in the receiving circuit 221. Since the output circuit 222 is used to transmit control signals to the display area AA, and the receiving circuit 221 is used to transmit signals in the gate driving unit 200a at this level, the load of the gate transistor in the output circuit 222 is larger than the load of the gate transistor in the receiving circuit 221. In order to ensure the output load of the output circuit 222, the present application makes the area of ​​the gate transistor in the output circuit 222 larger than the area of ​​the gate transistor in the receiving circuit 221, thereby improving the transmission capacity of the output circuit 222.

[0036] It should be noted that the silicon semiconductor transistor of the present application is a P-type transistor, and the oxide semiconductor transistor is an N-type transistor.

[0037] It should be noted that the pixel transistor in the present application is a transistor constituting the pixel driving circuit 300 , and the gate transistor is a transistor constituting the gate driving circuit 200 .

[0038] The technical solution of the present application is now described in conjunction with specific embodiments.

[0039] See also Figure 1 The display panel 100 includes a display area AA and a non-display area NA disposed adjacent to the display area AA, and the display area AA is disposed within the display area AA. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is an area within the display panel 100 for performing a display function, and a plurality of display units for realizing the display function are disposed therein. The non-display area NA may be a frame area of ​​the display panel 100, and a functional component that assists the display unit in the display area AA to perform display may be disposed therein.

[0040] See also Figure 1The lower side of the display area AA is provided with a binding terminal 400, which can be connected to an external circuit, and transmits the signal input by the external circuit to the data line, thereby driving the display panel 100 to display the picture. For example, the binding terminal 400 can be bound and connected to a chip or a flip chip film, etc., to provide power and driving signals for the display panel 100.

[0041] In this embodiment, a plurality of light-emitting devices LED and a pixel driving circuit 300 for driving the light-emitting devices LED may be arranged in an array in the display area AA. The pixel driving circuit 300 may be a 7T1C, 7T2C, 8T2C, 8T3C, 8T4C or other pixel driving circuit 300. This application does not impose any specific limitation thereto. The following description will be made using the 8T2C pixel driving circuit 300 as an example.

[0042] See also Figure 2 The pixel driving circuit 300 may include a switch transistor T2A, a driving transistor T1A, a compensation transistor T3A, a first reset transistor T4A, a second reset transistor T7A, a third reset transistor T8A, a first light emitting transistor T5A, a second light emitting transistor T6A, a boost capacitor Cboost, and a control capacitor Cst2.

[0043] See also Figure 2, a first electrode of the switch transistor T2A is connected to the data signal line Data, a second electrode of the switch transistor T2A is connected to the control node A1, and a gate of the switch transistor T2A receives a switch control signal Pscan1; a first electrode of the driving transistor T1A is connected to the control node A1, a second electrode of the driving transistor T1A is connected to the control node B1, and a gate of the driving transistor T1A is connected to the control node Q1; a first electrode of the compensation transistor T3A is connected to the control node Q1, a second electrode of the compensation transistor T3A is connected to the control node B1, and a gate of the compensation transistor T3A receives a compensation control signal Nscan1; a first electrode of the first reset transistor T4A receives a first reset signal Vi1, a second electrode of the first reset transistor T4A is connected to the control node Q1, and a gate of the first reset transistor T4A receives a first reset control signal Nscan2; a first electrode of the second reset transistor T7A is connected to a second reset signal Vi2, a second electrode of the second reset transistor T7A is connected to the anode of the light emitting device, and a The gate receives the second reset control signal Pscan2; the first electrode of the third reset transistor T8A receives the third reset signal Vi3, the second electrode of the third reset transistor T8A is connected to the control node A1, and the gate of the third reset transistor T8A receives the third reset control signal Vi3; the first electrode of the first light-emitting transistor T5A is connected to the high-level source VDD, the second electrode of the first light-emitting transistor T5A is connected to the control node A1, and the gate of the first light-emitting transistor T5A receives the light-emitting control signal EM; the first electrode of the second light-emitting transistor T6A is connected to the second node B1, the second electrode of the second light-emitting transistor T6A is connected to the anode of the light-emitting device, and the gate of the second light-emitting transistor T6A receives the light-emitting control signal EM; one end of the boost capacitor Cboost is connected to the control node Q1, and the other end of the boost capacitor Cboost is connected to the gate of the switching transistor T2A; one end of the control capacitor Cst2 is connected to the control node Q1, and the other end of the control capacitor Cst2 is connected to the high-level source VDD; the cathode of the light-emitting device is connected to the low-level source VSS.

[0044] In this embodiment, the high level source VDD is used to provide a constant high voltage level to the pixel driving circuit 300 , and the low level source VSS is used to provide a constant low voltage level to the pixel driving circuit 300 .

[0045] In this embodiment, the switch transistor T2A, the drive transistor T1A, the second reset transistor T7A, the third reset transistor T8A, the first light-emitting transistor T5A, and the second light-emitting transistor T6A can be one of P-type transistors or N-type transistors, and the compensation transistor T3A and the first reset transistor T4A can be the other of P-type transistors or N-type transistors; this application is described by taking the switch transistor T2A, the drive transistor T1A, the second reset transistor T7A, the third reset transistor T8A, the first light-emitting transistor T5A, and the second light-emitting transistor T6A as P-type transistors, and the compensation transistor T3A and the first reset transistor T4A as N-type transistors as an example.

[0046] In this embodiment, the capacitance value of the boost capacitor Cboost is less than the capacitance value of the control capacitor Cst2. In this embodiment, the control capacitor Cst2 is mainly used to maintain the stability of the potential of the third node Q1, so the capacitance of the control capacitor Cst2 is relatively large, for example, the capacitance value range of the control capacitor Cst2 can be 45fF to 55fF, and the capacitance value range of the boost capacitor Cboost can be 5fF to 15fF.

[0047] In this embodiment, the first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain.

[0048] See also Figure 3 and Figure 4 The gate driving circuit 200 is disposed in the non-display area NA, and the gate driving circuit 200 can be disposed on both sides of the display area AA; the gate driving circuit 200 can include N cascaded gate driving units 200a, the N gate driving units 200a can be arranged along the first direction X, and the structure of the gate driving unit 200a can be various, for example, Figure 3 In the structure, the non-display area NA may include a plurality of first gate circuits 210 arranged and cascaded along the first direction X, a plurality of second gate circuits 220 arranged and cascaded along the first direction X, a plurality of third gate circuits 230 arranged and cascaded along the first direction X, a plurality of fourth gate circuits 240 arranged and cascaded along the first direction X, and a plurality of fifth gate circuits 250 arranged and cascaded along the first direction X.

[0049] In this embodiment, the second direction Y is parallel to the scan line of the display panel 100, the angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°, and the scan line can be a gate signal transmission line, such as at least one of a compensation control line, a first reset control line, a switch control line, a second reset control line or a light emitting control line.

[0050] See also Figure 3 and Figure 4The first gate circuit 210 is arranged on both sides of the display area AA. The first gate circuit 210 is used to transmit the compensation control signal Nscan1. A first gate circuit 210 is connected to two compensation control lines, that is, a first gate circuit 210 is used to output the compensation control signal Nscan1 to two rows of pixel driving circuits 300, that is, two rows of pixel driving circuits 300 require a first gate circuit 210.

[0051] See also Figure 3 and Figure 4 The second gate circuit 220 is arranged on both sides of the display area AA, the second gate circuit 220 and the first gate circuit 210 can be arranged along the second direction Y or the first direction X, the second gate circuit 220 is used to transmit the first reset control signal Nscan2, and a second gate circuit 220 is connected to two first reset control lines; at the same time, the first-level second gate circuit 220 of the present application is used to output the first reset control signal Nscan2 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level second gate circuit 220.

[0052] It should be noted that the attached Figure 3 and Figure 4 The second gate circuit 220 and the first gate circuit 210 are alternately arranged along the first direction X as an example for explanation. The actual situation can be adjusted according to the wiring space of the display panel. For example, the first gate circuit 210 can be arranged in a single column along the first direction X, and the second gate circuit 220 can be arranged in a single column along the first direction X.

[0053] See also Figure 3 and Figure 4 The fifth gate circuit 250 is arranged on both sides of the display area AA, and is located between the display area AA and the first gate circuit 210, and between the display area AA and the second gate circuit 220. The fifth gate circuit 250 is used to transmit the switch control signal Pscan1, and a fifth gate circuit 250 is connected to two switch control lines; at the same time, the first-level fifth gate circuit 250 of the present application is used to output the switch control signal Pscan1 to a row of pixel driving circuits 300, that is, a row of pixel driving circuits 300 requires a first-level fifth gate circuit 250.

[0054] Please note that Figure 3 and Figure 4 , a first gate circuit 210, a second gate circuit 220 and a fifth gate circuit 250 are provided on both sides of each display area AA, that is, the first gate circuit 210, the second gate circuit 220 and the fifth gate circuit 250 of the present application are driven simultaneously on both sides.

[0055] See also Figure 3 and Figure 4The third gate circuit 230 is arranged on the first side of the display area AA, and the third gate circuit 230 is located on the side of the first gate circuit 210 away from the display area AA. The third gate circuit 230 is used to transmit the second reset control signal Pscan2, and a third gate circuit 230 is connected to two second reset control lines; at the same time, the first-level fourth gate circuit 240 of the present application is used to output the compensation control signal Nscan1 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level third gate circuit 230.

[0056] See also Figure 3 and Figure 4 The fourth gate circuit 240 is arranged on the second side of the display area AA, and the fourth gate circuit 240 is located on the side of the first gate circuit 210 away from the display area AA. The fourth gate circuit 240 is used to transmit the light-emitting control signal EM, and a fourth gate circuit 240 is connected to two light-emitting control lines; at the same time, the first-level fourth gate circuit 240 of the present application is used to output the compensation control signal Nscan1 to the two-row pixel driving circuit 300, that is, the two-row pixel driving circuit 300 requires a first-level fourth gate circuit 240.

[0057] It should be noted that, in the present application, only the third gate circuit 230 is provided on one side of the display area AA, and only the fourth gate circuit 240 is provided on the other side of the display area AA, that is, the third gate circuit 230 and the fourth gate circuit 240 are unilaterally driven.

[0058] It should be noted that since the first reset signal Vi1 , the second reset signal Vi2 and the third reset signal Vi3 are all constant voltages, they do not need to be controlled by the corresponding gate driving circuit 200 and can be directly connected to the corresponding constant voltage source.

[0059] In this embodiment, the first gate circuit 210, the second gate circuit 220, the third gate circuit 230, the fourth gate circuit 240, and the fifth gate circuit 250 of the present application can be gate circuits of mTnC. In the following embodiment, the structure of the gate driving unit 200a of the present application is explained by taking the fifth gate circuit 250 as 8T2C as an example.

[0060] It should be noted that Figure 3 and Figure 4 The difference is that Figure 4 The middle display panel also has an under-screen camera area CUP. Figure 3 The under-screen camera area CUP is not set.

[0061] See also Figure 5The gate driving unit 200a may include a receiving circuit 221 and an output circuit 222, the receiving circuit 221 and the output circuit 222 are arranged along the second direction Y, the receiving circuit 221 is used to receive the level transmission signal generated by the upper gate driving circuit 200, the output circuit 222 is electrically connected to the receiving circuit 221 through the second node Q2 and the first node P2, and is used to output the control signal of the current level and the level transmission signal of the next level according to the signal of the second node Q2 and the signal of the first node P2.

[0062] See also Figure 5 The output circuit 222 includes a second output transistor T7 and a first output transistor T6, the gate of the second output transistor T7 is electrically connected to the second node Q2, the drain of the second output transistor T7 is electrically connected to the high potential line VGH, and the source of the second output transistor T7 is electrically connected to the output terminal OUT in the gate driving circuit 200; the gate of the first output transistor T6 is electrically connected to the first node P2, the drain of the first output transistor T6 is electrically connected to the second-type clock line CK, and the source of the first output transistor T6 is electrically connected to the output terminal OUT.

[0063] See also Figure 5 The receiving circuit 221 includes a first node control module 221a and a second node control module 221b, the first output transistor T6 and the first node control module 221a are connected to the first node P2, and the second output transistor T7 and the second node control module 221b are connected to the second node Q2.

[0064] See also Figure 5 The storage capacitor includes a first capacitor C1 and a second capacitor C2. The first capacitor C1 includes a first plate C1a and a second plate C1b, wherein the first plate C1a is connected to the output terminal OUT in the gate drive circuit 200, and the second plate C1b is connected to the first node P2; the second capacitor C2 includes a third plate C2a and a fourth plate C2b, wherein the third plate C2a is connected to the high potential line VGH, and the fourth plate C2b is connected to the second node Q2.

[0065] See also Figure 5 , the receiving circuit 221 includes a first transistor T1, a gate of the first transistor T1 is connected to the first-type clock line XCK, a drain of the first transistor T1 is connected to the low-potential line VGL, and a source of the first transistor T1 is connected to the second node Q2;

[0066] See also Figure 5 , the receiving circuit 221 includes a second transistor T2, the gate of the second transistor T2 is loaded with the first type clock line XCK, the drain of the second transistor T3 is connected to the initial signal line STV or the output terminal OUT of the previous gate driving unit 200a, and the source of the second transistor T3 is connected to the third node N2;

[0067] See also Figure 5 , the receiving circuit 221 includes a third transistor T3, the gate of the third transistor T3 is connected to the third node N2, the drain of the third transistor T3 is connected to the first type clock line XCK, and the source of the third transistor T3 is connected to the second node Q2;

[0068] See also Figure 5 , the receiving circuit 221 includes a fourth transistor T4, a gate of the fourth transistor T4 is connected to the second-type clock line CK, a drain of the fourth transistor T4 is connected to the source of the fifth transistor T5, and a source of the fourth transistor T4 is connected to the third node N2;

[0069] See also Figure 5 , the receiving circuit 221 includes a fifth transistor T5, a gate of the fifth transistor T5 is connected to the second node Q2, and a drain of the fifth transistor T5 is connected to the high potential line VGH;

[0070] See also Figure 5 The receiving circuit 221 includes an eighth transistor T8, a gate of the eighth transistor T8 is connected to the low potential line VGH, a drain of the eighth transistor T8 is connected to the third node N2, and a source of the eighth transistor T8 is connected to the first node P2.

[0071] It should be noted that the drain of the second transistor T2 is connected to the initial signal line STV only in the first stage, and in the gate driving unit 200a after the second stage, the drain of the third transistor T3 is electrically connected to the output terminal OUT of the previous gate driving unit 200a.

[0072] It should be noted that the source and drain in the above-mentioned transistor of the present application are only different in naming, as long as one of them is the output end and the other is the input end. In the present application, a source is described as the output end of the transistor and a drain is described as the input end of the transistor.

[0073] It should be noted that all transistors in the gate driving circuit 200 of the present application may be N-type transistors or P-type transistors, and all transistors in the gate driving circuit 200 of this embodiment are described by taking P-type transistors as an example.

[0074] It should be noted that the first node control module 221a of the present application may include a fourth transistor T4, a fifth transistor T5, and an eighth transistor T8, and the second node control module 221b may include a first transistor T1 and a third transistor T3; secondly, the second transistor T2 may also belong to the first node control module 221a.

[0075] It should be noted that since the first output transistor T6 is used to output the low-level output of the switch control signal Pscan1, the output load of the first output transistor T6 is greater than the output load of the second output transistor T7. In order to increase the output load of the first output transistor T6, the present application can make the area of ​​the first output transistor T6 greater than the area of ​​the second output transistor T7, thereby improving the output load capacity of the first output transistor T6.

[0076] See also Figure 6 The display area AA and the non-display area NA of the display panel 100 may be provided with a base substrate 110 and an array driving layer 120 provided on the base substrate 110; in the display area AA, the display panel 100 may also be provided with a pixel definition layer (not shown) provided on the array driving layer 120, a light emitting device layer (not shown) provided on the same layer as the pixel definition layer, and an encapsulation layer (not shown) provided on the pixel definition layer. The following mainly describes the film layer structure in the non-display area NA and the display area AA.

[0077] In the present embodiment, the base substrate 110 supports various layers disposed on the base substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent base substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque base substrate as well as a transparent base substrate may be used.

[0078] In the present embodiment, the base substrate 110 is used to support various film layers disposed on the base substrate 110, and the base substrate 110 may be made of an insulating material such as glass, quartz, or a polymer resin. The base substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0079] In this embodiment, the base substrate 110 may include a first flexible substrate 111, a first barrier layer 112, a second flexible substrate 113, and a second barrier layer 114 that are stacked. The first flexible substrate 111 and the second flexible substrate 113 may be formed of the same material such as polyimide, and the first barrier layer 112 and the second barrier layer 114 may be formed of an inorganic material including, for example, at least one of SiOx and SiNx.

[0080] See also Figure 6, the array driving layer 120 may include a plurality of thin film transistors, the thin film transistors may be of an etching barrier type, a back channel etching type, or may be divided into a bottom gate thin film transistor, a top gate thin film transistor and the like according to the position of the gate electrode and the active layer, or may be divided into an N-type thin film transistor and a P-type thin film transistor according to the performance of the thin film transistor, for example, the gate transistor in the non-display area AA may be a P-type thin film transistor, and the pixel transistor in the display area AA may be an N-type thin film transistor and a P-type thin film transistor; secondly, Figure 6 The thin film transistor in the Figure 2 The structural diagram of any transistor is merely a schematic diagram of each film layer of the display panel 100 of the present application.

[0081] See also Figure 6 The array driving layer 120 may include a blocking insulating layer BF disposed on the base substrate 110, a light shielding layer 121 embedded in the blocking insulating layer BF, a buffer layer 122 disposed on the blocking insulating layer BF, a first active layer 123 disposed on the buffer layer 122, a first insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first insulating layer 124, a second insulating layer 126 disposed on the first gate layer 125, and a first gate layer 126 disposed on the second insulating layer 126. A second active layer 127, a third insulating layer 128 disposed on the second active layer 127, a second gate layer 129 disposed on the third insulating layer 128, a fourth insulating layer 130 disposed on the second gate layer 129, a first source-drain layer 131 disposed on the fourth insulating layer 130, a first planarizing layer 132 disposed on the first source-drain layer 131, a second source-drain layer 133 disposed on the first planarizing layer 132, and a second planarizing layer 134 disposed on the second source-drain layer 133.

[0082] See also Figure 6 The light-shielding layer 121 is disposed on the second blocking layer 114. The light-shielding layer 121 is used to block external light from entering the thin film transistor from the bottom. The material of the light-shielding layer 121 can be composed of a black light-shielding material, such as a black light-shielding metal or a black organic material. The light-shielding layer 121 of the present application can be only disposed in the display area AA.

[0083] See also Figure 6 The buffer layer 122 is disposed on the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may include a compound composed of nitrogen, silicon and oxygen, such as a single-layer silicon oxide film layer, or a silicon oxide-silicon nitride stacked structure.

[0084] See also Figure 6, a first active layer 123 is arranged on the buffer layer 122, and a second active layer 127 is arranged on the second insulating layer 126. In the present application, the material of the first active layer 123 can be a silicon semiconductor, such as low-temperature polycrystalline silicon, etc., and the material of the second active layer 127 can be an oxide semiconductor, such as metal oxide, etc.; since the transistors in the gate driving unit 200a are all P-type transistors, no metal oxide semiconductor is arranged in the non-display area AA of the present application, and the pixel driving circuit 300 has N-type transistors and P-type transistors, so the display area AA of the present application is provided with metal oxide semiconductors and low-temperature polycrystalline silicon semiconductors.

[0085] See also Figure 6 The first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 are respectively arranged on the corresponding metal layers or semiconductor layers, and are separated by different layers of metal layers or semiconductor layers; the materials of the first insulating layer 124, the second insulating layer 126, the third insulating layer 128, and the fourth insulating layer 130 can be an inorganic substance composed of at least two elements in silicon oxynitride or an organic material with flatness.

[0086] See also Figure 6 The first gate layer 125 and the second gate layer 129 are respectively disposed on corresponding insulating layers. The materials of the first gate layer 125 and the second gate layer 129 may be copper, molybdenum or molybdenum-titanium alloy.

[0087] See also Figure 6 The first source-drain electrode layer 131 is disposed on the fourth insulating layer 130 , and the second source-drain electrode layer 133 is disposed on the first planar layer 132 . The materials of the first source-drain electrode layer 131 and the second source-drain electrode layer 133 may be copper or molybdenum-titanium alloy, copper or titanium, etc.

[0088] See also Figure 6 The first flat layer 132 and the second flat layer 134 are laid in a whole layer to ensure the flatness of the film layer of the array driving layer 120. The materials of the first flat layer 132 and the second flat layer 134 can be inorganic substances composed of nitride oxide silicon or organic materials with flatness.

[0089] according to Figure 6 It can be seen from the structure that the two plates of the storage capacitor in the non-display area AA of the present application are respectively composed of the material of the first gate layer 125 and the material of the second active layer 127. For example, the first plate C1a and the third plate C2a are located in the second active layer 127, and the second plate C1b and the fourth plate C2b are located in the first gate layer 125. The metal layer and an insulating layer between the original second active layer 127 and the first gate layer 125 are removed, the number of film layers of the display panel 100 is reduced, the preparation process of the display panel 100 is simplified, and the cost of the display panel 100 is reduced.

[0090] It should be noted that when all transistors in the gate driving circuit 200 of this embodiment are N-type transistors, the second active layer 127 can be used to set the active parts of all transistors in the gate driving circuit 200, and the material of the first active layer 123 and the material of the first gate layer 125 can form two plates of the storage capacitor.

[0091] The structure of each film layer in the gate driving unit 200a is described below according to the stack diagram. Figure 7 To Attachment Fig.17 In each of the drawings, a structural diagram of a corresponding film layer in a two-stage gate driving unit 200a is provided. The following embodiments are described by taking the film layer of a one-stage gate driving unit 200a in the drawings as an example.

[0092] See also Figure 7 , Figure 7 FIG. 1 is a film layer diagram of the first gate layer 125 in the display panel 100 of the present application.

[0093] In the present embodiment, the first gate layer 125 includes a first gate T6G of the first output transistor T6 and a second gate T7G of the second output transistor T7 , and the first gate T6G and the second gate T7G are arranged in the first direction X.

[0094] In this embodiment, the first gate T6G includes a first trunk gate T6Ga and at least two first branch gates T6Gb connected to the first trunk gate T6Ga, the first trunk gate T6Ga extends along the first direction X, the at least two first branch gates T6Gb extend along the second direction Y, and the at least two first branch gates T6Gb are arranged at intervals in the first direction X, and the first trunk gate T6Ga and part of the first branch gates T6Gb are reused as the second electrode plate C1b; for example, Figure 7 In the structure, the first gate T6G includes a first trunk gate T6Ga and two first branch gates T6Gb, and the first trunk gate T6Ga is arranged on a side of the first branch gate T6Gb close to the display area AA.

[0095] In this embodiment, the second gate T7G includes a second main gate T7Ga and a second branch gate T7Gb connected to the second main gate T7Ga, the second branch gate T7Gb extends along the second direction Y, and the second main gate T7Ga and at most a portion of the second branch gate T7Gb are reused as a fourth plate C2b; for example, Figure 7 In the structure, the second gate T7G includes a second trunk gate T7Ga and a second branch gate T7Gb, and the second trunk gate T7Ga is arranged on a side of the second branch gate T7Gb close to the display area AA.

[0096] In this embodiment, the length and number of the strip-shaped branch gates in the second direction Y are positively correlated with the output load of the output transistor. Therefore, in order to improve the driving capability of the first output transistor T6 and the second output transistor T7, the present application sets the first output transistor T6 and the second output transistor T7 as separately arranged strip-shaped branch gates, each strip-shaped branch gate bears the load of the corresponding transistor, the strip-shaped branch electrode corresponds to the channel of the active part in the corresponding transistor, and the space between two adjacent strip-shaped branch gates corresponds to the source and drain of the upper layer. The composite electric field formed by multiple separately arranged strip-shaped branch gates can improve the driving capability of the transistor.

[0097] In this embodiment, in the first direction X, the interval between two adjacent first branch gates T6Gb may be equal to the interval between the adjacent first branch gates T6Gb and the second branch gates T7Gb;

[0098] In this embodiment, since the output load of the second output transistor T7 is smaller than the output load of the first output transistor T6, the area of ​​the first gate T6G of the present application can be larger than the area of ​​the second gate T7G to improve the driving capability of the gate in the first output transistor T6.

[0099] See also Figure 7 The first gate layer 125 further includes a gate T1G of the first transistor T1, a gate T2G of the second transistor T2, a gate T3G of the third transistor T3, a gate T4G of the fourth transistor T4, a gate T5G of the fifth transistor T5, and a gate T8G of the eighth transistor T8.

[0100] See also Figure 7 The gate T1G of the first transistor T1, the gate T2G of the second transistor T2, the gate T3G of the third transistor T3, the gate T4G of the fourth transistor T4, the gate T5G of the fifth transistor T5, and the gate T8G of the eighth transistor T8 can all be long strip structures extending along the second direction Y.

[0101] See also Figure 7 , the gate T1G of the first transistor T1 is connected to the gate T2G of the second transistor T2, the gate T1G of the fifth transistor T5 is connected to the second gate T7G at one end away from the display area AA, the gate T1G of the first transistor T1 is set away from the display area AA, and the gate T2G of the second transistor T2 is set between the gate T1G of the first transistor T1 and the second gate T2G.

[0102] See also Figure 7The gate T4G of the fourth transistor T4 is arranged at an end of the first gate T6G away from the display area AA, the gate T3G of the third transistor T3 and the gate T8G of the eighth transistor T8 are arranged in the first direction X, and the gate T3G of the third transistor T3 is arranged close to the gate T1G of the first transistor T1, and the gate T8G of the eighth transistor T8 is arranged away from the gate T2G of the second transistor T2.

[0103] See also Figure 7 The first gate layer 125 also includes a first connection line L1 and a second connection line L2. One end of the first connection line L1 is arranged close to the gate T1G of the first transistor T1 and away from the gate T2G of the second transistor T2. The other end of the first connection line L1 overlaps with the first type of clock line XCK and is electrically connected to the first type of clock line XCK through a via. One end of the second connection line L2 is connected to the gate T4G of the fourth transistor T4 and away from the first output transistor T6. The other end of the second connection line L2 overlaps with the second type of clock line CK and is connected to the second type of clock line CK through a via.

[0104] See also Figure 8 and Fig. 9 , Figure 8 is a film layer diagram of the first active layer 123 in the display panel 100 of the present application, Fig. 9 FIG. 1 is a film layer stacking diagram of the first active layer 123 and the first gate layer 125 in the display panel 100 of the present application.

[0105] In this embodiment, the first active layer 123 includes a first active portion T6A of the first output transistor T6 and a second active portion T7A of the second output transistor T7, the first active portion T6A and the second active portion T7A both extend along the first direction X, and the first active portion T6A and the second active portion T7A are connected; the first active portion T6A and the first branch gate T6Gb partially overlap, the second active portion T7A and the second branch gate T7Gb partially overlap, and the overlapping portion of the first active portion T6A and the first branch gate T6Gb is the channel of the first output transistor T6, and the overlapping portion of the second active portion T7A and the second branch gate T7Gb is the channel of the second output transistor T7.

[0106] Since the first output transistor T6 is used to control the low-level output to quickly turn on the pixel transistors in the display area AA, the first output transistor T6 needs a stronger output capability; see Figure 8 and Fig. 9 In the second direction Y, the width of the first active portion T6A is greater than the width of the second active portion T7A. The increase in the width of the first active portion T6A increases the channel width of the first active portion T6A, thereby increasing the driving capability of the first output transistor T6.

[0107] It should be noted that the first active portion T6A and the second active portion T7A both include two separately arranged sub-portions, and the two separately arranged sub-portions can reduce the size of the first active portion T6A and the second active portion T7A in the second direction Y, avoiding the technical problem of static electricity concentration in the active portion.

[0108] In this embodiment, the first active layer 123 also includes an active portion T1A of the first transistor T1, an active portion T2A of the second transistor T2, an active portion T3A of the third transistor T3, an active portion T4A of the fourth transistor T4, an active portion T5A of the fifth transistor T5, and an active portion T8A of the eighth transistor T8, and the above active portions can all be long strip structures extending along the first direction X.

[0109] In this embodiment, the first active layer 123 also includes a third connecting line L3 and a fourth connecting line L4, and the third connecting line L3 and the fourth connecting line L4 are both long strip structures extending along the second direction Y. The active portion T5A of the fifth transistor T5 is connected to an end of the second active portion T7A away from the first active portion T6A through the third connecting line L3, one end of the fourth connecting line L4 is connected to an end of the active portion T5A of the fifth transistor T5 away from the third connecting line L3, and one end of the fourth connecting line L4 is connected to the active portion T4A of the fourth transistor T4.

[0110] It should be noted that in order to increase the wiring space of the present application, the conductor parts located in the first active layer 123 and on both sides of the channel in some transistors of the present application are reused as the source or drain of the corresponding transistor, and there is no need to separately set the source or drain of the corresponding transistor in the first source and drain layer 131, as follows.

[0111] See also Fig. 9 The overlapping portion of the active portion T1A and the gate T1G of the first transistor T1 is the channel of the first transistor T1, and both sides of the channel of the first transistor T1 are multiplexed as the source T1S and the drain T1D of the first transistor T1.

[0112] See also Fig. 9, the overlapping part of the active part T2A and the gate T2G of the second transistor T2 is the channel of the second transistor T2, and the two sides of the channel of the second transistor T2 are reused as the source T2S and the drain T2D of the second transistor T2; secondly, the active part T2A of the second transistor T2 includes at least two active branches T2Aa connected to each other, and the at least two active branches T2Aa are arranged in parallel along the second direction Y. The gate T2G of the second transistor T2 has an overlapping part with the at least two active branches T2Aa, so the second transistor T2 has two spaced channel parts, that is, the second transistor T2 can be composed of two transistors connected in series, and the setting of the two active branches T2Aa increases the width of the channel part and reduces the leakage current of the second transistor T2.

[0113] See also Fig. 9 The overlapping portion of the active portion T3A and the gate T3G of the third transistor T3 is the channel of the third transistor T3, and both sides of the channel of the third transistor T3 are multiplexed as the source T3S and the drain T3D of the third transistor T3.

[0114] See also Fig. 9 The overlapping portion of the active portion T4A and the gate T4G of the fourth transistor T4 is the channel of the fourth transistor T4, and both sides of the channel of the fourth transistor T4 are multiplexed as the source T4S and the drain T4D of the fourth transistor T4.

[0115] See also Fig. 9 , the overlapping part of the active part T5A of the fifth transistor T5 and the fifth gate T5G is the channel of the fifth transistor T5, and the two sides of the channel of the fifth transistor T5 are multiplexed as the source T5S and the drain T5D of the fifth transistor T5; at the same time, since the fifth gate T5G of the present application has two fifth branch gates T5Gb, the fifth transistor T5 has two spaced channel parts, that is, the fifth transistor T5 can be composed of two transistors connected in series, and the two fifth branch gates T5Gb are set to increase the width of the channel part and reduce the leakage current of the fifth transistor T5.

[0116] See also Fig. 9 The overlapping portion of the active portion T8A and the gate T8G of the eighth transistor T8 is the channel of the eighth transistor T8, and both sides of the channel of the eighth transistor T8 are multiplexed as the source T8S and the drain T8D of the eighth transistor T8.

[0117] It should be noted that the source T4S and the source T5S share the same structure.

[0118] In this embodiment, since the second transistor T2 and the eighth transistor T8 are used to control the potential of the first node P2, in order to improve the accuracy of the potential of the first node P2, the present application can increase the width of the active portion T8A of the eighth transistor T8 and the active portion T2A of the second transistor T2. For example, the width of the active portion T8A of the eighth transistor T8 and the active portion T2A of the second transistor T2 can both be greater than the width of the first active layer 123 which also includes the active portion T1A of the first transistor T1, the active portion T3A of the third transistor T3, the active portion T4A of the fourth transistor T4, and the active portion T5A of the fifth transistor T5.

[0119] See also Fig.10 and Fig.11 , Fig.10 is a film layer diagram of the second active layer 127 in the display panel 100 of the present application, Fig.11 1 is a film layer stacking diagram of the first active layer 123 , the second active layer 127 and the first gate layer 125 in the display panel 100 of the present application.

[0120] In this embodiment, the second active layer 127 includes a first plate C1a of the first capacitor C1 and a third plate C2a of the second capacitor C2. The first plate C1a and the second plate C1b are at least partially overlapped, and the third plate C2a and the fourth plate C2b are at least partially overlapped.

[0121] See also Fig.11 In order to increase the capacitance of the storage capacitor, the present application makes part of the outer contour of the first electrode plate C1a expand outward relative to the outer contour of the second electrode plate C1b, and part of the outer contour of the third electrode plate C2a expand outward relative to the outer contour of the fourth electrode plate C2b, which is equivalent to increasing the areas of the first electrode plate C1a and the third electrode plate C2a as much as possible.

[0122] In this embodiment, since the stability of the potential of the first node P2 is related to the stability of the low level output by the first output transistor T6, in order to ensure the output load of the first output transistor T6, the present application makes the capacitance of the first capacitor C1 greater than the capacitance of the second capacitor C2, that is, the overlapping area of ​​the first plate C1a and the second plate C1b is smaller than the overlapping area of ​​the third plate C2a and the fourth plate C2b.

[0123] In this embodiment, in order to increase the overlapping area of ​​the first electrode plate C1a and the second electrode plate C1b, the first electrode plate C1a may include a first trunk electrode plate C1aa and at least two first branch electrode plates C1ab connected to the first trunk electrode plate C1aa, the first trunk electrode plate C1aa extends along the first direction, at least two first branch electrode plates C1ab extend along the second direction, and the plurality of first branch electrode plates C1ab are spaced apart in the first direction X; at the same time, the first trunk electrode plate C1aa at least partially overlaps with the first trunk gate T6Ga, the first branch electrode plate C1ab at least partially overlaps with the corresponding first branch gate T6Gb, and the length of the first branch electrode plate C1ab is less than the length of the first branch gate T6Gb.

[0124] See also Fig.12 and Fig.13 , Fig.12 is a film layer diagram of the second gate layer 129 in the display panel 100 of the present application, Fig.13 1 is a film layer stack diagram of the first active layer 123 , the second active layer 127 , the first gate layer 125 and the second gate layer 129 in the display panel 100 of the present application.

[0125] In this embodiment, the second gate layer 129 includes a fifth connection line L5 which is a zigzag line segment. One end of the fifth connection line L5 is connected to the drain T1D of the first transistor T1 , and the other end of the fifth connection line L5 is connected to the gate T5G of the fifth transistor T5 .

[0126] It should be noted that the structure of the fifth connecting line L5 in the drawings is only an embodiment of the present application, and it can be adaptively adjusted according to the corresponding wiring space.

[0127] See also Fig.14 and Fig.15 , Fig.14 1 is a film layer diagram of the first source-drain electrode layer 131 in the display panel 100 of the present application. Fig.15 1 is a film layer stack diagram of the first active layer 123 , the second active layer 127 , the first gate layer 125 , the second gate layer 129 and the first source and drain layer 131 in the display panel 100 of the present application.

[0128] In this embodiment, the display panel 100 also includes a first source-drain layer 131 disposed on a side of the second active layer 127 away from the first active layer 123, and the first source-drain layer 131 includes a first source T6S and a first drain T6D of the first output transistor T6, and a second source T7S and a second drain T7D of the second output transistor T7.

[0129] In this embodiment, the first drain T6D includes a first branch drain T6Db, and the first branch drain T6Db extends along the second direction Y; for example Fig.14 and Fig.15 In the structure, the first drain T6D includes one first branch drain T6Db.

[0130] In this embodiment, the first source T6S includes a first branch source T6Sb, and the first branch source T6Sb extends along the second direction Y; for example Fig.14 and Fig.15 In the structure, the first source T6S includes two first branch source electrodes T6Sb, and the two first branch source electrodes T6Sb are disposed between one first branch drain electrode T6Db.

[0131] See also Fig.14 , two first branch source electrodes T6Sb and one first branch drain electrode T6Db are arranged at intervals in the first direction X, and two first branch gate electrodes T6Gb are arranged between corresponding adjacent first branch source electrodes T6Sb and first branch drain electrodes T6Db.

[0132] In this embodiment, the second drain T7D includes a second branch drain T7Db, and the second branch drain T7Db extends along the second direction Y; for example Fig.14 and Fig.15 In the structure, the second drain T7D includes one second branch drain T7Db.

[0133] In this embodiment, the second source electrode T7S includes a second branch source electrode T7Sb, and the second branch source electrode T7Sb extends along the second direction Y; for example Fig.14 and Fig.15 In the structure, the second source T7S includes one second branch source T7Sb.

[0134] See also Fig.14 The second branch source T7Sb and the second branch drain T7Db are spaced apart in the first direction X, and a second branch gate T7Gb is disposed between the second branch source T7Sb and the second branch drain T7Db.

[0135] See also Fig.14 and Fig.15 Among the two first branch source electrodes T6Sb, the first branch source electrode T6Sb close to the second output transistor T7 can be reused as the second branch source electrode T7Sb.

[0136] See also Fig.14 and Fig.15 The first source-drain layer 131 also includes a source trunk 131a extending along the first direction X, and the two first branch sources are connected to the source trunk 131a, and at least part of the source trunk 131a overlaps with the first capacitor C1; for example, the positive projection of the source trunk 131a on the first capacitor C1 in the figure is located inside the first capacitor C1.

[0137] See also Fig.15 The display panel 100 includes a plurality of first contact holes HL1 and a plurality of second contact holes HL2 disposed in the region where the first output transistor T6 is located, the first drain electrode T6D is connected to the first active portion T6A through the plurality of first contact holes HL1, and the first source electrode T6S is connected to the first active portion T6A through the plurality of second contact holes HL2.

[0138] See also Fig.15 The display panel 100 includes a plurality of third contact holes HL3 and a plurality of fourth contact holes HL4 provided in the region where the second output transistor T7 is located. The second drain electrode T7D is connected to the second active portion T7A through the plurality of third contact holes HL3. The second source electrode T7S is connected to the first active portion T6A through the plurality of fourth contact holes HL4. Since the second source electrode T7S is reused as the first source electrode T6S, the fourth contact hole HL4 in the region where the second source electrode T7S is located may also be the second contact hole HL2.

[0139] In the present embodiment, the first contact hole HL1 , the second contact hole HL2 , the third contact hole HL3 , and the sixth contact hole HL5 penetrate the second insulating layer 126 , the third insulating layer 128 , the fourth insulating layer 130 and a portion of the first insulating layer 124 .

[0140] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a first transmission segment TS1, one end of the first transmission segment TS1 is connected to the low potential line VGL through a via hole, and the other end of the first transmission segment TS1 is connected to one end of the active portion T1A of the first transistor T1 through a via hole.

[0141] See also Fig.14 and Fig.15 The first source-drain layer 131 includes a second transmission segment TS2, one end of the second transmission segment TS2 is connected to the other end of the active portion T1A of the first transistor T1 through a via hole, the other end of the second transmission segment TS2 is connected to an end of the fifth connection line L5 away from the output circuit 222 through a via hole, and the middle area of ​​the second transmission segment TS2 has an extension segment toward the output circuit 222, and the extension segment is connected to one end of the active portion T3A of the third transistor T3 through a via hole.

[0142] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a third transmission segment TS3, one end of the third transmission segment TS3 is connected to the other end of the active portion T3A of the third transistor T3 through the via hole, and the other end of the third transmission segment TS3 is connected to the gate T1G of the first transistor T1 through the via hole.

[0143] See also Fig.14 and Fig.15The first source-drain layer 131 includes a fourth transmission segment TS4, one end of the fourth transmission segment TS4 is connected to the gate T1G of the first transistor T1 away from the gate T2G of the second transistor T2 through the via hole, and the other end of the fourth transmission segment TS4 is connected to the first connection line L1 through the via hole.

[0144] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a fifth transmission segment TS5, one end of the fifth transmission segment TS5 is connected to the low potential line VGL through the via hole, and the other end of the fifth transmission segment TS5 is connected to the gate T8G of the eighth transistor T8 away from the output circuit 222 through the via hole.

[0145] See also Fig.14 and Fig.15 The first source-drain layer 131 includes a sixth transmission segment TS6, one end of the sixth transmission segment TS6 is connected to the gate T5G of the fifth transistor T5 away from the output circuit 222 through the via hole, and the other end of the sixth transmission segment TS6 is connected to the other end of the fifth connection line L5 through the via hole.

[0146] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a seventh transmission segment TS7, one end of the seventh transmission segment TS7 passes through a via hole and is connected to an end of the first drain electrode T6D away from the display area AA, and the other end of the seventh transmission segment TS7 passes through a via hole and is connected to an end of the gate T4G of the fourth transistor T4 close to the output circuit 222.

[0147] See also Fig.14 and Fig.15 The first source-drain layer 131 includes an eighth transmission segment TS8, one end of the eighth transmission segment TS8 is connected to one end of an active branch T2Aa of the second transistor T2 through a via hole, the other end of the eighth transmission segment TS8 is connected to one end of the active portion T4A of the fourth transistor T4 away from the active portion T5A of the fifth transistor T5 through a via hole, and the middle area of ​​the eighth transmission segment TS8 has a longitudinal segment and a transverse segment, the longitudinal segment is connected to the gate T3G of the third transistor T3 through the via hole, and the transverse segment is connected to one end of the active portion T8A of the eighth transistor T8 through the via hole.

[0148] See also Fig.14 and Fig.15 The first source-drain layer 131 includes a ninth transmission segment TS9, one end of the ninth transmission segment TS9 is connected to the other end of the active portion T8A of the eighth transistor T8 through the via hole, and the other end of the ninth transmission segment TS9 is connected to the first branch gate T6Gb of the first output transistor T6 away from the output circuit 222 through the via hole.

[0149] See also Fig.14 and Fig.15 The first source-drain layer 131 includes a tenth transmission segment TS10 and an eleventh transmission segment T11; in a gate driving unit 200a, the tenth transmission segment TS10 is connected to the second connection line L2 and a clock line, and the eleventh transmission segment T11 is connected to the first connection line L1 and another clock line; in another gate driving unit 200a, the tenth transmission segment TS10 is connected to the first connection line L1 and a clock line, and the eleventh transmission segment T11 is connected to the second connection line L2 and another clock line; therefore, in different gate driving units 200a, the positions of the tenth transmission segment TS10 and the eleventh transmission segment T11 are different.

[0150] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a twelfth transmission segment TS12, one end of the twelfth transmission segment TS12 passes through a via hole and is connected to an end of the first branch source T6Sb of the previous stage away from the display area AA, and the other end of the twelfth transmission segment TS12 passes through a via hole and is connected to one end of another active branch T2Aa of the second transistor T2.

[0151] See also Fig.14 and Fig.15 The first source-drain electrode layer 131 includes a thirteenth transmission segment TS13, the thirteenth transmission segment TS13 extends along the first direction Y, one end of the thirteenth transmission segment TS13 is connected to the second drain electrode T7D, and the other end of the thirteenth transmission segment TS13 is connected to the high potential line VGH.

[0152] See also Figures 16 to 18 , Fig.16 1 is a film layer diagram of the second source-drain electrode layer 133 in the display panel 100 of the present application. Fig.17 1 is a film layer stack diagram of the first active layer 123, the second active layer 127, the first gate layer 125, the second gate layer 129, the first source-drain electrode layer 131 and the second source-drain electrode layer 133 in the display panel 100 of the present application, Fig.18 1 is a connection diagram between four consecutive gate driving units 200 a and clock lines in the display panel 100 of the present application.

[0153] See also Figures 16 to 18 The display panel 100 further includes a second source-drain layer 133 disposed on a side of the first source-drain layer 131 away from the second active layer 127, the second source-drain layer 133 includes a low potential line VGL and a high potential line VGH, the low potential line VGL and the high potential line VGH extend along the first direction X and are arranged along the second direction Y, the high potential line VGH has an overlapping portion with the output circuit 222, and the low potential line VGL has an overlapping portion with the receiving circuit 221; for example, the high potential line VGH passes through a via hole and is connected to the thirteenth transmission segment TS13, and the low potential line VGL passes through a via hole and is connected to the first transmission segment TS1.

[0154] In the present embodiment, in the second direction Y, the width of the high potential line VGH may be greater than the width of the low potential line VGL.

[0155] See also Figures 16 to 18 The second source-drain layer 133 also includes a plurality of clock lines disposed between the low potential line VGL and the high potential line VGH. The plurality of clock lines extend along the first direction X and are arranged along the second direction Y. Some of the plurality of clock lines have overlapping portions with the output circuit 222 , and some of the plurality of clock lines have overlapping portions with the receiving circuit 221 .

[0156] See also Figures 16 to 18 The multiple clock lines include a first clock line CK1, a second clock line CK2, a third clock line CK3 and a fourth clock line CK4 which are arranged at intervals. The first clock line CK1 has an overlapping portion with the output circuit 222, and the second clock line CK2, the third clock line CK3 and the fourth clock line CK4 have an overlapping portion with the receiving circuit 221.

[0157] In this embodiment, each gate driving unit 200a is connected to two different clock lines among the first clock line CK1, the second clock line CK2, the third clock line CK3 and the fourth clock line CK4, that is, the first type clock line XCK and the second type clock line CK are two different clock lines among the above four.

[0158] See for example Fig.18 , the gate T4G of the fourth transistor T4 of the first gate driving unit 200a is connected to the first clock line CK1, and the gate T1G of the first transistor T1 is connected to the second clock line CK2; the gate T4G of the fourth transistor T4 of the second gate driving unit 200a is connected to the fourth clock line CK4, and the gate T1G of the first transistor T1 is connected to the first clock line CK1; the gate T4G of the fourth transistor T4 of the third gate driving unit 200a is connected to the third clock line CK3, and the gate T1G of the first transistor T1 is connected to the fourth clock line CK4; the gate T4G of the fourth transistor T4 of the fourth gate driving unit 200a is connected to the second clock line CK2, and the gate T1G of the first transistor T1 is connected to the third clock line CK3

[0159] It should be noted that this application is attached Fig.17 The two gate driving units 200a in the embodiment are respectively a first gate driving unit 200a and a second gate driving unit 200a.

[0160] In this embodiment, in the second direction Y, the width of a clock line is greater than the width of the low potential line VGL, and the width of a clock line is less than the width of the high potential line VGH; meanwhile, the width of each clock line may be equal.

[0161] In this embodiment, the second source-drain layer 133 further includes an initial signal line STV, and the initial signal line STV is provided between the high potential line VGH and the first clock line CK1.

[0162] It should be noted that the initial signal line STV is only connected to the active part T2A of the second transistor T2 in the first-level gate driving unit 200a, and the active part T2A of the second transistor T2 in the second-level and above gate driving units 200a is connected to the output terminal OUT of the previous-level gate driving unit 200a through the twelfth transmission segment TS12.

[0163] It should be noted that in the present application, the signal line transmitting the signal extends along the first direction X or the second direction Y, which only refers to that the signal line extends in this direction, and does not represent that the signal line is a straight line in this direction. It can be a diagonal line or multiple straight lines, etc.

[0164] The present application also provides a display device, which includes the above-mentioned display panel. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0165] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0166] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0167] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0168] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The invention comprises a plurality of gate driving units, wherein the gate driving units comprise an output circuit, a receiving circuit and a storage capacitor connected to each other, wherein the output circuit comprises a first output transistor and a second output transistor connected to each other, wherein the drain of the first output transistor is connected to a clock line, the drain of the second output transistor is connected to a high potential line, and the area of ​​the first output transistor is larger than the area of ​​the second output transistor; Among them, the output circuit and the receiving circuit both include a gate transistor, the active part of the gate transistor is located in the first active layer, one plate of the storage capacitor is located in the second active layer, the gate of the gate transistor and the other plate of the storage capacitor are located in the first gate layer, and the first gate layer, the first active layer, and the second active layer are all arranged in different layers.

2. The display panel according to claim 1, characterized in that: The receiving circuit includes a first node control module, the first output transistor and the first node control module are connected to a first node; Among them, the storage capacitor includes a first capacitor, the first capacitor includes a first plate and a second plate, the first plate is connected to the source of the first output transistor, the second plate is connected to the first node, the first plate is located in the second active layer, and the second plate is located in the first gate layer.

3. The display panel according to claim 2, characterized in that: The receiving circuit includes a second node control module, and the second output transistor and the second node control module are connected to a second node; Among them, the storage capacitor includes a second capacitor, the second capacitor includes a third plate and a fourth plate, the third plate is connected to the high potential line, the fourth plate is connected to the second node, the third plate is located in the second active layer, and the fourth plate is located in the first gate layer.

4. The display panel according to claim 3, characterized in that: The overlapping area of ​​the first electrode plate and the second electrode plate is greater than the overlapping area of ​​the third electrode plate and the fourth electrode plate.

5. The display panel according to claim 3, characterized in that: The first gate layer includes a first gate of the first output transistor and a second gate of the second output transistor, and the first gate and the second gate are arranged in a first direction; The area of ​​the first gate is greater than the area of ​​the second gate.

6. The display panel according to claim 5, characterized in that: The first gate includes a first main gate and at least two first branch gates connected to the first main gate, the first main gate extends along the first direction, the first branch gates extend along the second direction, and at least two first branch gates are spaced apart in the first direction; The second gate includes a second main gate and a second branch gate connected to the second main gate, the second main gate and the second branch gate extend along the second direction, the first branch gate and the second branch gate are arranged at intervals in the first direction, and the first main gate and the second main gate are arranged at intervals in the first direction; Among them, the first main gate and part of the first branch gate are reused as the second electrode plate, the second main gate and at most part of the second branch gate are reused as the fourth electrode plate, the second direction is parallel to the scanning line of the display panel, and the angle between the first direction and the second direction is greater than 0° and less than or equal to 90°.

7. The display panel according to claim 6, characterized in that: The first active layer includes a first active portion of the first output transistor and a second active portion of the second output transistor, the first active portion and the second active portion both extend along the first direction, and the first active portion and the second active portion are connected; The first active portion and a plurality of the first branch gates partially overlap, and the second active portion and a plurality of the second branch gates partially overlap.

8. The display panel according to claim 7, characterized in that: In the second direction, a width of the first active portion is greater than a width of the second active portion.

9. The display panel according to claim 6, characterized in that: The second active layer includes a first plate of the first capacitor and a third plate of the second capacitor; Among them, at least part of the outer contour of the first electrode plate is expanded outward relative to the outer contour of the second electrode plate, and at least part of the outer contour of the third electrode plate is expanded outward relative to the outer contour of the fourth electrode plate.

10. The display panel according to claim 9, characterized in that: The second electrode plate includes a first main electrode plate and at least two first branch electrode plates connected to the first main electrode plate, the first main electrode plate extends along the first direction, at least two first branch electrode plates extend along the second direction, and a plurality of first branch electrode plates are spaced apart in the first direction; The first trunk electrode plate at least partially overlaps with the first trunk grid, the first branch electrode plate at least partially overlaps with the corresponding first branch grid, and the length of the first branch electrode plate is less than the length of the first branch grid.

11. The display panel according to claim 6, characterized in that: The display panel further includes a first source-drain electrode layer disposed on a side of the second active layer away from the first active layer, and the first source-drain electrode layer includes: a first source and a first drain of the first output transistor, the first drain comprising a first branch drain, and the first source comprising a first branch source; a second source and a second drain of the second output transistor, the second drain includes a second branch drain, the second source includes a second branch source, the first branch drain, the first branch source, the second branch drain, and the second branch drain all extend along the second direction and are arranged at intervals along the first direction Among them, the first branch gate is provided with a first branch drain and a first branch source on both sides of the second direction, the second branch gate is provided with a second branch drain and a second branch source on both sides of the second direction, and the second branch source close to the first output transistor is reused as the first branch source.

12. The display panel according to claim 11, characterized in that: in, The first source-drain layer further includes a source trunk extending along the first direction, the first branch source is connected to the source trunk, and at least a portion of the source trunk overlaps with the first capacitor.

13. The display panel according to claim 11, characterized in that: The display panel further comprises a second source-drain electrode layer disposed on a side of the first source-drain electrode layer away from the first active layer, the second source-drain electrode layer comprising a low potential line and a high potential line, the low potential line and the high potential line extending along the first direction and arranged along the second direction; The high potential line has an overlapping portion with the output circuit, and the low potential line has an overlapping portion with the receiving circuit.

14. The display panel according to claim 13, characterized in that: In the second direction, the width of the high potential line is greater than the width of the low potential line.

15. The display panel according to claim 13, characterized in that: The second source-drain layer further includes a plurality of clock lines disposed between the low potential line and the high potential line, wherein the plurality of clock lines extend along the first direction and are arranged along the second direction; Part of the plurality of clock lines has an overlapping portion with the output circuit, and part of the plurality of clock lines has an overlapping portion with the receiving circuit.

16. The display panel according to claim 15, characterized in that: The plurality of clock lines include a first clock line, a second clock line, a third clock line and a fourth clock line which are arranged at intervals, the first clock line has an overlapping portion with the output circuit, and the second clock line, the third clock line and the fourth clock line have an overlapping portion with the receiving circuit; Wherein, each of the gate driving units is connected to two different ones of the first clock line, the second clock line, the third clock line and the fourth clock line.

17. The display panel according to claim 15, characterized in that: In the second direction, a width of the clock line is greater than a width of the low potential line, and a width of the clock line is less than a width of the high potential line.

18. The display panel according to any one of claims 1 to 17, characterized in that: The receiving circuit comprises: a first transistor, wherein a gate of the first transistor is connected to a first-type clock line, a drain of the first transistor is connected to a low potential line, and a source of the first transistor is connected to a second node; a second transistor, wherein a gate of the second transistor is connected to the first-type clock line, a drain of the second transistor is connected to an initial signal line or an output end of the gate driving unit of a previous stage, and a source of the second transistor is connected to a third node; a third transistor, wherein a gate of the third transistor is connected to a third node, a drain of the third transistor is connected to the first-type clock line, and a source of the third transistor is connected to the second node; a fourth transistor, wherein a gate of the fourth transistor is connected to the second-type clock line, a drain of the fourth transistor is connected to the source of the fifth transistor, and a source of the fourth transistor is connected to the third node; a fifth transistor, wherein a gate of the fifth transistor is connected to the second node, and a drain of the fifth transistor is connected to the high potential line; an eighth transistor, wherein a gate of the eighth transistor is connected to the low potential line, a drain of the eighth transistor is connected to the third node, and a source of the eighth transistor is connected to the first node; Wherein, the drain of the first output transistor is connected to the second-type clock line.

19. The display panel according to claim 18, characterized in that: The first gate layer of the display panel includes the gate of the second transistor, the first active layer of the display panel includes the active portion of the second transistor, and the gate of the second transistor extends along a second direction; The active portion of the second transistor includes at least two connected active branches, the at least two active branches are arranged in parallel along the second direction, and the gate of the second transistor has overlapping parts with the at least two active branches.

20. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 19.

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