Cross-chip platform compilation tool chain method

Abstract

The embodiment of the present application provides a cross-chip platform compilation tool chain method, the method comprising: scanning the target platform architecture specification file to extract instruction set features, building a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, and normalizing the multi-language syntax tree into a unified intermediate representation; building a cross-platform compiler to convert the intermediate representation into target code, designing a unified intermediate language based on the platform difference matrix to support multi-language compilation, creating an instruction mapper to convert the intermediate representation into target platform instructions, identifying the target architecture type through a platform identification code, querying a platform feature database to obtain instruction set features, designing test cases to verify the compilation results, and deploying the optimized target program to the target platform; the present application can improve the scalability and code quality of the compilation tool chain by building a unified intermediate representation layer and optimization framework, and achieve more efficient cross-platform support.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a cross-chip platform compilation tool chain method. Background Art

[0002] With the continuous development of chip technology, various new processor architectures continue to emerge, which puts higher requirements on cross-platform compilation tool chains. Traditional compilation tool chains mainly use independent compiler backends to support different target platforms. This approach has obvious shortcomings when dealing with multi-platform adaptation. Existing compilation tool chains usually need to develop dedicated code generators and optimization modules for each processor architecture, resulting in high development and maintenance costs, and it is difficult to quickly support new processor architectures.

[0003] The current mainstream cross-platform compilation toolchain faces challenges when dealing with complex mixed-language programming scenarios, and often requires building independent parsing and optimization components for different programming languages. This design not only increases the complexity of the toolchain, but also affects the effect of compilation optimization. At the same time, existing solutions mainly rely on preset optimization rules for code optimization, lack a deep understanding and utilization of the characteristics of the target platform, and it is difficult to give full play to the performance advantages of different processor architectures.

[0004] In the code generation and verification phase, there is still much room for improvement in existing technologies. The compilation tool chain lacks a complete static analysis and test verification mechanism, making it difficult to ensure the correctness and performance of the generated code. In addition, the platform adaptation and resource management strategies are relatively simple, prone to compatibility issues, and affect the final deployment effect. These problems seriously restrict the efficiency and quality of cross-platform software development. Summary of the invention

[0005] In response to the problems in the prior art, the present application provides a cross-chip platform compilation tool chain method, which can improve the scalability and code quality of the compilation tool chain by building a unified intermediate representation layer and optimization framework, and achieve more efficient cross-platform support.

[0006] In order to solve at least one of the above problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a cross-chip platform compilation tool chain method, comprising:

[0008] Scan the target platform architecture specification file to extract instruction set features, parse the operating system function interface definition, build a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, analyze the execution characteristics and memory access patterns of the instruction set features to build a platform feature database, build a language identifier to parse the source code language type, create a corresponding syntax parser and lexical analyzer for each programming language based on the platform feature database, use a unified semantic analysis framework to process multi-language syntax trees, traverse the syntax tree structure based on the visitor pattern, use a type inference system to build a unified type representation, process cross-language calls through a language interoperability interface, and normalize the multi-language syntax trees into a unified intermediate representation;

[0009] Construct a cross-platform compiler to convert the intermediate representation into target code, design a unified intermediate language based on the platform difference matrix to support multi-language compilation, create an instruction mapper to convert the intermediate representation into target platform instructions, construct a code optimizer based on the instruction set characteristics to perform constant folding and loop unrolling, use a scheduling algorithm to optimize the execution order of the target platform instructions, establish a library file linker to manage external dependencies, create a resource allocator to handle memory management, and use a target code generator to convert the optimized instructions into machine code;

[0010] During compilation, the target platform configuration descriptor is loaded, the target architecture type is identified through the platform identification code, the platform feature database is queried to obtain the instruction set features, the corresponding code conversion strategy is selected according to the platform difference matrix, a compilation task queue is constructed, the correctness of the machine code is checked using static analysis technology, test cases are designed to verify the compilation results, and the optimized target program is deployed to the target platform.

[0011] Furthermore, the scanning of the target platform architecture specification file extracts instruction set features, parses the operating system function interface definition, builds a platform difference matrix based on the instruction set features to record instruction formats and system call differences of different chip platforms, and analyzes the execution characteristics and memory access patterns of the instruction set features to build a platform feature database, including:

[0012] Read the target platform specification file to parse XML format data, use the document parser to extract the instruction set definition, create an instruction feature descriptor to record the opcode format, use the function interface analyzer to interpret the system call specification, build a function prototype table to store the interface parameter type, use the interface mapper to mark the function call convention, establish a feature extractor to analyze the instruction semantic attributes, verify the instruction set integrity through the rule engine, and use the data serializer to save the extraction results;

[0013] Create a difference analyzer to compare platform instruction formats, use a matrix generator to build instruction mapping relationships, establish a feature vector space to store execution properties, use an access pattern analyzer to study memory operations, build a performance prediction model to evaluate instruction efficiency, use an index builder to create a fast retrieval table, optimize data access performance through a cache manager, and establish a version controller to manage database updates.

[0014] Furthermore, the language identifier is constructed to parse the language type of the source code, a corresponding syntax parser and lexical analyzer are created for each programming language based on the platform feature database, and a unified semantic analysis framework is used to process multi-language syntax trees, including:

[0015] A file scanner is loaded to read the content of the source code file, a feature extractor is used to analyze the source code file format, a language feature vector is constructed based on the file format to record keyword features, a pattern recognizer is used to match the language identifier in the feature vector, a language rule base is established to store the recognition rule set, a decision tree classifier is used to determine the language type based on the rule set, a confidence calculator is used to evaluate the recognition result of the language type, a language mapping table is established based on the recognition result to record the corresponding relationship of the source file, and a verifier is used to confirm the accuracy of the language type;

[0016] The platform feature database is read to obtain instruction set constraints, a grammar generator is used to construct language grammar rules based on the instruction set constraints, a lexical analyzer is established according to the grammar rules to identify code morpheme units, a grammar analysis table generator is used to create a parsing table entry for the morpheme unit, a symbol table manager is constructed to record identifier information in the parsing table entry, a grammar tree builder is used to organize the grammatical structure of the identifier information, an error recoverer is used to handle parsing exceptions of the grammatical structure, a semantic action table is established to define processing rules for the grammatical structure, and a parser generation tool is used to create a parsing program.

[0017] Furthermore, the traversing the syntax tree structure based on the visitor pattern, using the type inference system to construct a unified type representation, processing cross-language calls through a language interoperability interface, and normalizing the multi-language syntax tree into a unified intermediate representation includes:

[0018] A type deriver is used to analyze the type information of the syntax tree nodes, a type dependency graph is constructed based on the type information to record the variable relationship, a type constraint solver is used to process the type equations in the dependency graph, a unified type system mapping table is constructed to store type conversion rules, a type unification algorithm is used to process the polymorphic characteristics of the type equations, a type checker is used to verify the consistency of the type conversion, a type annotator is established to mark type attributes in the syntax tree, and the type derivation process is optimized through a type cache manager;

[0019] Read the syntax tree nodes to create an intermediate code generator, build intermediate representation conversion rules based on the type attributes, use a static single assignment converter to process the variable definitions of the syntax tree, use a control flow analyzer to build the basic blocks of the intermediate representation, establish a data flow graph generator to record the usage relationship of the variable definitions, use a code normalizer to unify the intermediate representation format, build an optimization information collector to record the program features of the intermediate representation, and check the integrity of the intermediate representation through a verifier.

[0020] Further, the construction of a cross-platform compiler converts the intermediate representation into target code, designs a unified intermediate language based on the platform difference matrix to support multi-language compilation, creates an instruction mapper to convert the intermediate representation into target platform instructions, and constructs a code optimizer according to the instruction set characteristics to perform constant folding and loop unrolling, including:

[0021] Read the platform difference matrix to create an intermediate language definer, build instruction semantic description rules based on the intermediate representation, use an opcode generator to create a basic instruction set of the intermediate language, use a type system builder to define the data type of the intermediate language, establish a memory model generator to describe the storage layout of the intermediate language, use a control flow constructor to design the process structure of the intermediate language, build an exception handling descriptor to define an error handling mechanism, and check the standardization of the intermediate language through a semantic validator;

[0022] Read the instruction set features to create an instruction selector, build an instruction pattern matching table based on the intermediate language, use a tree matching algorithm to map the intermediate language to target instructions, use a cost evaluator to calculate the execution overhead of the target instructions, establish a register allocator to manage hardware resource usage, use an instruction scheduler to optimize the target instruction sequence, build an instruction pipeline analyzer to evaluate parallel execution characteristics, and output the assembly code of the target platform through a code generator.

[0023] Furthermore, the use of a scheduling algorithm to optimize the execution order of the target platform instructions, establishing a library file linker to manage external dependencies, creating a resource allocator to handle memory management, and using a target code generator to convert the optimized instructions into machine code includes:

[0024] Read the target platform instructions to create a dependency analyzer, build an instruction dependency graph based on the instruction pipeline characteristics, use a critical path analyzer to identify execution bottlenecks in the dependency graph, use a list scheduling algorithm to reorder the target platform instructions, establish a resource constraint checker to verify hardware resource usage, use an instruction packager to merge the target platform instruction sequence, build a loop pipeline optimizer to process loop body instructions, evaluate the performance overhead of the instruction sequence through an execution time predictor, and use a conflict eliminator to resolve resource competition for the instruction sequence;

[0025] Read the target platform instruction sequence to create a code segment manager, build a symbol resolution table based on the external dependency, use a relocation information generator to process address references, use a segment merger to organize the code segment layout structure, establish a link address allocator to plan the memory space layout, use a symbol export table generator to manage external interfaces, build a machine code generator to convert the target platform instructions, optimize the memory layout of the machine code through a code aligner, and use a checksum calculator to generate integrity check information for the machine code.

[0026] Furthermore, the target platform configuration descriptor is loaded during compilation, the target architecture type is identified by the platform identification code, the platform feature database is queried to obtain the instruction set features, a corresponding code conversion strategy is selected according to the platform difference matrix, a compilation task queue is constructed, the correctness of the machine code is checked by using static analysis technology, a test case is designed to verify the compilation result, and the optimized target program is deployed to the target platform, including:

[0027] Read the platform identification code to create an architecture identifier, build a platform configuration parser based on the platform feature database, use a feature matcher to read the instruction set feature information, use a policy selector to determine the conversion rule according to the platform difference matrix, establish a task scheduler to manage the compilation task queue, use a resource allocator to plan the use of compilation resources, build a dependency parser to process the association relationship of the platform configuration, check the integrity of the platform configuration through a configuration validator, and use a cache manager to optimize the loading process of the platform configuration;

[0028] Read the machine code to create a static analyzer, build code checking rules based on the instruction set features, use a control flow analyzer to verify the program execution path, use a data flow analyzer to check variable usage, establish a memory access verifier to check the legitimacy of address references, use a test case generator to create a verification sample set, build a coverage analyzer to evaluate test integrity, transfer the target program to the target platform through a deployment manager, and use a runtime environment configurator to set program execution parameters.

[0029] In a second aspect, the present application provides a cross-chip platform compilation tool chain device, including:

[0030] An intermediate unified module is used to scan the target platform architecture specification file to extract instruction set features, parse the operating system function interface definition, build a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, analyze the execution characteristics and memory access patterns of the instruction set features to build a platform feature database, build a language identifier to parse the source code language type, create a corresponding syntax parser and lexical analyzer for each programming language based on the platform feature database, use a unified semantic analysis framework to process multi-language syntax trees, traverse the syntax tree structure based on the visitor pattern, use a type inference system to build a unified type representation, process cross-language calls through a language interoperability interface, and normalize the multi-language syntax trees into a unified intermediate representation;

[0031] An instruction conversion module is used to build a cross-platform compiler to convert the intermediate representation into target code, design a unified intermediate language based on the platform difference matrix to support multi-language compilation, create an instruction mapper to convert the intermediate representation into target platform instructions, build a code optimizer according to the instruction set characteristics to perform constant folding and loop unrolling, use a scheduling algorithm to optimize the execution order of the target platform instructions, establish a library file linker to manage external dependencies, create a resource allocator to handle memory management, and use a target code generator to convert the optimized instructions into machine code;

[0032] The code compilation module is used to load the target platform configuration descriptor during compilation, identify the target architecture type through the platform identification code, query the platform feature database to obtain the instruction set features, select the corresponding code conversion strategy according to the platform difference matrix, build a compilation task queue, use static analysis technology to check the correctness of the machine code, design test cases to verify the compilation results, and deploy the optimized target program to the target platform.

[0033] In a third aspect, the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the cross-chip platform compilation tool chain method when executing the program.

[0034] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the cross-chip platform compilation tool chain method.

[0035] In a fifth aspect, the present application provides a computer program product, including a computer program / instruction, which implements the steps of the cross-chip platform compilation tool chain method when executed by a processor.

[0036] It can be seen from the above technical solution that the present application provides a cross-chip platform compilation tool chain method, which extracts instruction set features by scanning the target platform architecture specification file, builds a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, and normalizes the multi-language syntax tree into a unified intermediate representation; builds a cross-platform compiler to convert the intermediate representation into target code, designs a unified intermediate language based on the platform difference matrix to support multi-language compilation, creates an instruction mapper to convert the intermediate representation into target platform instructions, identifies the target architecture type through the platform identification code, queries the platform feature database to obtain the instruction set features, designs test cases to verify the compilation results, and deploys the optimized target program to the target platform, thereby improving the scalability and code quality of the compilation tool chain by building a unified intermediate representation layer and optimization framework, and achieving more efficient cross-platform support. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 This is one of the flow charts of the cross-chip platform compilation tool chain method in the embodiment of the present application;

[0039] Figure 2 This is the second flow chart of the cross-chip platform compilation tool chain method in the embodiment of the present application;

[0040] Figure 3 This is the third flow chart of the cross-chip platform compilation tool chain method in the embodiment of the present application;

[0041] Figure 4 This is a fourth flow chart of the cross-chip platform compilation tool chain method in an embodiment of the present application;

[0042] Figure 5 This is a fifth flow chart of the cross-chip platform compilation tool chain method in the embodiment of the present application;

[0043] Figure 6 This is the sixth flow chart of the cross-chip platform compilation tool chain method in the embodiment of the present application;

[0044] Figure 7 FIG7 is a flowchart of a cross-chip platform compilation tool chain method in an embodiment of the present application;

[0045] Figure 8It is a structural diagram of a cross-chip platform compilation tool chain device in an embodiment of the present application;

[0046] Fig. 9 It is a schematic diagram of the structure of an electronic device in an embodiment of the present application.

[0047] Reference numerals:

[0048] Electronic device 9600, central processing unit 9100, memory 9140, communication module 9110, input unit 9120, audio processor 9130, display 9160, power supply 9170, buffer memory 9141, application / function storage unit 9142, data storage unit 9143, driver program storage unit 9144, antenna 9111, speaker 9131, microphone 9132. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0050] The acquisition, storage, use, and processing of data in the technical solution of this application comply with the relevant provisions of national laws and regulations.

[0051] In view of the problems existing in the prior art, the present application provides a cross-chip platform compilation tool chain method, which extracts instruction set features by scanning the target platform architecture specification file, builds a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, and normalizes the multi-language syntax tree into a unified intermediate representation; builds a cross-platform compiler to convert the intermediate representation into target code, designs a unified intermediate language based on the platform difference matrix to support multi-language compilation, creates an instruction mapper to convert the intermediate representation into target platform instructions, identifies the target architecture type through the platform identification code, queries the platform feature database to obtain the instruction set features, designs test cases to verify the compilation results, and deploys the optimized target program to the target platform, thereby improving the scalability and code quality of the compilation tool chain by building a unified intermediate representation layer and optimization framework.

[0052] In order to improve the scalability and code quality of the compilation tool chain and achieve more efficient cross-platform support by building a unified intermediate representation layer and optimization framework, the present application provides an embodiment of a cross-chip platform compilation tool chain method, see Figure 1 The cross-chip platform compilation tool chain method specifically includes the following contents:

[0053] Step S101: Scan the target platform architecture specification file to extract instruction set features, parse the operating system function interface definition, build a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, analyze the execution characteristics and memory access patterns of the instruction set features to build a platform feature database, build a language identifier to parse the source code language type, create a corresponding syntax parser and lexical analyzer for each programming language based on the platform feature database, use a unified semantic analysis framework to process multi-language syntax trees, traverse the syntax tree structure based on the visitor pattern, use a type inference system to build a unified type representation, process cross-language calls through a language interoperability interface, and normalize the multi-language syntax trees into a unified intermediate representation;

[0054] Optionally, the present embodiment first reads the XML format specification file of the target platform through the architecture specification parser to extract the instruction set feature information. Specifically, the parser uses the document object model to analyze the file structure layer by layer to extract features such as instruction encoding format, operand type, addressing mode, etc. For example, when processing the ARM architecture, the parser can identify and extract the encoding rules of the Thumb instruction set and the standard ARM instruction set, including key information such as conditional execution flags, data processing instruction formats, branch jump instruction features, etc.

[0055] In the process of operating system interface analysis, the function call relationship diagram is established by scanning the system header files and library files. The analyzer records the function prototype, parameter type, calling convention and other information through the symbol table technology, and establishes the system call mapping relationship for different operating system platforms to realize the correct calling of cross-platform code.

[0056] The platform difference matrix is ​​constructed using the feature vector method to map the instruction features of each platform into a multidimensional vector space. The matrix contains information such as instruction format conversion rules, register mapping relationships, and memory alignment requirements, which are used to handle instruction conversion between different platforms. At the same time, by analyzing the instruction execution characteristics, a performance prediction model that includes elements such as instruction latency, pipeline characteristics, and cache access patterns is constructed.

[0057] In the multi-language source code parsing phase, a recognition mechanism based on language feature vectors and decision trees is implemented to accurately determine the language type of the source file. The system customizes dedicated parsers and lexical analyzers for various programming languages, and uses LALR(1) grammar to support context-dependent grammatical features. Syntax tree traversal is achieved through the visitor pattern, effectively processing advanced language features such as templates, generics, and closures.

[0058] The type system uses the Hindley-Milner algorithm to implement type inference, and handles type conversions between different languages ​​through an intermediate representation layer to ensure type safety in object-oriented programming and functional programming scenarios. For example, when dealing with mixed programming of C++ and Rust, the type system differences between the two languages ​​can be correctly handled.

[0059] This embodiment solves the technical problems of traditional cross-platform compilation tools in terms of multi-language support and type system uniformity. By establishing a unified intermediate representation and type system, the development efficiency and code reliability of mixed language projects are significantly improved. In practical applications, this solution can support mixed language development for multiple CPU architectures, effectively reducing the complexity of cross-platform development and improving compilation efficiency and runtime performance.

[0060] Step S102: construct a cross-platform compiler to convert the intermediate representation into target code, design a unified intermediate language based on the platform difference matrix to support multi-language compilation, create an instruction mapper to convert the intermediate representation into target platform instructions, construct a code optimizer according to the instruction set characteristics to perform constant folding and loop unrolling, use a scheduling algorithm to optimize the execution order of the target platform instructions, establish a library file linker to manage external dependencies, create a resource allocator to handle memory management, and use a target code generator to convert the optimized instructions into machine code;

[0061] Optionally, this embodiment builds a cross-platform compiler to generate target code based on a unified intermediate representation. First, a unified intermediate language is designed as a bridge layer, which fully considers the instruction format and system call differences recorded in the platform difference matrix and can accurately express the semantic features of various high-level languages. For example, when processing object-oriented features, the intermediate language expresses the inheritance and polymorphism of the class through the virtual function table and object layout description.

[0062] The instruction mapper is responsible for converting the intermediate representation into the instruction sequence of the target platform. It selects the most suitable instruction sequence to implement specific computing logic based on the instruction set characteristics in the platform feature database. When processing SIMD instructions, the instruction mapper analyzes data parallelism and automatically selects vectorized instructions to improve performance. For special instructions on different platforms, such as ARM's conditional execution instructions or x86's SSE instructions, the mapper selects the optimal instruction combination based on the actual scenario.

[0063] The code optimizer implements a series of platform-dependent optimization strategies. During constant folding, the optimizer considers the endianness and alignment requirements of the target platform to ensure that the optimized code meets the platform constraints. When loop unrolling, the unrolling factor is adaptively adjusted according to the cache size and branch prediction characteristics of the target processor. At the same time, the optimizer also implements dead code elimination and common subexpression elimination based on data flow analysis.

[0064] The instruction scheduling algorithm uses an improved list scheduling method to reasonably arrange the instruction execution order by analyzing the dependencies between instructions and the pipeline characteristics of the processor. When processing multi-issue processors, the scheduler will consider instruction-level parallelism and make full use of the parallel execution capabilities of the processor as much as possible. In the case of resource competition, the scheduler can intelligently insert bubble instructions to avoid conflicts.

[0065] The library file linker manages external dependencies through symbol resolution and relocation technology. It can handle both static and dynamic linking, and supports delayed binding mechanism to reduce startup overhead. For cross-language calling scenarios, the linker implements unified calling convention conversion to ensure correct interoperation between modules in different languages.

[0066] The resource allocator is responsible for memory management and implements stack frame layout and register allocation for the target platform. In embedded systems, the resource allocator pays special attention to memory usage efficiency, optimizes register allocation through active variable analysis, and reduces the number of memory accesses. For real-time systems, it also ensures the predictability of memory allocation to avoid uncertain performance overhead.

[0067] The target code generator eventually converts the optimized instructions into machine code, and generates necessary relocation information and debugging information. During the generation process, the code alignment requirements and cache line size of the target platform are considered, and the code layout is optimized to improve the cache hit rate.

[0068] This compilation process has shown significant advantages in embedded system development, especially when dealing with multi-core heterogeneous platforms, it can fully utilize the characteristics of various processor cores to generate efficient target code. Through a unified optimization framework, code performance and development efficiency are effectively improved, while ensuring the correctness and reliability of cross-platform code.

[0069] Step S103: load the target platform configuration descriptor during compilation, identify the target architecture type through the platform identification code, query the platform feature database to obtain the instruction set features, select the corresponding code conversion strategy according to the platform difference matrix, build a compilation task queue, use static analysis technology to check the correctness of the machine code, design test cases to verify the compilation results, and deploy the optimized target program to the target platform.

[0070] Optionally, during the compilation process, this embodiment first loads the configuration descriptor of the target platform, which uses JSON format to store platform-related configuration information, including key parameters such as processor model, memory model, and interrupt vector table. By parsing the platform identification code, the specific model and version of the target architecture, such as ARM Cortex-M4, RISC-VRV32IMAC, etc., can be accurately identified to provide basic information for subsequent compilation optimization.

[0071] When querying the platform feature database, this embodiment extracts the corresponding instruction set features according to the target architecture type, including information such as instruction length, addressing mode, and privilege level. For heterogeneous computing platforms, feature descriptions of coprocessor instruction sets and dedicated acceleration units are also obtained. This information directly affects the selection of code generation strategies, ensuring that the generated machine code can fully utilize the hardware features of the target platform.

[0072] When determining the code conversion strategy, the embodiment selects the most suitable instruction sequence conversion scheme by querying the platform difference matrix. For example, when converting floating-point operation code to a platform without a hardware floating-point unit, a fixed-point simulation scheme will be automatically selected; when processing SIMD instructions, different vectorization strategies will be selected according to the vector processing capabilities of the target platform.

[0073] The compilation task queue is constructed using a dependency graph model, which decomposes the compilation process into multiple task units that can be executed in parallel. For large projects, multi-core processors are fully utilized to increase compilation speed through task division and scheduling optimization. Each task unit includes steps such as code generation, optimization, and verification, and records the dependencies between tasks.

[0074] Static analysis technology implements multi-level code correctness checks. At the instruction level, it verifies the legality of instruction encoding and operand constraints; at the function level, it checks the calling convention and stack frame usage; at the system level, it verifies the compliance of interrupt handling and memory access. Especially in embedded real-time systems, the timing characteristics of the code are also analyzed to ensure that real-time requirements are met.

[0075] The design of test cases covers key scenarios such as instruction execution, exception handling, and interrupt response. The functional correctness and performance of the generated code are verified through comparative tests between the simulator and the actual hardware platform. For safety-critical applications, fault injection tests are also performed to verify the fault tolerance of the system.

[0076] In the final deployment phase, this embodiment generates a program image suitable for the target platform, including code segments, data segments, and startup configuration. According to the boot program requirements of the target platform, the program entry point and initialization sequence are correctly set. For systems that require online updates, incremental update packages are also generated to support dynamic updates of code.

[0077] Through this meticulous compilation and deployment process, this embodiment effectively solves the accuracy and efficiency issues of cross-platform code generation, and is particularly suitable for the development of embedded systems and real-time control systems. In practical applications, this solution can significantly improve code quality and system reliability, and reduce the workload of development and debugging.

[0078] From the above description, it can be seen that the cross-chip platform compilation tool chain method provided in the embodiment of the present application can extract instruction set features by scanning the target platform architecture specification file, build a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, and normalize the multi-language syntax tree into a unified intermediate representation; build a cross-platform compiler to convert the intermediate representation into target code, design a unified intermediate language based on the platform difference matrix to support multi-language compilation, create an instruction mapper to convert the intermediate representation into target platform instructions, identify the target architecture type through the platform identification code, query the platform feature database to obtain the instruction set features, design test cases to verify the compilation results, and deploy the optimized target program to the target platform, thereby improving the scalability and code quality of the compilation tool chain by building a unified intermediate representation layer and optimization framework.

[0079] In one embodiment of the cross-chip platform compilation tool chain method of the present application, see Figure 2 , and can also include the following:

[0080] Step S201: read the target platform specification file to parse the XML format data, use the document parser to extract the instruction set definition, create an instruction feature descriptor to record the operation code format, use the function interface analyzer to interpret the system call specification, build a function prototype table to store the interface parameter type, use the interface mapper to mark the function call convention, establish a feature extractor to analyze the instruction semantic attributes, verify the instruction set integrity through the rule engine, and use the data serializer to save the extraction results;

[0081] Step S202: Create a difference analyzer to compare the platform instruction format, use the matrix generator to build the instruction mapping relationship, establish a feature vector space to store execution attributes, use the access pattern analyzer to study memory operations, build a performance prediction model to evaluate instruction efficiency, use the index builder to create a quick retrieval table, optimize data access performance through the cache manager, and establish a version controller to manage database updates.

[0082] Optionally, this embodiment first implements an XML processor based on DOM parsing to parse the specification file of the target platform. The parser uses a tree structure to represent the document content and accurately locates the instruction set definition node through the xpath expression. When processing the ARM architecture specification, the parser can extract the complete definition of the Thumb and ARM instruction sets, including key information such as condition codes, operand formats, and addressing modes. The instruction feature descriptor organizes this information into a structured data model for subsequent processing and query.

[0083] The function interface analyzer builds a complete function call relationship graph by scanning system header files and library files. It uses symbol table technology to record function prototype information, including parameter types, return value types, and calling conventions. For cross-platform calls, the interface mapper will establish calling convention conversion rules between different platforms to ensure the correctness of function calls. The feature extractor uses static analysis technology to extract the semantic attributes of instructions, such as data dependencies, control flow characteristics, etc.

[0084] The rule engine uses a forward reasoning mechanism to verify the integrity and consistency of the instruction set, check whether there are conflicts in the instruction encoding, and ensure that all opcode combinations are valid. The data serializer converts the extracted results into a compact binary format, supporting fast loading and efficient querying.

[0085] The difference analyzer generates an instruction mapping relationship matrix by comparing the instruction formats of different platforms. The matrix generator uses the feature vector method to map the opcode, operand and execution characteristics of the instruction to a multi-dimensional vector space, which is convenient for calculating the similarity and conversion cost between instructions. The feature vector space contains execution properties such as instruction latency, throughput, resource usage, etc., providing a basis for code optimization.

[0086] The access pattern analyzer tracks the memory operations of instructions and builds a memory access pattern model. It can identify patterns such as sequential access, jump access, and loop access, providing guidance for cache optimization. The performance prediction model uses machine learning methods to predict the execution efficiency of instruction sequences based on the collected execution characteristic data, helping the compiler select the optimal instruction combination.

[0087] The index builder creates a multi-level index structure for the platform feature database, supporting efficient feature query and update operations. The cache manager implements a data cache mechanism based on the LRU strategy to reduce database access overhead. The version controller adopts an incremental update strategy to ensure the consistency and traceability of database content.

[0088] This embodiment provides reliable data support for cross-platform code generation through accurate instruction set feature extraction and platform difference analysis. In practical applications, especially when dealing with heterogeneous computing platforms, this solution can accurately capture the feature differences of different processor architectures and provide precise guidance for code optimization. By establishing an efficient feature data management mechanism, the data access efficiency in the compilation process is significantly improved, and the code generation speed is accelerated.

[0089] In embedded system development, the feature extraction and difference analysis capabilities of this embodiment effectively support cross-platform code transplantation and optimization, and improve development efficiency and code quality. In particular, when dealing with complex multi-core heterogeneous platforms, it can accurately grasp the characteristics of various processor cores and generate more optimized target code.

[0090] In one embodiment of the cross-chip platform compilation tool chain method of the present application, see Figure 3 , and can also include the following:

[0091] Step S301: loading a file scanner to read the source code file content, using a feature extractor to analyze the source code file format, constructing a language feature vector based on the file format to record keyword features, using a pattern recognizer to match the language identifier in the feature vector, establishing a language rule base to store a recognition rule set, using a decision tree classifier to determine a language type based on the rule set, evaluating the recognition result of the language type through a confidence calculator, establishing a language mapping table based on the recognition result to record the corresponding relationship of the source files, and using a verifier to confirm the accuracy of the language type;

[0092] Step S302: read the platform feature database to obtain instruction set constraints, use a syntax generator to construct language grammar rules based on the instruction set constraints, establish a lexical analyzer to identify code morpheme units according to the grammar rules, use a syntax analysis table generator to create a parsing table entry for the morpheme unit, build a symbol table manager to record the identifier information in the parsing table entry, use a syntax tree builder to organize the grammatical structure of the identifier information, handle the parsing exceptions of the grammatical structure through an error recoverer, establish a semantic action table to define the processing rules of the grammatical structure, and use a parser generation tool to create a parsing program.

[0093] Optionally, this embodiment first reads the source code file in byte stream mode through a file scanner, and uses multi-character set encoding detection technology to identify the file encoding format. The feature extractor constructs a high-dimensional feature vector by analyzing the grammatical features, keyword distribution, and identifier naming pattern of the file content. When processing mixed-language projects, the feature extractor can accurately identify code snippets in different languages, such as C++ and assembly code mixed in the same project.

[0094] The pattern recognizer uses a statistical learning-based method to match language features in feature vectors. It builds a language feature model by analyzing the frequency of keyword occurrence, grammatical structure features, and identifier naming conventions. The language rule base stores feature rule sets for various programming languages, including features such as grammatical rules, naming conventions, and code organization.

[0095] The decision tree classifier builds a multi-level decision model based on the rule set, and determines the language type of the source code through layer-by-layer screening. The confidence calculator uses a probability model to evaluate the reliability of the recognition results. For mixed language codes, it can accurately identify the boundaries of different languages. The language mapping table records the correspondence between source files and language types, and supports incremental updates and version management.

[0096] After obtaining the instruction set constraints, the syntax generator constructs adaptive syntax rules according to the characteristics of the target platform. For example, for the RISC architecture, the generated syntax rules will pay special attention to the standardization of the instruction format and the restrictions on the addressing mode. The lexical analyzer uses a finite automaton model to achieve efficient morpheme recognition. It can handle complex preprocessing instructions and macro definitions to ensure the accuracy of lexical analysis.

[0097] The parsing table generator uses the LALR(1) algorithm to create compact parsing tables, optimizing memory usage and parsing efficiency. The symbol table manager uses a hash table structure to achieve fast symbol query and scope management. When processing large projects, the symbol table manager reduces memory usage through a hierarchical storage mechanism.

[0098] The syntax tree builder organizes the syntax structure in a bottom-up manner, supporting incremental construction and local updates. The error recoverer implements a multi-level error recovery strategy, which can continue parsing when encountering syntax errors and provide detailed error diagnostic information. The semantic action table defines the processing rules of the syntax structure, including operations such as type checking, scope analysis, and code generation.

[0099] Through this language recognition and parsing mechanism, this embodiment effectively solves the problem of source code understanding in cross-language compilation. In practical applications, especially when dealing with complex projects involving multiple programming languages, it can accurately identify and parse codes in different languages, providing a reliable foundation for subsequent code conversion and optimization. This solution significantly improves the accuracy and efficiency of cross-language compilation and simplifies the workflow of developers.

[0100] When processing mixed language codes commonly used in embedded system development, this embodiment demonstrates excellent language recognition capabilities and parsing efficiency. Through accurate language feature extraction and parsing, it can correctly handle interface calls and data exchanges between different languages, ensuring that the generated target code meets platform requirements and performance requirements.

[0101] In one embodiment of the cross-chip platform compilation tool chain method of the present application, see Figure 4 , and can also include the following:

[0102] Step S401: using a type deriver to analyze the type information of the syntax tree nodes, constructing a type dependency graph to record variable relationships based on the type information, using a type constraint solver to process type equations in the dependency graph, constructing a unified type system mapping table to store type conversion rules, using a type unification algorithm to process the polymorphic characteristics of the type equations, using a type checker to verify the consistency of the type conversion, establishing a type annotator to mark type attributes in the syntax tree, and optimizing the type derivation process through a type cache manager;

[0103] Step S402: read the syntax tree node to create an intermediate code generator, construct an intermediate representation conversion rule based on the type attribute, use a static single assignment converter to process the variable definition of the syntax tree, use a control flow analyzer to build the basic block of the intermediate representation, establish a data flow graph generator to record the usage relationship of the variable definition, use a code normalizer to unify the intermediate representation format, build an optimization information collector to record the program features of the intermediate representation, and check the integrity of the intermediate representation through a verifier.

[0104] Optionally, the type derivation of this embodiment first performs a depth-first traversal of the syntax tree to analyze the type information of each node. When processing complex embedded system codes, the type derivation can accurately handle special types such as hardware register access, bit field operations, and fixed-point operations. The type dependency graph uses a directed graph structure to record the type relationship between variables, including explicit conversions and implicit conversions, with special attention to the precision loss and range constraints between different data types.

[0105] The type constraint solver uses a unified solving algorithm to process constraint equations in the type dependency graph. When processing cross-platform code, the constraint solver takes into account the differences in data types between different platforms, such as the bit width differences of integer types and the precision requirements of floating-point numbers. The unified type system mapping table records the type conversion rules between different platforms to ensure the security and accuracy of data type conversion.

[0106] The type unification algorithm uses an improved Hindley-Milner algorithm to process polymorphic types and supports function templates and generic programming features. The type checker verifies the correctness of type conversions through type compatibility analysis, paying special attention to type conversions that may cause runtime errors. The type annotator adds detailed type information to the syntax tree nodes to facilitate subsequent code generation and optimization.

[0107] The intermediate code generator generates a platform-independent intermediate representation based on the annotated syntax tree. When processing embedded system code, the generator pays special attention to preserving the special operational semantics related to the hardware. The static single assignment converter converts program variables into SSA form, simplifying the data flow analysis and optimization process.

[0108] The control flow analyzer constructs a basic block diagram to represent the execution flow of the program by identifying loop structures, branch statements, and function calls. When processing real-time system code, the analyzer pays special attention to the execution time and resource usage of the critical path. The data flow graph generator records the definition and usage relationship of variables, providing a basis for subsequent dead code elimination and constant propagation optimization.

[0109] The code normalizer unifies the format of the intermediate representation and simplifies the implementation of the subsequent optimization stage. The optimization information collector records the behavioral characteristics of the program, such as memory access patterns, loop nesting depth, and function call relationships, to provide guidance for platform-related optimizations.

[0110] Through this set of type analysis and intermediate representation generation mechanism, this embodiment effectively solves the type safety and code representation problems in cross-platform compilation. When processing mixed language code of embedded systems, it can accurately handle type conversion and data exchange between different languages, ensuring that the generated code meets the type system requirements of the target platform.

[0111] In practical applications, this embodiment significantly improves the type safety and portability of cross-platform code. Through precise type analysis and standardized intermediate representation, a reliable foundation is provided for subsequent code optimization. Especially when dealing with safety-critical systems that require strict type checking, this solution can effectively prevent type-related program errors and improve system reliability. At the same time, the unified intermediate representation format simplifies the implementation of different backends and improves the maintainability and extensibility of the compiler.

[0112] In one embodiment of the cross-chip platform compilation tool chain method of the present application, see Figure 5 , and can also include the following:

[0113] Step S501: read the platform difference matrix to create an intermediate language definer, construct instruction semantic description rules based on the intermediate representation, use an opcode generator to create a basic instruction set of the intermediate language, use a type system builder to define the data type of the intermediate language, establish a memory model generator to describe the storage layout of the intermediate language, use a control flow constructor to design the process structure of the intermediate language, construct an exception handling descriptor to define an error handling mechanism, and check the standardization of the intermediate language through a semantic verifier;

[0114] Step S502: read the instruction set features to create an instruction selector, build an instruction pattern matching table based on the intermediate language, use a tree matching algorithm to map the intermediate language to a target instruction, use a cost evaluator to calculate the execution overhead of the target instruction, establish a register allocator to manage hardware resource usage, use an instruction scheduler to optimize the target instruction sequence, build an instruction pipeline analyzer to evaluate parallel execution characteristics, and output the assembly code of the target platform through a code generator.

[0115] Optionally, the intermediate language definer of this embodiment first reads the platform difference matrix to create an intermediate language that can uniformly express the characteristics of different processor architectures. When processing RISC and CISC hybrid architectures, the intermediate language realizes the decomposition of complex instructions and the combined representation of basic operations by abstracting instruction semantics. The instruction semantic description rules use formal methods to define the behavior of instructions, including characteristics such as operand constraints, side effects, and exception conditions.

[0116] The opcode generator builds a complete set of virtual instructions based on the intermediate representation, which can express common computational operations, control flow transfers, and memory access patterns. The type system builder defines a type system that supports different data precision and alignment requirements, with a special focus on fixed-point operations and bit-field operations in embedded systems. The memory model generator describes the access characteristics of different storage hierarchies, including cache behavior, memory alignment, and address space partitioning.

[0117] The control flow builder designs a flexible flow control structure and supports optimization techniques such as conditional execution, loop unrolling, and function inlining. The exception handling descriptor defines a unified error handling mechanism to ensure that hardware and software exceptions can be correctly handled on different platforms. The semantic verifier verifies the semantic consistency of the intermediate language through formal methods.

[0118] The instruction selector builds an efficient instruction selection strategy by analyzing the instruction characteristics of the target platform. When processing the VLIW architecture, the instruction selector can make full use of instruction-level parallelism and select the optimal instruction combination. The tree matching algorithm uses a dynamic programming method to map the operation tree of the intermediate language to the instruction sequence of the target platform.

[0119] The cost estimator takes into account factors such as instruction latency, throughput, and resource usage to provide a quantitative basis for instruction selection. In real-time systems, the estimator pays special attention to the worst-case execution time of instruction sequences. The register allocator uses a graph coloring algorithm to implement an efficient register allocation strategy and reduce memory access overhead.

[0120] The instruction scheduler optimizes the order of instruction execution by analyzing data dependencies and resource constraints. When dealing with superscalar processors, the scheduler can effectively utilize multi-issue and out-of-order execution features. The instruction pipeline analyzer evaluates the parallel execution characteristics of instruction sequences to avoid pipeline conflicts and resource competition.

[0121] Through this set of intermediate language definition and code generation mechanism, this embodiment effectively solves the code conversion problem between heterogeneous processors. In practical applications, especially when dealing with systems with mixed architectures, efficient code that fully utilizes hardware features can be generated. This solution significantly improves the execution efficiency and resource utilization of cross-platform code.

[0122] In embedded system development, the intermediate language representation and instruction generation strategy of this embodiment show excellent adaptability. Through precise instruction selection and scheduling optimization, the generated code can meet the timing requirements and resource constraints of the real-time system. At the same time, the unified intermediate language representation simplifies the implementation of the code generator and improves the maintainability and extensibility of the compiler.

[0123] When processing a heterogeneous multi-core system, this embodiment can generate optimized code according to the characteristics of different processor cores, effectively supports load balancing and task migration, and improves the overall performance and energy efficiency of the system.

[0124] In one embodiment of the cross-chip platform compilation tool chain method of the present application, see Figure 6 , and can also include the following:

[0125] Step S601: read the target platform instructions to create a dependency analyzer, build an instruction dependency graph based on the instruction pipeline characteristics, use a critical path analyzer to identify execution bottlenecks in the dependency graph, use a list scheduling algorithm to reorder the target platform instructions, establish a resource constraint checker to verify hardware resource usage, use an instruction packager to merge the target platform instruction sequence, build a loop pipeline optimizer to process loop body instructions, evaluate the performance overhead of the instruction sequence through an execution time predictor, and use a conflict eliminator to resolve resource competition for the instruction sequence;

[0126] Step S602: read the target platform instruction sequence to create a code segment manager, build a symbol resolution table based on the external dependency, use a relocation information generator to process address references, use a segment merger to organize the code segment layout structure, establish a link address allocator to plan the memory space layout, use a symbol export table generator to manage external interfaces, build a machine code generator to convert the target platform instructions, optimize the memory layout of the machine code through a code aligner, and use a checksum calculator to generate integrity check information for the machine code.

[0127] Optionally, the dependency analyzer of this embodiment first reads the target platform instructions and constructs a data dependency and control dependency graph between instructions. When processing a superscalar processor architecture, the dependency analyzer pays special attention to true dependencies, anti-dependencies, and output dependencies between instructions to fully utilize the parallel execution capabilities of the processor. In the process of constructing the dependency graph based on pipeline characteristics, factors such as execution delay, throughput, and resource usage are taken into account.

[0128] The critical path analyzer uses graph theory algorithms to identify the key execution paths in the instruction sequence, focusing on optimizing the instruction chain that affects the overall performance. The list scheduling algorithm reorders instructions while ensuring dependencies to improve instruction-level parallelism. In the VLIW architecture, the instruction packager can combine multiple independent instructions into the same execution package to improve the processor's resource utilization.

[0129] The loop pipeline optimizer optimizes the hot loops in the program and improves loop execution efficiency through loop unrolling and software pipelining technology. The execution time predictor accurately estimates the execution cycle of the instruction sequence based on the microarchitecture characteristics of the processor. The conflict eliminator solves pipeline conflicts and resource competition problems by adjusting the instruction sequence and inserting no operations.

[0130] The code segment manager is responsible for organizing the instruction sequence of the target platform and establishing a symbol resolution table to record the dependencies between modules. The relocation information generator processes address references in the code and supports the generation of position-independent code. In embedded systems, the segment merger optimizes the layout structure of the code segment based on memory characteristics and access patterns.

[0131] The link address allocator considers the target platform's memory hierarchy and rationally plans the layout of the code and data segments. When dealing with systems on a chip, special attention is paid to the access characteristics and capacity limitations of different memory areas. The symbol export table generator manages the interfaces between modules and supports dynamic linking and runtime symbol resolution.

[0132] The machine code generator converts the target platform instructions into binary format, and the code aligner ensures the alignment of instructions in memory and optimizes cache performance. The checksum calculator generates code integrity check information through algorithms such as CRC to ensure reliable loading and execution of the program.

[0133] Through this set of instruction optimization and code generation mechanism, this embodiment effectively solves the performance optimization problem on the target platform. In practical applications, especially when processing performance-sensitive real-time systems, efficient machine code can be generated to meet the timing requirements and resource constraints of the system.

[0134] In embedded system development, the instruction scheduling and code generation strategy of this embodiment shows excellent adaptability. Through precise dependency analysis and optimized scheduling, the generated code can make full use of the hardware characteristics of the processor and improve execution efficiency. At the same time, reasonable code layout and linking strategy ensure the efficient operation of the program in a resource-constrained environment.

[0135] When processing a heterogeneous multi-core system, this embodiment can generate optimized machine code according to the instruction characteristics of different processor cores, effectively supporting system performance optimization and power consumption management, and improving overall operating efficiency and reliability.

[0136] In one embodiment of the cross-chip platform compilation tool chain method of the present application, see Figure 7 , and can also include the following:

[0137] Step S701: read the platform identification code to create an architecture identifier, build a platform configuration parser based on the platform feature database, use a feature matcher to read the instruction set feature information, use a policy selector to determine the conversion rule according to the platform difference matrix, establish a task scheduler to manage the compilation task queue, use a resource allocator to plan the use of compilation resources, build a dependency parser to process the association relationship of the platform configuration, check the integrity of the platform configuration through a configuration validator, and use a cache manager to optimize the loading process of the platform configuration;

[0138] Step S702: read the machine code to create a static analyzer, build code checking rules based on the instruction set characteristics, use a control flow analyzer to verify the program execution path, use a data flow analyzer to check variable usage, establish a memory access verifier to check the legitimacy of address references, use a test case generator to create a verification sample set, build a coverage analyzer to evaluate test integrity, transfer the target program to the target platform through a deployment manager, and use a runtime environment configurator to set program execution parameters.

[0139] Optionally, the architecture identifier of this embodiment first reads the platform identification code and obtains detailed feature information of the target platform through the platform configuration parser, including processor type, instruction set architecture, storage hierarchy, and peripheral features. When processing heterogeneous systems, the feature matcher can accurately identify the feature differences of different processor cores and provide basic information for subsequent code conversion.

[0140] The strategy selector selects the optimal code conversion strategy for different platform combinations based on the platform difference matrix. When dealing with RISC and CISC hybrid architectures, factors such as the expressiveness of the instruction set, execution efficiency, and resource overhead are considered. The task scheduler uses a priority queue to manage compilation tasks to ensure that key modules are processed first.

[0141] The resource allocator dynamically adjusts the allocation of computing resources according to the complexity of the compilation task and the system resource status. The dependency parser handles the association between platform configurations to ensure that the configuration parameters of different modules remain consistent. The configuration validator ensures the correctness of the platform configuration through integrity checking and conflict detection.

[0142] The static analyzer reads the generated machine code and verifies the code quality through techniques such as disassembly and symbolic analysis. The code checking rules are based on the instruction set characteristics of the target platform to verify the legality and optimization effect of the instruction sequence. The control flow analyzer verifies the integrity and reachability of the program's execution path by constructing a control flow graph.

[0143] The data flow analyzer checks the definition and usage relationship of variables to identify potential data competition and memory leak problems. The memory access verifier focuses on checking the legality of pointer operations and array access to ensure that the program does not have out-of-bounds access. In embedded systems, special attention is paid to the access compliance of restricted resources.

[0144] The test case generator automatically generates test cases covering various execution paths based on the control flow and data flow characteristics of the program. The coverage analyzer evaluates the integrity of the test by counting instruction execution and branch coverage. The deployment manager is responsible for securely transferring the verified program to the target platform and setting the correct execution permissions.

[0145] The runtime configurator sets the program's runtime parameters according to application requirements and platform characteristics, including stack size, interrupt priority, and resource limits. In real-time systems, special attention is paid to configuring task priorities and time constraint parameters.

[0146] Through this platform identification and program verification mechanism, this embodiment effectively solves the problem of program correctness and reliability on heterogeneous platforms. In practical applications, especially when dealing with safety-critical systems, potential program defects can be discovered early to ensure the stable operation of the system.

[0147] In embedded system development, the platform configuration and verification strategy of this embodiment shows excellent adaptability. Through comprehensive static analysis and automated testing, the quality assurance efficiency of the program is significantly improved. At the same time, the flexible deployment mechanism ensures that the program can run correctly on different platforms.

[0148] When processing complex heterogeneous systems, this embodiment can accurately identify platform features and perform corresponding optimization and verification, effectively supporting system reliability assurance and performance optimization, and improving overall development efficiency and product quality.

[0149] In order to improve the scalability and code quality of the compilation tool chain and achieve more efficient cross-platform support by building a unified intermediate representation layer and optimization framework, the present application provides an embodiment of a cross-chip platform compilation tool chain device for implementing all or part of the content of the cross-chip platform compilation tool chain method, see Figure 8 The cross-chip platform compilation tool chain device specifically includes the following contents:

[0150] The intermediate unification module 10 is used to scan the target platform architecture specification file to extract instruction set features, parse the operating system function interface definition, build a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, analyze the execution characteristics and memory access patterns of the instruction set features to build a platform feature database, build a language identifier to parse the source code language type, create a corresponding syntax parser and lexical analyzer for each programming language based on the platform feature database, use a unified semantic analysis framework to process multi-language syntax trees, traverse the syntax tree structure based on the visitor pattern, use a type inference system to build a unified type representation, process cross-language calls through a language interoperability interface, and normalize the multi-language syntax trees into a unified intermediate representation;

[0151] An instruction conversion module 20 is used to construct a cross-platform compiler to convert the intermediate representation into target code, design a unified intermediate language based on the platform difference matrix to support multi-language compilation, create an instruction mapper to convert the intermediate representation into target platform instructions, construct a code optimizer according to the instruction set characteristics to perform constant folding and loop unrolling, use a scheduling algorithm to optimize the execution order of the target platform instructions, establish a library file linker to manage external dependencies, create a resource allocator to handle memory management, and use a target code generator to convert the optimized instructions into machine code;

[0152] The code compilation module 30 is used to load the target platform configuration descriptor during compilation, identify the target architecture type through the platform identification code, query the platform feature database to obtain the instruction set characteristics, select the corresponding code conversion strategy according to the platform difference matrix, build a compilation task queue, use static analysis technology to check the correctness of the machine code, design test cases to verify the compilation results, and deploy the optimized target program to the target platform.

[0153] From the above description, it can be seen that the cross-chip platform compilation tool chain device provided in the embodiment of the present application can extract instruction set features by scanning the target platform architecture specification file, build a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, and normalize the multi-language syntax tree into a unified intermediate representation; build a cross-platform compiler to convert the intermediate representation into target code, design a unified intermediate language based on the platform difference matrix to support multi-language compilation, create an instruction mapper to convert the intermediate representation into target platform instructions, identify the target architecture type through the platform identification code, query the platform feature database to obtain the instruction set features, design test cases to verify the compilation results, and deploy the optimized target program to the target platform, thereby improving the scalability and code quality of the compilation tool chain by building a unified intermediate representation layer and optimization framework.

[0154] From the hardware level, in order to improve the scalability and code quality of the compilation tool chain and achieve more efficient cross-platform support by building a unified intermediate representation layer and optimization framework, the present application provides an embodiment of an electronic device for implementing all or part of the content in the cross-chip platform compilation tool chain method, and the electronic device specifically includes the following content:

[0155] Processor, memory, communication interface and bus; wherein the processor, memory and communication interface communicate with each other through the bus; the communication interface is used to realize information transmission between the cross-chip platform compilation tool chain device and the core business system, user terminal and related database and other related devices; the logic controller can be a desktop computer, a tablet computer and a mobile terminal, etc., but the present embodiment is not limited thereto. In the present embodiment, the logic controller can be implemented with reference to the embodiment of the cross-chip platform compilation tool chain method and the embodiment of the cross-chip platform compilation tool chain device in the embodiment, and the contents thereof are incorporated herein, and the repeated parts are not repeated.

[0156] It is understandable that the user terminal may include a smart phone, a tablet electronic device, a network set-top box, a portable computer, a desktop computer, a personal digital assistant (PDA), a vehicle-mounted device, a smart wearable device, etc. Among them, the smart wearable device may include smart glasses, a smart watch, a smart bracelet, etc.

[0157] In practical applications, part of the cross-chip platform compilation tool chain method can be executed on the electronic device side as described above, or all operations can be completed in the client device. The specific selection can be based on the processing capability of the client device and the limitations of the user's usage scenario. This application does not limit this. If all operations are completed in the client device, the client device may also include a processor.

[0158] The client device may have a communication module (i.e., a communication unit) that can communicate with a remote server to achieve data transmission with the server. The server may include a server on the task scheduling center side, and other implementation scenarios may also include a server on an intermediate platform, such as a server on a third-party server platform that has a communication link with the task scheduling center server. The server may include a single computer device, or a server cluster consisting of multiple servers, or a server structure of a distributed device.

[0159] Fig. 9 FIG. 9 is a schematic block diagram of the system structure of the electronic device 9600 according to an embodiment of the present application. Fig. 9 As shown, the electronic device 9600 may include a central processor 9100 and a memory 9140; the memory 9140 is coupled to the central processor 9100. It is worth noting that Fig. 9 is exemplary; other types of structures may also be used to supplement or replace this structure to implement telecommunication functions or other functions.

[0160] In one embodiment, the cross-chip platform compilation tool chain method function may be integrated into the central processing unit 9100. The central processing unit 9100 may be configured to perform the following control:

[0161] Step S101: Scan the target platform architecture specification file to extract instruction set features, parse the operating system function interface definition, build a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, analyze the execution characteristics and memory access patterns of the instruction set features to build a platform feature database, build a language identifier to parse the source code language type, create a corresponding syntax parser and lexical analyzer for each programming language based on the platform feature database, use a unified semantic analysis framework to process multi-language syntax trees, traverse the syntax tree structure based on the visitor pattern, use a type inference system to build a unified type representation, process cross-language calls through a language interoperability interface, and normalize the multi-language syntax trees into a unified intermediate representation;

[0162] Step S102: construct a cross-platform compiler to convert the intermediate representation into target code, design a unified intermediate language based on the platform difference matrix to support multi-language compilation, create an instruction mapper to convert the intermediate representation into target platform instructions, construct a code optimizer according to the instruction set characteristics to perform constant folding and loop unrolling, use a scheduling algorithm to optimize the execution order of the target platform instructions, establish a library file linker to manage external dependencies, create a resource allocator to handle memory management, and use a target code generator to convert the optimized instructions into machine code;

[0163] Step S103: load the target platform configuration descriptor during compilation, identify the target architecture type through the platform identification code, query the platform feature database to obtain the instruction set features, select the corresponding code conversion strategy according to the platform difference matrix, build a compilation task queue, use static analysis technology to check the correctness of the machine code, design test cases to verify the compilation results, and deploy the optimized target program to the target platform.

[0164] From the above description, it can be seen that the electronic device provided in the embodiment of the present application extracts instruction set features by scanning the target platform architecture specification file, builds a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, and normalizes the multi-language syntax tree into a unified intermediate representation; builds a cross-platform compiler to convert the intermediate representation into target code, designs a unified intermediate language based on the platform difference matrix to support multi-language compilation, creates an instruction mapper to convert the intermediate representation into target platform instructions, identifies the target architecture type through the platform identification code, queries the platform feature database to obtain the instruction set features, designs test cases to verify the compilation results, and deploys the optimized target program to the target platform, thereby improving the scalability and code quality of the compilation tool chain by building a unified intermediate representation layer and optimization framework.

[0165] In another embodiment, the cross-chip platform compilation tool chain device can be configured separately from the central processing unit 9100. For example, the cross-chip platform compilation tool chain device can be configured as a chip connected to the central processing unit 9100, and the cross-chip platform compilation tool chain method function is implemented through the control of the central processing unit.

[0166] like Fig. 9 As shown, the electronic device 9600 may also include: a communication module 9110, an input unit 9120, an audio processor 9130, a display 9160, and a power supply 9170. It is worth noting that the electronic device 9600 does not necessarily have to include Fig. 9 In addition, the electronic device 9600 may also include Fig. 9 For components not shown, reference may be made to the prior art.

[0167] like Fig. 9 As shown, the central processing unit 9100 is sometimes also referred to as a controller or an operation control, and may include a microprocessor or other processor device and / or logic device. The central processing unit 9100 receives input and controls the operation of various components of the electronic device 9600.

[0168] The memory 9140 may be, for example, one or more of a cache, a flash memory, a hard drive, a removable medium, a volatile memory, a non-volatile memory or other suitable devices. The above-mentioned information related to the failure may be stored, and a program for executing the relevant information may also be stored. The CPU 9100 may execute the program stored in the memory 9140 to implement information storage or processing, etc.

[0169] The input unit 9120 provides input to the central processing unit 9100. The input unit 9120 is, for example, a key or a touch input device. The power supply 9170 is used to provide power to the electronic device 9600. The display 9160 is used to display display objects such as images and texts. The display may be, for example, an LCD display, but is not limited thereto.

[0170] The memory 9140 may be a solid-state memory, such as a read-only memory (ROM), a random access memory (RAM), a SIM card, etc. It may also be a memory that saves information even when the power is off, can be selectively erased, and is provided with more data, examples of which are sometimes referred to as EPROMs, etc. The memory 9140 may also be some other type of device. The memory 9140 includes a buffer memory 9141 (sometimes referred to as a buffer). The memory 9140 may include an application / function storage unit 9142, which is used to store application programs and function programs or processes for executing the operation of the electronic device 9600 through the central processor 9100.

[0171] The memory 9140 may also include a data storage unit 9143 for storing data, such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. The driver storage unit 9144 of the memory 9140 may include various drivers for communication functions of the electronic device and / or for executing other functions of the electronic device (such as messaging applications, address book applications, etc.).

[0172] The communication module 9110 is a transmitter / receiver that sends and receives signals via the antenna 9111. The communication module 9110 (transmitter / receiver) is coupled to the central processor 9100 to provide input signals and receive output signals, which may be the same as the case of a conventional mobile communication terminal.

[0173] Based on different communication technologies, multiple communication modules 9110 may be provided in the same electronic device, such as a cellular network module, a Bluetooth module and / or a wireless LAN module. The communication module 9110 (transmitter / receiver) is also coupled to a speaker 9131 and a microphone 9132 via an audio processor 9130 to provide an audio output via the speaker 9131 and receive an audio input from the microphone 9132, thereby realizing a common telecommunication function. The audio processor 9130 may include any suitable buffer, decoder, amplifier, etc. In addition, the audio processor 9130 is also coupled to the central processor 9100, so that recording can be performed on the local machine through the microphone 9132, and the sound stored on the local machine can be played through the speaker 9131.

[0174] The embodiments of the present application also provide a computer-readable storage medium capable of implementing all the steps of the cross-chip platform compilation tool chain method in the above-mentioned embodiment, where the execution subject is a server or a client. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, all the steps of the cross-chip platform compilation tool chain method in the above-mentioned embodiment are implemented. For example, when the processor executes the computer program, the following steps are implemented:

[0175] Step S101: Scan the target platform architecture specification file to extract instruction set features, parse the operating system function interface definition, build a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, analyze the execution characteristics and memory access patterns of the instruction set features to build a platform feature database, build a language identifier to parse the source code language type, create a corresponding syntax parser and lexical analyzer for each programming language based on the platform feature database, use a unified semantic analysis framework to process multi-language syntax trees, traverse the syntax tree structure based on the visitor pattern, use a type inference system to build a unified type representation, process cross-language calls through a language interoperability interface, and normalize the multi-language syntax trees into a unified intermediate representation;

[0176] Step S102: construct a cross-platform compiler to convert the intermediate representation into target code, design a unified intermediate language based on the platform difference matrix to support multi-language compilation, create an instruction mapper to convert the intermediate representation into target platform instructions, construct a code optimizer according to the instruction set characteristics to perform constant folding and loop unrolling, use a scheduling algorithm to optimize the execution order of the target platform instructions, establish a library file linker to manage external dependencies, create a resource allocator to handle memory management, and use a target code generator to convert the optimized instructions into machine code;

[0177] Step S103: load the target platform configuration descriptor during compilation, identify the target architecture type through the platform identification code, query the platform feature database to obtain the instruction set features, select the corresponding code conversion strategy according to the platform difference matrix, build a compilation task queue, use static analysis technology to check the correctness of the machine code, design test cases to verify the compilation results, and deploy the optimized target program to the target platform.

[0178] From the above description, it can be seen that the computer-readable storage medium provided in the embodiment of the present application extracts instruction set features by scanning the target platform architecture specification file, builds a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, and normalizes the multi-language syntax tree into a unified intermediate representation; builds a cross-platform compiler to convert the intermediate representation into target code, designs a unified intermediate language based on the platform difference matrix to support multi-language compilation, creates an instruction mapper to convert the intermediate representation into target platform instructions, identifies the target architecture type through the platform identification code, queries the platform feature database to obtain the instruction set features, designs test cases to verify the compilation results, and deploys the optimized target program to the target platform, thereby improving the scalability and code quality of the compilation tool chain by building a unified intermediate representation layer and optimization framework.

[0179] The embodiments of the present application also provide a computer program product capable of implementing all the steps of the cross-chip platform compilation tool chain method in the above-mentioned embodiment, where the execution subject is a server or a client. When the computer program / instruction is executed by a processor, the steps of the cross-chip platform compilation tool chain method are implemented. For example, the computer program / instruction implements the following steps:

[0180] Step S101: Scan the target platform architecture specification file to extract instruction set features, parse the operating system function interface definition, build a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, analyze the execution characteristics and memory access patterns of the instruction set features to build a platform feature database, build a language identifier to parse the source code language type, create a corresponding syntax parser and lexical analyzer for each programming language based on the platform feature database, use a unified semantic analysis framework to process multi-language syntax trees, traverse the syntax tree structure based on the visitor pattern, use a type inference system to build a unified type representation, process cross-language calls through a language interoperability interface, and normalize the multi-language syntax trees into a unified intermediate representation;

[0181] Step S102: construct a cross-platform compiler to convert the intermediate representation into target code, design a unified intermediate language based on the platform difference matrix to support multi-language compilation, create an instruction mapper to convert the intermediate representation into target platform instructions, construct a code optimizer according to the instruction set characteristics to perform constant folding and loop unrolling, use a scheduling algorithm to optimize the execution order of the target platform instructions, establish a library file linker to manage external dependencies, create a resource allocator to handle memory management, and use a target code generator to convert the optimized instructions into machine code;

[0182] Step S103: load the target platform configuration descriptor during compilation, identify the target architecture type through the platform identification code, query the platform feature database to obtain the instruction set features, select the corresponding code conversion strategy according to the platform difference matrix, build a compilation task queue, use static analysis technology to check the correctness of the machine code, design test cases to verify the compilation results, and deploy the optimized target program to the target platform.

[0183] From the above description, it can be seen that the computer program product provided in the embodiment of the present application extracts instruction set features by scanning the target platform architecture specification file, builds a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, and normalizes the multi-language syntax tree into a unified intermediate representation; builds a cross-platform compiler to convert the intermediate representation into target code, designs a unified intermediate language based on the platform difference matrix to support multi-language compilation, creates an instruction mapper to convert the intermediate representation into target platform instructions, identifies the target architecture type through the platform identification code, queries the platform feature database to obtain instruction set features, designs test cases to verify the compilation results, and deploys the optimized target program to the target platform, thereby improving the scalability and code quality of the compilation tool chain by building a unified intermediate representation layer and optimization framework.

[0184] It should be understood by those skilled in the art that embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0185] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (apparatus), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0186] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0187] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0188] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A cross-chip platform compilation tool chain method, characterized in that: The method comprises: Scan the target platform architecture specification file to extract instruction set features, parse the operating system function interface definition, build a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, analyze the execution characteristics and memory access patterns of the instruction set features to build a platform feature database, build a language identifier to parse the source code language type, create a corresponding syntax parser and lexical analyzer for each programming language based on the platform feature database, use a unified semantic analysis framework to process multi-language syntax trees, traverse the syntax tree structure based on the visitor pattern, use a type inference system to build a unified type representation, process cross-language calls through a language interoperability interface, and normalize the multi-language syntax trees into a unified intermediate representation; Construct a cross-platform compiler to convert the intermediate representation into target code, design a unified intermediate language based on the platform difference matrix to support multi-language compilation, create an instruction mapper to convert the intermediate representation into target platform instructions, construct a code optimizer based on the instruction set characteristics to perform constant folding and loop unrolling, use a scheduling algorithm to optimize the execution order of the target platform instructions, establish a library file linker to manage external dependencies, create a resource allocator to handle memory management, and use a target code generator to convert the optimized instructions into machine code; During compilation, the target platform configuration descriptor is loaded, the target architecture type is identified through the platform identification code, the platform feature database is queried to obtain the instruction set features, the corresponding code conversion strategy is selected according to the platform difference matrix, a compilation task queue is constructed, the correctness of the machine code is checked using static analysis technology, test cases are designed to verify the compilation results, and the optimized target program is deployed to the target platform.

2. The cross-chip platform compilation tool chain method according to claim 1, characterized in that: The scanning of the target platform architecture specification file extracts instruction set features, parses the operating system function interface definition, builds a platform difference matrix based on the instruction set features to record instruction formats and system call differences of different chip platforms, and analyzes the execution characteristics and memory access patterns of the instruction set features to build a platform feature database, including: Read the target platform specification file to parse XML format data, use the document parser to extract the instruction set definition, create an instruction feature descriptor to record the opcode format, use the function interface analyzer to interpret the system call specification, build a function prototype table to store the interface parameter type, use the interface mapper to mark the function call convention, establish a feature extractor to analyze the instruction semantic attributes, verify the instruction set integrity through the rule engine, and use the data serializer to save the extraction results; Create a difference analyzer to compare platform instruction formats, use a matrix generator to build instruction mapping relationships, establish a feature vector space to store execution properties, use an access pattern analyzer to study memory operations, build a performance prediction model to evaluate instruction efficiency, use an index builder to create a fast retrieval table, optimize data access performance through a cache manager, and establish a version controller to manage database updates.

3. The cross-chip platform compilation tool chain method according to claim 1, characterized in that: The language identifier is constructed to parse the language type of the source code, a corresponding syntax parser and lexical analyzer are created for each programming language based on the platform feature database, and a unified semantic analysis framework is used to process multi-language syntax trees, including: A file scanner is loaded to read the content of the source code file, a feature extractor is used to analyze the source code file format, a language feature vector is constructed based on the file format to record keyword features, a pattern recognizer is used to match the language identifier in the feature vector, a language rule base is established to store the recognition rule set, a decision tree classifier is used to determine the language type based on the rule set, a confidence calculator is used to evaluate the recognition result of the language type, a language mapping table is established based on the recognition result to record the corresponding relationship of the source file, and a verifier is used to confirm the accuracy of the language type; The platform feature database is read to obtain instruction set constraints, a grammar generator is used to construct language grammar rules based on the instruction set constraints, a lexical analyzer is established according to the grammar rules to identify code morpheme units, a grammar analysis table generator is used to create a parsing table entry for the morpheme unit, a symbol table manager is constructed to record identifier information in the parsing table entry, a grammar tree builder is used to organize the grammatical structure of the identifier information, an error recoverer is used to handle parsing exceptions of the grammatical structure, a semantic action table is established to define processing rules for the grammatical structure, and a parser generation tool is used to create a parsing program.

4. The cross-chip platform compilation tool chain method according to claim 1, characterized in that: The method of traversing the syntax tree structure based on the visitor pattern, using the type inference system to construct a unified type representation, processing cross-language calls through a language interoperability interface, and normalizing the multi-language syntax tree into a unified intermediate representation includes: A type deriver is used to analyze the type information of the syntax tree nodes, a type dependency graph is constructed based on the type information to record the variable relationship, a type constraint solver is used to process the type equations in the dependency graph, a unified type system mapping table is constructed to store type conversion rules, a type unification algorithm is used to process the polymorphic characteristics of the type equations, a type checker is used to verify the consistency of the type conversion, a type annotator is established to mark type attributes in the syntax tree, and the type derivation process is optimized through a type cache manager; Read the syntax tree nodes to create an intermediate code generator, build intermediate representation conversion rules based on the type attributes, use a static single assignment converter to process the variable definitions of the syntax tree, use a control flow analyzer to build the basic blocks of the intermediate representation, establish a data flow graph generator to record the usage relationship of the variable definitions, use a code normalizer to unify the intermediate representation format, build an optimization information collector to record the program features of the intermediate representation, and check the integrity of the intermediate representation through a verifier.

5. The cross-chip platform compilation tool chain method according to claim 1, characterized in that: The cross-platform compiler is constructed to convert the intermediate representation into target code, a unified intermediate language is designed based on the platform difference matrix to support multi-language compilation, an instruction mapper is created to convert the intermediate representation into target platform instructions, and a code optimizer is constructed according to the instruction set characteristics to perform constant folding and loop unrolling, including: Read the platform difference matrix to create an intermediate language definer, build instruction semantic description rules based on the intermediate representation, use an opcode generator to create a basic instruction set of the intermediate language, use a type system builder to define the data type of the intermediate language, establish a memory model generator to describe the storage layout of the intermediate language, use a control flow constructor to design the process structure of the intermediate language, build an exception handling descriptor to define an error handling mechanism, and check the standardization of the intermediate language through a semantic validator; Read the instruction set features to create an instruction selector, build an instruction pattern matching table based on the intermediate language, use a tree matching algorithm to map the intermediate language to target instructions, use a cost evaluator to calculate the execution overhead of the target instructions, establish a register allocator to manage hardware resource usage, use an instruction scheduler to optimize the target instruction sequence, build an instruction pipeline analyzer to evaluate parallel execution characteristics, and output the assembly code of the target platform through a code generator.

6. The cross-chip platform compilation tool chain method according to claim 1, characterized in that: The method uses a scheduling algorithm to optimize the execution order of the target platform instructions, establishes a library file linker to manage external dependencies, creates a resource allocator to handle memory management, and uses a target code generator to convert the optimized instructions into machine code, including: Read the target platform instructions to create a dependency analyzer, build an instruction dependency graph based on the instruction pipeline characteristics, use a critical path analyzer to identify execution bottlenecks in the dependency graph, use a list scheduling algorithm to reorder the target platform instructions, establish a resource constraint checker to verify hardware resource usage, use an instruction packager to merge the target platform instruction sequence, build a loop pipeline optimizer to process loop body instructions, evaluate the performance overhead of the instruction sequence through an execution time predictor, and use a conflict eliminator to resolve resource competition for the instruction sequence; Read the target platform instruction sequence to create a code segment manager, build a symbol resolution table based on the external dependency, use a relocation information generator to process address references, use a segment merger to organize the code segment layout structure, establish a link address allocator to plan the memory space layout, use a symbol export table generator to manage external interfaces, build a machine code generator to convert the target platform instructions, optimize the memory layout of the machine code through a code aligner, and use a checksum calculator to generate integrity check information for the machine code.

7. The cross-chip platform compilation tool chain method according to claim 1, characterized in that: The target platform configuration descriptor is loaded during compilation, the target architecture type is identified by the platform identification code, the platform feature database is queried to obtain the instruction set features, a corresponding code conversion strategy is selected according to the platform difference matrix, a compilation task queue is constructed, the correctness of the machine code is checked by using static analysis technology, a test case is designed to verify the compilation result, and the optimized target program is deployed to the target platform, including: Read the platform identification code to create an architecture identifier, build a platform configuration parser based on the platform feature database, use a feature matcher to read the instruction set feature information, use a policy selector to determine the conversion rule according to the platform difference matrix, establish a task scheduler to manage the compilation task queue, use a resource allocator to plan the use of compilation resources, build a dependency parser to process the association relationship of the platform configuration, check the integrity of the platform configuration through a configuration validator, and use a cache manager to optimize the loading process of the platform configuration; Read the machine code to create a static analyzer, build code checking rules based on the instruction set features, use a control flow analyzer to verify the program execution path, use a data flow analyzer to check variable usage, establish a memory access verifier to check the legitimacy of address references, use a test case generator to create a verification sample set, build a coverage analyzer to evaluate test integrity, transfer the target program to the target platform through a deployment manager, and use a runtime environment configurator to set program execution parameters.

8. A cross-chip platform compilation tool chain device, characterized in that: The device comprises: An intermediate unified module is used to scan the target platform architecture specification file to extract instruction set features, parse the operating system function interface definition, build a platform difference matrix based on the instruction set features to record the instruction formats and system call differences of different chip platforms, analyze the execution characteristics and memory access patterns of the instruction set features to build a platform feature database, build a language identifier to parse the source code language type, create a corresponding syntax parser and lexical analyzer for each programming language based on the platform feature database, use a unified semantic analysis framework to process multi-language syntax trees, traverse the syntax tree structure based on the visitor pattern, use a type inference system to build a unified type representation, process cross-language calls through a language interoperability interface, and normalize the multi-language syntax trees into a unified intermediate representation; An instruction conversion module is used to build a cross-platform compiler to convert the intermediate representation into target code, design a unified intermediate language based on the platform difference matrix to support multi-language compilation, create an instruction mapper to convert the intermediate representation into target platform instructions, build a code optimizer according to the instruction set characteristics to perform constant folding and loop unrolling, use a scheduling algorithm to optimize the execution order of the target platform instructions, establish a library file linker to manage external dependencies, create a resource allocator to handle memory management, and use a target code generator to convert the optimized instructions into machine code; The code compilation module is used to load the target platform configuration descriptor during compilation, identify the target architecture type through the platform identification code, query the platform feature database to obtain the instruction set features, select the corresponding code conversion strategy according to the platform difference matrix, build a compilation task queue, use static analysis technology to check the correctness of the machine code, design test cases to verify the compilation results, and deploy the optimized target program to the target platform.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the cross-chip platform compilation tool chain method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the cross-chip platform compilation tool chain method according to any one of claims 1 to 7 are implemented.

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