Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of repairing a transistor. According to an embodiment of the disclosure, a display device includes: a pixel including a light emitting element and a pixel circuit; and a signal line connected to the pixel, in which the pixel circuit includes: a first main transistor connected between the driving voltage line and the anode electrode of the light emitting element; a second main transistor connected between the data line and a gate electrode of the first main transistor; a third main transistor connected between the driving voltage line and a source electrode of the first main transistor; a fourth main transistor connected between a drain electrode of the first main transistor and the initialization line; and at least one auxiliary transistor disposed adjacent to at least one of the first to fourth main transistors.

Description

[0001] This application claims priority to and all rights arising from Korean Patent Application No. 10-2023-0092558 filed in the Korean Intellectual Property Office on July 17, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device capable of repairing a transistor. Background Art

[0003] An organic light emitting display device includes a display element, for example, an organic light emitting diode, whose brightness is changed by electric current. Summary of the invention

[0004] Aspects of the present disclosure provide a display device capable of repairing a transistor.

[0005] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0006] According to the disclosed embodiment, the display device includes: a pixel including a light-emitting element and a pixel circuit connected to the light-emitting element; and a signal line connected to the pixel, wherein the signal line includes a gate line, an emission line and a data line, and the pixel circuit includes: a first main transistor connected between a driving voltage line and an anode electrode of the light-emitting element; a second main transistor connected between the data line and a gate electrode of the first main transistor; a third main transistor connected between a driving voltage line and a source electrode of the first main transistor; a fourth main transistor connected between a drain electrode of the first main transistor and an initialization line; and at least one auxiliary transistor, arranged to be adjacent to at least one main transistor among the first to fourth main transistors. The gate electrode, source electrode and drain electrode of the at least one auxiliary transistor have a floating state.

[0007] In an embodiment, at least one auxiliary transistor is arranged adjacent to a corresponding main transistor.

[0008] In an embodiment, the at least one auxiliary transistor includes a second auxiliary transistor disposed adjacent to the second main transistor and a third auxiliary transistor disposed adjacent to the third main transistor.

[0009] In an embodiment, at least one auxiliary transistor is connected to at least one main transistor of the first to fourth main transistors.

[0010] In an embodiment, when at least one auxiliary transistor is connected to at least one main transistor among the first to fourth main transistors, a source electrode and a drain electrode of at least one main transistor corresponding to the at least one auxiliary transistor have a floating state.

[0011] In an embodiment, a gate electrode of at least one main transistor corresponding to the at least one auxiliary transistor is connected to one of a node of the pixel circuit and a signal line.

[0012] In an embodiment, the display device further includes: a gate connecting electrode connected to a gate electrode of at least one auxiliary transistor; and a gate extension electrode disposed on a different layer from the gate connecting electrode and connected to the gate connecting electrode, wherein a short circuit repairing portion of the gate extension electrode overlaps with a short circuit repairing portion of the gate line.

[0013] In an embodiment, the gate extension electrode is disposed over the gate connection electrode and the gate line.

[0014] In an embodiment, the repairing short portion of the gate extension electrode and the repairing short portion of the gate line contact each other.

[0015] In an embodiment, a gate electrode of at least one main transistor corresponding to the at least one auxiliary transistor is connected to a gate line.

[0016] In an embodiment, the display device also includes: a first source connecting electrode, connected to the source electrode of at least one auxiliary transistor; and a source extension electrode, which is arranged on a different layer from the first source connecting electrode and is connected to the first source connecting electrode, wherein the repaired short circuit portion of the source extension electrode overlaps with the repaired short circuit portion of the second source connecting electrode connected to the data line.

[0017] In an embodiment, the source extension electrode is disposed on the first source connection electrode and the second source connection electrode, and is disposed on the same layer as the data line.

[0018] In an embodiment, the repaired short portion of the source extension electrode contacts the repaired short portion of the second source connection electrode.

[0019] In an embodiment, a source electrode of at least one main transistor corresponding to the at least one auxiliary transistor is connected to the second source connection electrode.

[0020] In an embodiment, the second source connection electrode is disconnected so that the data line and the source electrode of the at least one main transistor are separated.

[0021] In an embodiment, the disconnected portion of the second source connection electrode overlaps an overlapping portion between the repaired short-circuited portion of the non-source extension electrode and the repaired short-circuited portion of the second source connection electrode.

[0022] In an embodiment, the display device also includes: a drain connecting electrode connected to the drain electrode of at least one auxiliary transistor; and a gate / drain connecting electrode, which is arranged on a different layer from the drain connecting electrode, wherein the short-circuit repairing portion of the gate / drain connecting electrode overlaps with the short-circuit repairing portion of the drain connecting electrode.

[0023] In an embodiment, the gate / drain connection electrode is arranged above the drain connection electrode.

[0024] In an embodiment, the repaired short portion of the gate / drain connection electrode and the repaired short portion of the drain connection electrode contact each other.

[0025] In an embodiment, a drain electrode of at least one main transistor corresponding to at least one auxiliary transistor is connected to the gate / drain connection electrode.

[0026] In an embodiment, the drain connection electrode connected to the drain electrode of the at least one main transistor is disconnected so that the gate / drain connection electrode and the drain electrode of the at least one main transistor are separated.

[0027] In an embodiment, the disconnected portion of the drain connecting electrode connected to the drain electrode of at least one main transistor overlaps the overlapping portion between the repaired short circuit portion of the gate / drain connecting electrode and the repaired short circuit portion of the drain connecting electrode connected to the drain electrode of at least one auxiliary transistor.

[0028] In an embodiment, the display device further includes: a gate connecting electrode connected to a gate electrode of at least one auxiliary transistor; and a gate extension electrode disposed on a different layer from the gate connecting electrode and connected to an emission line, wherein a short circuit repairing portion of the gate extension electrode overlaps with a short circuit repairing portion of the gate line.

[0029] In an embodiment, the gate extension electrode is disposed over the gate connection electrode and the gate line.

[0030] In an embodiment, the repairing short portion of the gate extension electrode and the repairing short portion of the gate line contact each other.

[0031] In an embodiment, a gate electrode of at least one main transistor corresponding to the at least one auxiliary transistor is connected to an emission line.

[0032] In an embodiment, the display device also includes a source connecting electrode, which is connected to the source electrode of at least one auxiliary transistor, wherein the driving voltage line includes a lower driving voltage line and an upper driving voltage line connected to each other, the upper driving voltage line and the source connecting electrode are arranged on different layers, and the repaired short circuit portion of the upper driving voltage line overlaps with the repaired short circuit portion of the source connecting electrode.

[0033] In an embodiment, the upper driving voltage line is disposed above the source connection electrode.

[0034] In an embodiment, the repaired short portion of the upper driving voltage line and the repaired short portion of the source connection electrode contact each other.

[0035] In an embodiment, a source electrode of at least one main transistor corresponding to the at least one auxiliary transistor is connected to a lower driving voltage line.

[0036] In an embodiment, the lower driving voltage line is disconnected so that the lower driving voltage line and a source electrode of the at least one main transistor are separated.

[0037] In an embodiment, the disconnected portion of the lower driving voltage line does not overlap with the overlapping portion between the repaired short-circuited portion of the upper driving voltage line and the repaired short-circuited portion of the source connection electrode.

[0038] In an embodiment, the display device also includes: a drain connecting electrode connected to the drain electrode of at least one auxiliary transistor; and a source / drain connecting electrode, which is arranged on a different layer from the drain connecting electrode, wherein the repaired short circuit portion of the source / drain connecting electrode overlaps with the repaired short circuit portion of the drain connecting electrode.

[0039] In an embodiment, the source / drain connection electrode is arranged above the drain connection electrode.

[0040] In an embodiment, the repaired short portion of the source / drain connection electrode and the repaired short portion of the drain connection electrode contact each other.

[0041] In an embodiment, a drain electrode of at least one main transistor corresponding to at least one auxiliary transistor is connected to the source / drain connection electrode.

[0042] In an embodiment, the drain connection electrode connected to the drain electrode of the at least one main transistor is disconnected so that the source / drain connection electrode and the drain electrode of the at least one main transistor are separated.

[0043] In an embodiment, the disconnected portion of the drain connection electrode connected to the drain electrode of at least one main transistor overlaps the overlapping portion between the repaired short circuit portion of the source / drain connection electrode and the repaired short circuit portion of the drain connection electrode connected to the drain electrode of at least one auxiliary transistor.

[0044] In an embodiment, the at least one auxiliary transistor includes at least one of a second auxiliary transistor corresponding to the second main transistor and a third auxiliary transistor corresponding to the third main transistor.

[0045] In an embodiment, a pixel includes a first-first transistor region, a first-second transistor region, a second-first transistor region, a second-second transistor region, a third-first transistor region, and a third-second transistor region arranged in three rows and two columns.

[0046] In an embodiment, a first main transistor is arranged in a first-first transistor region corresponding to a first column of a first row, a second main transistor is arranged in a third-second transistor region corresponding to a second column of a third row, a third main transistor is arranged in a second-second transistor region corresponding to a second column of a second row, a fourth main transistor is arranged in a second-first transistor region corresponding to a first column of a second row, a second auxiliary transistor is arranged in a third-first transistor region corresponding to a first column of a third row, and a third auxiliary transistor is arranged in a first-second transistor region corresponding to a second column of a first row.

[0047] In an embodiment, in a pixel, a first main transistor is arranged in a first-first transistor region corresponding to a first column of a first row, a second main transistor is arranged in a third-second transistor region corresponding to a second column of a third row, a third main transistor is arranged in a second-second transistor region corresponding to a second column of a second row, a fourth main transistor is arranged in a second-first transistor region corresponding to a first column of a second row, a second auxiliary transistor is arranged in a third-first transistor region corresponding to a first column of a third row, and a third auxiliary transistor is arranged in a first-second transistor region corresponding to a second column of a first row. In a second pixel arranged adjacent to the pixel, a first main transistor is arranged in a first-second transistor region corresponding to a second column of a first row, a second main transistor is arranged in a third-first transistor region corresponding to a first column of a third row, a third main transistor is arranged in a second-first transistor region corresponding to a first column of a second row, a fourth main transistor is arranged in a second-second transistor region corresponding to a second column of a second row, a second auxiliary transistor is arranged in a third-second transistor region corresponding to a second column of a third row, and a third auxiliary transistor is arranged in a first-first transistor region corresponding to a first column of a first row.

[0048] In an embodiment, a first main transistor is arranged in a third-first transistor region corresponding to a first column of a third row, a second main transistor is arranged in a second-first transistor region corresponding to a first column of a second row, a third main transistor is arranged in a second-second transistor region corresponding to a second column of a second row, a fourth main transistor is arranged in a third-second transistor region corresponding to a second column of a third row, a second auxiliary transistor is arranged in a first-first transistor region corresponding to a first column of a first row, and a third auxiliary transistor is arranged in a first-second transistor region corresponding to a second column of a first row.

[0049] In an embodiment, a first main transistor is arranged in a first-second transistor region corresponding to the second column of the first row, a second main transistor is arranged in a second-second transistor region corresponding to the second column of the second row, a third main transistor is arranged in the second-first transistor region corresponding to the first column of the second row, a fourth main transistor is arranged in the first-first transistor region corresponding to the first column of the first row, a second auxiliary transistor is arranged in a third-second transistor region corresponding to the second column of the third row, and a third auxiliary transistor is arranged in a third-first transistor region corresponding to the first column of the third row.

[0050] In an embodiment, a first main transistor is arranged in a first-first transistor region corresponding to a first column of a first row, a second main transistor is arranged in a first-second transistor region corresponding to a second column of a first row, a third main transistor is arranged in a third-first transistor region corresponding to a first column of a third row, a fourth main transistor is arranged in a third-second transistor region corresponding to a second column of a third row, a second auxiliary transistor is arranged in a second-second transistor region corresponding to a second column of a second row, and a third auxiliary transistor is arranged in a second-first transistor region corresponding to a first column of a second row.

[0051] In an embodiment, the display device further includes: a sensing line connected to the pixel; and a sensing transistor provided in the pixel circuit and connected between the sensing line and a gate electrode of the first main transistor.

[0052] In an embodiment, a first main transistor is arranged in a first-first transistor region corresponding to a first column of a first row, a second main transistor is arranged in a third-second transistor region corresponding to a second column of a third row, a third main transistor is arranged in a second-second transistor region corresponding to a second column of a second row, a fourth main transistor is arranged in a second-first transistor region corresponding to a first column of a second row, a second auxiliary transistor is arranged in a third-first transistor region corresponding to a first column of a third row, and a sensing transistor is arranged in a first-second transistor region corresponding to a second column of a first row.

[0053] In an embodiment, the display device further includes: a first capacitor connected between the gate electrode of the first main transistor and the anode electrode of the light emitting element; and a second capacitor connected between the gate electrode of the first main transistor and the source electrode of the first main transistor.

[0054] According to the display device of the present disclosure, the pixel circuit includes an auxiliary transistor that can replace the main transistor. Therefore, the transistor can be repaired by removing the main transistor that has been determined to be defective from the pixel circuit and then connecting the auxiliary transistor to the pixel circuit.

[0055] The effects of the present disclosure are not limited to the above-mentioned effects, and various other effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0057] Figure 1 is a perspective view showing a display device according to an embodiment;

[0058] Figure 2 is a cross-sectional view showing a display device according to an embodiment;

[0059] Figure 3 is a plan view showing a display unit of a display device according to an embodiment;

[0060] Figure 4 is a block diagram showing a display panel and a display driver according to one embodiment;

[0061] Figure 5 is a circuit diagram of one pixel of a display device according to one embodiment;

[0062] Figure 6 yes Figure 5 A timing diagram of a first gate signal, a second gate signal, an emission signal, a data voltage and an initialization voltage;

[0063] Figure 7 is a cross-sectional view of a display device according to an embodiment;

[0064] Figure 8 is a plan view of a display device according to an embodiment;

[0065] Fig. 9 is a plan view of a display device according to an embodiment;

[0066] Fig.10 is where a second metal layer is further added to Fig. 9 's view;

[0067] Fig.11 It is along Fig.10 A cross-sectional view taken along line II';

[0068] Fig.12 It is along Fig.10 A cross-sectional view taken along line II-II';

[0069] Fig.13 , Fig.14 , Fig.15 and Fig.16 is a diagram showing a method for repairing a display device according to an embodiment;

[0070] Fig.17 is a diagram showing a method for repairing a display device according to an embodiment;

[0071] Fig.18 is a plan view of a display device according to an embodiment;

[0072] Fig.19 is a plan view of a display device according to an embodiment;

[0073] Fig. 20 is a plan view of a display device according to an embodiment;

[0074] Fig.21 is a plan view of a display device according to an embodiment;

[0075] Fig. 22 is a circuit diagram of one pixel of a display device according to one embodiment;

[0076] Fig.23 is a plan view of a display device according to an embodiment;

[0077] Fig.24 is an exemplary diagram showing a virtual reality device including a display device according to one embodiment; and

[0078] Fig.25 and Fig.26 : is an exemplary view showing a head mounted display device to which a display device according to one embodiment is applied. DETAILED DESCRIPTION

[0079] Advantages and features of the present disclosure and methods for achieving them will become apparent from the description of exemplary embodiments with reference to the accompanying drawings hereinafter. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but may be implemented in a variety of different ways. Exemplary embodiments are provided to make the disclosure of the present disclosure thorough and to fully convey the scope of the present disclosure to those skilled in the art. It will be noted that the scope of the present disclosure is limited only by the claims.

[0080] As used herein, the phrase "element A on element B" means that element A may be directly disposed on element B and / or element A may be indirectly disposed on element B via another element C. Throughout the description, the same reference numerals denote the same elements. The figures, dimensions, proportions, angles, and numbers of elements given in the drawings are merely illustrative and not limiting.

[0081] Although terms such as first, second, etc. are used to arbitrarily distinguish between the elements described by these terms, these terms are not necessarily intended to represent the time priority or other priority of these elements. These terms are only used to distinguish one element from another element. Therefore, as used herein, within the technical scope of the present disclosure, a first element may be a second element.

[0082] The features of various exemplary embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interlocks and operations are technically feasible. Various exemplary embodiments may be practiced individually or in combination.

[0083] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0084] Figure 1 is a perspective view showing a display device according to an embodiment.

[0085] Reference Figure 1 , the display device 10 can be applied to portable electronic devices (such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMP), navigation systems, ultra-mobile PCs (UMPCs), etc.). For example, the display device 10 can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. For another example, the display device 10 can be applied to a wearable device (such as a smart watch, a watch phone, a glasses-type display, or a head-mounted display (HMD)).

[0086] The display device 10 may have a planar shape similar to a quadrilateral shape. For example, the display device 10 may have a planar shape similar to a quadrilateral shape having short sides in the first direction DR1 and long sides in the second direction DR2. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be a right angle or rounded (rounded) with a predetermined curvature. The planar shape of the display device 10 is not limited to a quadrilateral shape, and may be formed in a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0087] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , a touch driver 400 , and a power supply unit 500 .

[0088] The display panel 100 may include a main area MA and a sub area SBA.

[0089] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit PC including a switching element (see Figure 5 ), a pixel defining layer that defines an emission area or an opening area, and a self-luminous element.

[0090] For example, the self-luminous element may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0091] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver supplying a gate signal to a gate line and a fan-out line connecting the display driver 200 to the display area DA.

[0092] The sub-region SBA may extend from one side of the main region MA. The sub-region SBA may include a flexible material that may be bent, folded, or curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (e.g., the third direction DR3). The sub-region SBA may include a display driver 200 and a pad (also referred to as a "pad" or "solder pad") portion connected to the circuit board 300. Alternatively, the sub-region SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0093] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may provide a signal to the data line DL (see Figure 3 ) supplies a data voltage. The display driver 200 may supply a power voltage to the power line, and may supply a gate control signal to the gate driver. The display driver 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be disposed in the sub-region SBA, and may overlap with the main region MA in the thickness direction (third direction DR3) by bending of the sub-region SBA. For another example, the display driver 200 may be mounted on the circuit board 300.

[0094] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0095] The touch driver 400 may be mounted on the circuit board 300 .

[0096] The power supply unit 500 may be provided on the circuit board 300 to supply a power voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage to supply it to the driving voltage line VDL (see Figure 3 ), and a common voltage may be generated to supply it to a common electrode common to the light emitting elements of a plurality of pixels. For example, the driving voltage may be a high potential voltage for driving the light emitting element, and the common voltage may be a low potential voltage for driving the light emitting element.

[0097] Figure 2 is a cross-sectional view showing a display device according to an embodiment.

[0098] Reference Figure 2 , the display panel 100 may include a display unit DU and a color filter layer CFL. The display unit DU may include a substrate SUB, a driving circuit layer DCL, a light emitting element layer EMTL, and an encapsulation layer ENC.

[0099] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate SUB that can be bent, folded, or curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0100] The driving circuit layer DCL may be disposed on the substrate SUB. The driving circuit layer DCL may include a plurality of transistors. The driving circuit layer DCL may also include a gate line, a data line DL, a power line, a gate control line, a fan-out line connecting the display driver 200 to the data line DL, and a lead connecting the display driver 200 to the pad portion. Each of the transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a transistor.

[0101] The driving circuit layer DCL may be arranged in the display area DA, the non-display area NDA, and the sub-area SBA. The transistors, gate lines, data lines DL, and power lines of the pixels of the driving circuit layer DCL may be arranged in the display area DA. The gate control lines and fan-out lines of the driving circuit layer DCL may be arranged in the non-display area NDA. The leads of the driving circuit layer DCL may be arranged in the sub-area SBA.

[0102] The light emitting element layer EMTL may be disposed on the driving circuit layer DCL. The light emitting element layer EMTL may include a plurality of light emitting elements ED in which pixel electrodes, light emitting layers, and common electrodes are sequentially stacked to emit light (see Figure 5 ) and a pixel defining layer defining pixels. A plurality of light emitting elements ED of the light emitting element layer EMTL may be disposed in the display area DA.

[0103] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a predetermined voltage through the transistor of the driving circuit layer DCL and the common electrode receives a cathode voltage, holes and electrons may be respectively transmitted to the organic light-emitting layer through the hole transport layer and the electron transport layer, and may be combined with each other to emit light in the organic light-emitting layer. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode, but the present disclosure is not limited thereto.

[0104] For another example, each of the plurality of light emitting elements ED may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0105] The encapsulation layer ENC may cover the top surface and the side surface of the light emitting element layer EMTL and may protect the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EMTL.

[0106] The color filter layer CFL may be disposed on the encapsulation layer ENC. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each of the color filters may selectively transmit light of a specific wavelength, and may block or absorb light of a different wavelength. The color filter layer CFL may absorb a portion of light from outside the display device 10 to reduce reflected light due to external light. Therefore, the color filter layer CFL may prevent color distortion caused by reflection of external light.

[0107] The sub-region SBA of the display panel 100 may extend from one side of the main region MA. The sub-region SBA may include a flexible material that may be bent, folded, or curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap the main region MA in the thickness direction (third direction DR3). The sub-region SBA may include a display driver 200 and a pad portion electrically connected to the circuit board 300.

[0108] When the sub-area SBA is bent, as Figure 2 As shown in FIG. 8 , a protection layer 800 may be further disposed on the bent portion of the sub-area SBA.

[0109] Figure 3 is a plan view showing a display unit of a display device according to an embodiment. Figure 4 is a block diagram showing a display panel and a display driver according to one embodiment.

[0110] Reference Figure 3 and Figure 4 , the display panel 100 may include a display area DA and a non-display area NDA.

[0111] The display area DA may include a plurality of pixels PX and a plurality of signal transmission lines connected to the plurality of pixels PX. Here, the plurality of signal transmission lines may include a plurality of gate lines GL, a plurality of common voltage lines VSL (see Figure 5 ), multiple emission lines EML and multiple data lines DL and fan-out lines FL connected to the above lines.

[0112] Each of the plurality of pixels PX may be connected to a gate line GL, a data line DL, an emission line EML, a driving voltage line VDL, and a common voltage line VSL. Each of the pixels PX may include at least one transistor, a light emitting element ED, and a capacitor.

[0113] Each of the gate lines GL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 crossing the first direction DR1. The gate lines GL may be arranged along the second direction DR2. The gate lines GL may sequentially supply gate signals to the plurality of pixels PX.

[0114] The emission lines EML may each extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The emission lines EML may be arranged along the second direction DR2. The emission lines EML may sequentially supply emission signals EM to the plurality of pixels PX (see Figure 5 ).

[0115] The data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The data lines DL may be arranged along the first direction DR1. The data lines DL may supply data voltages to the plurality of pixels PX. The data voltages may determine the brightness of each of the pixels PX.

[0116] The driving voltage lines VDL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The driving voltage lines VDL may be arranged along the first direction DR1. The driving voltage lines VDL may supply a driving voltage to a plurality of pixels PX. The driving voltage may be a high potential voltage for driving the light emitting element ED of the pixel PX.

[0117] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 610, an emission control driver 620, a fan-out line FL, a first gate control line GSL1, and a second gate control line GSL2.

[0118] The fan-out line FL may extend from the display driver 200 to the display area DA. The fan-out line FL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0119] The first gate control line GSL1 may extend from the display driver 200 to the gate driver 610. The first gate control line GSL1 may supply the gate control signal GCS received from the display driver 200 to the gate driver 610.

[0120] The second gate control line GSL2 may extend from the display driver 200 to the emission control driver 620. The second gate control line GSL2 may supply the emission control signal ECS received from the display driver 200 to the emission control driver 620.

[0121] The sub-area SBA may extend from one side of the non-display area NDA. The sub-area SBA may include a display driver 200 and a pad portion DP. The pad portion DP may be disposed closer to one edge of the sub-area SBA than the display driver 200. The pad portion DP may be electrically connected to the circuit board 300 through an anisotropic conductive film (ACF).

[0122] The display driver 200 may include a timing controller 210 and a data driver 220 .

[0123] The timing controller 210 may receive the digital video data signal DATA and the timing signal from the circuit board 300. The timing controller 210 may generate a data control signal DCS for controlling the operation timing of the data driver 220, a gate control signal GCS for controlling the operation timing of the gate driver 610, and an emission control signal ECS for controlling the operation timing of the emission control driver 620 based on the timing signal. The timing controller 210 may supply the gate control signal GCS to the gate driver 610 through the first gate control line GSL1. The timing controller 210 may supply the emission control signal ECS to the emission control driver 620 through the second gate control line GSL2. The timing controller 210 may supply the digital video data signal DATA and the data control signal DCS to the data driver 220.

[0124] The data driver 220 may convert the digital video data signals DATA into analog data voltages and supply them to the data lines DL through the fan-out lines FL. The gate signal of the gate driver 610 may select the pixel PX to which the data voltage is supplied, and the selected pixel PX may receive the data voltage through the data line DL.

[0125] The power supply unit 500 may be provided on the circuit board 300 to supply power voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage to supply it to the driving voltage line VDL, and may generate a common voltage to supply it to a common electrode common to the light emitting elements ED of a plurality of pixels.

[0126] The gate driver 610 may be disposed on one outer side of the display area DA or one side of the non-display area NDA. The emission control driver 620 may be disposed on the other outer side of the display area DA or the other side of the non-display area NDA. However, the present disclosure is not limited thereto. As another example, the gate driver 610 and the emission control driver 620 may be disposed on any side of the non-display area NDA.

[0127] The gate driver 610 may include a plurality of transistors for generating gate signals based on the gate control signal GCS. The emission control driver 620 may include a plurality of transistors for generating emission signals EM based on the emission control signal ECS. For example, the transistors of the gate driver 610 and the transistors of the emission control driver 620 may be formed in the same layer as the transistors of each of the pixels PX. The gate driver 610 may supply the gate signal to the gate line GL, and the emission control driver 620 may supply the emission signal EM to the emission line EML.

[0128] Figure 5 is a circuit diagram of one pixel of a display device according to an embodiment.

[0129] like Figure 5 As shown in FIG, the pixel PX may be connected to a first gate line GL1, a second gate line GL2, an emission line EML, an initialization line VIL, a data line DL, a driving voltage line VDL, and a common voltage line VSL. Here, the common voltage line VSL may be connected to a common electrode (e.g., a cathode electrode) of the light emitting element ED.

[0130] The pixel PX may include a pixel circuit PC and a light emitting element ED.

[0131] The pixel circuit PC may include a first main transistor MT1, a second main transistor MT2, a third main transistor MT3, a fourth main transistor MT4, a second auxiliary transistor AT2, a third auxiliary transistor AT3, a first capacitor C1, and a second capacitor C2.

[0132] The first main transistor MT1 (e.g., a driving transistor) may include a gate electrode, a source electrode, and a drain electrode. The first main transistor MT1 may control a source-drain current (hereinafter, a driving current) according to a data voltage applied to the gate electrode. A driving current (e.g., Isd) flowing through a channel region of the first main transistor MT1 may be proportional to the square of a difference between a threshold voltage (e.g., Vth) of the first main transistor MT1 and a voltage (e.g., Vsg) between a source electrode and a gate electrode of the first main transistor MT1 (Isd=k×(Vsg–Vth)). 2 ). Here, k is a proportionality coefficient determined by the structure and physical characteristics of the first main transistor MT1, Vsg is a source-gate voltage of the first main transistor MT1, and Vth is a threshold voltage of the first main transistor MT1. The gate electrode of the first main transistor MT1 may be connected to the first node N1, its source electrode may be connected to the second node N2, and its drain electrode may be connected to the third node N3.

[0133] The light emitting element ED may emit light by receiving a driving current (e.g., Isd). The emission amount or brightness of the light emitting element ED may be proportional to the size of the driving current (e.g., Isd). The light emitting element ED may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode. As another example, the light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For another example, the light emitting element ED may be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot light emitting layer disposed between the first electrode and the second electrode. For another example, the light emitting element ED may be a micro light emitting diode. The first electrode (e.g., an anode electrode) of the light emitting element ED may be electrically connected to the third node N3. The second electrode (e.g., a cathode electrode) of the light emitting element ED may be connected to a common voltage line VSL. The second electrode of the light emitting element ED may receive a common voltage (e.g., a low potential voltage) from the common voltage line VSL.

[0134] The second main transistor MT2 may be turned on by the first gate signal GS1 of the first gate line GL1 to electrically connect the data line DL to the first node N1. A gate electrode of the second main transistor MT2 may be electrically connected to the first gate line GL1, a source electrode thereof may be electrically connected to the data line DL, and a drain electrode thereof may be electrically connected to the first node N1. The data line DL may transmit a digital video data signal DATA or a data voltage Vdt.

[0135] The third main transistor MT3 may be turned on by the emission signal EM of the emission line EML to electrically connect the driving voltage line VDL to the second node N2. A gate electrode of the third main transistor MT3 may be electrically connected to the emission line EML, a source electrode thereof may be electrically connected to the driving voltage line VDL, and a drain electrode thereof may be electrically connected to the second node N2.

[0136] The fourth main transistor MT4 may be turned on by the second gate signal GS2 of the second gate line GL2 to electrically connect the third node N3 to the initialization line VIL. The gate electrode of the fourth main transistor MT4 may be electrically connected to the second gate line GL2, the source electrode thereof may be electrically connected to the third node N3, and the drain electrode thereof may be electrically connected to the initialization line VIL. On the other hand, a plurality of initialization lines VIL may be provided, and the plurality of initialization lines VIL may be connected to each other. For example, the initialization line VIL may include a plurality of horizontal initialization lines VIL extending along the first direction DR1 and arranged in the second direction DR2, and a plurality of vertical initialization lines VIL extending along the second direction DR2 and arranged along the first direction DR1, and the horizontal initialization lines VIL and the vertical initialization lines VIL may be connected to each other.

[0137] The first capacitor C1 may be electrically connected between the first node N1 and the second node N2. For example, a first electrode of the first capacitor C1 may be electrically connected to the first node N1, and a second electrode of the first capacitor C1 may be electrically connected to the second node N2.

[0138] The second capacitor C2 may be electrically connected between the first node N1 and the third node N3. For example, a first electrode of the second capacitor C2 may be electrically connected to the first node N1, and a second electrode of the second capacitor C2 may be electrically connected to the third node N3.

[0139] When the first and third main transistors MT1 and MT3 are turned on, a driving current is supplied to the light emitting element ED so that the light emitting element ED may emit light.

[0140] At least one of the first to fourth main transistors MT1 to MT4 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to fourth main transistors MT1 to MT4 may be a P-type MOSFET. On the other hand, for another example, each of the first to fourth main transistors MT1 to MT4 may be an N-type MOSFET. For yet another example, at least one of the first to fourth main transistors MT1 to MT4 may be a P-type MOSFET, and the other transistors may be N-type MOSFETs.

[0141] The auxiliary transistor may include a transistor having the same configuration as that of at least one of the first to fourth main transistors MT1 to MT4 described above. For example, the auxiliary transistor may include a second auxiliary transistor AT2 and a third auxiliary transistor AT3.

[0142] The second auxiliary transistor AT2 may be a transistor capable of replacing the second main transistor MT2 when a defect occurs in the second main transistor MT2. The second auxiliary transistor AT2 may have the same configuration as the second main transistor MT2. The second auxiliary transistor AT2 may be disposed close to the second main transistor MT2.

[0143] When no defect occurs in the second main transistor MT2, the second auxiliary transistor AT2 may have a floating state. For example, the gate electrode, source electrode and drain electrode of the second auxiliary transistor AT2 may be maintained in a floating state. On the other hand, when a defect occurs in the second main transistor MT2, the second main transistor MT2 may be separated from the pixel circuit PC, and the second auxiliary transistor AT2 may be connected to the pixel circuit PC. For example, the connection portion between the gate electrode of the second main transistor MT2 and the first gate line GL1 may be disconnected, the connection portion between the source electrode of the second main transistor MT2 and the data line DL may be disconnected, and the connection portion between the drain electrode of the second main transistor MT2 and the first node N1 may be disconnected, so that the second main transistor MT2 may be separated from the pixel circuit PC. In addition, the gate electrode of the second auxiliary transistor AT2 and the first gate line GL1 may be connected, the source electrode of the second auxiliary transistor AT2 and the data line DL may be connected, and the drain electrode of the second auxiliary transistor AT2 and the first node N1 may be connected, so that the second auxiliary transistor AT2 may be connected to the pixel circuit PC.

[0144] The third auxiliary transistor AT3 may be a transistor capable of replacing the third main transistor MT3 when a defect occurs in the third main transistor MT3. The third auxiliary transistor AT3 may have the same configuration as that of the third main transistor MT3. The third auxiliary transistor AT3 may be disposed close to the third main transistor MT3.

[0145] When no defect occurs in the third main transistor MT3, the third auxiliary transistor AT3 may have a floating state. For example, the gate electrode, source electrode and drain electrode of the third auxiliary transistor AT3 may be maintained in a floating state. On the other hand, when a defect occurs in the third main transistor MT3, the third main transistor MT3 may be separated from the pixel circuit PC, and the third auxiliary transistor AT3 may be connected to the pixel circuit PC. For example, the connection portion between the gate electrode of the third main transistor MT3 and the emission line EML may be disconnected, the connection portion between the source electrode of the third main transistor MT3 and the driving voltage line VDL may be disconnected, and the connection portion between the drain electrode of the third main transistor MT3 and the second node N2 may be disconnected, so that the third main transistor MT3 may be separated from the pixel circuit PC. In addition, the gate electrode of the third auxiliary transistor AT3 and the emission line EML may be connected, the source electrode of the third auxiliary transistor AT3 and the driving voltage line VDL may be connected, and the drain electrode of the third auxiliary transistor AT3 and the second node N2 may be connected, so that the third auxiliary transistor AT3 may be connected to the pixel circuit PC.

[0146] In another embodiment, the pixel circuit PC may further include, for example, a first auxiliary transistor corresponding to the first main transistor MT1 and a fourth auxiliary transistor corresponding to the fourth main transistor MT4 .

[0147] On the other hand, whether the main transistor is defective can be determined based on visual inspection. For example, whether the main transistor is defective can be determined by an automatic optical inspection (AOI) device. The AOI device can detect defects in micrometers (μm) using an image processing algorithm and a high-resolution camera.

[0148] Figure 6 yes Figure 5 A timing diagram of a first gate signal, a second gate signal, an emission signal, a data voltage and an initialization voltage.

[0149] As in Figure 6 In the example shown in , the operation of the display device 10 may include an initialization / writing period P1 , a compensation period P2 , a bypass period P3 , and an emission period P4 .

[0150] The initialization / write period P1, the compensation period P2, the bypass period P3, and the emission period P4 may correspond to one horizontal period 1H. In other words, one horizontal period 1H may include the initialization / write period P1, the compensation period P2, the bypass period P3, and the emission period P4. Here, the horizontal period 1H may refer to a period during which pixels (e.g., pixels in a row) arranged in a horizontal direction (e.g., a first direction DR1) are driven. Here, the pixels in a row may refer to a plurality of pixels commonly connected to a gate line (e.g., a first gate line GL1) and respectively connected to a plurality of different data lines DL.

[0151] For each period, the first gate signal GS1, the second gate signal GS2 and the emission signal EM may all have an effective level or an ineffective level. Here, the effective level of each signal GS1, GS2, EM may mean a voltage of a level that can turn on the corresponding transistor to which the corresponding signal is applied. In other words, the effective level signal may have a value less than the threshold voltage of the corresponding transistor. For example, Figure 5 As shown in , when each of the main transistors MT1 to MT4 is a P-type transistor, the effective level of each signal GS1, GS2, EM may mean a voltage lower than the threshold voltage of the corresponding transistor. On the other hand, the ineffective level of each signal GS1, GS2, EM may mean a voltage of a level capable of turning off the corresponding transistor. In other words, the ineffective level signal may have a value greater than the threshold voltage of the corresponding transistor. For example, Figure 5As shown in , when each of the main transistors MT1 to MT4 is a P-type transistor, the inactive level of each signal GS1, GS2, EM may mean a voltage higher than the threshold voltage of the corresponding transistor. On the other hand, when each of the main transistors MT1 to MT4 is an N-type transistor, the active level of each signal GS1, GS2, EM may mean a voltage higher than the threshold voltage of the corresponding transistor, and the inactive level of each signal GS1, GS2, EM may mean a voltage lower than the threshold voltage of the corresponding transistor.

[0152] In the initialization / write period P1, the emission signal EM, the first gate signal GS1 and the second gate signal GS2 may all have an effective level. In addition, in the initialization / write period P1, the data voltage Vdt may be applied to the data line DL. The data voltage Vdt may be a voltage having a specific grayscale (or brightness) for displaying an image. In this case, the data voltage Vdt in the initialization / write period P1 may be a data voltage Vdt1 of a previous horizontal period (hereinafter, referred to as a previous data voltage).

[0153] In the compensation period P2, the first gate signal GS1 and the second gate signal GS2 may both have an active level. In addition, in the compensation period P2, the previous data voltage Vdt1 may be applied to the data line DL.

[0154] In the bypass period P3, the emission signal EM and the second gate signal GS2 may both have an effective level, and the first gate signal GS1 may have an ineffective level. In addition, in the bypass period P3, the data voltage Vdt of the data line DL may be a transient data voltage Vtrs that changes (or shifts) from the previous data voltage Vdt1 to the current data voltage Vdt2.

[0155] In the emission period P4, the emission signal EM may have an effective level, and the first gate signal GS1 and the second gate signal GS2 may both have an ineffective level. In addition, in the emission period P4, the data voltage Vdt may be applied to the data line DL. The data voltage Vdt may be a voltage having a specific grayscale (or brightness) for displaying an image. In this case, the data voltage Vdt in the emission period P4 may be a data voltage Vdt2 (hereinafter, referred to as the current data voltage) of the current horizontal period.

[0156] On the other hand, the above-mentioned initialization voltage Vinit may be maintained at a constant level during all periods including the initialization / write period P1, the compensation period P2, the bypass period P3, and the emission period P4. For example, the initialization voltage Vinit may be a DC voltage having a constant level regardless of the period. Here, the initialization voltage Vinit may be, for example, a DC voltage higher than the common voltage ELVSS and lower than the driving voltage ELVDD.

[0157] Will refer to Figure 5 and Figure 6 The operation of the display device according to one embodiment of the present disclosure is described.

[0158] First, the operation of the display device in the initialization / writing period P1 will be described.

[0159] like Figure 6 As shown in , in the initialization / write period P1, the emission signal EM, the first gate signal GS1, and the second gate signal GS2 may all have an effective level. In addition, in the initialization / write period P1, the previous data voltage Vdt1 may be applied to the data line DL.

[0160] The first gate signal GS1 of an active level may be applied to the gate electrode of the second main transistor MT2 through the first gate line GL1. Therefore, the second main transistor MT2 may be turned on.

[0161] The second gate signal GS2 of the active level may be applied to the gate electrode of the fourth main transistor MT4 through the second gate line GL2. Therefore, the fourth main transistor MT4 may be turned on.

[0162] The emission signal EM of the effective level may be applied to the gate electrode of the third master transistor MT3 through the emission line EML. Therefore, the third master transistor MT3 may be turned on.

[0163] The first master transistor MT1 may be turned on by the previous data voltage Vdt1 .

[0164] Since the above-mentioned second main transistor MT2, the third main transistor MT3 and the fourth main transistor MT4 are turned on in the initialization / write period P1, the gate electrode (e.g., the first node N1) of the first main transistor MT1, the source electrode (e.g., the second node N2) of the first main transistor MT1 and the drain electrode (e.g., the third node N3) of the first main transistor MT1 can be initialized. For example, the previous data voltage Vdt1 from the data line DL can be applied to the first node N1 as the gate electrode of the first main transistor MT1 through the turned-on second main transistor MT2. In addition, the driving voltage ELVDD from the driving voltage line VDL can be applied to the second node N2 as the source electrode of the first main transistor MT1 through the turned-on third main transistor MT3. In addition, the initialization voltage Vinit from the initialization line VIL can be applied to the third node N3 as the drain electrode of the first main transistor MT1 through the turned-on fourth main transistor MT4. Therefore, the voltage of each of the gate electrode of the first main transistor MT1, the source electrode of the first main transistor MT1 and the drain electrode of the first main transistor MT1 can be initialized. For example, the gate electrode of the first main transistor MT1 may be initialized to the previous data voltage Vdt1, the source electrode of the first main transistor MT1 may be initialized to the driving voltage ELVDD, and the drain electrode of the first main transistor MT1 (or the anode electrode of the light emitting element ED) may be initialized to the initialization voltage Vinit.

[0165] In addition, a current path may be generated between the driving voltage line VDL and the initialization line VIL through the turned-on first main transistor MT1. A voltage of each of the source electrode and the drain electrode of the first main transistor MT1 may be initialized by the current flowing through the current path.

[0166] Next, the operation of the display device in the compensation period P2 will be described.

[0167] like Figure 6 As shown in , in the compensation period P2, the first gate signal GS1 and the second gate signal GS2 may both have an active level, and the emission signal EM may have a non-active level. In addition, in the compensation period P2, the previous data voltage Vdt1 may be applied to the data line DL.

[0168] The first gate signal GS1 of an active level may be applied to the gate electrode of the second main transistor MT2 through the first gate line GL1. Therefore, the second main transistor MT2 may be turned on.

[0169] The second gate signal GS2 of the active level may be applied to the gate electrode of the fourth main transistor MT4 through the second gate line GL2. Therefore, the fourth main transistor MT4 may be turned on.

[0170] The emission signal EM of the non-active level may be applied to the gate electrode of the third master transistor MT3 through the emission line EML. Therefore, the third master transistor MT3 may be turned off.

[0171] The first master transistor MT1 may be turned on by the previous data voltage Vdt1 .

[0172] In the compensation period P2, the threshold voltage of the first main transistor MT1 may be stored in the first capacitor C1. For example, the threshold voltage of the first main transistor MT1 may be stored in the first capacitor C1 in a source follower method. In this case, the voltage of the second node N2 may be, for example, a voltage obtained by subtracting the threshold voltage of the first main transistor MT1 described above from the previous data voltage Vdt1.

[0173] Next, the operation of the display device in the bypass period P3 will be described.

[0174] like Figure 6 As shown in , in the bypass period P3, the emission signal EM and the second gate signal GS2 may both have an effective level, and the first gate signal GS1 may have an ineffective level. In addition, in the bypass period P3, the data voltage Vdt of the data line DL may be a transient data voltage Vtrs that changes (or shifts) from the previous data voltage Vdt1 to the current data voltage Vdt2.

[0175] The first gate signal GS1 of the non-active level may be applied to the gate electrode of the second main transistor MT2 through the first gate line GL1. Therefore, the second main transistor MT2 may be turned off.

[0176] The second gate signal GS2 of the active level may be applied to the gate electrode of the fourth main transistor MT4 through the second gate line GL2. Therefore, the fourth main transistor MT4 may be turned on.

[0177] The emission signal EM of the effective level may be applied to the gate electrode of the third master transistor MT3 through the emission line EML. Therefore, the third master transistor MT3 may be turned on.

[0178] The first master transistor MT1 may be turned on by the previous data voltage Vdt1 .

[0179] In the bypass period P3, the first gate signal GS1 changes (or shifts) from the effective level to the non-effective level, so that the second main transistor MT2 may be turned on in a short time. Then, there may be a problem that the abnormal drive current generated by the transient data voltage Vtrs of the data line DL may be supplied to the light-emitting element ED. In order to prevent the above problem, the fourth main transistor MT4 is turned on in the bypass period P3, so that the abnormal drive current generated by the transient data voltage Vtrs is not applied to the light-emitting element ED. For example, the abnormal drive current generated by the transient data voltage Vtrs can be bypassed to the initialization line VIL through the turned-on fourth main transistor MT4.

[0180] Next, the operation of the display device in the emission period P4 will be described.

[0181] like Figure 6 As shown in , in the emission period P4, the emission signal EM may have an active level, and the first gate signal GS1 and the second gate signal GS2 may both have an inactive level. In addition, in the emission period P4, the current data voltage Vdt2 may be applied to the data line DL.

[0182] The first gate signal GS1 of the non-active level may be applied to the gate electrode of the second main transistor MT2 through the first gate line GL1. Therefore, the second main transistor MT2 may be turned off.

[0183] The second gate signal GS2 of the non-active level may be applied to the gate electrode of the fourth main transistor MT4 through the second gate line GL2. Therefore, the fourth main transistor MT4 may be turned off.

[0184] The emission signal EM of the effective level may be applied to the gate electrode of the third master transistor MT3 through the emission line EML. Therefore, the third master transistor MT3 may be turned on.

[0185] The first master transistor MT1 may be turned on by the current data voltage Vdt2 .

[0186] A current path from the driving voltage line VDL to the common voltage line VSL may be generated by the turned-on third main transistor MT3 and the first main transistor MT1, and a driving current may flow through the current path. The driving current is supplied to the light emitting element ED, and the light emitting element ED may emit light according to the driving current.

[0187] Figure 7 is a cross-sectional view of a display device according to an embodiment.

[0188] like Figure 7 As shown in , the display device 10 may include a driving circuit layer DCL, a light emitting element layer EMTL, an encapsulation layer ENC, and a color filter layer CFL.

[0189] The substrate SUB may be a silicon substrate, a germanium substrate or a silicon germanium substrate. The substrate SUB may be a substrate SUB doped with first type impurities.

[0190] The well region W may be disposed on (or in) the substrate SUB. The well region W may be a region doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. On the other hand, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0191] The source region S, drain region D, and channel region CH of the transistor TR may be arranged in the well region W. For example, the source region S (or source electrode) and drain region D (or drain electrode) of the transistor TR may be arranged in the well region W. Each of the source region S and the drain region D may be a region doped with the second type of impurities described above. The gate electrode G of the transistor TR may intersect and overlap with the well region W. In a plan view, the well region W intersecting with the gate electrode G may include two parts, the source region S may be arranged in any one of the two parts, and the drain region D may be arranged in the other of the two parts. In other words, in the well region W, the source region S and the drain region D may be arranged on both sides of the gate electrode G, and the gate electrode G is placed between the source region S and the drain region D in a plan view. The channel region CH of the transistor TR may be arranged in a region of the well region W overlapping with the gate electrode G. Figure 7 The transistor TR shown in FIG. 1 may be, for example, Figure 5 The first main transistor MT1.

[0192] On the other hand, the source region S may include a first lightly doped impurity region having an impurity concentration relatively lower than that of another portion of the source region S. In other words, the lightly doped source region S may include impurities at a lower concentration than that of another portion of the source region S. The drain region D may include a second lightly doped impurity region having an impurity concentration relatively lower than that of another portion of the drain region D. In other words, the lightly doped drain region D may include impurities at a lower concentration than that of another portion of the drain region D.

[0193] The first lightly doped impurity region and the second lightly doped impurity region may be disposed closer to the channel region CH of the transistor TR to form a lightly doped drain (LDD) structure. For example, the first lightly doped impurity region may be disposed close to the channel region CH to overlap with a first sidewall disposed on one side of the gate electrode G, and the second lightly doped impurity region may be disposed close to the channel region CH to overlap with a second sidewall disposed on the other side of the gate electrode G. In this way, due to the first lightly doped impurity region and the second lightly doped impurity region, the distance between the heavily doped impurity region of the source region S and the heavily doped impurity region of the drain region D may be increased, and due to the increase in the distance, the length of the channel region CH may be increased. Therefore, punch-through and hot carrier phenomena caused by a short channel may be prevented.

[0194] An interlayer insulating layer VA may be disposed on the substrate SUB.

[0195] A passivation layer PAS may be disposed on the interlayer insulating layer VA.

[0196] The light emitting element layer EMTL may be disposed on the passivation layer PAS. The light emitting element layer EMTL may include, for example, a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3 disposed in different emission regions. For example, the first light emitting element ED1 of the light emitting element layer EMTL may be disposed in the first emission region EA1, the second light emitting element ED2 of the light emitting element layer EMTL may be disposed in the second emission region EA2, and the third light emitting element ED3 of the light emitting element layer EMTL may be disposed in the third emission region EA3.

[0197] Each of the first light emitting element ED1 , the second light emitting element ED2 , and the third light emitting element ED3 may provide white light.

[0198] The first light emitting element ED1 may include a first pixel electrode PE1 (or a first anode electrode), a light-providing layer LPL, and a common electrode CE, which are stacked in the third direction DR3 .

[0199] The second light emitting element ED2 may include a second pixel electrode PE2 (or a second anode electrode), a light-providing layer LPL, and a common electrode CE, which are stacked in the third direction DR3 .

[0200] The third light emitting element ED3 may include a third pixel electrode PE3 (or a third anode electrode), a light-providing layer LPL, and a common electrode CE stacked in the third direction DR3.

[0201] Here, the light-supplying layer LPL and the common electrode CE may be common layers commonly used by the light emitting elements ED1 to ED3. In other words, the plurality of light emitting elements ED1 to ED3 of the light emitting element layer EMTL may share the light-supplying layer LPL and the common electrode CE.

[0202] The light-providing layer LPL may include a plurality of light-emitting layers providing light of different colors, and the plurality of light-emitting layers may be stacked along the third direction DR3. Different lights from the plurality of light-emitting layers may be mixed to generate white light. On the other hand, the light-providing layer LPL may further include a charge generation layer.

[0203] The first pixel electrode PE1 , the second pixel electrode PE2 , and the third pixel electrode PE3 may be connected to each drain region D of each transistor TR through the pixel connection electrode PCE.

[0204] The first pixel electrode PE1 may be disposed to correspond to the first emission area EA1, the second pixel electrode PE2 may be disposed to correspond to the second emission area EA2, and the third pixel electrode PE3 may be disposed to correspond to the third emission area EA3.

[0205] A bank PDL (or pixel defining layer) may be disposed on the first pixel electrode PE1 , the second pixel electrode PE2 , and the third pixel electrode PE3 .

[0206] The embankment PDL may define the emission area of ​​the pixel (e.g., the first emission area EA1 of the first pixel PX1, the second emission area EA2 of the second pixel PX2, and the third emission area EA3 of the third pixel PX3). To this end, the embankment PDL may be provided to expose a partial area of ​​each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 on the passivation layer PAS. The embankment PDL may cover the edge of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The embankment PDL may be formed of an organic layer (such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.).

[0207] The light-providing layer LPL may be disposed on the pixel electrodes PE1, PE2, and PE3 and the bank PDL. For example, the light-providing layer LPL may be disposed on the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the bank PDL.

[0208] The light providing layer LPL may include a plurality of light emitting units. For example, the light providing layer LPL may include a first light emitting unit, a second light emitting unit, and a third light emitting unit stacked in the third direction DR3. The light emitting units may provide light of different wavelengths. For example, the first light emitting unit, the second light emitting unit, and the third light emitting unit may emit light of different colors. For example, the light providing layer LPL may have a series structure in which a plurality of light emitting units providing light of different colors are stacked in a vertical direction (e.g., the third direction DR3).

[0209] The first light emitting unit may be disposed on the pixel electrodes PE1, PE2, and PE3. The first light emitting unit may include a first light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0210] The second light emitting unit may be disposed on the first light emitting unit. The second light emitting unit may include a second light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0211] The third light emitting unit may be disposed on the second light emitting unit. The third light emitting unit may include a third light emitting layer, a hole transport layer, an organic material layer, and an electron transport layer.

[0212] The light emitting elements ED1, ED2, and ED3 can provide white light by mixing light of a first color (e.g., blue) from a first light emitting unit, light of a second color (e.g., red) from a second light emitting unit, and light of a third color (e.g., green) from a third light emitting unit. For example, each of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 can provide white light.

[0213] In addition, in addition to the above-mentioned light-emitting units, the light-providing layer LPL may further include at least one charge generating layer. For example, the charge generating layer may be disposed between light-emitting units adjacent to each other in the third direction DR3. For example, the charge generating layer may include a first charge generating layer and a second charge generating layer stacked in the third direction DR3. In this case, the first charge generating layer may be disposed between the first light-emitting unit and the second light-emitting unit, and the second charge generating layer may be disposed between the second light-emitting unit and the third light-emitting unit.

[0214] On the other hand, each charge generation layer may include a negative charge generation layer and a positive charge generation layer. For example, the first charge generation layer may include a first negative charge generation layer and a first positive charge generation layer stacked in the third direction DR3, and the second charge generation layer may include a second negative charge generation layer and a second positive charge generation layer stacked in the third direction DR3.

[0215] The common electrode CE may be disposed on the light providing layer LPL. For example, the common electrode CE may be disposed on the light providing layer LPL to overlap with the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, the first emission area EA1, the second emission area EA2, the third emission area EA3, and the dike PDL. In the top emission structure, the common electrode CE may be formed of a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)). When the common electrode CE is formed of a semi-transmissive conductive material, the light emission efficiency may be increased due to the microcavity effect.

[0216] The cap layer CPL may be disposed on the common electrode CE. The cap layer CPL may include an inorganic insulating material. In an exemplary embodiment, the cap layer CPL may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0217] The encapsulation layer ENC may be disposed on the cap layer CPL. The encapsulation layer ENC may cover the top surface and the side surface of the light emitting element layer EMTL, and may protect the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer TFE1 and TFE3 to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer ENC may include at least one organic layer to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer ENC may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0218] The first inorganic encapsulation layer TFE1 may be disposed on the cap layer CPL, the organic encapsulation layer TFE2 may be disposed on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may be formed of a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The organic encapsulation layer TFE2 may be an organic layer such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0219] The light blocking layer BM may be disposed on the encapsulation layer ENC. The light blocking layer BM may include a plurality of holes OPT1, OPT2, and OPT3 disposed to overlap the emission areas EA1, EA2, and EA3. For example, the first hole OPT1 may be disposed in an area corresponding to the first emission area EA1. The second hole OPT2 may be disposed in an area corresponding to the second emission area EA2, and the third hole OPT3 may be disposed in an area corresponding to the third emission area EA3. The areas or sizes of the holes OPT1, OPT2, and OPT3 may be respectively larger than the areas or sizes of the emission areas EA1, EA2, and EA3 defined by the embankment PDL. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM are formed to be larger than the emission areas EA1, EA2, and EA3, so that the light emitted from the emission areas EA1, EA2, and EA3 can be visually recognized by the user not only from the front surface of the display device 10 but also from the side surface of the display device 10.

[0220] The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but they are not limited thereto. The light blocking layer BM may prevent visible light penetration and color mixing between the first to third emission areas EA1, EA2, and EA3, which results in an improvement in the color reproducibility of the display device 10.

[0221] In addition, the display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed in the emission areas EA1, EA2, and EA3. The plurality of color filters CF1, CF2, and CF3 may be disposed to correspond to the emission areas EA1, EA2, and EA3, respectively. For example, the color filters CF1, CF2, and CF3 may be disposed on a light blocking layer BM including a plurality of holes OPT1, OPT2, and OPT3 disposed to correspond to the emission areas EA1, EA2, and EA3, respectively.

[0222] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are respectively arranged to correspond to different emission areas EA1, EA2, and EA3. The color filters CF1, CF2, and CF3 may include a colorant (such as a dye or a pigment) that absorbs light in a band other than light in a specific band, and may be arranged to correspond to the color of light emitted from the emission areas EA1, EA2, and EA3. For example, the first color filter CF1 may be a red color filter that is arranged to overlap with the first emission area EA1 and transmits only a red first light. The second color filter CF2 may be a green color filter that is arranged to overlap with the second emission area EA2 and transmits only a green second light, and the third color filter CF3 may be a blue color filter that is arranged to overlap with the third emission area EA3 and transmits only a blue third light.

[0223] A plurality of color filters CF1, CF2 and CF3 may be spaced apart from other adjacent color filters CF1, CF2 and CF3 on the light blocking layer BM. The color filters CF1, CF2 and CF3 may have an area larger than the area of ​​the holes OPT1, OPT2 and OPT3 of the light blocking layer BM, respectively, while covering the holes OPT1, OPT2 and OPT3, and may have an area sufficient to be spaced apart from other color filters CF1, CF2 and CF3 on the light blocking layer BM. However, the present disclosure is not limited thereto. A plurality of color filters CF1, CF2 and CF3 may be arranged to partially overlap with other adjacent color filters CF1, CF2 and CF3 on the light blocking layer BM. Different color filters CF1, CF2 and CF3 do not overlap each other in the emission areas EA1, EA2 and EA3, and may overlap each other on the light blocking layer BM. In the display device, the color filters CF1, CF2 and CF3 are arranged to overlap each other on the light blocking layer BM, so that the intensity of light reflected by external light can be reduced. Furthermore, by adjusting the arrangement, shape, and area of ​​the color filters CF1, CF2, CF3 in a plan view, the color of light reflected by external light can be controlled.

[0224] The overcoat layer OC may be disposed on the color filters CF1, CF2, and CF3 to flatten the steps formed on the color filters CF1, CF2, and CF3. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as acrylic resin.

[0225] Figure 8 is a plan view of a display device according to an embodiment.

[0226] like Figure 8 As shown in , the display device may include a plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6. The plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6 may be arranged in a first direction DR1 and a second direction DR2.

[0227] Each of the pixels PX1, PX2, PX3, PX4, PX5, and PX6 may include six transistor regions arranged in three rows and two columns. For example, the first pixel PX1 may include a first-first transistor region A1-1, a first-second transistor region A1-2, a second-first transistor region A2-1, a second-second transistor region A2-2, a third-first transistor region A3-1, and a third-second transistor region A3-2 arranged in three rows and two columns.

[0228] The first main transistor MT1 may be disposed in a first-first transistor region A1 - 1 corresponding to a first column of a first row.

[0229] The second main transistor MT2 may be disposed in the third-second transistor region A3 - 2 corresponding to the second column of the third row.

[0230] The third main transistor MT3 may be disposed in the second-second transistor region A2 - 2 corresponding to the second column of the second row.

[0231] The fourth main transistor MT4 may be disposed in the second-first transistor region A2 - 1 corresponding to the first column of the second row.

[0232] The second auxiliary transistor AT2 may be disposed in the third-first transistor region A3 - 1 corresponding to the first column of the third row.

[0233] The third auxiliary transistor AT3 may be disposed in the first-second transistor region A1 - 2 corresponding to the second column of the first row.

[0234] When a region including the first-first transistor region A1-1, the second-first transistor region A2-1, the second-second transistor region A2-2, and the third-second transistor region A3-2 is defined as a main transistor region MTA, the main transistor region MTA may have a bent shape.

[0235] The first-second transistor region A1 - 2 may be a first auxiliary transistor region ATA1 , and the third-first transistor region A3 - 1 may be a second auxiliary transistor region ATA2 .

[0236] The first-second transistor region A1-2 in which the third auxiliary transistor AT3 is disposed may be disposed close to the second-second transistor region A2-2 in the second direction DR2 in which the third main transistor MT3 is disposed. Therefore, the third auxiliary transistor AT3 may be disposed close to the third main transistor MT3. Therefore, when the third main transistor MT3 is defective, the third auxiliary transistor AT3 may be connected to the pixel circuit PC of the third main transistor MT3 disposed close to the third auxiliary transistor AT3.

[0237] The third-first transistor region A3-1 provided with the second auxiliary transistor AT2 may be provided close to the third-second transistor region A3-2 in the first direction DR1 provided with the second main transistor MT2. Therefore, the second auxiliary transistor AT2 may be provided close to the second main transistor MT2. Therefore, when the second main transistor MT2 is defective, the second auxiliary transistor AT2 may be connected to the pixel circuit PC provided close to the second main transistor MT2 of the second auxiliary transistor AT2.

[0238] Fig. 9 is a plan view of a display device according to an embodiment, Fig.10 is where a second metal layer is further added to Fig. 9 View, Fig.11 It is along Fig.10 A cross-sectional view taken along line II' of Fig.12 It is along Fig.10 A cross-sectional view taken along line II-II'.

[0239] like Fig.11 and Fig.12 As shown in , the display device may include a driving circuit layer DCL, a first interlayer insulating layer VA1, a first metal layer ML1, a second interlayer insulating layer VA2, and a second metal layer ML2 stacked along a third direction DR3.

[0240] As in Figures 9 to 12 In the example shown in , the driving circuit layer DCL may include a substrate SUB, a gate insulating layer GTI, a body electrode BE, a passivation layer 135, a first main transistor MT1, a second main transistor MT2, a third main transistor MT3, a fourth main transistor MT4, a second auxiliary transistor AT2, and a third auxiliary transistor AT3.

[0241] like Fig. 9 As shown in, the first main transistor MT1 may include a first gate electrode G1 overlapping the first well region W1, a first source electrode S1 arranged at one edge of the first well region W1 so as not to overlap with the first gate electrode G1, and a first drain electrode D1 arranged at a central portion of the first well region W1 so as not to overlap with the first gate electrode G1.

[0242] like Fig. 9 As shown in, the second main transistor MT2 may include a second gate electrode G2 overlapping with the second well region W2, a second source electrode S2 arranged at one edge of the second well region W2 so as not to overlap with the second gate electrode G2, and a second drain electrode D2 arranged at the other edge of the second well region W2 so as not to overlap with the second gate electrode G2.

[0243] like Fig. 9 As shown in, the third main transistor MT3 may include a third gate electrode G3 overlapping with the third well region W3, a third source electrode S3 arranged at one edge of the third well region W3 so as not to overlap with the third gate electrode G3, and a third drain electrode D3 arranged at another edge of the third well region W3 so as not to overlap with the third gate electrode G3.

[0244] like Fig. 9 As shown in , the fourth main transistor MT4 may include a fourth gate electrode G4 overlapping the first well region W1, a fourth source electrode S4 disposed at a central portion of the first well region W1 so as not to overlap the fourth gate electrode G4, and a fourth drain electrode D4 disposed at another edge of the first well region W1 so as not to overlap the fourth gate electrode G4. Here, the fourth source electrode S4 and the above-mentioned first drain electrode D1 may be formed integrally.

[0245] like Fig. 9 As shown in, the second auxiliary transistor AT2 may include a second gate electrode G2-A overlapping with the second auxiliary well region W2-A, a second source electrode S2-A arranged at one edge of the second auxiliary well region W2-A so as not to overlap with the second gate electrode G2-A, and a second drain electrode D2-A arranged at the other edge of the second auxiliary well region W2-A so as not to overlap with the second gate electrode G2-A.

[0246] like Fig. 9 As shown in, the third auxiliary transistor AT3 may include a third gate electrode G3-A overlapping with the third auxiliary well region W3-A, a third source electrode S3-A arranged at one edge of the third auxiliary well region W3-A so as not to overlap with the third gate electrode G3-A, and a third drain electrode D3-A arranged at the other edge of the third auxiliary well region W3-A so as not to overlap with the third gate electrode G3-A.

[0247] When the substrate SUB is a substrate doped with first-type impurities, the first well region W1, the second well region W2, the third well region W3, the second auxiliary well region W2-A, and the third auxiliary well region W3-A may be regions doped with second-type impurities. The second-type impurities may be different from the first-type impurities described above. For example, when the first-type impurities are p-type impurities, the second-type impurities may be n-type impurities. On the other hand, when the first-type impurities are n-type impurities, the second-type impurities may be p-type impurities.

[0248] In addition, each transistor (eg, each main transistor and each auxiliary transistor) may further include a channel region, a lightly doped impurity region, and a sidewall. Fig.11 As shown in , the second main transistor MT2 may further include a second channel region CH2, a first lightly doped impurity region LDD1, a second lightly doped impurity region LDD2, a first side wall SW1, and a second side wall SW2. For another example, as shown in Fig.12 As shown in , the second auxiliary transistor AT2 may further include a second channel region CH2 -A, a first lightly doped impurity region LDD1 , a second lightly doped impurity region LDD2 , a first side wall SW1 -A, and a second side wall SW2 -A.

[0249] The body electrode BE may be connected to the driving voltage line VDL. The body electrode BE may be made of the same material as that of the source electrode or the drain electrode of the above-mentioned transistor. For example, the body electrode BE may be made of the same material as that of the first source electrode SE1.

[0250] like Fig.11 and Fig.12As shown in , the first interlayer insulating layer VA1 may be disposed on the driving circuit layer DCL. For example, the first interlayer insulating layer VA1 may be disposed on the entire surface of the driving circuit layer DCL.

[0251] like Fig.11 and Fig.12 As shown in FIG. 1 , the first metal layer ML1 may be disposed on the first interlayer insulating layer VA1 .

[0252] like Figures 9 to 12 As shown in , the first metal layer ML1 may include a first gate connection electrode GCE1, a second gate connection electrode GCE2, a third gate connection electrode GCE3, a first source connection electrode SCE1, a second source connection electrode SCE2, a third source connection electrode SCE3, a fourth source connection electrode SCE4, a first drain connection electrode DCE1, a second drain connection electrode DCE2, a third drain connection electrode DCE3, a fourth drain connection electrode DCE4, a fifth drain connection electrode DCE5, a first source / drain connection electrode SDCE1, a first gate line GL1, a second gate line GL2, an emission line EML, and a lower driving voltage line VDLa. The first metal layer ML1 may be formed of, for example, tungsten.

[0253] The first gate connection electrode GCE1 may be connected to the first gate electrode G1 of the first main transistor MT1 through a first contact hole CT1 formed through the first interlayer insulating layer VA1 and the passivation layer 135 .

[0254] The second gate connection electrode GCE2 may be connected to the second gate electrode G2 -A of the second auxiliary transistor AT2 through a twenty-second contact hole CT22 formed through the first interlayer insulating layer VA1 and the passivation layer 135 .

[0255] The third gate connection electrode GCE3 may be connected to the third gate electrode G3-A of the third auxiliary transistor AT3 through a twenty-fifth contact hole CT25 formed through the first interlayer insulating layer VA1 and the passivation layer 135. The third gate connection electrode GCE3 may include a repairing short portion RSP.

[0256] The first source connection electrode SCE1 may be connected to the first source electrode S1 of the first main transistor MT1 through a second contact hole CT2 formed through the first interlayer insulating layer VA1 and the passivation layer 135 .

[0257] The second source connection electrode SCE2 may be connected to the second source electrode S2 of the second main transistor MT2 through a fifth contact hole CT5 formed through the first interlayer insulating layer VA1 and the passivation layer 135. The second source connection electrode SCE2 may include a repairing short portion RSP.

[0258] The third source connection electrode SCE3 may be connected to the second source electrode S2 -A of the second auxiliary transistor AT2 through a twenty-third contact hole CT23 formed through the first interlayer insulating layer VA1 and the passivation layer 135 .

[0259] The fourth source connection electrode SCE4 may be connected to the third source electrode S3-A of the third auxiliary transistor AT3 through a twenty-sixth contact hole CT26 formed through the first interlayer insulating layer VA1 and the passivation layer 135. The fourth source connection electrode SCE4 may include a repairing short portion RSP.

[0260] The first drain connection electrode DCE1 may be connected to the second drain electrode D2-A of the second auxiliary transistor AT2 through a twenty-fourth contact hole CT24 formed through the first interlayer insulating layer VA1 and the passivation layer 135. The first drain connection electrode DCE1 may include a repairing short portion RSP.

[0261] The second drain connection electrode DCE2 may be connected to the second drain electrode D2 of the second main transistor MT2 through a sixth contact hole CT6 formed through the first interlayer insulating layer VA1 and the passivation layer 135 .

[0262] The third drain connection electrode DCE3 may be connected to the third drain electrode D3 of the third main transistor MT3 through a ninth contact hole CT9 formed through the first interlayer insulating layer VA1 and the passivation layer 135 .

[0263] The fourth drain connection electrode DCE4 may be connected to the fourth drain electrode D4 of the fourth master transistor MT4 through an eleventh contact hole CT11 formed through the first interlayer insulating layer VA1 and the passivation layer 135 .

[0264] The fifth drain connection electrode DCE5 may be connected to the third drain electrode D3-A of the third auxiliary transistor AT3 through a twenty-seventh contact hole CT27 formed through the first interlayer insulating layer VA1 and the passivation layer 135. The fifth drain connection electrode DCE5 may include a repairing short portion RSP.

[0265] The first source / drain connection electrode SDCE1 may be connected to the first drain electrode D1 of the first main transistor MT1 and the fourth source electrode S4 of the fourth main transistor MT4 through a third contact hole CT3 formed through the first interlayer insulating layer VA1 and the passivation layer 135 .

[0266] The first gate line GL1 may be connected to the second gate electrode G2 of the second main transistor MT2 through a fourth contact hole CT4 formed through the first interlayer insulating layer VA1 and the passivation layer 135. The first gate line GL1 may include a repairing short portion RSP.

[0267] The second gate line GL2 may be connected to the fourth gate electrode G4 of the fourth main transistor MT4 through a tenth contact hole CT10 formed through the first interlayer insulating layer VA1 and the passivation layer 135 .

[0268] The emission line EML may be connected to the third gate electrode G3 of the third master transistor MT3 through a seventh contact hole CT7 formed through the first interlayer insulating layer VA1 and the passivation layer 135 .

[0269] The lower driving voltage line VDLa may be connected to the third source electrode S3 of the third main transistor MT3 through the eighth contact hole CT8 formed through the first interlayer insulating layer VA1 and the passivation layer 135. The lower driving voltage line VDLa may be a part of the above-mentioned driving voltage line VDL. For example, the driving voltage line VDL may include a lower driving voltage line VDLa and an upper driving voltage line VDLb disposed in different layers. The lower driving voltage line VDLa and the upper driving voltage line VDLb may extend in directions intersecting each other. For example, the lower driving voltage line VDLa may extend along the first direction DR1, and the upper driving voltage line VDLb may extend along the second direction DR2. A plurality of lower driving voltage lines VDLa and a plurality of upper driving voltage lines VDLb may be provided. A plurality of lower driving voltage lines VDLa may be arranged along the second direction DR2, and a plurality of upper driving voltage lines VDLb may be arranged along the first direction DR1. A plurality of lower driving voltage lines VDLa and a plurality of upper driving voltage lines VDLb may be connected to each other through contact holes (not shown) formed through the second interlayer insulating layer VA2 to form a driving voltage line VDL. The driving voltage line VDL including the plurality of lower driving voltage lines VDLa and the plurality of upper driving voltage lines VDLb may have a mesh shape.

[0270] like Fig.11 and Fig.12 As shown in FIG. 5 , the second interlayer insulating layer VA2 may be disposed on the first metal layer ML1. For example, the second interlayer insulating layer VA2 may be disposed on the entire surface of the substrate SUB between the first metal layer ML1 and the second metal layer ML2.

[0271] like Figures 10 to 12 As shown in , the second metal layer ML2 may include a pixel connection electrode PCE, a gate / drain connection electrode GDCE, a second source / drain connection electrode SDCE2, a first gate extension electrode GEE1, a second gate extension electrode GEE2, a source extension electrode SEE, a data line DL, an upper driving voltage line VDLb, and a common voltage line VSL. The second metal layer ML2 may be formed of, for example, tungsten.

[0272] The pixel connection electrode PCE may be connected to the first source / drain connection electrode SDCE1 through a fourteenth contact hole CT14 formed through the second interlayer insulating layer VA2 .

[0273] The gate / drain connection electrode GDCE may be connected to the first gate connection electrode GCE1 through a twelfth contact hole CT12 formed through the second interlayer insulating layer VA2. In addition, the gate / drain connection electrode GDCE may be connected to the second drain connection electrode DCE2 through a twenty-first contact hole CT21 formed through the second interlayer insulating layer VA2. In addition, the gate / drain connection electrode GDCE may include a repair short portion RSP, and the repair short portion RSP of the gate / drain connection electrode GDCE may overlap with the repair short portion RSP of the first drain connection electrode DCE1 described above.

[0274] The second source / drain connection electrode SDCE2 may be connected to the first source connection electrode SCE1 through a thirteenth contact hole CT13 formed through the second interlayer insulating layer VA2. In addition, the second source / drain connection electrode SDCE2 may be connected to the third drain connection electrode DCE3 through a sixteenth contact hole CT16 formed through the second interlayer insulating layer VA2. In addition, the second source / drain connection electrode SDCE2 may include a repairing short portion RSP, and the repairing short portion RSP of the second source / drain connection electrode SDCE2 may overlap with the repairing short portion RSP of the fifth drain connection electrode DCE5.

[0275] The first gate extension electrode GEE1 may be connected to the second gate connection electrode GCE2 through a nineteenth contact hole CT19 formed through the second interlayer insulating layer VA2. In addition, the first gate extension electrode GEE1 may include a repairing short portion RSP, and the repairing short portion RSP of the first gate extension electrode GEE1 may overlap the repairing short portion RSP of the first gate line GL1.

[0276] The second gate extension electrode GEE2 may be connected to the emission line EML through a fifteenth contact hole CT15 formed through the second interlayer insulating layer VA2. In addition, the second gate extension electrode GEE2 may include a repair short portion RSP, and the repair short portion RSP of the second gate extension electrode GEE2 may overlap the repair short portion RSP of the third gate connection electrode GCE3.

[0277] The source extension electrode SEE may be connected to the third source connection electrode SCE3 through a twentieth contact hole CT20 formed through the second interlayer insulating layer VA2. In addition, the source extension electrode SEE may include a repairing short portion RSP, and the repairing short portion RSP of the source extension electrode SEE may overlap the repairing short portion RSP of the second source connection electrode SCE2.

[0278] The data line DL may be connected to the second source link electrode SCE2 through a seventeenth contact hole CT17 formed through the second interlayer insulating layer VA2 .

[0279] The upper driving voltage line VDLb may be connected to the lower driving voltage line VDLa through a twenty-eighth contact hole CT28 formed through the second interlayer insulating layer VA2. In addition, the upper driving voltage line VDLb may include a repairing short portion RSP, and the repairing short portion RSP of the upper driving voltage line VDLb may overlap with the repairing short portion RSP of the fourth source connection electrode SCE4.

[0280] The common voltage line VSL may be connected to the fourth drain link electrode DCE4 through an eighteenth contact hole CT18 formed through the second interlayer insulating layer VA2 .

[0281] Fig.13 , Fig.14 , Fig.15 and Fig.16 is a diagram illustrating a method of repairing a display device according to an embodiment.

[0282] When it is determined that the second main transistor MT2 is defective due to the inspection of the second main transistor MT2, the connection between the second main transistor MT2 and the pixel circuit PC may be disconnected. As an example of this, Fig.13 and Fig.14As shown in , by irradiating the laser LS to the second source connection electrode SCE2 and the second drain connection electrode DCE2 of the second main transistor MT2, respectively, the second source connection electrode SCE2 and the second drain connection electrode DCE2 can be disconnected. In other words, the second source connection electrode SCE2 can be disconnected so that the data line DL and the second source electrode S2 of the second main transistor MT2 are separated, and the disconnected portion of the second source connection electrode SCE2 is overlapped with the overlapping portion between the repaired short-circuit portion RSP of the source extension electrode SEE and the repaired short-circuit portion RSP of the second source connection electrode SCE2, and the second drain connection electrode DCE2 can be disconnected so that the gate / drain connection electrode GDCE and the second drain electrode D2 of the second main transistor MT2 are separated, and the disconnected portion of the second drain connection electrode DCE2 is overlapped with the overlapping portion between the repaired short-circuit portion RSP of the gate / drain connection electrode GDCE and the repaired short-circuit portion RSP of the second drain connection electrode DCE2. For example, the second source connection electrode SCE2 is removed by laser LS in the preset first disconnection area CA1 of the second source connection electrode SCE2, so that the electrical connection between the second source connection electrode SCE2 and the data line DL can be cut off. In addition, the second drain connection electrode DCE2 is removed by laser LS in the preset second disconnection area CA2 of the second drain connection electrode DCE2, so that the electrical connection between the second drain connection electrode DCE2 and the gate / drain connection electrode GDCE can be cut off. Therefore, the second source electrode S2 and the second drain electrode D2 of the second main transistor MT2 can be electrically separated from the data line DL and the gate / drain connection electrode GDCE, respectively.

[0283] Then, the second auxiliary transistor AT2 can be connected to the pixel circuit PC. Fig.13 , Fig.15 and Fig.16As shown in, by irradiating laser LS to the repaired short-circuit portion RSP of the first gate extension electrode GEE1, the repaired short-circuit portion RSP of the source extension electrode SEE and the repaired short-circuit portion RSP of the gate / drain connection electrode GDCE, the repaired short-circuit portion RSP of the first gate extension electrode GEE1 and the repaired short-circuit portion RSP of the first gate line GL1 disposed thereunder can contact each other at their first overlapping area OA1, the repaired short-circuit portion RSP of the source extension electrode SEE and the repaired short-circuit portion RSP of the second source connection electrode SCE2 disposed thereunder can contact each other at their second overlapping area OA2, and the repaired short-circuit portion RSP of the gate / drain connection electrode GDCE and the repaired short-circuit portion RSP of the first drain connection electrode DCE1 disposed thereunder can contact each other at their third overlapping area OA3. Therefore, the first gate extension electrode GEE1 and the first gate line GL1 may be electrically connected, the source extension electrode SEE and the second source connection electrode SCE2 may be electrically connected, and the gate / drain connection electrode GDCE and the first drain connection electrode DCE1 may be electrically connected. Therefore, the second gate electrode G2-A of the second auxiliary transistor AT2 may be connected to the first gate line GL1, the second source electrode S2-A of the second auxiliary transistor AT2 may be connected to the data line DL, and the second drain electrode D2-A of the second auxiliary transistor AT2 may be connected to the gate / drain connection electrode GDCE.

[0284] Fig.17 is a diagram illustrating a method of repairing a display device according to an embodiment.

[0285] When it is determined that the third main transistor MT3 is defective due to the inspection of the third main transistor MT3, the connection between the third main transistor MT3 and the pixel circuit PC may be disconnected. As an example of this, Fig.17As shown in , by irradiating the laser LS to the lower driving voltage line VDLa and the third drain connection electrode DCE3 respectively, the lower driving voltage line VDLa and the third drain connection electrode DCE3 can be disconnected. In other words, the lower driving voltage line VDLa can be disconnected so that the lower driving voltage line VDLa and the source electrode S3 of the third main transistor MT3 are separated, and the disconnected portion of the lower driving voltage line VDLa is overlapped with the overlapping portion between the repaired short-circuit portion RSP of the upper driving voltage line VDLb and the repaired short-circuit portion RSP of the fourth source connection electrode SCE4, and the third drain connection electrode DCE3 can be disconnected so that the second source / drain connection electrode SDCE2 and the drain electrode D3 of the third main transistor MT3 are separated, and the disconnected portion of the third drain connection electrode DCE3 is overlapped with the overlapping portion between the repaired short-circuit portion RSP of the second source / drain connection electrode SDCE2 and the repaired short-circuit portion RSP of the fifth drain connection electrode DCE5. For example, the lower driving voltage line VDLa is removed by laser LS in the preset third disconnection area CA3 of the lower driving voltage line VDLa, so that the electrical connection between the lower driving voltage line VDLa and the third source electrode S3 of the third main transistor MT3 can be cut off. In addition, the third drain connection electrode DCE3 is removed by laser LS in the preset fourth disconnection area CA4 of the third drain connection electrode DCE3, so that the electrical connection between the third drain connection electrode DCE3 and the second source / drain connection electrode SDCE2 can be cut off. Therefore, the third source electrode S3 and the third drain electrode D3 of the third main transistor MT3 can be electrically separated from the lower driving voltage line VDLa and the second source / drain connection electrode SDCE2, respectively.

[0286] Then, the third auxiliary transistor AT3 can be connected to the pixel circuit PC. Fig.17As shown in, by irradiating laser LS to the repaired short-circuit portion RSP of the second gate extension electrode GEE2, the repaired short-circuit portion RSP of the upper driving voltage line VDLb and the repaired short-circuit portion RSP of the second source / drain connection electrode SDCE2, the repaired short-circuit portion RSP of the second gate extension electrode GEE2 and the repaired short-circuit portion RSP of the third gate connection electrode GCE3 disposed thereunder can contact each other at their fourth overlapping area OA4, the repaired short-circuit portion RSP of the upper driving voltage line VDLb and the repaired short-circuit portion RSP of the fourth source connection electrode SCE4 disposed thereunder can contact each other at their fifth overlapping area OA5, and the repaired short-circuit portion RSP of the second source / drain connection electrode SDCE2 and the repaired short-circuit portion RSP of the fifth drain connection electrode DCE5 disposed thereunder can contact each other at their sixth overlapping area OA6. Therefore, the second gate extension electrode GEE2 and the third gate connection electrode GCE3 may be electrically connected, the upper driving voltage line VDLb and the fourth source connection electrode SCE4 may be electrically connected, and the second source / drain connection electrode SDCE2 and the fifth drain connection electrode DCE5 may be electrically connected. Therefore, the third gate electrode G3-A of the third auxiliary transistor AT3 may be connected to the emission line EML, the third source electrode S3-A of the third auxiliary transistor AT3 may be connected to the upper driving voltage line VDLb, and the third drain electrode D3-A of the third auxiliary transistor AT3 may be connected to the second source / drain connection electrode SDCE2.

[0287] On the other hand, the above-mentioned disconnection areas CA1, CA2, CA3, and CA4 and the overlap areas OA1, OA2, OA3, OA4, OA5, and OA6 may not overlap each other.

[0288] Fig.18 is a plan view of a display device according to an embodiment.

[0289] like Fig.18 As shown in , the display device may include a plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6. The plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6 may be arranged in a first direction DR1 and a second direction DR2.

[0290] Fig.18 The display device and Figure 8 The display device of is different in that transistors of adjacent pixels are arranged differently, and the difference will be mainly described below.

[0291] like Fig.18 As shown in FIG. 1 , transistors of pixels adjacent in the first direction DR1 may be arranged differently. For example, the first pixel PX1 and the second pixel PX2 may include transistors arranged differently. This will be described in detail below.

[0292] The first main transistor MT1 of the first pixel PX1 may be disposed in the first-first transistor area A1 - 1 corresponding to the first column of the first row.

[0293] The second main transistor MT2 of the first pixel PX1 may be disposed in the third-second transistor region A3 - 2 corresponding to the second column of the third row.

[0294] The third main transistor MT3 of the first pixel PX1 may be disposed in the second-second transistor region A2 - 2 corresponding to the second column of the second row.

[0295] The fourth main transistor MT4 of the first pixel PX1 may be disposed in the second-first transistor region A2 - 1 corresponding to the first column of the second row.

[0296] The second auxiliary transistor AT2 of the first pixel PX1 may be disposed in the third-first transistor area A3 - 1 corresponding to the first column of the third row.

[0297] The third auxiliary transistor AT3 of the first pixel PX1 may be disposed in the first-second transistor region A1 - 2 corresponding to the second column of the first row.

[0298] The first main transistor MT1 of the second pixel PX2 may be disposed in the first-second transistor area A1 - 2 corresponding to the second column of the first row.

[0299] The second main transistor MT2 of the second pixel PX2 may be disposed in the third-first transistor region A3 - 1 corresponding to the first column of the third row.

[0300] The third main transistor MT3 of the second pixel PX2 may be disposed in the second-first transistor region A2 - 1 corresponding to the first column of the second row.

[0301] The fourth main transistor MT4 of the second pixel PX2 may be disposed in the second-second transistor region A2 - 2 corresponding to the second column of the second row.

[0302] The second auxiliary transistor AT2 of the second pixel PX2 may be disposed in the third-second transistor area A3 - 2 corresponding to the second column of the third row.

[0303] The third auxiliary transistor AT3 of the second pixel PX2 may be disposed in the first-first transistor area A1 - 1 corresponding to the first column of the first row.

[0304] Fig.19 is a plan view of a display device according to an embodiment.

[0305] like Fig.19As shown in , the display device may include a plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6. The plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6 may be arranged in a first direction DR1 and a second direction DR2.

[0306] Each of the pixels PX1, PX2, PX3, PX4, PX5, and PX6 may include six transistor regions arranged in three rows and two columns. For example, the first pixel PX1 may include a first-first transistor region A1-1, a first-second transistor region A1-2, a second-first transistor region A2-1, a second-second transistor region A2-2, a third-first transistor region A3-1, and a third-second transistor region A3-2 arranged in three rows and two columns.

[0307] The first main transistor MT1 may be disposed in the third-first transistor region A3 - 1 corresponding to the first column of the third row.

[0308] The second main transistor MT2 may be disposed in the second-first transistor region A2 - 1 corresponding to the first column of the second row.

[0309] The third main transistor MT3 may be disposed in the second-second transistor region A2 - 2 corresponding to the second column of the second row.

[0310] The fourth main transistor MT4 may be disposed in the third-second transistor region A3 - 2 corresponding to the second column of the third row.

[0311] The second auxiliary transistor AT2 may be disposed in the first-first transistor region A1 - 1 corresponding to the first column of the first row.

[0312] The third auxiliary transistor AT3 may be disposed in the first-second transistor region A1 - 2 corresponding to the second column of the first row.

[0313] When a region including the second-first transistor region A2-1, the second-second transistor region A2-2, the third-first transistor region A3-1, and the third-second transistor region A3-2 is defined as a main transistor region MTA, the main transistor region MTA may have a quadrilateral shape.

[0314] When a region including the first-first transistor region A1 - 1 and the first-second transistor region A1 - 2 is defined as the auxiliary transistor region ATA, the auxiliary transistor region ATA may have a quadrangular shape.

[0315] Fig. 20 is a plan view of a display device according to an embodiment.

[0316] like Fig. 20As shown in , the display device may include a plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6. The plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6 may be arranged in a first direction DR1 and a second direction DR2.

[0317] Fig. 20 The display device and Fig.19 The display device of is different in that transistors of adjacent pixels are arranged differently, and the difference will be mainly described below.

[0318] like Fig. 20 As shown in FIG. 1 , transistors of pixels adjacent in the first direction DR1 may be arranged differently. For example, the first pixel PX1 and the second pixel PX2 may include transistors arranged differently. This will be described in detail below.

[0319] The first main transistor MT1 of the first pixel PX1 may be disposed in the third-first transistor region A3 - 1 corresponding to the first column of the third row.

[0320] The second main transistor MT2 of the first pixel PX1 may be disposed in the second-first transistor area A2 - 1 corresponding to the first column of the second row.

[0321] The third main transistor MT3 of the first pixel PX1 may be disposed in the second-second transistor region A2 - 2 corresponding to the second column of the second row.

[0322] The fourth main transistor MT4 of the first pixel PX1 may be disposed in the third-second transistor region A3 - 2 corresponding to the second column of the third row.

[0323] The second auxiliary transistor AT2 of the first pixel PX1 may be disposed in the first-first transistor area A1 - 1 corresponding to the first column of the first row.

[0324] The third auxiliary transistor AT3 of the first pixel PX1 may be disposed in the first-second transistor region A1 - 2 corresponding to the second column of the first row.

[0325] The first main transistor MT1 of the second pixel PX2 may be disposed in the first-second transistor area A1 - 2 corresponding to the second column of the first row.

[0326] The second main transistor MT2 of the second pixel PX2 may be disposed in the second-second transistor area A2 - 2 corresponding to the second column of the second row.

[0327] The third main transistor MT3 of the second pixel PX2 may be disposed in the second-first transistor region A2 - 1 corresponding to the first column of the second row.

[0328] The fourth main transistor MT4 of the second pixel PX2 may be disposed in the first-first transistor region A1 - 1 corresponding to the first column of the first row.

[0329] The second auxiliary transistor AT2 of the second pixel PX2 may be disposed in the third-second transistor area A3 - 2 corresponding to the second column of the third row.

[0330] The third auxiliary transistor AT3 of the second pixel PX2 may be disposed in the third-first transistor area A3 - 1 corresponding to the first column of the third row.

[0331] Fig.21 is a plan view of a display device according to an embodiment.

[0332] like Fig.21 As shown in , the display device may include a plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6. The plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6 may be arranged in a first direction DR1 and a second direction DR2.

[0333] Each of the pixels PX1, PX2, PX3, PX4, PX5, and PX6 may include six transistor regions defined by three rows and two columns. For example, the first pixel PX1 may include a first-first transistor region A1-1, a first-second transistor region A1-2, a second-first transistor region A2-1, a second-second transistor region A2-2, a third-first transistor region A3-1, and a third-second transistor region A3-2 arranged in three rows and two columns.

[0334] The first main transistor MT1 may be disposed in a first-first transistor region A1 - 1 corresponding to a first column of a first row.

[0335] The second main transistor MT2 may be disposed in the first-second transistor region A1 - 2 corresponding to the second column of the first row.

[0336] The third main transistor MT3 may be disposed in the third-first transistor region A3 - 1 corresponding to the first column of the third row.

[0337] The fourth main transistor MT4 may be disposed in the third-second transistor region A3 - 2 corresponding to the second column of the third row.

[0338] The second auxiliary transistor AT2 may be disposed in the second-second transistor region A2 - 2 corresponding to the second column of the second row.

[0339] The third auxiliary transistor AT3 may be disposed in the second-first transistor region A2 - 1 corresponding to the first column of the second row.

[0340] When a region including the first-first transistor region A1 - 1 and the first-second transistor region A1 - 2 is defined as a first main transistor region MTA1 , the first main transistor region MTA1 may have a quadrangular shape.

[0341] When a region including the third-first transistor region A3 - 1 and the third-second transistor region A3 - 2 is defined as the second main transistor region MTA2 , the second main transistor region MTA2 may have a quadrangular shape.

[0342] When a region including the second-first transistor region A2 - 1 and the second-second transistor region A2 - 2 is defined as the auxiliary transistor region ATA, the auxiliary transistor region ATA may have a quadrangular shape.

[0343] Fig. 22 is a circuit diagram of one pixel of a display device according to an embodiment.

[0344] like Fig. 22 As shown in , the pixel PX can be connected to the first gate line GL1, the second gate line GL2, the third gate line GL3, the emission line EML, the initialization line VIL, the data line DL, the sensing line SSL, the driving voltage line VDL and the common voltage line VSL. Here, the common voltage line VSL can be connected to the common electrode (e.g., cathode electrode) of the light emitting element ED.

[0345] The pixel PX may include a pixel circuit PC and a light emitting element ED.

[0346] The pixel circuit PC may include a first main transistor MT1, a second main transistor MT2, a third main transistor MT3, a fourth main transistor MT4, a second auxiliary transistor AT2, a sensing transistor ST, a first capacitor C1, and a second capacitor C2.

[0347] because Fig. 22 The first main transistor MT1, the second main transistor MT2, the third main transistor MT3, the fourth main transistor MT4, the second auxiliary transistor AT2, the first capacitor C1 and the second capacitor C2 are respectively connected to the above Figure 5 The first main transistor MT1, the second main transistor MT2, the third main transistor MT3, the fourth main transistor MT4, the second auxiliary transistor AT2, the first capacitor C1 and the second capacitor C2 are the same, so Fig. 22 The description of the first main transistor MT1, the second main transistor MT2, the third main transistor MT3, the fourth main transistor MT4, the second auxiliary transistor AT2, the first capacitor C1 and the second capacitor C2 refers to Figure 5 and related descriptions.

[0348] The sensing transistor ST may be turned on by the third gate signal GS3 of the third gate line GL3 to electrically connect the first node N1 and the sensing line SSL. The gate electrode of the sensing transistor ST may be electrically connected to the third gate line GL3, the source electrode thereof may be electrically connected to the first node N1, and the drain electrode thereof may be electrically connected to the sensing line SSL.

[0349] For example, the sensing transistor ST may remain in the on state during the on period of the second main transistor MT2. In other words, the period during which the third gate signal GS3 applied to the gate electrode of the sensing transistor ST remains at an effective level may be the same as the period during which the first gate signal GS1 applied to the gate electrode of the second main transistor MT2 remains at an effective level.

[0350] For example, the reference voltage Vref may be applied to the data line DL during the conduction period of the sensing transistor ST. Therefore, the current flowing from the data line DL to the sensing line SSL may be detected by the turned-on sensing transistor ST. The detected current (hereinafter, referred to as the sensing current) may be supplied to the detector through the sensing line SSL. The detector may determine whether the second main transistor MT2 is defective based on the supplied sensing current. For example, the detector may convert the sensing current supplied by the sensing line SSL into a voltage (e.g., a sensing voltage Vs), compare the sensing voltage Vs with a preset determination voltage, and determine whether the second main transistor MT2 is defective based on the comparison result. For example, when it is confirmed that the sensing voltage Vs is within a predetermined normal range of the determination voltage as a result of the comparison, the detector may determine that there is no abnormality in the second main transistor MT2. For a specific example, the determination voltage may have a lower limit voltage and an upper limit voltage, and when the sensing voltage Vs is higher than or equal to the lower limit voltage of the determination voltage and lower than or equal to the upper limit voltage of the determination voltage, the detector may determine that the second main transistor MT2 is normal. On the other hand, when the sensing voltage Vs is not within the normal range of the determination voltage as a result of the comparison, the detector may determine that the second main transistor MT2 is abnormal. For a specific example, when the sensing voltage Vs is lower than the lower limit voltage of the determination voltage or higher than the upper limit voltage of the determination voltage, the detector may determine that the second main transistor MT2 is abnormal. In other words, the detector may determine that the second main transistor MT2 is a defective transistor.

[0351] In one embodiment, in order to perform a defect inspection of the third main transistor MT3, for example, another sensing transistor (hereinafter, referred to as a second sensing transistor) may be connected between the second node N2 and another sensing line (hereinafter, referred to as a second sensing line). For example, a gate electrode of the second sensing transistor may be connected to the third gate line GL3, a source electrode of the second sensing transistor may be connected to the second node N2, and a drain electrode of the second sensing transistor may be connected to the second sensing line.

[0352] On the other hand, after the defect inspection of the main transistor, it is possible to perform Figures 13 to 17 However, if there is no abnormality in the main transistor, the above repair process can be omitted.

[0353] After the repair process or defect inspection process, Fig. 22 The sensing transistor ST can be constantly maintained in the off state. As an example of this, the third gate signal GS3 of the third gate line GL3 connected to the gate electrode of the sensing transistor ST can be maintained at a non-effective level regardless of the period. In other words, the third gate signal GS3 can be a DC signal with a level that can turn off the sensing transistor ST.

[0354] In addition, after the repair process or the defect inspection process, the data voltage Vdt may be applied to Fig. 22 After the repair process or defect inspection process, Figure 6 The signals shown in the figure can be applied to Fig. 22 In other words, after the repair process or defect inspection process, Fig. 22 The pixel circuit PC can be based on Figure 6 The signal and timing diagrams of the

[0355] Fig.23 is a plan view of a display device according to an embodiment.

[0356] like Fig.23 As shown in , the display device may include a plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6. The plurality of pixels PX1, PX2, PX3, PX4, PX5, and PX6 may be arranged in a first direction DR1 and a second direction DR2.

[0357] Each pixel may include six transistor regions arranged in three rows and two columns. For example, the first pixel PX1 may include a first-first transistor region A1-1, a first-second transistor region A1-2, a second-first transistor region A2-1, a second-second transistor region A2-2, a third-first transistor region A3-1, and a third-second transistor region A3-2 arranged in three rows and two columns.

[0358] The first main transistor MT1 may be disposed in a first-first transistor region A1 - 1 corresponding to a first column of a first row.

[0359] The second main transistor MT2 may be disposed in the third-second transistor region A3 - 2 corresponding to the second column of the third row.

[0360] The third main transistor MT3 may be disposed in the second-second transistor region A2 - 2 corresponding to the second column of the second row.

[0361] The fourth main transistor MT4 may be disposed in the second-first transistor region A2 - 1 corresponding to the first column of the second row.

[0362] The second auxiliary transistor AT2 may be disposed in the third-first transistor region A3 - 1 corresponding to the first column of the third row.

[0363] The sensing transistor ST may be disposed in the first-second transistor region A1 - 2 corresponding to the second column of the first row.

[0364] When a region including the first-first transistor region A1-1, the second-first transistor region A2-1, the second-second transistor region A2-2, and the third-second transistor region A3-2 is defined as a main transistor region MTA, the main transistor region MTA may have a bent shape.

[0365] The first-second transistor region A1 - 2 may be a sensing transistor region STA, and the third-first transistor region A3 - 1 may be an auxiliary transistor region ATA.

[0366] Fig.24 is an exemplary diagram showing a virtual reality device including a display device according to an embodiment. Fig.24 FIG. 1 shows a virtual reality device 1 to which a display device 10_1 according to an embodiment is applied. Here, the display device 10_1 may be, for example, a device including the above-mentioned Figures 1 to 23 A display device of a component.

[0367] Reference Fig.24 The virtual reality device 1 according to one embodiment may be a glass type device. The virtual reality device 1 according to one embodiment may include a display device 10_1, a left lens 10a, a right lens 10b, a support frame 20, temples 30a and 30b, a reflective member 40, and a display device housing 50.

[0368] although Fig.24 The virtual reality device 1 including the temples 30a and 30b is shown, but the virtual reality device 1 according to one embodiment can be applied to a head mounted display including a headband that can be worn on the head instead of the temples 30a and 30b. That is, the virtual reality device 1 according to one embodiment is not limited to Fig.24 The virtual reality device shown in the figure can be applied to various electronic devices in various forms.

[0369] The display device housing 50 can accommodate the display device 10_1 and the reflective member 40. The image displayed on the display device 10_1 can be reflected by the reflective member 40 and provided to the right eye of the user through the right lens 10b. Therefore, the user can watch the virtual reality image displayed on the display device 10_1 through the right eye.

[0370] although Fig.24 The display device housing 50 is shown to be disposed at the right end of the supporting frame 20, but the embodiments of the present specification are not limited thereto. For example, the display device housing 50 may be disposed at the left end of the supporting frame 20, and in this case, the image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the user's left eye through the left lens 10a. Therefore, the user may view the virtual reality image displayed on the display device 10_1 through the left eye. Alternatively, the display device housing 50 may be disposed at both the left and right ends of the supporting frame 20. In this case, the user may view the virtual reality image displayed on the display device 10_1 through both the left and right eyes.

[0371] Fig.25 and Fig.26 : is an exemplary view showing a head mounted display device to which a display device according to one embodiment is applied.

[0372] Reference Fig.25 and Fig.26 According to one embodiment, the display device 10_2 may be applied to a head mounted display. The first display device 1100 provides an image to the right eye of the user, and the second display device 1200 provides an image to the left eye of the user. Here, the display device 10_2 may be, for example, a display device including the above Figures 1 to 23 A display device of a component.

[0373] The first lens array 1310 may be disposed between the first display device 1100 and the housing cover 1700. The first lens array 1310 may include a plurality of lenses 1311. The plurality of lenses 1311 may be formed as convex lenses convex in a direction toward the housing cover 1700.

[0374] The second lens array 1410 may be disposed between the second display device 1200 and the housing cover 1700. The second lens array 1410 may include a plurality of lenses 1411. The plurality of lenses 1411 may be formed as convex lenses convex in a direction toward the housing cover 1700.

[0375] The display panel housing 1600 is used to accommodate the first display device 1100, the second display device 1200, the first lens array 1310 and the second lens array 1410. One surface of the display panel housing 1600 may be opened to accommodate the first display device 1100, the second display device 1200, the first lens array 1310 and the second lens array 1410.

[0376] The housing cover 1700 is provided to cover the opening surface of the display panel housing 1600. The housing cover 1700 may include a first opening 1710 where the left eye of the user is located and a second opening 1720 where the right eye of the user is located. Fig.25 and Fig.26 It is shown that the first opening 1710 and the second opening 1720 are formed in a rectangular shape, but the present disclosure is not limited thereto. The first opening 1710 and the second opening 1720 may be formed in a circular shape or an elliptical shape. Alternatively, the first opening 1710 and the second opening 1720 may be combined to form one opening.

[0377] The second opening 1720 may be aligned with the first display device 1100 and the first lens array 1310, and the first opening 1710 may be aligned with the second display device 1200 and the second lens array 1410. Therefore, the user may view the image of the first display device 1100 as a virtual image magnified by the first lens array 1310 through the second opening 1720, and view the image of the second display device 1200 as a virtual image magnified by the second lens array 1410 through the first opening 1710.

[0378] The headband 1800 is used to fix the display panel housing 1600 to the user's head so that the first opening 1710 and the second opening 1720 of the housing cover 1700 are respectively located in front of the user's left eye and right eye. The headband 1800 can be connected to the top surface, left surface and right surface of the display panel housing 1600.

[0379] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the inventive concept. Therefore, the disclosed preferred embodiments of the inventive concept are used only in a general and descriptive sense, and not for the purpose of limitation.

Claims

1. A display device, comprising: A pixel including a light emitting element and a pixel circuit connected to the light emitting element; as well as signal lines, connected to the pixels, Wherein, the signal line includes a gate line, an emission line and a data line, and Among them, the pixel circuit includes: a first main transistor, connected between a driving voltage line and an anode electrode of the light-emitting element; a second main transistor, connected between the data line and a gate electrode of the first main transistor; a third main transistor, connected between the driving voltage line and a source electrode of the first main transistor; a fourth main transistor, connected between a drain electrode of the first main transistor and an initialization line; and at least one auxiliary transistor, arranged to be adjacent to at least one main transistor among the first to fourth main transistors, a gate electrode, a source electrode and a drain electrode of the at least one auxiliary transistor having a floating state.

2. The display device according to claim 1, wherein: The at least one auxiliary transistor is disposed adjacent to a corresponding main transistor.

3. The display device according to claim 1, wherein: The at least one auxiliary transistor includes a second auxiliary transistor disposed adjacent to the second main transistor and a third auxiliary transistor disposed adjacent to the third main transistor.

4. The display device according to claim 1, wherein: The at least one auxiliary transistor is connected to the at least one main transistor among the first to fourth main transistors.

5. The display device according to claim 4, wherein: When the at least one auxiliary transistor is connected to the at least one main transistor among the first to fourth main transistors, a source electrode and a drain electrode of the at least one main transistor corresponding to the at least one auxiliary transistor have a floating state.

6. The display device according to claim 5, wherein: A gate electrode of the at least one main transistor corresponding to the at least one auxiliary transistor is connected to one of a node of the pixel circuit and the signal line.

7. The display device according to claim 1, further comprising: a gate connection electrode connected to the gate electrode of the at least one auxiliary transistor; as well as a gate extension electrode disposed at a different layer from the gate connection electrode and connected to the gate connection electrode, Wherein, the short-circuit repairing portion of the gate extension electrode overlaps with the short-circuit repairing portion of the gate line.

8. The display device according to claim 7, wherein: The gate extension electrode is disposed on the gate connection electrode and the gate line.

9. The display device according to claim 7, wherein: The repairing short-circuit portion of the gate extension electrode and the repairing short-circuit portion of the gate line contact each other.

10. The display device according to claim 7, wherein: A gate electrode of the at least one main transistor corresponding to the at least one auxiliary transistor is connected to the gate line.

11. The display device according to claim 1, further comprising: a first source connection electrode connected to the source electrode of the at least one auxiliary transistor; as well as a source extension electrode disposed on a different layer from the first source connection electrode and connected to the first source connection electrode, The short-circuit repairing portion of the source extension electrode overlaps with the short-circuit repairing portion of the second source connection electrode connected to the data line.

12. The display device according to claim 11, wherein: The source extension electrode is disposed on the first source connection electrode and the second source connection electrode, and is disposed on the same layer as the data line.

13. The display device according to claim 11, wherein: The short-circuit repairing portion of the source extension electrode contacts the short-circuit repairing portion of the second source connection electrode.

14. The display device according to claim 11, wherein: A source electrode of the at least one main transistor corresponding to the at least one auxiliary transistor is connected to the second source connection electrode.

15. The display device according to claim 14, wherein: The second source connection electrode is disconnected so that the data line and the source electrode of the at least one main transistor are separated.

16. The display device according to claim 15, wherein: The disconnected portion of the second source connection electrode does not overlap with the overlapping portion between the repaired short-circuited portion of the source extension electrode and the repaired short-circuited portion of the second source connection electrode.

17. The display device according to claim 1, further comprising: a drain connection electrode connected to the drain electrode of the at least one auxiliary transistor; as well as a gate / drain connection electrode disposed at a different layer from the drain connection electrode, Wherein, the short-circuit repairing portion of the gate / drain connecting electrode overlaps with the short-circuit repairing portion of the drain connecting electrode.

18. The display device according to claim 17, wherein: The gate / drain connection electrode is disposed on the drain connection electrode.

19. The display device according to claim 17, wherein: The repairing short-circuit portion of the gate / drain connection electrode and the repairing short-circuit portion of the drain connection electrode contact each other.

20. The display device according to claim 17, wherein: A drain electrode of the at least one main transistor corresponding to the at least one auxiliary transistor is connected to the gate / drain connection electrode.

21. The display device according to claim 20, wherein: A drain connection electrode connected to the drain electrode of the at least one main transistor is disconnected so that the gate / drain connection electrode and the drain electrode of the at least one main transistor are separated.

22. The display device according to claim 21, wherein: The disconnected portion of the drain connecting electrode connected to the drain electrode of the at least one main transistor overlaps with the overlapping portion between the repaired short-circuit portion of the gate / drain connecting electrode and the repaired short-circuit portion of the drain connecting electrode connected to the drain electrode of the at least one auxiliary transistor.

23. The display device according to claim 1, further comprising: a gate connection electrode connected to the gate electrode of the at least one auxiliary transistor; as well as a gate extension electrode disposed at a different layer from the gate connection electrode and connected to the emission line, Wherein, the short-circuit repairing portion of the gate extension electrode overlaps with the short-circuit repairing portion of the gate line.

24. The display device according to claim 23, wherein: The gate extension electrode is disposed on the gate connection electrode and the gate line.

25. The display device according to claim 23, wherein: The repairing short-circuit portion of the gate extension electrode and the repairing short-circuit portion of the gate line contact each other.

26. The display device according to claim 23, wherein: A gate electrode of the at least one main transistor corresponding to the at least one auxiliary transistor is connected to the emission line.

27. The display device according to claim 1, further comprising a source connection electrode connected to a source electrode of the at least one auxiliary transistor, in, The driving voltage line includes a lower driving voltage line and an upper driving voltage line connected to each other, Wherein, the upper driving voltage line and the source connecting electrode are arranged at different layers, and Wherein, the repaired short-circuit portion of the upper driving voltage line overlaps with the repaired short-circuit portion of the source connecting electrode.

28. The display device according to claim 27, wherein: The upper driving voltage line is disposed on the source connecting electrode.

29. The display device according to claim 27, wherein: The repairing short portion of the upper driving voltage line and the repairing short portion of the source connection electrode contact each other.

30. The display device according to claim 27, wherein: A source electrode of the at least one main transistor corresponding to the at least one auxiliary transistor is connected to the lower driving voltage line.

31. The display device according to claim 30, wherein: The lower driving voltage line is disconnected so that the lower driving voltage line and the source electrode of the at least one main transistor are separated.

32. The display device according to claim 31, wherein: The disconnected portion of the lower driving voltage line does not overlap an overlapping portion between the repairing short-circuited portion of the upper driving voltage line and the repairing short-circuited portion of the source connection electrode.

33. The display device according to claim 1, further comprising: a drain connection electrode connected to the drain electrode of the at least one auxiliary transistor; as well as a source / drain connection electrode disposed on a different layer from the drain connection electrode, Wherein, the short-circuit repairing portion of the source / drain connecting electrode overlaps with the short-circuit repairing portion of the drain connecting electrode.

34. The display device according to claim 33, wherein: The source / drain connection electrode is disposed on the drain connection electrode.

35. The display device according to claim 33, wherein: The repairing short portion of the source / drain connection electrode and the repairing short portion of the drain connection electrode contact each other.

36. The display device according to claim 33, wherein: A drain electrode of the at least one main transistor corresponding to the at least one auxiliary transistor is connected to the source / drain connection electrode.

37. The display device according to claim 36, wherein: A drain connection electrode connected to the drain electrode of the at least one main transistor is disconnected so that the source / drain connection electrode and the drain electrode of the at least one main transistor are separated.

38. The display device according to claim 37, wherein: The disconnected portion of the drain connecting electrode connected to the drain electrode of the at least one main transistor overlaps with the overlapping portion between the repaired short-circuit portion of the source / drain connecting electrode and the repaired short-circuit portion of the drain connecting electrode connected to the drain electrode of the at least one auxiliary transistor.

39. The display device according to claim 1, wherein: The at least one auxiliary transistor includes at least one of a second auxiliary transistor corresponding to the second main transistor and a third auxiliary transistor corresponding to the third main transistor.

40. The display device according to claim 39, wherein: The pixel includes a first-first transistor region, a first-second transistor region, a second-first transistor region, a second-second transistor region, a third-first transistor region, and a third-second transistor region arranged in three rows and two columns.

41. The display device according to claim 40, wherein: The first main transistor is arranged in the first-first transistor region corresponding to the first column of the first row, the second main transistor is arranged in the third-second transistor region corresponding to the second column of the third row, the third main transistor is arranged in the second-second transistor region corresponding to the second column of the second row, the fourth main transistor is arranged in the second-first transistor region corresponding to the first column of the second row, the second auxiliary transistor is arranged in the third-first transistor region corresponding to the first column of the third row, and the third auxiliary transistor is arranged in the first-second transistor region corresponding to the second column of the first row.

42. The display device according to claim 40, wherein: In the pixel, the first main transistor is arranged in the first-first transistor region corresponding to the first column of the first row, the second main transistor is arranged in the third-second transistor region corresponding to the second column of the third row, the third main transistor is arranged in the second-second transistor region corresponding to the second column of the second row, the fourth main transistor is arranged in the second-first transistor region corresponding to the first column of the second row, the second auxiliary transistor is arranged in the third-first transistor region corresponding to the first column of the third row, and the third auxiliary transistor is arranged in the first-second transistor region corresponding to the second column of the first row, and Wherein, in a second pixel set to be adjacent to the pixel, a first main transistor is set in a first-second transistor region corresponding to the second column of the first row, a second main transistor is set in a third-first transistor region corresponding to the first column of the third row, a third main transistor is set in a second-first transistor region corresponding to the first column of the second row, a fourth main transistor is set in a second-second transistor region corresponding to the second column of the second row, a second auxiliary transistor is set in the third-second transistor region corresponding to the second column of the third row, and a third auxiliary transistor is set in the first-first transistor region corresponding to the first column of the first row.

43. The display device according to claim 40, wherein: The first main transistor is arranged in the third-first transistor region corresponding to the first column of the third row, the second main transistor is arranged in the second-first transistor region corresponding to the first column of the second row, the third main transistor is arranged in the second-second transistor region corresponding to the second column of the second row, the fourth main transistor is arranged in the third-second transistor region corresponding to the second column of the third row, the second auxiliary transistor is arranged in the first-first transistor region corresponding to the first column of the first row, and the third auxiliary transistor is arranged in the first-second transistor region corresponding to the second column of the first row.

44. The display device according to claim 40, wherein: The first main transistor is arranged in the first-second transistor region corresponding to the second column of the first row, the second main transistor is arranged in the second-second transistor region corresponding to the second column of the second row, the third main transistor is arranged in the second-first transistor region corresponding to the first column of the second row, the fourth main transistor is arranged in the first-first transistor region corresponding to the first column of the first row, the second auxiliary transistor is arranged in the third-second transistor region corresponding to the second column of the third row, and the third auxiliary transistor is arranged in the third-first transistor region corresponding to the first column of the third row.

45. The display device according to claim 40, wherein: The first main transistor is arranged in the first-first transistor region corresponding to the first column of the first row, the second main transistor is arranged in the first-second transistor region corresponding to the second column of the first row, the third main transistor is arranged in the third-first transistor region corresponding to the first column of the third row, the fourth main transistor is arranged in the third-second transistor region corresponding to the second column of the third row, the second auxiliary transistor is arranged in the second-second transistor region corresponding to the second column of the second row, and the third auxiliary transistor is arranged in the second-first transistor region corresponding to the first column of the second row.

46. ​​The display device according to claim 40, further comprising: A sensing line connected to the pixel; as well as A sensing transistor is provided in the pixel circuit and connected between the sensing line and the gate electrode of the first main transistor.

47. The display device according to claim 46, wherein: The first main transistor is arranged in the first-first transistor region corresponding to the first column of the first row, the second main transistor is arranged in the third-second transistor region corresponding to the second column of the third row, the third main transistor is arranged in the second-second transistor region corresponding to the second column of the second row, the fourth main transistor is arranged in the second-first transistor region corresponding to the first column of the second row, the second auxiliary transistor is arranged in the third-first transistor region corresponding to the first column of the third row, and the sensing transistor is arranged in the first-second transistor region corresponding to the second column of the first row.

48. The display device according to claim 1, further comprising: a first capacitor connected between the gate electrode of the first main transistor and the anode electrode of the light emitting element; as well as A second capacitor is connected between the gate electrode of the first main transistor and the source electrode of the first main transistor.

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