Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of determining whether a pixel is defective. According to an embodiment of the present disclosure, a display device includes a light emitting element, a driving transistor connected between a driving voltage line and an anode of the light emitting element, and a fifth transistor connected between the anode of the light emitting element and a sensing line, in which the fifth transistor always remains off during normal operation of the display device.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0092568 filed in the Korean Intellectual Property Office on July 17, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device capable of determining whether a pixel is defective. Background Art

[0003] An organic light emitting display device includes a display element having brightness that varies according to current, for example, an organic light emitting diode. Summary of the invention

[0004] The display device according to the embodiments described in the present disclosure can determine whether a pixel is defective. However, the embodiments according to the present disclosure are not limited to the specific examples set forth herein. By referring to the detailed description given below, the features and aspects of the present disclosure will become more clear to those of ordinary skill in the art to which the present disclosure belongs.

[0005] According to an embodiment of the present disclosure, a display device may include a light emitting element, a driving transistor connected between a driving voltage line and an anode of the light emitting element, and a fifth transistor connected between the anode of the light emitting element and a sensing line, wherein the fifth transistor is always turned off. Specifically, the fifth transistor may always be turned off during normal operation of the display device and is turned on only when a defective pixel in the display device is tested (e.g., during manufacture or testing of the display device).

[0006] In an embodiment, the display device may also include a second transistor connected between the data line and the gate electrode of the driving transistor, a third transistor connected between the driving voltage line and the source electrode of the driving transistor, a fourth transistor connected between the initialization line and the anode of the light-emitting element, a first capacitor connected between the gate electrode of the driving transistor and the source electrode of the driving transistor, and a second capacitor connected between the gate electrode of the driving transistor and the anode of the light-emitting element.

[0007] In an embodiment, the display device may further include a first gate line connected to the gate electrode of the second transistor, an emitter line connected to the gate electrode of the third transistor, a second gate line connected to the gate electrode of the fourth transistor, and a third gate line connected to the gate electrode of the fifth transistor.

[0008] In an implementation, the third gate signal of the third gate line has a non-active level.

[0009] In an embodiment, in an initialization / write period, an emission signal of the emission line, a first gate signal of the first gate line, and a second gate signal of the second gate line each have a valid level, while a third gate signal of the third gate line has a non-valid level, wherein, in a compensation period, the first gate signal and the second gate signal each have a valid level, while the emission signal and the third gate signal each have a non-valid level, wherein, in a bypass period, the emission signal and the second gate signal each have a valid level, while the first gate signal and the third gate signal each have a non-valid level, and wherein, in an emission period, the emission signal has a valid level, while the first gate signal, the second gate signal, and the third gate signal each have a non-valid level.

[0010] In an embodiment, a previous data voltage is applied to the data line in the initialization / write period and the compensation period, wherein a current data voltage is applied to the data line in the emission period, and wherein a transient data voltage converted from the previous data voltage to the current data voltage is applied to the data line in the bypass period.

[0011] In an implementation, the display device may further include a detector or a power supply unit connected to the sensing line.

[0012] According to an embodiment of the present disclosure, a display device includes a light-emitting element, a driving transistor connected between a driving voltage line and an anode of the light-emitting element, a second transistor connected between a data line and a gate electrode of the driving transistor, a third transistor connected between the driving voltage line and a source electrode of the driving transistor, and a fourth transistor connected between an initialization / sensing line and the anode of the light-emitting element.

[0013] In an embodiment, the display device may further include a first capacitor connected between a gate electrode of the driving transistor and a source electrode of the driving transistor, and a second capacitor connected between the gate electrode of the driving transistor and an anode of the light emitting element.

[0014] In an implementation, the display device may further include a first gate line connected to the gate electrode of the second transistor, an emitter line connected to the gate electrode of the third transistor, and a second gate line connected to the gate electrode of the fourth transistor.

[0015] In an embodiment, in an initialization / writing period, an emission signal of an emission line, a first gate signal of a first gate line, and a second gate signal of a second gate line each have a valid level, wherein, in a compensation period, the emission signal has a non-valid level and the first gate signal and the second gate signal each have a valid level, wherein, in a bypass period, the emission signal and the second gate signal each have a valid level and the first gate signal has a non-valid level, and wherein, in an emission period, the emission signal has a valid level and the first gate signal and the second gate signal each have a non-valid level.

[0016] In an embodiment, a previous data voltage is applied to the data line in the initialization / write period and the compensation period, wherein a current data voltage is applied to the data line in the emission period, and wherein a transient data voltage converted from the previous data voltage to the current data voltage is applied to the data line in the bypass period.

[0017] According to an embodiment of the present disclosure, a display device may include a light-emitting element, a driving transistor connected between a driving voltage line and an anode of the light-emitting element, a first capacitor including a first electrode connected to a gate electrode of the driving transistor, a second transistor connected between a data line and a second electrode of the first capacitor, and a fifth transistor connected between the anode of the light-emitting element and a sensing line, wherein the fifth transistor is always kept off.

[0018] In an embodiment, the display device may also include a sixth transistor connected between the gate electrode of the driving transistor and the drain electrode of the driving transistor, a seventh transistor connected between the drain electrode of the driving transistor and the anode of the light-emitting element, a fourth transistor connected between the initialization line and the anode of the light-emitting element, a third transistor connected between the driving voltage line and the source electrode of the driving transistor, and a second capacitor connected between the driving voltage line and the gate electrode of the driving transistor.

[0019] In an embodiment, the display device may further include a first gate line connected to the gate electrode of the second transistor, a second gate line connected to the gate electrode of the fourth transistor, an emission line connected to the gate electrode of the third transistor and the gate electrode of the seventh transistor, a third gate line connected to the gate electrode of the fifth transistor, and a fourth gate line connected to the gate electrode of the sixth transistor.

[0020] In an implementation, the third gate signal of the third gate line has a non-active level.

[0021] In an implementation, the display device may further include a detector connected to the sensing line.

[0022] According to an embodiment of the present disclosure, a display device may include a light-emitting element, a driving transistor connected between a driving voltage line and an anode of the light-emitting element, a second transistor connected between a data line and a gate electrode of the driving transistor, a third transistor connected between the driving voltage line and a source electrode of the driving transistor, a fourth transistor connected between an initialization line and the anode of the light-emitting element, and a fifth transistor connected between the anode of the light-emitting element and a sensing line.

[0023] In an embodiment, the display device may further include a first capacitor connected between a gate electrode of the driving transistor and a source electrode of the driving transistor, and a second capacitor connected between the gate electrode of the driving transistor and an anode of the light emitting element.

[0024] In an embodiment, the fifth transistor is always kept off.

[0025] In an implementation, the display device may further include a detector or a power supply unit connected to the sensing line.

[0026] According to an embodiment of the present disclosure, it is possible to receive a sensing voltage from a pixel through a sensing line and a transistor and determine whether the pixel is defective based on the sensing voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0028] Figure 1 is a perspective view showing a display device according to an embodiment of the present disclosure.

[0029] Figure 2 is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0030] Figure 3 is a plan view showing a display unit of a display device according to an embodiment of the present disclosure.

[0031] Figure 4 is a block diagram illustrating a display panel and a display driver according to an embodiment of the present disclosure.

[0032] Figure 5 is a plan view of a display device according to an embodiment of the present disclosure.

[0033] Figure 6 is a circuit diagram of a pixel of a display device according to an embodiment of the present disclosure.

[0034] Figure 7 It is shown Figure 6 A timing diagram of the first gate signal to the third gate signal, the emission signal, the reference voltage and the initialization voltage.

[0035] Figure 8 Shows Figure 6 The display device is Figure 7 Operations during the initialization period.

[0036] Fig. 9 Shows Figure 6 The display device is Figure 7 Operations during the sensing period.

[0037] Fig.10 Shows Figure 6 The display device is Figure 7 operation during the off period.

[0038] Fig.11 It is shown Figure 6 A timing diagram of the first gate signal to the third gate signal, the emission signal, the data voltage and the initialization voltage.

[0039] Fig.12 Shows Figure 6 The display device is Fig.11 Operations during the initialization / write period of .

[0040] Fig.13 Shows Figure 6 The display device is Fig.11 Operations during the compensation period.

[0041] Fig.14 Shows Figure 6 The display device is Fig.11 Operation during the bypass period.

[0042] Fig.15 Shows Figure 6 The display device is Fig.11 Operations during the transmission period.

[0043] Fig.16 is a circuit diagram of a pixel of a display device according to an embodiment of the present disclosure.

[0044] Fig.17 It is shown Fig.16 A timing diagram of a first gate signal, a second gate signal, an emission signal, a reference voltage and an initialization voltage.

[0045] Fig.18 The display device is shown in Fig.17 Operations during the initialization period.

[0046] Fig.19 The display device is shown in Fig.17 Operations during the sensing period.

[0047] Fig. 20 The display device is shown in Fig.17 operation during the off period.

[0048] Fig.21 is a circuit diagram of a pixel of a display device according to an embodiment of the present disclosure.

[0049] Fig. 22 It is shown Fig.21 A timing diagram of the first gate signal to the fourth gate signal, the emission signal, the reference voltage and the initialization voltage.

[0050] Fig.23 Shows Fig.21 The display device is Fig. 22 Operations during the initialization period.

[0051] Fig.24 Shows Fig.21 The display device is Fig. 22 Operations during the sensing period.

[0052] Fig.25 Shows Fig.21 The display device is Fig. 22 operation during the off period.

[0053] Fig.26 An example of a virtual reality device including a display device according to an embodiment is shown.

[0054] Fig. 27 and Fig.28 A perspective view and an exploded view are respectively shown of a head mounted display device using a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] The advantages and features of the present disclosure and the methods for achieving them will become apparent through the description of the embodiments hereinafter with reference to the accompanying drawings. However, the present disclosure is not limited to the specific embodiments disclosed herein, but can be implemented in various different ways. Some specific embodiments are described in detail to make the present disclosure detailed and to convey the scope of the present disclosure to those skilled in the art. It should be noted that the scope of the present disclosure is limited only by the claims.

[0056] As used herein, the phrase "element A on element B" means that element A may be directly disposed on element B and / or element A may be indirectly disposed on element B via another element C. Throughout the description, the same reference numerals denote the same elements. The figures, dimensions, proportions, angles, and numbers of elements given in the drawings are illustrative only and not limiting.

[0057] Although terms such as first, second, etc. are used to distinguish between elements, such terms are not necessarily intended to indicate the time or other priority of such elements. These terms are only used to distinguish one element from another element. Accordingly, as used herein, the first element may be the second element within the technical scope of the present disclosure.

[0058] The features of the various exemplary embodiments of the present disclosure may be combined in part or in whole. As will be clearly understood by those skilled in the art, various interactions and operations in technology are possible. The various embodiments disclosed herein may be practiced individually or in combination.

[0059] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0060] Figure 1 is a perspective view showing a display device according to an embodiment of the present disclosure.

[0061] Reference Figure 1 The display device 10 may be adopted by or located in a portable electronic device such as a mobile phone, a smart phone, a tablet PC, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigation device, or an ultra mobile PC (UMPC). The display device 10 may also be adopted by or located in a television, a laptop computer, a monitor, an electronic billboard, or an Internet of Things (IOT) device. In addition, the display device 10 may be adopted by or located in a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head-mounted display (HMD) device.

[0062] When viewed from the top, the display device 10 may have a shape similar to a quadrilateral shape. For example, the display device 10 may have a shape similar to a rectangle having short sides extending in the first direction DR1 and long sides extending in the second direction DR2. Corners where the short sides meet the long sides may be rounded with a predetermined curvature or may be right angles. The display device 10 when viewed from the top is not limited to a quadrilateral shape, but may have any shape, such as a shape similar to another polygonal shape, a circular shape, or an elliptical shape.

[0063] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , a touch driver 400 , and a power supply unit 500 .

[0064] The display panel 100 may include a main area MA and a sub area SBA.

[0065] The main area MA may include a display area DA having pixels for displaying an image and a non-display area NDA positioned around the display area DA. The display area DA may output light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel defining layer defining an emission area or an opening area, each area corresponding to a self-luminous element (LEL) connected to a pixel circuit including a switching element. The self-luminous element may include, for example, at least one of the following: an organic light emitting diode including an organic emission layer, a quantum dot light emitting diode (quantum LED) including a quantum dot emission layer, an inorganic light emitting diode (inorganic LED) including an inorganic semiconductor, and a micro light emitting diode (micro LED).

[0066] The non-display area NDA may be arranged on the outside or periphery of the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) that applies a gate signal to a gate line and a fan-out line (not shown) that connects the display driver 200 to the display area DA.

[0067] The sub-region SBA may extend from one side of the main region MA. The sub-region SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap with the main region MA in the thickness direction (e.g., the third direction DR3). The sub-region SBA may include a pad connected to the display driver 200 and the circuit board 300. Alternatively, the sub-region SBA may be removed, and the display driver 200 and the pad may be arranged in the non-display area NDA.

[0068] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to the data lines DL (see Figure 3 ). The display driver 200 may apply a power supply voltage to the voltage line and may supply a gate control signal to the gate driver. The display driver 200 may be implemented as an integrated circuit (IC) and may be attached to the display panel 100 using a chip on glass (COG) technology, a chip on plastic (COP) technology, or ultrasonic bonding. For example, the display driver 200 may be arranged in the sub-area SBA, and when the sub-area SBA is bent, the display driver 200 may overlap with the main area MA in the thickness direction (third direction DR3) or be located below the main area MA. As another example, the display driver 200 may be mounted on the circuit board 300.

[0069] The circuit board 300 may be attached to the pad area of ​​the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 may be electrically connected to the pads of the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB), a rigid printed circuit board (RPCB), or a flexible film such as a chip on film (COF).

[0070] The touch driver 400 may be mounted on the circuit board 300 .

[0071] The power supply unit 500 may be located on the circuit board 300 and connected to apply a power supply voltage to the display driver 200 and the display panel 100. More specifically, the power supply unit 500 may generate a driving voltage to supply the driving voltage to the driving voltage line VDL (see Figure 3 ), and a common voltage may be generated to supply the common voltage to a common electrode shared by light-emitting elements of a plurality of pixels. For example, the driving voltage may be a high-level voltage for driving the light-emitting element, and the common voltage may be a low-level voltage for driving the light-emitting element.

[0072] Figure 2 is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0073] Reference Figure 2 , the display panel 100 may include a display unit DU and a color filter layer CFL. The display unit DU may include a substrate SUB, a driver circuit layer DCL, an emission material layer EMTL, and an encapsulation layer ENC.

[0074] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate SUB may include a glass material or a metal material.

[0075] The driver circuit layer DCL may be arranged on the substrate SUB. The driver circuit layer DCL may include a plurality of transistors. The driver circuit layer DCL may include a gate line, a data line DL, a voltage line, a gate control line, a fan-out line for connecting the display driver 200 to the data line DL, and a lead for connecting the display driver 200 to a pad. Each of the transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of a non-display area NDA of the display panel 100, the gate driver may include a transistor formed in the driver circuit layer DCL.

[0076] The driver circuit layer DCL may be arranged in the display area DA, the non-display area NDA, and the sub-area SBA. The transistors, gate lines, data lines DL, and voltage lines of the pixels in the driver circuit layer DCL may be arranged in the display area DA. The gate control lines and fan-out lines in the driver circuit layer DCL may be arranged in the non-display area NDA. The leads of the driver circuit layer DCL may be arranged in the sub-area SBA.

[0077] The emission material layer EMTL may be arranged on the driver circuit layer DCL. The emission material layer EMTL may include a plurality of light emitting elements ED (see, for example, Figure 6 ). Each light emitting element ED may include a pixel electrode, an emission layer, and a common electrode sequentially stacked on each other to emit light. The emission material layer EMTL may also include a pixel defining layer for defining a light emitting area of ​​the pixel. A plurality of light emitting elements ED in the emission material layer EMTL may be arranged in the display area DA.

[0078] The emission layer may be, for example, an organic emission layer including an organic material. The emission layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the pixel electrode receives a voltage through a transistor of the driver circuit layer DCL and the common electrode receives a different voltage, holes and electrons may move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, so that the electrons and holes are recombined in the organic light emitting layer to emit light. For example, the pixel electrode may be an anode, and the common electrode may be a cathode. However, it should be understood that the present disclosure is not limited thereto.

[0079] As another example, the light emitting elements ED may include quantum dot light emitting diodes each including a quantum dot emission layer, inorganic light emitting diodes each including an inorganic semiconductor, or micro light emitting diodes.

[0080] The encapsulation layer ENC may cover the upper surface and the side surface of the emission material layer EMTL and may protect the emission material layer EMTL. The encapsulation layer ENC may include at least one inorganic layer and at least one organic layer for encapsulating the emission material layer EMTL.

[0081] The color filter layer CFL may be arranged on the encapsulation layer ENC. The color filter layer CFL may include a plurality of color filters respectively associated with a plurality of emission regions. Each of the color filters may selectively transmit light of a specific wavelength or in a specific wavelength band and block or absorb light of other wavelengths. The color filter layer CFL may absorb some of the light introduced from the outside of the display device 10 to reduce the reflection of the external light. Accordingly, the color filter layer CFL can prevent the distortion of the color caused by the reflection of the external light.

[0082] The sub-area SBA of the display panel 100 may extend from one side or edge of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or rolled. For example, when the sub-area SBA is bent, as shown in FIG. Figure 2 As shown in , the sub-area SBA may overlap the main area MA in the thickness direction (third direction DR3 ). The sub-area SBA may include a pad electrically connected to the display driver 200 and the circuit board 300 .

[0083] When the sub-area SBA is bent, as Figure 2 As shown in FIG. 8 , a protection layer 800 may be further disposed on the bent portion of the sub-area SBA.

[0084] Figure 3 is a plan view showing a display unit of a display device according to an embodiment of the present disclosure. Figure 4 is a block diagram showing a display panel and a display driver according to an embodiment.

[0085] Reference Figure 3 and Figure 4 , the display panel 100 may include a display area DA and a non-display area NDA.

[0086] The display area DA may include a plurality of pixels PX and a plurality of signal transmission lines connected to the plurality of pixels PX. The plurality of signal transmission lines may include a plurality of gate lines GL, a plurality of emission lines EML, a plurality of data lines DL, a plurality of sensing lines SSL, a plurality of driving voltage lines VDL, and a plurality of common voltage lines VSL (see Figure 6 ). A plurality of fan-out lines FL may be connected to some of the above-mentioned lines.

[0087] Each of the plurality of pixels PX may be connected to a gate line GL, a data line DL, a sensing line SSL, an emission line EML, a driving voltage line VDL, and a common voltage line VSL. Each of the plurality of pixels PX may include at least one transistor, a light emitting element ED (see Figure 6 ) and capacitors.

[0088] The gate lines GL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 crossing the first direction DR1. The gate lines GL may be arranged along the second direction DR2. The gate lines GL may sequentially supply gate signals to the plurality of pixels PX.

[0089] The emission lines EML may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. Thus, the emission lines EML may be arranged along the second direction DR2. The emission lines EML may transmit the emission signals EM (see Figure 6 ) are sequentially supplied to the pixels PX.

[0090] The data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. Therefore, the data lines DL may be arranged in the first direction DR1. The data lines DL may supply a data voltage to the pixels PX. The data voltage may determine the brightness of each of the plurality of pixels PX.

[0091] The sensing lines SSL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. Therefore, the sensing lines SSL may be arranged or distributed along the first direction DR1. One sensing line SSL may be commonly connected to pixels PX arranged in a column extending in the second direction DR2. A plurality of sensing lines SSL may be respectively connected to a plurality of columns of pixels PX. For example, the pixels PX in the first column may be commonly connected to a first sensing line, the pixels PX in the second column may be commonly connected to a second sensing line, and the pixels PX in the third column may be commonly connected to a third sensing line. The sensing lines SSL may not be connected to each other. The sensing lines SSL may transmit a sensing voltage Vs (see Figure 6 ) is provided to the detector 230. To this end, a sensing line SSL may be connected to the detector 230.

[0092] The driving voltage lines VDL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. Therefore, the driving voltage lines VDL may be arranged in the first direction DR1. The driving voltage lines VDL may supply one or more driving voltages to the pixels PX. The driving voltage may be a high level voltage for driving the light emitting elements ED of the pixels PX.

[0093] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 610, an emission control driver 620, a fan-out line FL, a first gate control line GSL1, and a second gate control line GSL2.

[0094] The fan-out line FL may extend to the display area DA from the display driver 200. The fan-out line FL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0095] The first gate control line GSL1 may extend from the display driver 200 to the gate driver 610. The first gate control line GSL1 may supply the gate control signal GCS from the display driver 200 to the gate driver 610.

[0096] The second gate control line GSL2 may extend from the display driver 200 to the emission control driver 620. The second gate control line GSL2 may supply the emission control signal ECS from the display driver 200 to the emission control driver 620.

[0097] The sub-area SBA may extend from one side or edge of the non-display area NDA. The sub-area SBA may include a display driver 200 and a pad DP. The pad DP may be arranged closer to one edge of the sub-area SBA than the display driver 200. The pad DP may be electrically connected to the circuit board 300 through an anisotropic conductive film (ACF).

[0098] The display driver 200 may include Figure 4 The timing controller 210 and the data driver 220 are shown in FIG.

[0099] The timing controller 210 may receive the digital video data signal DATA and the timing signal from the circuit board 300. Based on the timing signal, the timing controller 210 may generate the data control signal DCS to control the operation timing of the data driver 220, may generate the gate control signal GCS to control the operation timing of the gate driver 610, and may generate the emission control signal ECS to control the operation timing of the emission control driver 620. The timing controller 210 may supply the gate control signal GCS to the gate driver 610 through the first gate control line GSL1. The timing controller 210 may supply the emission control signal ECS to the emission control driver 620 through the second gate control line GSL2. The timing controller 210 may supply the digital video data signal DATA and the data control signal DCS to the data driver 220.

[0100] The data driver 220 may convert the digital video data signals DATA into analog data voltages and may supply them to the data lines DL through the fan-out lines FL. The gate signals from the gate driver 610 may be used to select the pixels PX to which the data voltages are applied, and the selected pixels PX may receive the data voltages through the data lines DL.

[0101] The detector 230 may detect a sensing voltage Vs from the pixel PX through the sensing line SSL. For example, the detector 230 may convert a sensing current supplied through the sensing line SSL into a voltage (e.g., a sensing voltage Vs), may compare the sensing voltage Vs with a predetermined standard voltage, and may determine whether the pixel PX is defective based on the comparison result.

[0102] The power supply unit 500 may be disposed on the circuit board 300 to supply power to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage and supply the driving voltage to the driving voltage line VDL, and may generate a common voltage and supply the common voltage to a common electrode shared by the light emitting elements ED of the pixels PX.

[0103] The gate driver 610 may be arranged on one outer side of the display area DA or on one side of the non-display area NDA, and the emission control driver 620 may be arranged on the opposite outer side of the display area DA or on the opposite side of the non-display area NDA. However, it should be understood that the present disclosure is not limited thereto. As another example, both the gate driver 610 and the emission control driver 620 may be located on one side of the non-display area NDA.

[0104] The gate driver 610 may include a plurality of thin film transistors for generating gate signals based on the gate control signal GCS. For example, the transistors of the gate driver 610 and the transistors of the emission control driver 620 may be formed on the same layer as the transistors of the pixel PX. The gate driver 610 may provide the gate signal to the gate line GL, and the emission control driver 620 may provide the emission signal EM to the emission line EML.

[0105] Figure 5 is a plan view of a portion of a display device according to an embodiment of the present disclosure.

[0106] Reference Figure 5 , for example, pixels PX in a first column CL1 may be commonly connected to a first sensing line SSL1 , pixels PX in a second column CL2 may be commonly connected to a second sensing line SSL2 , and pixels PX in a third column CL3 may be commonly connected to a third sensing line SSL3 .

[0107] The pixels PX in the first column CL1 may provide light of a first color, the pixels PX in the second column CL2 may provide light of a second color, and the pixels PX in the third column CL3 may provide light of a third color. In this article, the first color may be one of red, blue, and green. The second color may be one of red, blue, and green and may be different from the first color. The third color may be one of red, blue, and green and may be different from the first color and the second color.

[0108] The first, second, and third sensing lines SSL1, SSL2, and SSL3 may be disconnected from each other.

[0109] The pixels PX in the first column CL1 may also be commonly connected to the first data line DL1 , the pixels PX in the second column CL2 may be commonly connected to the second data line DL2 , and the pixels PX in the third column CL3 may be commonly connected to the third data line DL3 .

[0110] Pixels PX in the same row, for example, pixels PX arranged along the first direction DR1 may be commonly connected to the first gate line GL1 , the second gate line GL2 , the third gate line GL3 , and the emission line EML for the row.

[0111] Figure 6is a circuit diagram of a pixel of a display device according to an embodiment of the present disclosure.

[0112] like Figure 6 As shown in FIG. 1 , the pixel PX may be connected to a first gate line GL1, a second gate line GL2, a third gate line GL3, a sensing line SSL, an initialization line VIL, an emission line EML, a data line DL, a driving voltage line VDL, and a common voltage line VSL. The common voltage line VSL may be connected to a common electrode (e.g., a cathode) of the light emitting element ED.

[0113] The pixel PX may include a pixel circuit PC and a light emitting element ED. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1 and a second capacitor C2.

[0114] The first transistor T1 (e.g., a driving transistor) may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 may control a source-drain current (hereinafter referred to as a driving current) according to a data voltage applied to the gate electrode. The driving current (e.g., Isd) flowing through the channel region of the first transistor T1 may be proportional to the square of the difference between the threshold voltage Vth of the first transistor T1 and the voltage Vsg between the source electrode and the gate electrode of the first transistor T1, for example, Isd=k×(Vsg-Vth) 2 , wherein k represents a proportionality coefficient determined by the structure and physical properties of the first transistor T1, Vsg represents a source-gate voltage of the first transistor T1, and Vth represents a threshold voltage of the first transistor T1. A gate electrode of the first transistor ST1 may be connected to the first node N1, a source electrode of the first transistor T1 may be connected to the second node N2, and a drain electrode of the first transistor T1 may be connected to the third node N3.

[0115] The light emitting element ED may receive a driving current to emit light. The amount or brightness of light emitted from the light emitting element ED may be proportional to the size of the driving current or otherwise depend on the size of the driving current. The light emitting element ED may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer arranged between the first electrode and the second electrode. Alternatively, the light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor arranged between the first electrode and the second electrode. Alternatively, the light emitting element ED may be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot emission layer located between the first electrode and the second electrode. As another example, the light emitting element ED may be a micro light emitting diode. The first electrode of the light emitting element ED may be electrically connected to the third node N3. The second electrode of the light emitting element ED may be connected to the common voltage line VSL. The second electrode of the light emitting element ED may receive a common voltage ELVSS (e.g., a low level voltage) from the common voltage line VSL.

[0116] The second transistor T2 may be turned on by the first gate signal GS1 of the first gate line GL1 to electrically connect the data line DL to the first node N1. A gate electrode of the second transistor T2 may be electrically connected to the first gate line GL1, a source electrode of the second transistor T2 may be electrically connected to the data line DL, and a drain electrode of the second transistor T2 may be electrically connected to the first node N1. The data line DL may transmit a data voltage Vdt or a reference voltage Vref.

[0117] The third transistor T3 may be turned on by the emission signal EM of the emission line EML to electrically connect the driving voltage line VDL to the second node N2. A gate electrode of the third transistor T3 may be electrically connected to the emission line EML, a source electrode of the third transistor T3 may be electrically connected to the driving voltage line VDL, and a drain electrode of the third transistor T3 may be electrically connected to the second node N2.

[0118] The fourth transistor T4 may be turned on by the second gate signal GS2 of the second gate line GL2 to electrically connect the third node N3 to the initialization line VIL. The gate electrode of the fourth transistor T4 may be electrically connected to the second gate line GL2, the source electrode of the fourth transistor T4 may be electrically connected to the third node N3, and the drain electrode of the fourth transistor T4 may be electrically connected to the initialization line VIL. There may be a plurality of initialization lines VIL, and the plurality of initialization lines VIL may be connected to each other. For example, the initialization line VIL may include a plurality of transverse initialization lines extending in the first direction DR1 and arranged along the second direction DR2 and a plurality of longitudinal initialization lines extending in the second direction DR2 and arranged along the first direction DR1, and the transverse initialization lines and the longitudinal initialization lines may be connected to each other.

[0119] The fifth transistor T5 may be turned on by the third gate signal GS3 of the third gate line GL3 to electrically connect the third node N3 with the sensing line SSL. A gate electrode of the fifth transistor T5 may be electrically connected to the third gate line GL3, a source electrode of the fifth transistor T5 may be electrically connected to the third node N3, and a drain electrode of the fifth transistor T5 may be electrically connected to the sensing line SSL.

[0120] The first capacitor C1 may be electrically connected between the first node N1 and the second node N2. For example, a first electrode of the first capacitor C1 may be electrically connected to the first node N1, and a second electrode of the first capacitor C1 may be electrically connected to the second node N2.

[0121] The second capacitor C2 may be electrically connected between the first node N1 and the third node N3. For example, a first electrode of the second capacitor C2 may be electrically connected to the first node N1, and a second electrode of the second capacitor C2 may be electrically connected to the third node N3.

[0122] When the first transistor T1 and the third transistor T3 are turned on, a driving current is supplied to the light emitting element ED, so that the light emitting element ED can emit light.

[0123] At least one of the first to fifth transistors T1 to T5 described above may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to fifth transistors T1 to T5 may be a p-type MOSFET. As another example, each of the first to fifth transistors T1 to T5 may be an n-type MOSFET. As yet another example, some of the first to fifth transistors T1 to T5 may be p-type MOSFETs, while the other transistors may be n-type MOSFETs.

[0124] Figure 7 It is shown Figure 6 The timing diagram of the first gate signal GS1 to the third gate signal GS3, the emission signal EM, the reference voltage Vref and the initialization voltage Vinit. Figure 7 In the example shown in , the display device 10 of the present disclosure may operate the pixel PX based on the initialization period P1 , the sensing period P2 , and the turn-off period P3 . Figure 7 The operation of the display device 10 for detecting defective pixels (eg, during manufacture or testing of the display device 10) may be specifically shown, and Figure 7 The operations shown in may not be used during normal operation of the display device 10 (eg, when the display device 10 is displaying an image).

[0125] The first gate signal GS1, the second gate signal GS2, the third gate signal GS3, and the emission signal EM may each have an effective level or an ineffective level for each period. The effective level of each of the signals GS1, GS2, GS3, and EM may indicate a voltage at a level capable of turning on the corresponding transistor to which the signal is applied. In other words, the signal at an effective level may have a value greater than the threshold voltage of the corresponding transistor. For example, Figure 6 As shown in , when each of the transistors T1 to T5 is a p-type transistor, the active level of each of the signals GS1, GS2, GS3, and EM may indicate a low level. The inactive level of each of the signals GS1, GS2, GS3, and EM may indicate a voltage at a level capable of turning off the corresponding transistor. In other words, the signal at the inactive level may have a value smaller than the threshold voltage of the corresponding transistor. For example, Figure 6As shown in , when each of the transistors T1 to T5 is a p-type transistor, the inactive level of each of the signals GS1, GS2, GS3, and EM may indicate a high level. When each of the transistors T1 to T5 is an n-type transistor, the active level of each of the signals GS1, GS2, GS3, and EM may indicate a high level, and the inactive level of each of the signals GS1, GS2, GS3, and EM may indicate a low level.

[0126] In the initialization period P1, the emission signal EM, the first gate signal GS1, and the second gate signal GS2 may each have an effective level, and the third gate signal GS3 may have an ineffective level. For example, during most of the initialization period P1, the emission signal EM, the first gate signal GS1, and the second gate signal GS2 may each have an effective level, and the third gate signal GS3 may have an ineffective level. At this time, for a specific time period in the initialization period P1, the emission signal EM, the first gate signal GS1, and the second gate signal GS2 may each have an effective level, and the third gate signal GS3 may have an ineffective level at the same time. In other words, in the initialization period P1, the effective level of the emission signal EM, the effective level of the first gate signal GS1, the effective level of the second gate signal GS2, and the ineffective level of the third gate signal GS3 may overlap with each other for a specific time period. In the initialization period P1, the reference voltage Vref may have a level of the first voltage Vr1. For example, the reference voltage Vref may be greater than zero and less than the driving voltage ELVDD.

[0127] The initialization period P1 may include, for example, a first sub-period S1 , a second sub-period S2 , and a third sub-period S3 .

[0128] In the first sub-period S1, the emission signal EM, the first gate signal GS1, and the third gate signal GS3 may each have a non-active level, and the second gate signal GS2 may have an active level. In addition, in the first sub-period S1, the reference voltage Vref may have a level of the first voltage Vr1.

[0129] In the second sub-period S2, the emission signal EM, the first gate signal GS1, and the second gate signal GS2 may each have an effective level, and the third gate signal GS3 may have an ineffective level. In addition, in the second sub-period S2, the reference voltage Vref may have a level of the first voltage Vr1. For example, a substantial initialization operation of the initialization period P1 may be performed during the second sub-period S2.

[0130] In the third sub-period S3, the emission signal EM and the first gate signal GS1 may each have an active level, and the second gate signal GS2 and the third gate signal GS3 may have an inactive level. In addition, in the third sub-period S3, the reference voltage Vref may have the level of the first voltage Vr1.

[0131] In the sensing period P2, the emission signal EM and the third gate signal GS3 may each have an active level, and the first gate signal GS1 and the second gate signal GS2 may each have an inactive level. In addition, in the sensing period P2, the reference voltage Vref may have the level of the first voltage Vr1.

[0132] In the off period P3, the emission signal EM, the first gate signal GS1, the second gate signal GS2, and the third gate signal GS3 may each have a non-effective level. In addition, in the off period P3, the reference voltage Vref may have a level of the second voltage Vr2. For example, the second voltage Vr2 of the reference voltage Vref may be lower than the first voltage Vr1 of the reference voltage Vref.

[0133] It should be noted that the initialization voltage Vinit may be maintained at a constant level during all periods including the initialization period P1, the sensing period P2, and the off period P3. For example, the initialization voltage Vinit may be a DC voltage that always has a constant level regardless of the period. Herein, the initialization voltage Vinit may be, for example, a DC voltage that is greater than the common voltage ELVSS and less than the driving voltage ELVDD.

[0134] Figure 6 The display device may include an emission layer. For example, Figure 6 The light emitting element ED of the display device may include a pixel electrode (eg, an anode), an emission layer, and a common electrode (eg, a cathode).

[0135] Will refer to Figures 7 to 10 The operation of the display device according to the embodiment of the present disclosure is described. Figures 8 to 10 In FIG. 1 , a transistor surrounded by a relatively thick circle indicates that the transistor is turned on. On the other hand, a transistor surrounded by a dotted circle indicates that the transistor is turned off. In addition, Figures 8 to 10 The arrows in the diagram indicate the flow of current.

[0136] Figures 8 to 10 The display device may be operable or may be defective, for example, may not include an emissive layer. Figures 8 to 10 The light emitting element ED of the display device may include an anode and does not include an emission layer or a common electrode. In other words, the light emitting element ED of the display device may include an anode and does not include an emission layer or a common electrode. Figure 7 The signal Figures 8 to 10The light emitting element ED of the display device may include a pixel electrode, but does not include an emission layer or a common electrode. Figures 8 to 10 The light emitting element ED of the display device may include only a pixel electrode.

[0137] First, refer to Figure 7 and Figure 8 The operation of the display device in the initialization period P1 is described.

[0138] Figure 8 Shows Figure 6 The display device is Figure 7 Operations in the initialization period P1. Figure 7 As shown in, in the second sub-period S2 of the initialization period P1, the emission signal EM, the first gate signal GS1 and the second gate signal GS2 may each have an effective level, and the third gate signal GS3 may have an ineffective level. In addition, in the second sub-period S2, the reference voltage Vref may have the level of the first voltage Vr1.

[0139] like Figure 8 As shown in FIG. 1 , the first gate signal GS1 at an effective level may be applied to the gate electrode of the second transistor T2 through the first gate line GL1 . Accordingly, the second transistor T2 may be turned on.

[0140] like Figure 8 As shown in FIG. 1 , the second gate signal GS2 at the effective level may be applied to the gate electrode of the fourth transistor T4 through the second gate line GL2. Accordingly, the fourth transistor T4 may be turned on.

[0141] like Figure 8 As shown in FIG. 1 , the third gate signal GS3 at the inactive level may be applied to the gate electrode of the fifth transistor T5 through the third gate line GL3 . Accordingly, the fifth transistor T5 may be turned off.

[0142] like Figure 8 As shown in FIG. 1 , the emission signal EM at an effective level may be applied to the gate electrode of the third transistor T3 through the emission line EML. Accordingly, the third transistor T3 may be turned on.

[0143] As the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on during the initialization period P1, the gate electrode (e.g., the first node N1) of the first transistor T1, the source electrode (e.g., the second node N2) of the first transistor T1, and the drain electrode (e.g., the third node N3) of the first transistor T1 may be initialized. For example, the reference voltage Vref from the data line DL may be applied to the first node N1 as the gate electrode of the first transistor T1 through the turned-on second transistor T2. In addition, the driving voltage ELVDD from the driving voltage line VDL may be applied to the second node N2 as the source electrode of the first transistor T1 through the turned-on third transistor T3. In addition, the initialization voltage Vinit from the initialization line VIL may be applied to the third node N3 as the drain electrode of the first transistor T1 through the turned-on fourth transistor T4. Accordingly, the voltage of each of the gate electrode of the first transistor T1, the source electrode of the first transistor T1, and the drain electrode of the first transistor T1 may be initialized. For example, the gate electrode of the first transistor T1 may be initialized to the reference voltage Vref, the source electrode of the first transistor T1 may be initialized to the driving voltage ELVDD, and the drain electrode of the first transistor T1 (or the anode of the light emitting element ED) may be initialized to the initialization voltage Vinit.

[0144] In addition, the first transistor T1 is a p-type transistor, and the reference voltage Vref applied to the first node N1 as the gate electrode of the first transistor T1 is less than the driving voltage ELVDD applied to the source electrode of the first transistor T1. Accordingly, during the initialization period P1, the voltage difference between the gate electrode and the source electrode of the first transistor T1 (hereinafter referred to as the gate-source voltage) may be a voltage of negative polarity. Accordingly, in the initialization period P1, the first transistor T1 may be turned on by the gate-source voltage of negative polarity. Therefore, a current path may be generated between the driving voltage line VDL and the initialization line VIL by the turned-on first transistor T1. The voltages of the source electrode and the drain electrode of the first transistor T1 may also be initialized by the current flowing along the current path.

[0145] Will refer to Figure 7 and Fig. 9 The operation of the display device in the sensing period P2 is described. Fig. 9 Shows Figure 6 The display device is Figure 7 In an embodiment, the sensing period P2 may be used for an inspection process and may be the only time that the fifth transistor T5 is turned on, and the fifth transistor T5 may always remain off during normal display operation.

[0146] like Figure 7As shown in , in the sensing period P2, the emission signal EM and the third gate signal GS3 may each have an effective level, and the first gate signal GS1 and the second gate signal GS2 may each have an ineffective level. In addition, in the sensing period P2, the reference voltage Vref may have the level of the first voltage Vr1.

[0147] like Fig. 9 As shown in FIG. 1 , the first gate signal GS1 at the non-active level may be applied to the gate electrode of the second transistor T2 through the first gate line GL1. Accordingly, the second transistor T2 may be turned off.

[0148] like Fig. 9 As shown in FIG. 1 , the second gate signal GS2 at the inactive level may be applied to the gate electrode of the fourth transistor T4 through the second gate line GL2. Accordingly, the fourth transistor T4 may be turned off.

[0149] like Fig. 9 As shown in FIG. 1 , the third gate signal GS3 at the effective level may be applied to the gate electrode of the fifth transistor T5 through the third gate line GL3 . Accordingly, the fifth transistor T5 may be turned on.

[0150] like Fig. 9 As shown in FIG. 1 , the emission signal EM at an effective level may be applied to the gate electrode of the third transistor T3 through the emission line EML. Accordingly, the third transistor T3 may be turned on.

[0151] As the second transistor T2 is turned off, the first node N1 as the gate electrode of the first transistor T1 may be electrically floated, and the first voltage Vrl of the reference voltage Vref applied during the previous period (e.g., the initialization period P1) may be maintained at the floating first node N1. At this time, the first voltage Vr1 of the first node N1 may be maintained by the first capacitor C1. By the first voltage Vr1 maintained by the first capacitor C1, the first transistor T1 may be kept turned on.

[0152] For each of the pixels PX, the second capacitor C2 can compensate for the magnitude of the driving current according to the deviation of the threshold voltage of the first transistor T1 (e.g., the threshold voltage generated by the body electrode of the first transistor T1). For example, due to variables during the manufacturing process, the threshold voltage of the first transistor T1 of each pixel PX may have a deviation within or outside the allowable range. Therefore, the second capacitor C2 can adjust the voltage of the gate electrode of the first transistor T1 (hereinafter referred to as the gate voltage) according to the level of the threshold voltage of the first transistor T1. In this way, it is possible to compensate for the deviation of the driving current according to the deviation of the threshold voltage of the first transistor T1 of each pixel PX. For example, if the threshold voltage of the first transistor T1 is less than a predetermined reference threshold voltage, the first transistor T1 may flow a driving current more than the normal value. Then, the voltage of the drain electrode of the first transistor T1 (hereinafter referred to as the drain voltage) increases due to the driving current greater than the normal value, and the voltage on the opposite side of the second capacitor C2 (e.g., the voltage of the gate electrode of the first transistor T1) may also increase as much as the increased drain voltage. As the gate voltage of the first transistor T1 increases, the gate-source voltage of the first transistor T1 may increase in the positive direction. In other words, the gate-source voltage of the p-type first transistor T1 is offset so that the gate-source voltage becomes less than the threshold voltage. As a result, if the driving current flowing through the first transistor T1 is greater than the normal value, the second capacitor C2 reduces the gate-source voltage of the first transistor T1, and therefore the driving current of the first transistor T1 may be reduced to the normal value. On the other hand, if the threshold voltage of the first transistor T1 is greater than the predetermined reference threshold voltage, the first transistor T1 may flow through a driving current less than the normal value. Then, the drain voltage of the first transistor T1 is reduced due to the driving current less than the normal value, and the voltage on the opposite side of the second capacitor C2 (for example, the voltage of the gate electrode of the first transistor T1) may also be reduced as much as the reduced drain voltage. As the gate voltage of the first transistor T1 decreases, the gate-source voltage of the first transistor T1 may increase in the negative direction. In other words, the gate-source voltage of the p-type first transistor T1 is offset so that it becomes greater than the threshold voltage. As a result, if the driving current flowing through the first transistor T1 is less than the normal value, the second capacitor C2 increases the gate-source voltage of the first transistor T1, and thus the driving current of the first transistor T1 can be increased to the normal value. Accordingly, the deviation of the driving current according to the deviation of the threshold voltage of each of the pixels PX can be reduced. By the way, the above-mentioned first capacitor C1 can store the gate voltage (for example, the voltage of the first node N1) compensated by the second capacitor C2.

[0153] As described above, as the third transistor T3, the first transistor T1, and the fifth transistor T5 are turned on, a current path may be formed between the driving voltage line VDL and the sensing line SSL through the third transistor T3, the first transistor T1, and the fifth transistor T5. Therefore, a current (e.g., a sensing current) flowing along the driving voltage line VDL, the third transistor T3, the first transistor T1, the fifth transistor T5, and the sensing line SSL may be formed. The sensing current may be provided to the detector 230 through the sensing line SSL. The detector 230 may receive the sensing current flowing through the third transistor T3, the first transistor T1, and the fifth transistor T5 via the sensing line SSL, and may determine whether the pixel PX is defective based on the received sensing current. For example, the detector 230 may convert the sensing current supplied through the sensing line SSL into a voltage (e.g., a sensing voltage Vs), may compare the sensing voltage Vs with a predetermined standard voltage, and may determine whether the pixel PX is defective based on the comparison result. For example, if it is determined based on the comparison result that the sensing voltage Vs falls within a predetermined normal range of the standard voltage, the detector 230 may determine that the pixel PX is not defective. As a specific example, the standard voltage may have a lower limit voltage and an upper limit voltage, and accordingly, if it is determined that the sensing voltage Vs is equal to or greater than the lower limit voltage of the standard voltage and equal to or less than the upper limit voltage of the standard voltage, the detector 230 may determine that the pixel PX is normal. On the other hand, if it is determined based on the comparison result that the sensing voltage Vs falls outside the predetermined normal range of the standard voltage, the detector 230 may determine that the pixel PX is defective. As a specific example, if it is determined that the sensing voltage Vs is less than the lower limit voltage of the standard voltage or greater than the upper limit voltage of the standard voltage, the detector 230 may determine that the pixel PX is defective. In other words, the detector 230 may determine that the pixel PX is a bad pixel.

[0154] Will refer to Figure 7 and Fig.10 The operation of the display device in the turn-off period P3 is described.

[0155] Fig.10 Shows Figure 6 The display device is Figure 7 Operation in the off period P3.

[0156] like Figure 7 As shown in , in the off period P3, the emission signal EM, the first gate signal GS1, the second gate signal GS2, and the third gate signal GS3 may each have a non-effective level. In addition, in the off period P3, the reference voltage Vref may have a level of the second voltage Vr2. For example, the second voltage Vr2 of the reference voltage Vref may be less than the first voltage Vr1 of the reference voltage Vref.

[0157] like Fig.10As shown in FIG. 1 , the first gate signal GS1 at the non-active level may be applied to the gate electrode of the second transistor T2 through the first gate line GL1. Accordingly, the second transistor T2 may be turned off.

[0158] like Fig.10 As shown in FIG. 1 , the second gate signal GS2 at the inactive level may be applied to the gate electrode of the fourth transistor T4 through the second gate line GL2. Accordingly, the fourth transistor T4 may be turned off.

[0159] like Fig.10 As shown in FIG. 1 , the third gate signal GS3 at the inactive level may be applied to the gate electrode of the fifth transistor T5 through the third gate line GL3 . Accordingly, the fifth transistor T5 may be turned off.

[0160] like Fig.10 As shown in FIG. 1 , the emission signal EM at a non-active level may be applied to the gate electrode of the third transistor T3 through the emission line EML. Accordingly, the third transistor T3 may be turned off.

[0161] like Fig.10 As shown in , the first transistor T1 can be turned off.

[0162] Pixels in a column that are commonly connected to one sensing line may be sequentially connected to the sensing line. Figure 5 As shown in , a plurality of pixels PX in the first column CL1 may be sequentially connected to the first sensing line SSL1. Specifically, let us define the three pixels PX in the first column CL1 as a first pixel, a second pixel, and a third pixel in reverse order along the second direction DR2 from the top side. In this order, the third gate signal GS3 may be first applied to the third transistor T3 of the first pixel, then the third gate signal GS3 may be applied to the third transistor T3 of the second pixel, and then the third gate signal GS3 may be applied to the third transistor T3 of the third pixel. Accordingly, the sensing voltage Vs of the pixels PX of the first column CL1 may be sequentially applied to the first sensing line SSL1.

[0163] Fig.11 It is shown Figure 6 The timing diagram of the first gate signal GS1 to the third gate signal GS3, the emission signal EM, the data voltage Vdt and the initialization voltage Vinit. For example, Fig.11 The display device is shown in Figure 7 Operation after the off period P3. Fig.11 The display device may be, for example, a display device including an emission layer. Fig.11 The light emitting element ED of the display device for transmitting a signal may include a pixel electrode (eg, an anode), an emission layer, and a common electrode (eg, a cathode). Fig.11The operations shown in may in particular be employed during normal operation of the display device, for example, to display images.

[0164] The display device 10 of the present disclosure as described above may be manufactured such that the display device 10 includes an emission layer on a pixel electrode, a common electrode on the emission layer, and an encapsulation layer ENC on the common electrode (see Figure 2 ) and the color filter layer CFL on the encapsulation layer ENC (see Figure 2 ), and performing the above inspection process can determine whether the pixel is defective. Subsequently, the display device including the emission layer, the common electrode, etc. can be based on the following Fig.11 11, the compensation period P22, the bypass period P33, and the emission period P44 in the example shown in FIG. 11. For example, after the shutdown period, the display device 10 of the present disclosure may be based on Fig.11 The first gate line GL3 connected to the gate electrode of the fifth transistor T5 may be operated by the initialization / writing period P11, the compensation period P22, the bypass period P33 and the emission period P44. It should be noted that the fifth transistor T5 may always remain off regardless of the period P11, P22, P33 or P44. As an example, the third gate signal GS3 of the third gate line GL3 connected to the gate electrode of the fifth transistor T5 may be Fig.11 The period shown in is maintained at the inactive level. In other words, the third gate signal GS3 may be a DC signal having a magnitude capable of turning off the fifth transistor T5. In addition, the sensing line SSL of the display device including the emission layer, the common electrode, etc. may be connected to the detector 230 or the power supply unit 500 (see Figure 4 ), and may receive a DC voltage from the detector 230 or the power supply unit 500.

[0165] The initialization / write period P11, the compensation period P22, the bypass period P33, and the emission period P44 may correspond to one horizontal period 1H. In other words, one horizontal period 1H may include the initialization / write period P11, the compensation period P22, the bypass period P33, and the emission period P44. The horizontal period 1H may indicate the number of times the initialization / write period P11, the compensation period P22, the bypass period P33, and the emission period P44 are in the horizontal direction (e.g., Figure 5 The period during which pixels arranged in a first direction DR1 (for example, pixels in a row) operate. The pixels in a row may indicate a plurality of pixels commonly connected to the same gate line (for example, the first gate line GL1) and also connected to different data lines DL. In addition, the pixels in a row may be connected to a plurality of sensing lines SSL.

[0166] The first gate signal GS1, the second gate signal GS2, the third gate signal GS3, and the emission signal EM may each have an effective level or an ineffective level for each period. The effective level of each of the signals GS1, GS2, GS3, and EM may indicate a voltage at a level capable of turning on the corresponding transistor to which the signal is applied. In other words, the signal at an effective level may have a value greater than the threshold voltage of the corresponding transistor. Fig.11 In the example shown in FIG. 1 , each of transistors T1 to T5 is as follows Figure 6 , and the active level of each of the signals GS1, GS2, GS3, and EM may indicate a low level. The inactive level of each of the signals GS1, GS2, GS3, and EM may indicate a voltage at a level capable of turning off the corresponding transistor. In other words, the signal at the inactive level may have a value smaller than the threshold voltage of the corresponding transistor. Fig.11 In the example shown in FIG. 1 , each of transistors T1 to T5 is as follows Figure 6 , and the inactive level of each of the signals GS1, GS2, GS3, and EM may indicate a high level. If each of the transistors T1 to T5 is an n-type transistor, the active level of each of the signals GS1, GS2, GS3, and EM may indicate a high level, and the inactive level of each of the signals GS1, GS2, GS3, and EM may indicate a low level.

[0167] In the initialization / write period P11, the emission signal EM, the first gate signal GS1, and the second gate signal GS2 may each have an effective level, and the third gate signal GS3 may have an ineffective level. In addition, during the initialization / write period P11, the data voltage Vdt may be applied to the data line DL. The data voltage Vdt may be a voltage representing a specific gray level (or brightness) for displaying an image. In the initialization / write period P11, the data voltage Vdt may be a data voltage Vdt1 (hereinafter referred to as a previous data voltage) of a previous horizontal period.

[0168] In the compensation period P22, the first gate signal GS1 and the second gate signal GS2 may each have an active level, and the emission signal EM and the third gate signal GS3 may each have an inactive level. In addition, in the compensation period P22, the previous data voltage Vdt1 may be applied to the data line DL.

[0169] In the bypass period P33, the emission signal EM and the second gate signal GS2 may each have an effective level, and the first gate signal GS1 and the third gate signal GS3 may each have an ineffective level. In addition, in the bypass period P33, the data voltage Vdt of the data line DL may be a transient data voltage Vtrs that changes (or transitions) from the previous data voltage Vdt1 to the current data voltage Vdt2.

[0170] In the emission period P44, the emission signal EM may have an effective level, and the first gate signal GS1, the second gate signal GS2, and the third gate signal GS3 may each have an ineffective level. In addition, in the emission period P44, the data voltage Vdt may be applied to the data line DL. The data voltage Vdt may be a voltage representing a specific gray level (or brightness) for displaying an image. In the emission period P44, the data voltage Vdt may be a data voltage Vdt2 (also referred to as a current data voltage) of the current horizontal period.

[0171] The initialization voltage Vinit may be maintained at a constant level during all periods including the initialization / write period P11, the compensation period P22, the bypass period P33, and the emission period P44. For example, the initialization voltage Vinit may be a DC voltage that always has a constant level regardless of the period P11, P22, P33, or P44. Herein, the initialization voltage Vinit may be, for example, a DC voltage that is greater than the common voltage ELVSS and less than the driving voltage ELVDD.

[0172] Will refer to Figures 11 to 15 The operation of the display device according to the embodiment of the present disclosure is described. Figures 12 to 15 In FIG. 1 , a transistor surrounded by a relatively thick circle indicates that the transistor is turned on. On the other hand, a transistor surrounded by a dotted circle indicates that the transistor is turned off. In addition, Figures 12 to 15 The arrows in the diagram indicate the flow of current.

[0173] First, refer to Fig.11 and Fig.12 The operation of the display device in the initialization / writing period P11 is described. Fig.12 Shows Figure 6 The display device is Fig.11 Operations in the initialization / writing period P11. Fig.11 As shown in, in the initialization / write period P11, the emission signal EM, the first gate signal GS1 and the second gate signal GS2 may each have an effective level, and the third gate signal GS3 may have an ineffective level. In addition, during the initialization / write period P11, the previous data voltage Vdt1 may be applied to the data line DL.

[0174] like Fig.12As shown in FIG. 1 , the first gate signal GS1 at an effective level may be applied to the gate electrode of the second transistor T2 through the first gate line GL1 . Accordingly, the second transistor T2 may be turned on.

[0175] like Fig.12 As shown in FIG. 1 , the second gate signal GS2 at the effective level may be applied to the gate electrode of the fourth transistor T4 through the second gate line GL2. Accordingly, the fourth transistor T4 may be turned on.

[0176] like Fig.12 As shown in FIG. 1 , the emission signal EM at an effective level may be applied to the gate electrode of the third transistor T3 through the emission line EML. Accordingly, the third transistor T3 may be turned on.

[0177] like Fig.12 As shown in FIG. 1 , the third gate signal GS3 at the inactive level may be applied to the gate electrode of the fifth transistor T5 through the third gate line GL3 . Accordingly, the fifth transistor T5 may be turned off.

[0178] like Fig.12 As shown in , the first transistor T1 may be turned on by the previous data voltage Vdt1.

[0179] As the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on during the initialization / write period P11, the gate electrode (e.g., the first node N1) of the first transistor T1, the source electrode (e.g., the second node N2) of the first transistor T1, and the drain electrode (e.g., the third node N3) of the first transistor T1 may be initialized. For example, the previous data voltage Vdt1 from the data line DL may be applied to the first node N1 as the gate electrode of the first transistor T1 through the turned-on second transistor T2. In addition, the driving voltage ELVDD from the driving voltage line VDL may be applied to the second node N2 as the source electrode of the first transistor T1 through the turned-on third transistor T3. In addition, the initialization voltage Vinit from the initialization line VIL may be applied to the third node N3 as the drain electrode of the first transistor T1 through the turned-on fourth transistor T4. Accordingly, the voltage of each of the gate electrode of the first transistor T1, the source electrode of the first transistor T1, and the drain electrode of the first transistor T1 may be initialized. For example, the gate electrode of the first transistor T1 may be initialized to the previous data voltage Vdt1, the source electrode of the first transistor T1 may be initialized to the driving voltage ELVDD, and the drain electrode of the first transistor T1 (or the anode of the light emitting element ED) may be initialized to the initialization voltage Vinit.

[0180] In addition, a current path may be generated between the driving voltage line VDL and the initialization line VIL by the turned-on first transistor T1. Voltages of the source and drain electrodes of the first transistor T1 may also be initialized by the current flowing along the current path.

[0181] Will refer to Fig.11 and Fig.13 The operation of the display device in the compensation period P22 is described. Fig.13 The display device is shown in Fig.11 The operation in the compensation period P22. Fig.11 As shown in , the first gate signal GS1 and the second gate signal GS2 may each have an active level, and the emission signal EM and the third gate signal GS3 may each have an inactive level. In addition, in the compensation period P22, the previous data voltage Vdt1 may be applied to the data line DL.

[0182] like Fig.13 As shown in FIG. 1 , the first gate signal GS1 at an effective level may be applied to the gate electrode of the second transistor T2 through the first gate line GL1 . Accordingly, the second transistor T2 may be turned on.

[0183] like Fig.13 As shown in FIG. 1 , the second gate signal GS2 at the effective level may be applied to the gate electrode of the fourth transistor T4 through the second gate line GL2. Accordingly, the fourth transistor T4 may be turned on.

[0184] like Fig.13 As shown in FIG. 1 , the emission signal EM at a non-active level may be applied to the gate electrode of the third transistor T3 through the emission line EML. Accordingly, the third transistor T3 may be turned off.

[0185] like Fig.13 As shown in FIG. 1 , the third gate signal GS3 at the inactive level may be applied to the gate electrode of the fifth transistor T5 through the third gate line GL3 . Accordingly, the fifth transistor T5 may be turned off.

[0186] like Fig.13 As shown in , the first transistor T1 may be turned on by the previous data voltage Vdt1.

[0187] In the compensation period P22, the threshold voltage of the first transistor T1 may be stored in the first capacitor C1. For example, the threshold voltage of the first transistor T1 may be stored in the first capacitor C1 in a source follower mode. At this time, the voltage of the second node N2 may be obtained, for example, by subtracting the threshold voltage of the first transistor T1 from the previous data voltage Vdt1.

[0188] Will refer to Fig.11 and Fig.14 The operation of the display device in the bypass period P33 is described. Fig.14 The display device is shown in Fig.11 The operation in the bypass period P33. Fig.11 As shown in , in the bypass period P33, the emission signal EM and the second gate signal GS2 may each have an effective level, and the first gate signal GS1 and the third gate signal GS3 may each have an ineffective level. In addition, in the bypass period P33, the data voltage Vdt of the data line DL may be a transient data voltage Vtrs that changes (or transforms) from the previous data voltage Vdt1 to the current data voltage Vdt2.

[0189] like Fig.14 As shown in FIG. 1 , the first gate signal GS1 at the non-active level may be applied to the gate electrode of the second transistor T2 through the first gate line GL1. Accordingly, the second transistor T2 may be turned off.

[0190] like Fig.14 As shown in FIG. 1 , the second gate signal GS2 at the effective level may be applied to the gate electrode of the fourth transistor T4 through the second gate line GL2. Accordingly, the fourth transistor T4 may be turned on.

[0191] like Fig.14 As shown in FIG. 1 , the emission signal EM at an effective level may be applied to the gate electrode of the third transistor T3 through the emission line EML. Accordingly, the third transistor T3 may be turned on.

[0192] like Fig.14 As shown in FIG. 1 , the third gate signal GS3 at the inactive level may be applied to the gate electrode of the fifth transistor T5 through the third gate line GL3 . Accordingly, the fifth transistor T5 may be turned off.

[0193] like Fig.14 As shown in , the first transistor T1 may be turned on by the previous data voltage Vdt1.

[0194] During the bypass period P33, the first gate signal GS1 changes (or transitions) from the effective level to the non-effective level, and therefore, the second transistor T2 may be turned on in a short period of time. Then, there may be a problem that the abnormal drive current generated by the transient data voltage Vtrs of the data line DL may be supplied to the light emitting element ED. In order to prevent such a problem, the fourth transistor T4 is turned on during the bypass period P33 so that the abnormal drive current generated by the transient data voltage Vtrs is not applied to the light emitting element ED. For example, the abnormal drive current generated by the transient data voltage Vtrs can be guided to the bypass path to the initialization line VIL through the turned-on fourth transistor T4.

[0195] Will refer to Fig.11 and Fig.15 The operation of the display device in the emission period P44 is described. Fig.15 The display device is shown in Fig.11 Operation in the transmission period P44. Fig.11 As shown in , in the emission period P44, the emission signal EM may have an effective level, and the first gate signal GS1, the second gate signal GS2 and the third gate signal GS3 may each have an ineffective level. In addition, in the emission period P44, the current data voltage Vdt2 may be applied to the data line DL.

[0196] like Fig.15 As shown in FIG. 1 , the first gate signal GS1 at the non-active level may be applied to the gate electrode of the second transistor T2 through the first gate line GL1. Accordingly, the second transistor T2 may be turned off.

[0197] like Fig.15 As shown in FIG. 1 , the second gate signal GS2 at the inactive level may be applied to the gate electrode of the fourth transistor T4 through the second gate line GL2. Accordingly, the fourth transistor T4 may be turned off.

[0198] like Fig.15 As shown in FIG. 1 , the emission signal EM at an effective level may be applied to the gate electrode of the third transistor T3 through the emission line EML. Accordingly, the third transistor T3 may be turned on.

[0199] like Fig.15 As shown in FIG. 1 , the third gate signal GS3 at the inactive level may be applied to the gate electrode of the fifth transistor T5 through the third gate line GL3 . Accordingly, the fifth transistor T5 may be turned off.

[0200] like Fig.15 As shown in , the first transistor T1 may be turned on by the current data voltage Vdt2 .

[0201] A current path from the driving voltage line VDL to the common voltage line VSL can be generated by the turned-on third transistor T3 and the turned-on first transistor T1, and a driving current can flow through the current path. The driving current is supplied to the light emitting element ED, and thus the light emitting element ED can emit light with brightness corresponding to the driving current.

[0202] It should be noted that all of the pixels PX of the display device including the emission layer, the common electrode, etc. can simultaneously receive the third gate signal GS3 at the non-active level.

[0203] Fig.16 is a circuit diagram of a pixel of a display device according to an embodiment of the present disclosure.

[0204] Except that the sensing line SSL and the fifth transistor T5 are removed and the initialization / sensing line VISL is connected to the fourth transistor T4, Fig.16 Pixels and Figure 6 The pixels are essentially the same. Fig.16 In the following description, redundant descriptions of the elements described above are omitted.

[0205] Fig.16 The fourth transistor T4 in the embodiment may be turned on by the second gate signal GS2 of the second gate line GL2 to electrically connect the third node N3 with the initialization / sensing line VISL. The gate electrode of the fourth transistor T4 may be electrically connected to the second gate line GL2, the source electrode thereof may be electrically connected to the third node N3, and the drain electrode thereof may be electrically connected to the initialization / sensing line VISL.

[0206] The initialization / sensing line VISL may be connected to, for example, the above-described detector 230. For example, the initialization / sensing line VISL may transmit an initialization voltage Vinit during a certain period and transmit a sensing voltage Vs during another period. In other words, the initialization / sensing line VISL may be used as an initialization line VIL and a sensing line SSL. In this case, the initialization voltage Vinit of the initialization / sensing line VISL may have different voltages during different periods.

[0207] The initialization / sense line VISL may be similar to the sense line (eg, Figure 5 The first sensing line SSL1 is commonly connected to the pixels PX in one column. Figure 5 Like the sensing lines SSL1, SSL2, ... of FIG. 1 , there may be a plurality of initialization / sensing lines VISL. The plurality of initialization / sensing lines VISL may correspond to a plurality of columns, respectively. In this case, the initialization / sensing lines VISL may not be connected to each other.

[0208] Fig.17 It is shown Fig.16 The timing diagram of the first gate signal GS1, the second gate signal GS2, the emission signal EM, the reference voltage Vref and the initialization voltage Vinit. Fig.17 In the example shown in , the display device 10 of the present disclosure may operate based on an initialization period P1 , a sensing period P2 , and a turn-off period P3 . Fig.17 The operation of the display device 10 for detecting defective pixels (eg, during manufacture or testing of the display device 10) may be specifically illustrated, and Fig.17 The operations shown in may not be used during normal operation of the display device 10 (eg, when the display device 10 is displaying an image).

[0209] The first gate signal GS1, the second gate signal GS2, and the emission signal EM may each have an effective level or an ineffective level during each period. The effective level of each of the signals GS1, GS2, and EM may indicate a voltage at a level capable of turning on the corresponding transistor to which the signal is applied. In other words, the signal at an effective level may have a value greater than the threshold voltage of the corresponding transistor. For example, Fig.17 As shown in , when each of the transistors T1 to T4 is a p-type transistor, the active level of each of the signals GS1, GS2, and EM may indicate a low level. The inactive level of each of the signals GS1, GS2, and EM may indicate a voltage at a level capable of turning off the corresponding transistor. In other words, the signal at the inactive level may have a value smaller than the threshold voltage of the corresponding transistor. For example, Fig.17 As shown in , when each of the transistors T1 to T4 is a p-type transistor, the inactive level of each of the signals GS1, GS2, and EM may indicate a high level. When each of the transistors T1 to T4 is an n-type transistor, the active level of each of the signals GS1, GS2, and EM may indicate a high level, and the inactive level of each of the signals GS1, GS2, and EM may indicate a low level.

[0210] In the initialization period P1, the emission signal EM, the first gate signal GS1 and the second gate signal GS2 may each have an effective level. For example, in most of the initialization period P1, the emission signal EM, the first gate signal GS1 and the second gate signal GS2 may each have an effective level. In the initialization period P1, the emission signal EM, the first gate signal GS1 and the second gate signal GS2 may have an effective level at the same time for a specific time period. In other words, in the initialization period P1, the effective level of the emission signal EM, the effective level of the first gate signal GS1 and the effective level of the second gate signal GS2 may overlap with each other for a specific time period. In the initialization period P1, the reference voltage Vref may have a level of the first voltage Vr1. In addition, in the initialization period P1, the initialization voltage Vinit may have a level of the first voltage Vi1. The first voltage Vi1 of the initialization voltage Vinit may be, for example, a voltage lower than the drive voltage ELVDD.

[0211] The initialization period P1 may include, for example, a first sub-period S1 and a second sub-period S2.

[0212] In the first sub-period S1, the emission signal EM and the first gate signal GS1 may each have a non-active level, and the second gate signal GS2 may have an active level. In addition, in the first sub-period S1, the reference voltage Vref may have a level of the first voltage Vr1. In addition, in the first sub-period S1, the initialization voltage Vinit may have a level of the first voltage Vi1.

[0213] In the second sub-period S2, the emission signal EM, the first gate signal GS1, and the second gate signal GS2 may each have an effective level. In addition, in the second sub-period S2, the reference voltage Vref may have a level of the first voltage Vr1. In addition, in the second sub-period S2, the initialization voltage Vinit may have a level of the first voltage Vi1. For example, a substantial initialization operation of the initialization period P1 may be performed in the second sub-period S2.

[0214] In the sensing period P2, the emission signal EM and the second gate signal GS2 may each have an effective level, while the first gate signal GS1 may have an ineffective level. In addition, in the sensing period P2, the reference voltage Vref may have a level of the first voltage Vr1. In the sensing period P2, the initialization voltage Vinit may have a level of the second voltage Vi2. The second voltage Vi2 of the initialization voltage Vinit may be less than the above-mentioned driving voltage ELVDD. For example, the second voltage Vi2 of the initialization voltage Vinit may be greater than the common voltage ELVSS and less than the first voltage Vi1 of the initialization voltage Vinit. By the way, according to an embodiment of the present disclosure, the first gate signal GS1 may have an effective level instead of an ineffective level in the sensing period P2.

[0215] In the off period P3, the emission signal EM, the first gate signal GS1, and the second gate signal GS2 may each have a non-active level. In addition, in the off period P3, the reference voltage Vref may have a level of the second voltage Vr2. In addition, in the off period P3, the initialization voltage Vinit may have a level of the first voltage Vi1.

[0216] Will refer to Figures 17 to 20 The operation of the display device according to the embodiment of the present disclosure is described. Figures 18 to 20 In FIG. 1 , a transistor surrounded by a relatively thick circle indicates that the transistor is turned on. On the other hand, a transistor surrounded by a dotted circle indicates that the transistor is turned off. In addition, Figures 18 to 20 The arrows in the diagram indicate the flow of current. Figures 18 to 20 The display device may not include an emission layer. For example, Figures 18 to 20 The light emitting element of the display device may include an anode and does not include an emission layer or a common electrode. In other words, the receiving Fig.17 The signal Figures 18 to 20 The light emitting element of the display device may include a pixel electrode, and may not include an emission layer or a common electrode.

[0217] Will refer to Fig.17 and Fig.18 The operation of the display device in the initialization period P1 is described.

[0218] Fig.18 The display device is shown in Fig.17 Operations in the initialization period P1.

[0219] like Fig.17 As shown in, in the second sub-period S2 of the initialization period P1, the emission signal EM, the first gate signal GS1 and the second gate signal GS2 may each have an effective level. In addition, in the second sub-period S2, the reference voltage Vref may have the level of the first voltage Vr1, and the initialization voltage Vinit may have the level of the first voltage Vi1.

[0220] like Fig.18 As shown in FIG. 1 , the first gate signal GS1 at an effective level may be applied to the gate electrode of the second transistor T2 through the first gate line GL1 . Accordingly, the second transistor T2 may be turned on.

[0221] like Fig.18 As shown in FIG. 1 , the second gate signal GS2 at the effective level may be applied to the gate electrode of the fourth transistor T4 through the second gate line GL2. Accordingly, the fourth transistor T4 may be turned on.

[0222] like Fig.18 As shown in FIG. 1 , the emission signal EM at an effective level may be applied to the gate electrode of the third transistor T3 through the emission line EML. Accordingly, the third transistor T3 may be turned on.

[0223] As the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned on during the initialization period P1, the gate electrode (e.g., the first node N1) of the first transistor T1, the source electrode (e.g., the second node N2) of the first transistor T1, and the drain electrode (e.g., the third node N3) of the first transistor T1 may be initialized. For example, the first voltage Vr1 from the data line DL may be applied to the first node N1 as the gate electrode of the first transistor T1 through the turned-on second transistor T2. In addition, the driving voltage ELVDD from the driving voltage line VDL may be applied to the second node N2 as the source electrode of the first transistor T1 through the turned-on third transistor T3. In addition, the first voltage Vi1 from the initialization / sense line VISL may be applied to the third node N3 as the drain electrode of the first transistor T1 through the turned-on fourth transistor T4. Accordingly, the voltage of each of the gate electrode of the first transistor T1, the source electrode of the first transistor T1, and the drain electrode of the first transistor T1 may be initialized. For example, the gate electrode of the first transistor T1 may be initialized to a first voltage Vr1 of a reference voltage Vref, the source electrode of the first transistor T1 may be initialized to a driving voltage ELVDD, and the drain electrode of the first transistor T1 (or an anode of the light emitting element ED) may be initialized to a first voltage Vi1 of an initialization voltage Vinit.

[0224] In addition, the first transistor T1 is a p-type transistor, and the first voltage Vr1 of the reference voltage Vref applied to the first node N1 as the gate electrode of the first transistor T1 is less than the driving voltage ELVDD applied to the source electrode of the first transistor T1. Accordingly, during the initialization period P1, the gate-source voltage of the first transistor T1 may be a voltage of negative polarity. Accordingly, in the initialization period P1, the first transistor T1 may be turned on by the gate-source voltage of negative polarity. Therefore, a current path may be generated between the driving voltage line VDL and the initialization / sensing line VISL by the turned-on first transistor T1. The voltages of the source electrode and the drain electrode of the first transistor T1 may also be initialized by the current flowing along the current path.

[0225] Will refer to Fig.17 and Fig.19 The operation of the display device in the sensing period P2 is described. Fig.19 The display device is shown in Fig.17 The operation in the sensing period P2.

[0226] like Fig.17 As shown in , the emission signal EM and the second gate signal GS2 may each have an effective level, and the first gate signal GS1 may have an ineffective level. In addition, in the sensing period P2, the reference voltage Vref may have a level of the first voltage Vr1, and the initialization voltage Vinit may have a level of the second voltage Vi2.

[0227] like Fig.19 As shown in FIG. 1 , the first gate signal GS1 at the non-active level may be applied to the gate electrode of the second transistor T2 through the first gate line GL1. Accordingly, the second transistor T2 may be turned off.

[0228] like Fig.19 As shown in FIG. 1 , the second gate signal GS2 at the effective level may be applied to the gate electrode of the fourth transistor T4 through the second gate line GL2. Accordingly, the fourth transistor T4 may be turned on.

[0229] like Fig.19 As shown in FIG. 1 , the emission signal EM at an effective level may be applied to the gate electrode of the third transistor T3 through the emission line EML. Accordingly, the third transistor T3 may be turned on.

[0230] As the second transistor T2 is turned off, the first node N1 as the gate electrode of the first transistor T1 may be electrically floated, and the first voltage Vrl of the reference voltage Vref applied during the previous period (e.g., the initialization period P1) may be maintained at the floating first node N1. At this time, the first voltage Vr1 of the first node N1 may be maintained by the first capacitor C1. The first transistor T1 may be kept turned on by the first voltage Vr1 of the reference voltage Vref maintained by the first capacitor C1.

[0231] For each of the pixels PX, the second capacitor C2 may compensate for the magnitude of the driving current according to the deviation of the threshold voltage of the first transistor T1 .

[0232] As described above, as the third transistor T3, the first transistor T1, and the fourth transistor T4 are turned on, a current path may be formed between the driving voltage line VDL and the initialization / sensing line VISL through the third transistor T3, the first transistor T1, and the fourth transistor T4. Therefore, a current (e.g., a sensing current) may be formed that flows along the driving voltage line VDL, the third transistor T3, the first transistor T1, the fourth transistor T4, and the initialization / sensing line VISL. The sensing current may be provided to the detector 230 through the initialization / sensing line VISL. The detector 230 may receive the sensing current flowing through the third transistor T3, the first transistor T1, and the fourth transistor T4 via the initialization / sensing line VISL, and may determine whether the pixel PX is defective based on the received sensing current. Reference has been made to Fig. 9 The operation of the detector 230 for determining whether a pixel is defective is described.

[0233] Will refer to Fig.17 and Fig. 20 The operation of the display device in the turn-off period P3 is described. Fig. 20 The display device is shown in Fig.17 Operation in the off period P3.

[0234] like Fig.17 As shown in FIG, in the off period P3, the emission signal EM, the first gate signal GS1 and the second gate signal GS2 may each have a non-active level. In addition, in the off period P3, the reference voltage Vref may have the level of the second voltage Vr2, and the initialization voltage Vinit may have the level of the first voltage Vi1.

[0235] like Fig. 20 As shown in FIG. 1 , the first gate signal GS1 at the non-active level may be applied to the gate electrode of the second transistor T2 through the first gate line GL1. Accordingly, the second transistor T2 may be turned off.

[0236] like Fig. 20As shown in FIG. 1 , the second gate signal GS2 at the inactive level may be applied to the gate electrode of the fourth transistor T4 through the second gate line GL2. Accordingly, the fourth transistor T4 may be turned off.

[0237] like Fig. 20 As shown in FIG. 1 , the emission signal EM at a non-active level may be applied to the gate electrode of the third transistor T3 through the emission line EML. Accordingly, the third transistor T3 may be turned off.

[0238] like Fig. 20 As shown in , the first transistor T1 can be turned off.

[0239] Pixels in a column that are commonly connected to one sensing line may be sequentially connected to the sensing line. Figure 5 As shown in , a plurality of pixels PX in the first column CL1 may be sequentially connected to the first sensing line SSL1. Specifically, let us define the three pixels PX in the first column CL1 as a first pixel, a second pixel, and a third pixel in reverse order along the second direction DR2 from the top side. In this order, the second gate signal GS2 may be first applied to the fourth transistor T4 of the first pixel, then the second gate signal GS2 may be applied to the fourth transistor T4 of the second pixel, and then the second gate signal GS2 may be applied to the fourth transistor T4 of the third pixel. Accordingly, the sensing voltage Vs of the pixels PX of the first column CL1 may be sequentially applied to the first sensing line SSL1. The same process may be applied to the pixels PX connected to Fig.16 columns of pixels with the same initialization / sense line VISL.

[0240] The display device 10 of the present disclosure may be manufactured to include an emission layer on a pixel electrode, a common electrode on the emission layer, and an encapsulation layer ENC on the common electrode (see Figure 2 ) and the color filter layer CFL on the encapsulation layer ENC (see Figure 2 ). After such manufacture, perform Figures 17 to 20 The above inspection process can determine whether the pixel is defective. After passing the inspection, the display device including the emission layer and the common electrode can be based on the following Fig.11 11, the compensation period P22, the bypass period P33, and the emission period P44 in the example shown in FIG. 11. For example, after the shutdown period, the display device 10 of the present disclosure may be based on Fig.11 In other words, as described above, Fig.11 The emission signal EM, the first gate signal GS1, the second gate signal GS2, the data voltage Vdt and the initialization voltage Vinit in the Fig.16 The display device further includes an emission layer, a common electrode, etc. Fig.16 The display device does not apply or need the third gate signal GS3. In addition, the initialization / sensing line VISL of the display device including the emission layer, the common electrode, etc. can be connected to the detector 230 or the power supply unit 500, and can receive the initialization voltage Vinit from the detector 230 or the power supply unit 500.

[0241] Fig.21 is a circuit diagram of a pixel of a display device according to an embodiment of the present disclosure.

[0242] like Fig.21 As shown in , the pixel PX may be connected to a first gate line GL1, a second gate line GL2, a third gate line GL3, a fourth gate line GL4, a sensing line SSL, an initialization line VIL, an emission line EML, a data line DL, a driving voltage line VDL, and a common voltage line VSL. The common voltage line VSL may be connected to a common electrode (e.g., a cathode) of the light emitting element ED. The pixel PX may include a pixel circuit PC and a light emitting element ED. The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1', and a second capacitor C2'.

[0243] The first transistor T1 (e.g., a driving transistor) may include a gate electrode, a source electrode, and a drain electrode. The first transistor T1 may control a source-drain current (hereinafter referred to as a driving current) according to a data voltage Vdt applied to the gate electrode. The driving current (e.g., Isd) flowing through the channel region of the first transistor T1 may be proportional to the square of the difference between the threshold voltage Vth of the first transistor T1 and the voltage Vsg between the source electrode and the gate electrode of the first transistor T1, for example, Isd=k×(Vsg-Vth) 2 , wherein k represents a proportionality coefficient determined by the structure and physical properties of the first transistor T1, Vsg represents a source-gate voltage of the first transistor T1, and Vth represents a threshold voltage of the first transistor T1. The gate electrode of the first transistor T1 may be connected to the first node N1, the source electrode of the first transistor T1 may be connected to the drain electrode of the third transistor T3, and the drain electrode of the first transistor T1 may be connected to the node N3A.

[0244] The light emitting element ED may receive a driving current to emit light. The amount or brightness of light emitted from the light emitting element ED may be proportional to the size of the driving current or otherwise depend on the size of the driving current. The light emitting element ED may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer arranged between the first electrode and the second electrode. Alternatively, the light emitting element ED may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor arranged between the first electrode and the second electrode. Alternatively, the light emitting element ED may be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot emission layer located between the first electrode and the second electrode. As another example, the light emitting element ED may be a micro light emitting diode. The first electrode of the light emitting element ED may be electrically connected to the node N3B. The second electrode of the light emitting element ED may be connected to the common voltage line VSL. The second electrode of the light emitting element ED may receive a common voltage ELVSS from the common voltage line VSL.

[0245] The second transistor T2 may be turned on by the first gate signal GS1 of the first gate line GL1 to electrically connect the data line DL with the second electrode of the first capacitor C1'. The gate electrode of the second transistor T2 may be electrically connected to the first gate line GL1, the source electrode of the second transistor T2 may be electrically connected to the data line DL, and the drain electrode of the second transistor T2 may be electrically connected to the second electrode of the first capacitor C1'. The data line DL may transmit a data voltage Vdt or a reference voltage Vref.

[0246] The sixth transistor T6 can be turned on by the fourth gate signal GS4 of the fourth gate line GL4 to electrically connect the first node N1 with the node N3A. The gate electrode of the sixth transistor T6 can be connected to the fourth gate line GL4, the source electrode of the sixth transistor T6 can be electrically connected to the first node N1, and the drain electrode of the sixth transistor T6 can be electrically connected to the node N3A.

[0247] The seventh transistor T7 may be turned on by the emission signal EM of the emission line EML to electrically connect the node N3A with the node N3B. A gate electrode of the seventh transistor T7 may be electrically connected to the emission line EML, a source electrode of the seventh transistor T7 may be electrically connected to the node N3A, and a drain electrode of the seventh transistor T7 may be electrically connected to the node N3B.

[0248] The fourth transistor T4 may be turned on by the second gate signal GS2 of the second gate line GL2 to electrically connect the node N3B to the initialization line VIL. The gate electrode of the fourth transistor T4 may be electrically connected to the second gate line GL2, the source electrode of the fourth transistor T4 may be electrically connected to the node N3B, and the drain electrode of the fourth transistor T4 may be electrically connected to the initialization line VIL. There may be a plurality of initialization lines VIL, and the plurality of initialization lines VIL may be connected to each other. For example, the initialization line VIL may include a plurality of transverse initialization lines extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of longitudinal initialization lines extending in the second direction DR2 and arranged in the first direction DR1. The transverse initialization lines and the longitudinal initialization lines may be connected to each other.

[0249] The third transistor T3 may be turned on by the emission signal EM of the emission line EML to electrically connect the driving voltage line VDL with the source electrode of the first transistor T1. A gate electrode of the third transistor T3 may be electrically connected to the emission line EML, a source electrode of the third transistor T3 may be electrically connected to the driving voltage line VDL, and a drain electrode of the third transistor T3 may be electrically connected to the source electrode of the first transistor T1.

[0250] The fifth transistor T5 can be turned on by the third gate signal GS3 of the third gate line GL3 to electrically connect the node N3B with the sensing line SSL. The gate electrode of the fifth transistor T5 can be electrically connected to the third gate line GL3, the source electrode of the fifth transistor T5 can be electrically connected to the node N3B, and the drain electrode of the fifth transistor T5 can be electrically connected to the sensing line SSL.

[0251] The second capacitor C2' may be electrically connected between the first node N1 and the driving voltage line VDL. For example, a first electrode of the second capacitor C2' may be electrically connected to the first node N1, and a second electrode of the second capacitor C2' may be electrically connected to the driving voltage line VDL. The second capacitor C2' may store, for example, a reference voltage Vref or a data voltage Vdt supplied from the data line DL through the second transistor T2.

[0252] The first capacitor C1' may be electrically connected between the first node N1 and the drain electrode of the second transistor T2. For example, the first electrode of the first capacitor C1' may be electrically connected to the first node N1, and the second electrode of the first capacitor C1' may be electrically connected to the drain electrode of the second transistor T2. The first capacitor C1' may maintain a threshold voltage of the first transistor T1 detected by the sixth transistor T6.

[0253] When the third transistor T3 , the first transistor T1 , and the seventh transistor T7 are turned on, a driving current is supplied to the light emitting element ED to enable the light emitting element ED to emit light.

[0254] At least one of the first to seventh transistors T1 to T7 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to seventh transistors T1 to T7 may be a p-type MOSFET. As another example, each of the first to seventh transistors T1 to T7 may be an n-type MOSFET. As yet another example, some of the first to seventh transistors T1 to T7 may be p-type MOSFETs, while the other transistors may be n-type MOSFETs.

[0255] Fig. 22 It is shown Fig.21 The timing diagram of the first gate signal GS1 to the fourth gate signal GS4, the emission signal EM, the reference voltage Vref and the initialization voltage Vinit. Fig. 22 In the example shown in , the display device 10 of the present disclosure may operate based on an initialization period P1 , a sensing period P2 , and a turn-off period P3 . Fig. 22 The operation of the display device 10 for detecting defective pixels (eg, during manufacture or testing of the display device 10) may be specifically illustrated, and Fig. 22 The operations shown in may not be used during normal operation of the display device 10 (eg, when the display device 10 is displaying an image).

[0256] The first gate signal GS1, the second gate signal GS2, the third gate signal GS3, the fourth gate signal GS4, and the emission signal EM may have an effective level or an ineffective level for each period. The effective level of each of the signals GS1, GS2, GS3, GS4, and EM may indicate a voltage at a level capable of turning on the corresponding transistor to which the signal is applied. In other words, the signal at an effective level may have a value greater than the threshold voltage of the corresponding transistor. For example, Fig. 22 As shown in , when each of the transistors T1 to T7 is a p-type transistor, the active level of each of the signals GS1, GS2, GS3, GS4, and EM may indicate a low level. The inactive level of each of the signals GS1, GS2, GS3, GS4, and EM may indicate a voltage at a level capable of turning off the corresponding transistor. In other words, the signal at the inactive level may have a value smaller than the threshold voltage of the corresponding transistor. For example, Fig. 22 As shown in , when each of the transistors T1 to T7 is a p-type transistor, the inactive level of each of the signals GS1, GS2, GS3, GS4, and EM may indicate a high level. When each of the transistors T1 to T7 is an n-type transistor, the active level of each of the signals GS1, GS2, GS3, GS4, and EM may indicate a high level, and the inactive level of each of the signals GS1, GS2, GS3, GS4, and EM may indicate a low level.

[0257] In the initialization period P1, the emission signal EM, the first gate signal GS1, the second gate signal GS2 and the fourth gate signal GS4 may each have an effective level, and the third gate signal GS3 may have an ineffective level. For example, in most of the initialization period P1, the emission signal EM, the first gate signal GS1, the second gate signal GS2 and the fourth gate signal GS4 may each have an effective level, and the third gate signal GS3 may have an ineffective level. At this time, for a specific time period in the initialization period P1, the emission signal EM, the first gate signal GS1, the second gate signal GS2 and the fourth gate signal GS4 may each have an effective level, and the third gate signal GS3 may have an ineffective level at the same time. In other words, in the initialization period P1, the effective level of the emission signal EM, the effective level of the first gate signal GS1, the effective level of the second gate signal GS2, the effective level of the fourth gate signal GS4 and the ineffective level of the third gate signal GS3 may overlap with each other in a specific time period. In the initialization period P1, the reference voltage Vref may have a level of the first voltage Vr1. For example, the first voltage Vr1 of the reference voltage Vref may be less than the driving voltage ELVDD.

[0258] The initialization period P1 may include, for example, a first sub-period S1 , a second sub-period S2 , and a third sub-period S3 .

[0259] In the first sub-period S1, the emission signal EM, the first gate signal GS1 and the third gate signal GS3 may each have an inactive level, and the second gate signal GS2 and the fourth gate signal GS4 may each have an active level. In addition, in the first sub-period S1, the reference voltage Vref may have the level of the first voltage Vr1.

[0260] In the second sub-period S2, the emission signal EM, the first gate signal GS1, the second gate signal GS2, and the fourth gate signal GS4 may each have an effective level, and the third gate signal GS3 may have an ineffective level. In addition, in the second sub-period S2, the reference voltage Vref may have a level of the first voltage Vr1. For example, a substantial initialization operation of the initialization period P1 may be performed in the second sub-period S2.

[0261] In the third sub-period S3, the emission signal EM and the first gate signal GS1 may each have an effective level, and the second gate signal GS2, the third gate signal GS3, and the fourth gate signal GS4 may have an ineffective level. In addition, in the third sub-period S3, the reference voltage Vref may have the level of the first voltage Vr1.

[0262] In the sensing period P2, the emission signal EM and the third gate signal GS3 may each have an effective level, and the first gate signal GS1, the second gate signal GS2, and the fourth gate signal GS4 may each have an ineffective level. In addition, in the sensing period P2, the reference voltage Vref may have the level of the first voltage Vr1.

[0263] In the off period P3, the emission signal EM, the first gate signal GS1, the second gate signal GS2, the third gate signal GS3, and the fourth gate signal GS4 may each have a non-active level. In addition, in the off period P3, the reference voltage Vref may have a level of the second voltage Vr2.

[0264] Incidentally, the initialization voltage Vinit may be maintained at a constant level during all periods including the initialization period P1, the sensing period P2, and the off period P3. For example, the initialization voltage Vinit may be a DC voltage that always has a constant level regardless of the period. Herein, the initialization voltage Vinit may be, for example, a DC voltage that is greater than the common voltage ELVSS and less than the driving voltage ELVDD.

[0265] Will refer to Figure 22 to Figure 25 The operation of the display device according to the embodiment of the present disclosure is described. Figure 23 to Figure 25 In FIG. 1 , a transistor surrounded by a relatively thick circle indicates that the transistor is turned on. On the other hand, a transistor surrounded by a dotted circle indicates that the transistor is turned off. In addition, Figure 23 to Figure 25 The arrows in the diagram indicate the flow of current. Figure 23 to Figure 25 The display device may be operable or may be defective, for example, may not include an emissive layer. Figure 23 to Figure 25 The light emitting element ED of the display device may include an anode and does not include an emission layer or a cathode. In other words, the light emitting element ED of the display device may include an anode and does not include an emission layer or a cathode. Fig. 22 The signal Figure 23 to Figure 25 The light emitting element ED of the display device may include a pixel electrode but does not include an emission layer or a common electrode.

[0266] Will refer to Fig. 22 and Fig.23 The operation of the display device in the initialization period P1 is described. Fig.23 The display device is shown in Fig. 22 Operations in the initialization period P1.

[0267] like Fig. 22As shown in, in the second sub-period S2 of the initialization period P1, the emission signal EM, the first gate signal GS1, the second gate signal GS2 and the fourth gate signal GS4 may each have an effective level, and the third gate signal GS3 may have a non-effective level. In addition, in the second sub-period S2, the reference voltage Vref may have the level of the first voltage Vr1.

[0268] like Fig.23 As shown in FIG. 1 , the first gate signal GS1 at an effective level may be applied to the gate electrode of the second transistor T2 through the first gate line GL1 . Accordingly, the second transistor T2 may be turned on.

[0269] like Fig.23 As shown in FIG. 1 , the second gate signal GS2 at the effective level may be applied to the gate electrode of the fourth transistor T4 through the second gate line GL2. Accordingly, the fourth transistor T4 may be turned on.

[0270] like Fig.23 As shown in FIG. 1 , the third gate signal GS3 at the inactive level may be applied to the gate electrode of the fifth transistor T5 through the third gate line GL3 . Accordingly, the fifth transistor T5 may be turned off.

[0271] like Fig.23 As shown in FIG. 1 , the fourth gate signal GS4 at the effective level may be applied to the gate electrode of the sixth transistor T6 through the fourth gate line GL4. Accordingly, the sixth transistor T6 may be turned on.

[0272] like Fig.23 As shown in FIG. 1 , the emission signal EM at an effective level may be applied to the gate electrode of the third transistor T3 and the gate electrode of the seventh transistor T7 through the emission line EML. Accordingly, each of the third transistor T3 and the seventh transistor T7 may be turned on.

[0273] As the second transistor T2, the sixth transistor T6, the seventh transistor T7, the fourth transistor T4 and the third transistor T3 are turned on during the initialization period P1, the gate electrode (e.g., the first node N1) of the first transistor T1, the source electrode of the first transistor T1 and the drain electrode (e.g., the node N3A) of the first transistor T1 may be initialized. For example, the first voltage Vrl from the data line DL may be applied to the first node N1 as the gate electrode of the first transistor T1 through the turned-on second transistor T2 and the first capacitor C1'. In addition, the driving voltage ELVDD from the driving voltage line VDL may be applied to the source electrode of the first transistor T1 through the turned-on third transistor T3. In addition, the initialization voltage Vinit from the initialization line VIL may be applied to the node N3A as the drain electrode of the first transistor T1 through the turned-on fourth transistor T4 and the seventh transistor T7. Accordingly, the voltage of each of the gate electrode of the first transistor T1, the source electrode of the first transistor T1 and the drain electrode of the first transistor T1 may be initialized. For example, the gate electrode of the first transistor T1 may be initialized to the first voltage Vr1 of the reference voltage Vref, the source electrode of the first transistor T1 may be initialized to the driving voltage ELVDD, and the drain electrode of the first transistor T1 may be initialized to the initialization voltage Vinit. Incidentally, the node N3B as the anode of the light emitting element ED may be initialized by the initialization voltage Vinit supplied through the turned-on fourth transistor T4.

[0274] In addition, the first transistor T1 is a p-type transistor, and the first voltage Vr1 of the reference voltage Vref applied to the first node N1 as the gate electrode of the first transistor T1 is less than the driving voltage ELVDD applied to the source electrode of the first transistor T1. Accordingly, during the initialization period P1, the voltage difference between the gate electrode and the source electrode of the first transistor T1 (hereinafter referred to as the gate-source voltage) may be a voltage of negative polarity. Accordingly, in the initialization period P1, the first transistor T1 may be turned on by the gate-source voltage of negative polarity. Therefore, a current path may be generated between the driving voltage line VDL and the initialization line VIL by the turned-on first transistor T1. The voltages of the source electrode and the drain electrode of the first transistor T1 may also be initialized by the current flowing along the current path.

[0275] Will refer to Fig. 22 and Fig.24 The operation of the display device in the sensing period P2 is described. Fig.24 The display device is shown in Fig. 22 The operation in the sensing period P2.

[0276] like Fig. 22As shown in, in the sensing period P2, the emission signal EM and the third gate signal GS3 may each have an effective level, while the first gate signal GS1, the second gate signal GS2 and the fourth gate signal GS4 may each have an ineffective level. In addition, in the sensing period P2, the reference voltage Vref may have the level of the first voltage Vr1.

[0277] like Fig.24 As shown in FIG. 1 , the first gate signal GS1 at the non-active level may be applied to the gate electrode of the second transistor T2 through the first gate line GL1. Accordingly, the second transistor T2 may be turned off.

[0278] like Fig.24 As shown in FIG. 1 , the second gate signal GS2 at the inactive level may be applied to the gate electrode of the fourth transistor T4 through the second gate line GL2. Accordingly, the fourth transistor T4 may be turned off.

[0279] like Fig.24 As shown in FIG. 1 , the third gate signal GS3 at the effective level may be applied to the gate electrode of the fifth transistor T5 through the third gate line GL3 . Accordingly, the fifth transistor T5 may be turned on.

[0280] like Fig.24 As shown in FIG. 1 , the fourth gate signal GS4 at the inactive level may be applied to the gate electrode of the sixth transistor T6 through the fourth gate line GL4. Accordingly, the sixth transistor T6 may be turned off.

[0281] like Fig.24 As shown in FIG. 1 , the emission signal EM at an effective level may be applied to the gate electrode of the third transistor T3 and the gate electrode of the seventh transistor T7 through the emission line EML. Accordingly, each of the third transistor T3 and the seventh transistor T7 may be turned on.

[0282] As the second transistor T2 is turned off, the first node N1 as the gate electrode of the first transistor T1 may be electrically floated, and the first voltage Vrl of the reference voltage Vref applied during the previous period (e.g., the initialization period P1) may be maintained at the floating first node N1. At this time, the first voltage Vr1 of the first node N1 may be maintained by the first capacitor C1' and the second capacitor C2'. The first transistor T1 can be kept turned on by the reference voltage Vref maintained by the first capacitor C1' and the second capacitor C2'.

[0283] As described above, as the third transistor T3, the first transistor T1, the seventh transistor T7, and the fifth transistor T5 are turned on, a current path may be formed between the driving voltage line VDL and the sensing line SSL through the third transistor T3, the first transistor T1, the seventh transistor T7, and the fifth transistor T5. Therefore, a current (e.g., a sensing current) flowing along the driving voltage line VDL, the third transistor T3, the first transistor T1, the seventh transistor T7, the fifth transistor T5, and the sensing line SSL may be formed. The sensing current may be provided to the detector 230 through the sensing line SSL. The detector 230 may receive the sensing current flowing through the third transistor T3, the first transistor T1, the seventh transistor T7, and the fifth transistor T5 via the sensing line SSL, and may determine whether the pixel PX is defective based on the received sensing current. Reference has been made to the above. Fig. 9 The operation of the detector 230 for determining whether a pixel is defective is described.

[0284] Will refer to Fig. 22 and Fig.25 The operation of the display device in the turn-off period P3 is described. Fig.25 The display device is shown in Fig. 22 Operation in the off period P3.

[0285] like Fig. 22 As shown in , in the off period P3, the emission signal EM, the first gate signal GS1, the second gate signal GS2, the third gate signal GS3 and the fourth gate signal GS4 may each have a non-effective level. In addition, in the off period P3, the reference voltage Vref may have a level of the second voltage Vr2.

[0286] like Fig.25 As shown in FIG. 1 , the first gate signal GS1 at the non-active level may be applied to the gate electrode of the second transistor T2 through the first gate line GL1. Accordingly, the second transistor T2 may be turned off.

[0287] like Fig.25 As shown in FIG. 1 , the second gate signal GS2 at the inactive level may be applied to the gate electrode of the fourth transistor T4 through the second gate line GL2. Accordingly, the fourth transistor T4 may be turned off.

[0288] like Fig.25 As shown in FIG. 1 , the third gate signal GS3 at the inactive level may be applied to the gate electrode of the fifth transistor T5 through the third gate line GL3 . Accordingly, the fifth transistor T5 may be turned off.

[0289] like Fig.25 As shown in FIG. 1 , the fourth gate signal GS4 at the inactive level may be applied to the gate electrode of the sixth transistor T6 through the fourth gate line GL4. Accordingly, the sixth transistor T6 may be turned off.

[0290] like Fig.25 As shown in FIG. 1 , the emission signal EM at the non-active level may be applied to the gate electrode of the third transistor T3 and the gate electrode of the seventh transistor T7 through the emission line EML. Accordingly, each of the third transistor T3 and the seventh transistor T7 may be turned off.

[0291] like Fig.25 As shown in , the first transistor T1 can be turned off.

[0292] Pixels in a column that are commonly connected to one sensing line may be sequentially connected to the sensing line. Figure 5 As shown in , a plurality of pixels PX in the first column CL1 may be sequentially connected to the first sensing line SSL1. Specifically, let us define the three pixels PX in the first column CL1 as a first pixel, a second pixel, and a third pixel in reverse order along the second direction DR2 from the top side. If each pixel PX has Fig.24 In the structure shown in , in this order, the third gate signal GS3 may be first applied to the fifth transistor T5 of the first pixel, then the third gate signal GS3 may be applied to the fifth transistor T5 of the second pixel, and then the third gate signal GS3 may be applied to the fifth transistor T5 of the third pixel. Accordingly, the sensing voltage Vs of the pixels PX of the first column CL1 may be sequentially applied to the first sensing line SSL1.

[0293] The display device 10 of the present disclosure may be manufactured to include an emission layer on a pixel electrode, a common electrode on the emission layer, and an encapsulation layer ENC on the common electrode (see Figure 2 ) and the color filter layer CFL on the encapsulation layer ENC (see Figure 2 ). Execute reference Figure 21 to Figure 25 The above-described inspection process can determine whether a pixel is defective. Subsequently, a display device including an emission layer, a common electrode, etc. can operate normally based on an initialization period, a compensation period, and an emission period. The fifth transistor T5 can always remain turned off during normal operation, regardless of the period. As an example, the third gate signal GS3 of the third gate line GL3 connected to the gate electrode of the fifth transistor T5 can be maintained at a non-effective level, regardless of the period. In other words, the third gate signal GS3 may be a DC signal having a level capable of turning off the fifth transistor T5. In addition, a sensing line SSL of a display device including an emission layer, a common electrode, etc. can be connected to a detector 230 or a power supply unit 500, and a DC voltage can be received from the detector 230 or the power supply unit 500.

[0294] It should be noted that all of the pixels PX of the display device including the emission layer and the common electrode may simultaneously receive the third gate signal GS3 at the inactive level.

[0295] Fig.26 : is a view showing an example of a virtual reality device including a display device according to an embodiment. Fig.26 The virtual reality device 1 using the display device 10_1 according to the embodiment is shown. The display device 10_1 can be used, for example, as described above. Figures 1 to 25 Any of the embodiments described.

[0296] Reference Fig.26 The virtual reality device 1 according to the embodiment may be a device in the form of glasses. The virtual reality device 1 according to the embodiment of the present disclosure may include a display device 10_1, a left eye lens 10a, a right eye lens 10b, a support frame 20, temples 30a and 30b, a reflective member 40, and a display housing 50.

[0297] Although Fig.26 The virtual reality device 1 including the temples 30a and 30b is shown, but a head mounted display having a headband instead of the temples 30a and 30b may be adopted as the virtual reality device 1 according to the embodiment of the present disclosure. That is, the virtual reality device 1 is not limited to Fig.26 The virtual reality device shown in the figure can be applied to various electronic devices in various forms.

[0298] The display housing 50 may include a display device 10_1 and a reflective member 40. The image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the user's right eye through the right eye lens 10b. Accordingly, the user may view the virtual reality image displayed on the display device 10_1 through the user's right eye.

[0299] Although in Fig.26 In the example shown in , the display housing 50 is arranged at the right end of the support frame 20, but the embodiments of the present disclosure are not limited thereto. For example, the display housing 50 may be arranged at the left end of the support frame 20. In this case, the image displayed on the display device 10_1 may be reflected by the reflective member 40 and provided to the left eye of the user through the left eye lens 10a. Accordingly, the user can watch the virtual reality image displayed on the display device 10_1 through the left eye. Alternatively, the display housing 50 may be arranged at both the left end and the right end of the support frame 20, respectively. In this case, the user can watch the virtual reality image displayed on the display device 10_1 through both the left eye and the right eye.

[0300] Fig. 27 and Fig.28 is a view showing a head mounted display device employing a display device according to an embodiment of the present disclosure.

[0301] Reference Fig. 27 and Fig.28, the display device 10_2 according to the embodiment may be applied to a head mounted display. The first display device 1100 provides an image to the right eye of the user, and the second display device 1200 provides an image to the left eye of the user. The display device 10_2 may include, for example, Figures 1 to 25 Describes an element or feature.

[0302] The first lens array 1310 may be disposed between the first display device 1100 and the housing cover 1700. The first lens array 1310 may include a plurality of lenses 1311. The plurality of lenses 1311 may be formed as convex lenses that protrude toward the housing cover 1700.

[0303] The second lens array 1410 may be disposed between the second display device 1200 and the housing cover 1700. The second lens array 1410 may include a plurality of lenses 1411. The plurality of lenses 1411 may be formed as convex lenses convex toward the housing cover 1700.

[0304] The display panel housing 1600 may accommodate the first display device 1100, the second display device 1200, the first lens array 1310, and the second lens array 1410. The surface of the display panel housing 1600 may be open to accommodate the first display device 1100, the second display device 1200, the first lens array 1310, and the second lens array 1410.

[0305] The housing cover 1700 is arranged to cover the open surface of the display panel housing 1600. The housing cover 1700 may include a first opening 1710 where the user's left eye is located and a second opening 1720 where the user's right eye is located. Fig. 27 and Fig.28 In the example shown in FIG. 1 , the first opening 1710 and the second opening 1720 are formed in a rectangular shape, but the present disclosure is not limited thereto. The first opening 1710 and the second opening 1720 may be formed in a circular shape or an elliptical shape. Alternatively, the first opening 1710 and the second opening 1720 may be combined to form a single opening.

[0306] The first opening 1710 may be aligned with the second display device 1200 and the second lens array 1410, and the second opening 1720 may be aligned with the first display device 1100 and the first lens array 1310. Therefore, the user may view the image on the second display device 1200 magnified by the second lens array 1410 through the first opening 1710, and view the image on the first display device 1100 magnified by the first lens array 1310 through the second opening 1720.

[0307] The headband 1800 fixes the display panel housing 1600 to the user's head so that the first opening 1710 and the second opening 1720 of the housing cover 1700 are aligned with the user's left and right eyes, respectively. The headband 1800 may be connected to the top, left, and right sides of the display panel housing 1600 .

[0308] At the end of the detailed description, those skilled in the art will recognize that many changes and modifications can be made to the disclosed embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments of the present invention are used only in a general and descriptive sense, and not for the purpose of limitation.

Claims

1. A display device, comprising: Light emitting element; A driving transistor connected between a driving voltage line and an anode of the light emitting element; as well as a fifth transistor connected between the anode of the light emitting element and a sensing line, The fifth transistor is always turned off.

2. The display device according to claim 1, further comprising: a second transistor connected between the data line and the gate electrode of the driving transistor; a third transistor connected between the driving voltage line and a source electrode of the driving transistor; a fourth transistor connected between an initialization line and the anode of the light emitting element; a first capacitor connected between the gate electrode of the driving transistor and the source electrode of the driving transistor; as well as A second capacitor is connected between the gate electrode of the driving transistor and the anode of the light emitting element.

3. The display device according to claim 2, further comprising: a first gate line connected to a gate electrode of the second transistor; an emission line connected to a gate electrode of the third transistor; a second gate line connected to a gate electrode of the fourth transistor; as well as A third gate line is connected to a gate electrode of the fifth transistor.

4. The display device according to claim 3, wherein: The third gate signal of the third gate line has a non-active level.

5. The display device according to claim 3, wherein: In an initialization / writing period, the emission signal of the emission line, the first gate signal of the first gate line, and the second gate signal of the second gate line each have an effective level, and the third gate signal of the third gate line has an ineffective level, wherein, in the compensation period, the first gate signal and the second gate signal each have the valid level, and the emission signal and the third gate signal each have the non-valid level, wherein, in a bypass period, the emission signal and the second gate signal each have the valid level, and the first gate signal and the third gate signal each have the non-valid level, and In which, in the emission period, the emission signal has the effective level, and the first gate signal, the second gate signal and the third gate signal each have the ineffective level.

6. The display device according to claim 5, wherein: In the initialization / writing period and the compensation period, a previous data voltage is applied to the data line, wherein, during the emission period, the current data voltage is applied to the data line, and In the bypass period, a transient data voltage converted from the previous data voltage to the current data voltage is applied to the data line.

7. The display device according to claim 1, further comprising: A detector or a power supply unit is connected to the sensing line.

8. A display device, comprising: Light emitting element; A driving transistor connected between a driving voltage line and an anode of the light emitting element; a second transistor connected between the data line and the gate electrode of the driving transistor; a third transistor connected between the driving voltage line and a source electrode of the driving transistor; as well as A fourth transistor is connected between an initialization / sensing line and the anode of the light emitting element.

9. The display device according to claim 8, further comprising: a first capacitor connected between the gate electrode of the driving transistor and the source electrode of the driving transistor; as well as A second capacitor is connected between the gate electrode of the driving transistor and the anode of the light emitting element.

10. The display device according to claim 9, further comprising: a first gate line connected to a gate electrode of the second transistor; an emission line connected to a gate electrode of the third transistor; as well as A second gate line is connected to a gate electrode of the fourth transistor.

11. The display device according to claim 10, wherein: In the initialization / writing period, the emission signal of the emission line, the first gate signal of the first gate line, and the second gate signal of the second gate line each have an effective level, wherein, in the compensation period, the emission signal has a non-effective level, and the first gate signal and the second gate signal each have the effective level, wherein, in a bypass period, the emission signal and the second gate signal each have the valid level, and the first gate signal has the non-valid level, and Wherein, in the emission period, the emission signal has the effective level, and the first gate signal and the second gate signal each have the ineffective level.

12. The display device according to claim 11, wherein: In the initialization / writing period and the compensation period, a previous data voltage is applied to the data line, wherein, during the emission period, the current data voltage is applied to the data line, and In the bypass period, a transient data voltage converted from the previous data voltage to the current data voltage is applied to the data line.

13. A display device, comprising: Light emitting element; A driving transistor connected between a driving voltage line and an anode of the light emitting element; a first capacitor including a first electrode connected to a gate electrode of the drive transistor; a second transistor connected between the data line and a second electrode of the first capacitor; as well as A fifth transistor is connected between the anode of the light emitting element and a sensing line, wherein the fifth transistor is always kept off.

14. The display device according to claim 13, further comprising: a sixth transistor connected between the gate electrode of the driving transistor and the drain electrode of the driving transistor; a seventh transistor connected between the drain electrode of the driving transistor and the anode of the light emitting element; a fourth transistor connected between an initialization line and the anode of the light emitting element; a third transistor connected between the driving voltage line and a source electrode of the driving transistor; as well as A second capacitor is connected between the driving voltage line and the gate electrode of the driving transistor.

15. The display device according to claim 14, further comprising: a first gate line connected to a gate electrode of the second transistor; a second gate line connected to a gate electrode of the fourth transistor; an emission line connected to a gate electrode of the third transistor and a gate electrode of the seventh transistor; a third gate line connected to a gate electrode of the fifth transistor; as well as A fourth gate line is connected to a gate electrode of the sixth transistor.

16. The display device according to claim 15, wherein: The third gate signal of the third gate line has a non-active level.

17. The display device according to claim 13, further comprising: A detector is connected to the sensing line.

18. A display device comprising: Light emitting element; A driving transistor connected between a driving voltage line and an anode of the light emitting element; a second transistor connected between the data line and the gate electrode of the driving transistor; a third transistor connected between the driving voltage line and a source electrode of the driving transistor; a fourth transistor connected between an initialization line and the anode of the light emitting element; as well as A fifth transistor is connected between the anode of the light emitting element and a sensing line.

19. The display device according to claim 18, further comprising: a first capacitor connected between the gate electrode of the driving transistor and the source electrode of the driving transistor; as well as A second capacitor is connected between the gate electrode of the driving transistor and the anode of the light emitting element.

20. The display device according to claim 18, wherein: The fifth transistor is always kept off.

21. The display device according to claim 18, further comprising: A detector or a power supply unit is connected to the sensing line.

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