A novel ultra-low power consumption multi-state non-destructive read ferroelectric memory container and a preparation method thereof

Abstract

The application belongs to the technical field of novel storage materials and microelectronic devices, and specifically discloses a novel super-low-power multi-state nondestructive reading ferroelectric memory container and a preparation method thereof. The ferroelectric memory container comprises a first electrode, a second electrode and a ferroelectric layer arranged between the first electrode and the second electrode, and the ferroelectric layer is a laminated structure in which hafnium oxide (HfO2) layers and zirconium oxide (ZrO2) layers are alternately arranged. The application has the advantages of simple structure, compatibility with CMOS technology, microminiaturization, low-power nondestructive fast reading, good durability and the like by means of structural design combined with process optimization. The nonvolatile polarization effect of the hafnium-zirconium-oxygen ferroelectric layer can change the dielectric constant, so that nonvolatile adjustable capacitance is formed to store data, the storage window is maximized, the operating voltage is minimized, multi-state storage is realized, and the problems of slow reading and writing speed, high write power consumption and poor durability commonly existing in current nonvolatile memories are effectively overcome.

Description

Technical Field

[0001] This invention relates to the field of novel storage materials and microelectronic devices, specifically to a novel ultra-low power multi-state lossless read ferroelectric memory and its preparation method. Background Technology

[0002] In the future, advanced fields such as high-bandwidth DRAM (Dynamic Random Access Memory), in-memory computing, neural network artificial intelligence, and nonlinear science will place higher demands on the read / write speed, operating voltage, power consumption, and integration of memory devices.

[0003] Compared with current DRAM which uses the charge storage principle, nonferrous memory has a wider range of application prospects because it does not require voltage to maintain the storage state and does not require periodic refresh of the stored content. However, due to the limitations of current material technology, mainstream nonferrous memory on the market generally has disadvantages such as slow read and write speeds and high write power consumption, making it difficult to replace or even surpass current DRAM.

[0004] However, current ferroelectric memories on the market or reported often require a structure of one ferroelectric capacitor and one transistor switch (1T1C). This structure not only affects integration density and process complexity, but also the reading method of the ferroelectric capacitor's polarization current causes the memory state to be rewritten. If the original memory state needs to be maintained, the necessary write-back operation will seriously affect its read / write efficiency and power consumption, and it will not be able to fully utilize the polymorphic storage potential of the ferroelectric material itself. In addition, due to the semiconductor-ferroelectric interface problem, the durability of ferroelectric transistors (FeFETs) is usually much lower than that of DRAM.

[0005] Therefore, introducing a simple, CMOS-compatible, miniaturizable, low-power, lossless read polymorphic memory can provide powerful, high-performance, low-power hardware support for the upcoming era of artificial intelligence (AI). Summary of the Invention

[0006] The purpose of this invention is to provide a novel ultra-low power multi-state lossless read ferroelectric memory and its preparation method to solve the above-mentioned technical problems.

[0007] To achieve the above objectives, the specific technical solution adopted by the present invention is as follows:

[0008] In a first aspect, the present invention provides a novel ultra-low power multi-state lossless read ferroelectric memory, which is a sandwich structure, including a first electrode, a second electrode disposed opposite to each other, and a ferroelectric layer disposed between the first electrode and the second electrode. The ferroelectric layer is a stacked structure of alternating hafnium oxide (HfO2) layers and zirconium oxide (ZrO2) layers.

[0009] Furthermore, the materials of the first electrode and the second electrode are any one of ruthenium, molybdenum, titanium, gold, silver, nickel, platinum, tungsten, aluminum, indium, tin, and chromium, or any one of the alloys of the above materials, oxynitrides, and metal oxide semiconductors.

[0010] Furthermore, the thickness of the first electrode and the second electrode is 2–50 nm.

[0011] Furthermore, the thickness of the ferroelectric layer is 1.5–30 nm, and the thickness of the stacked monolayer is 0.1–2 nm.

[0012] Furthermore, the hafnium-zirconium mixing ratio of the ferroelectric layer is (10-0.1):1.

[0013] Secondly, the present invention provides a method for preparing the above-mentioned novel ultra-low power multi-state lossless readout ferroelectric memory, comprising the following steps:

[0014] S1. Preparation of insulating dielectric layer: An insulating material is grown on the upper surface of a semiconductor as an insulating dielectric layer by means of sol-gel, spin coating, chemical vapor deposition, thermal oxidation, vacuum evaporation, magnetron sputtering, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy.

[0015] S2. Preparation of the first electrode: A conductive dielectric is deposited on the upper surface of the insulating dielectric layer using methods such as spin coating, magnetron sputtering, atomic layer deposition or vacuum evaporation as the first electrode;

[0016] S3. Preparation of ferroelectric layer: Ferroelectric material is prepared as a multistate ferroelectric layer on the upper surface of the first electrode by methods such as sol-gel, spin coating, chemical vapor deposition, thermal oxidation, vacuum evaporation, magnetron sputtering, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy.

[0017] S4. Fabrication of the second electrode: A conductive dielectric is deposited on the upper surface of the ferroelectric layer as the second electrode by methods such as spin coating, magnetron sputtering, atomic layer deposition or vacuum evaporation.

[0018] S5. Three-phase composition control of ferroelectric layer: After completing the above steps, the device is subjected to high-temperature annealing treatment by methods such as rapid heating device, rapid laser pulse, thin film deposition or growth device heating. Under the combined action of thin film stack and electrode, the ferroelectric layer material undergoes phase transformation to form a mixed crystal of ferroelectric phase, antiferroelectric phase and nonferroelectric phase.

[0019] Furthermore, in step S5, the annealing temperature is 350–650°C.

[0020] The present invention has the following beneficial effects:

[0021] 1. This invention utilizes the non-volatile polarization effect of the hafnium-zirconium ferroelectric layer to change its dielectric constant, forming a non-volatile adjustable capacitance value for data storage. Based on this variable capacitance principle and structural design, it achieves the innovative application of hafnium-zirconium ferroelectrics in memory cells. It only requires an MFM structure to operate, unlike existing memory cells such as MFMS and MFMIS, which require semiconductors for read operations. Furthermore, hafnium-zirconium ferroelectric materials exhibit compatibility with CMOS processes and scalability.

[0022] 2. The memory container of this invention can retain data for more than 10 years and can withstand up to 1E11 erase / write cycles, exhibiting good durability.

[0023] 3. The memory container of this invention can achieve clear 4-bit polymorphic storage, which can meet the computing needs of basic neural networks.

[0024] 4. Using ferroelectric memory requires opening the storage window at a fixed read voltage point, that is, adjusting the capacitance value using different erase and write voltages to achieve polymorphic storage. In order to reduce power consumption, the read voltage is usually as small as possible. However, the maximum capacitance window of traditional ferroelectric memory is often far away from the zero voltage point, and the zero point window is the smallest point. The memory of this invention maximizes the capacitance window near the zero point, thereby achieving the purpose of ultra-low read power consumption. Due to the small operating voltage, the read speed is also greatly improved.

[0025] 5. The memory capacitor of this invention only requires one capacitor, without the need for transistors, has a simple structure, low manufacturing cost, and is easy to achieve high integration.

[0026] In summary, this invention uses a first electrode – ferroelectric layer – second electrode as its basic structure. By setting the ferroelectric layer as a stacked structure of alternating HfO2 and ZrO2, and by controlling the thickness, material, hafnium-zirconium mixing ratio of each layer, as well as the annealing treatment during the preparation process, it overcomes the problems of slow read and write speed, high write power consumption, and poor durability that are common in current non-volatile memories. Attached Figure Description

[0027] Figure 1 The present invention provides a schematic structural diagram of a ferroelectric storage capacitor according to a specific embodiment.

[0028] Figure 2 : A schematic structural diagram of the capacitor's internal ferroelectric structure according to a specific embodiment of the present invention.

[0029] Figure 3 The results of opening and enlarging the capacitor storage window in a specific embodiment of the present invention.

[0030] Figure 4 : Illustrative results of capacitive multistable states in specific embodiments of the present invention.

[0031] In the figure: 1-first electrode, 2-second electrode, 3-ferroelectric layer; 31-hafnium oxide layer, 32-zirconia layer. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the technical content of this invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments represent only some, and not all, implementations of this invention. Based on the embodiments of this invention, those skilled in the art can deduce all other implementations without creative work, and these implementations all fall within the scope of protection of this invention.

[0033] The terms such as "first" and "second" used in the embodiments, claims, and drawings of this invention are for descriptive purposes only and should not be construed as indicating or implying a relative order of importance. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to encompass rather than exclude; for example, including a series of steps or units. A method, system, product, or apparatus is not limited to the explicitly listed steps or units but may include other steps or units inherent to these processes, methods, products, or apparatuses. Terms such as "upper," "lower," "left," and "right," etc., are used only to describe the position of components in the drawings and are relative concepts; their specific orientation may be adjusted accordingly depending on the orientation of the components in the drawings.

[0034] The following describes the principle and technical effects of the technical solution of the present invention.

[0035] like Figure 1 As shown, the ferroelectric device provided by the present invention includes a first electrode 1, a ferroelectric layer 3, and a second electrode 2. Figure 1 For illustrative purposes only, the sandwich structures 01 and 02 can be metal electrode-ferroelectric thin film-metal electrode (MFM) structures, but are not limited to this. In some embodiments, electrode 1 and electrode 2 can also be made of materials other than metals, such as metal oxide semiconductors;

[0036] Those skilled in the art will understand that in ferroelectric devices, the first electrode 1 and the second electrode 2 are two electrodes arranged opposite to each other, mainly referring to the materials used to introduce the electric field and to which the ferroelectric layer is attached. The present invention does not limit the shape of the electrodes.

[0037] The ferroelectric layer 3 of the present invention is a stacked structure of hafnium oxide layer 31 and zirconium oxide layer 32. This multi-state ferroelectric layer can ensure the compatibility of ferroelectric devices with CMOS process and the scalability of size.

[0038] Due to their low power consumption, high-density polymorphic memory has a positive impact on memory performance and storage density. The capacitance / dielectric constant of most hafnium oxide-based ferroelectric materials changes with polarization state, and they exhibit a symmetrical maximum capacitance / storage window distribution on both sides of the zero point, such as... Figure 3 As shown in -01, the optimal window point is often far from the zero voltage point, which causes difficulties in reading and writing and increases power consumption;

[0039] This invention utilizes the regulation of metal electrodes (such as the combination of molybdenum and tungsten electrodes in Example 1) to enable the capacitor to have a certain built-in electric field when the applied voltage is zero, thereby bringing the window that was originally far from zero closer to zero. It should be understood that since the built-in electric field generated by the metal has certain limitations, and the growth, phase regulation, and reliability of ferroelectricity are highly dependent on the interface metal, further optimization of the storage window is needed by means of interface optimization.

[0040] This invention also employs annealing, which causes the metal electrode to cavitate oxygen from the ferroelectric thin film, thereby generating a certain number of oxygen vacancies at the metal-ferroelectric layer interface and inducing a built-in electric field. It should be noted that this built-in field is generally unfavorable for traditional ferroelectric applications, but in this invention, it promotes window optimization. The optimized ferroelectric memory capacitor can achieve a maximum zero-point window value. Figure 3 As shown in -02, the peak position in the figure is adjusted by controlling the phase composition (including the thickness of the laminate, the hafnium-zirconium ratio, and the annealing temperature).

[0041] Those skilled in the art will understand that the degree of ferroelectric remanent polarization can be controlled by the magnitude of the polarization electric field. However, the dielectric constant in this invention is influenced by the polarization intensity, such as... Figure 4 As shown in -01, the capacitance value at the zero point can be continuously adjusted from the maximum value to the minimum value in the current window;

[0042] It should be understood that a positive voltage can increase the capacitance value, which can be regarded as an operation that increases the value of the memory capacitor, while a negative voltage can decrease the capacitance value, which can be regarded as an operation that decreases the value of the memory capacitor; the capacitance value of the memory capacitor after the write voltage is removed is determined by the maximum applied voltage value.

[0043] It is worth noting that the memory container of the present invention only requires a small voltage pulse (less than 0.1V) to charge the capacitor for reading the stored value. The integral of current and time (charge amount) can correspond to the current stored value of the memory.

[0044] like Figure 4 As shown in -02, the memory container of the present invention can achieve clear 4-bit polymorphic storage, which can meet the computing needs of basic neural networks.

[0045] It should be noted that, compared with existing memory devices, the memory container of this invention has many advantages:

[0046] Unlike current mainstream non-volatile lossless read memory such as FLASH, the method of controlling the dielectric constant of the memory container in this invention has more prominent advantages, with lower erase and write voltages (only about 1V above the polarization voltage of ferroelectric materials are needed, while mainstream FLASH requires more than 5V).

[0047] Compared to other emerging memory technologies such as resistive random access memory (RRAM), this memory device offers a significant advantage in read / write power consumption. Unlike resistive devices, capacitive devices inherently limit the total charge flowing through them, thus constraining power consumption. During writing, the total charge flowing through the device is primarily determined by the ferroelectric polarization charge. During reading, the current automatically stops when the charge reaches the upper limit of the capacitor's storage capacity.

[0048] The read and write speeds also offer significant advantages. As those skilled in the art will understand, the intrinsic polarization speed (write operation) of ferroelectric materials can reach the nanosecond level. Similar to DRAM, the read operation of the memory container of this invention is similar to the write operation of DRAM, i.e., charging the capacitor (which can usually be completed in the nanosecond level). Therefore, it has the potential to replace or even surpass DRAM in performance.

[0049] The data retention capability is determined by the ferroelectric material, which can typically reach more than 10 years. Furthermore, the durability of the memory container of this invention can reach 1E11, which is close to the durability index of current DRAM.

[0050] Compared to most memory types (FLAH, resistive random access memory), especially polymorphic memory, the memory container of this invention does not require an erase operation before the rewrite operation, thus having advantages in write efficiency and power consumption.

[0051] The simpler process structure requires only one capacitor for the core memory device, unlike DRAM and FLAH memories which require FET transistors, resulting in lower manufacturing costs. Experiments revealed that thinning the ferroelectric layer of this memory device to 5nm maintains a higher window and lower operating voltage, achieving high integration and low power consumption.

[0052] The following specific embodiment is provided to illustrate the technical solution of the present invention in more detail.

[0053] Example 1

[0054] This embodiment provides a novel ultra-low power multi-state lossless read ferroelectric memory container, which possesses the aforementioned technical effects and advantages. Its structure is as follows: Figure 1 -02 and Figure 2As shown, the electrode includes a first electrode 1 and a second electrode 2 disposed opposite to each other, and a ferroelectric layer 3 disposed between the first electrode 1 and the second electrode 2. The first electrode 1 is made of molybdenum and has a thickness of 50 nm; the second electrode 2 is made of tungsten and has a thickness of 50 nm. The ferroelectric layer 3 is a stacked structure of alternating hafnium oxide layers 31 and zirconium oxide layers 32; the thickness of the ferroelectric layer 3 is 6 nm, and the thickness of a single stacked layer is 1.2 nm; the hafnium-zirconium mixing ratio of the ferroelectric layer 3 is 0.7:1.

[0055] The ferroelectric memory capacitor is prepared by the following method:

[0056] S1. Preparation of insulating dielectric layer: Silicon dioxide insulating material is grown on the upper surface of the semiconductor by CVD deposition as an insulating dielectric layer;

[0057] S2. Preparation of the first electrode: A conductive dielectric is deposited on the upper surface of the insulating dielectric layer using a PVD method as the first electrode;

[0058] S3. Preparation of ferroelectric layer: Ferroelectric material is prepared as a multi-state ferroelectric layer on the upper surface of the first electrode by atomic layer deposition.

[0059] S4. Fabrication of the second electrode: A conductive dielectric is deposited on the upper surface of the ferroelectric layer using a PVD method as the second electrode;

[0060] S5. Three-phase composition control of ferroelectric layer: After completing the above steps, the device is subjected to high-temperature treatment at 500℃ by rapid annealing. Under the combined action of the thin film stack and the electrode, the ferroelectric layer material undergoes a phase transformation to form a mixed crystal of ferroelectric phase, antiferroelectric phase and nonferroelectric phase.

[0061] In summary, the above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A novel ultra-low power multi-state lossless read ferroelectric memory container, characterized in that: It includes a first electrode and a second electrode disposed opposite to each other, and a ferroelectric layer disposed between the first electrode and the second electrode, wherein the ferroelectric layer is a stacked structure of alternating hafnium oxide layer and zirconium oxide layer; The thickness of the first electrode and the second electrode is 2 to 50 nm; the materials of the first electrode and the second electrode are any one of ruthenium, molybdenum, titanium, gold, silver, nickel, platinum, tungsten, aluminum, indium, tin, and chromium, or any one of the alloys of the above materials, oxynitrides, and metal oxide semiconductors. The thickness of the ferroelectric layer is 1.5–30 nm, the thickness of the stacked monolayer is 0.1–2 nm, and the hafnium-zirconium mixing ratio of the ferroelectric layer is (10–0.1):1; The ferroelectric layer is subjected to high-temperature annealing at 350–650°C. Under the combined action of the thin film stack and the electrode, the ferroelectric layer material undergoes a phase transformation to form a mixed crystal of ferroelectric, antiferroelectric, and nonferroelectric phases.

2. The method for preparing the novel ultra-low power multi-state lossless readout ferroelectric memory capacitor as described in claim 1, characterized in that: Includes the following steps: S1. Preparation of insulating dielectric layer: An insulating material is grown on the upper surface of the semiconductor as an insulating dielectric layer; S2. Fabrication of the first electrode: A conductive dielectric is deposited on the upper surface of the insulating dielectric layer as the first electrode; S3. Fabrication of a ferroelectric layer: A ferroelectric material is fabricated on the upper surface of the first electrode as a multi-state ferroelectric layer; S4. Fabrication of the second electrode: A conductive dielectric is deposited on the upper surface of the ferroelectric layer as the second electrode; S5. Three-phase composition control of ferroelectric layer: After completing the above steps, the device is subjected to high-temperature annealing treatment at 350-650℃. Under the combined action of the thin film stack and the electrode, the ferroelectric layer material undergoes a phase transformation to form a mixed crystal of ferroelectric phase, antiferroelectric phase and nonferroelectric phase.

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