Array substrate, electromagnetic touch display device and driving method of electromagnetic touch display device

Abstract

The invention discloses an array substrate, an electromagnetic touch display device and a driving method thereof. The array substrate comprises a substrate body, a source-drain metal layer, a common electrode layer located on the side, away from the substrate body, of the source-drain metal layer, and a plurality of first electromagnetic wires located on the side, facing the substrate body, of the common electrode layer. The source-drain metal layer comprises a plurality of data lines, and the common electrode layer comprises a plurality of first strip-shaped common electrode columns; each first electromagnetic wire is arranged corresponding to one of the multiple data lines, the multiple first electromagnetic wires and the multiple first strip-shaped common electrode columns are arranged in a one-to-one correspondence mode, and for the data lines, the first strip-shaped common electrode columns and the first electromagnetic wires which correspond to one another, the first electromagnetic wires are arranged in a one-to-one correspondence mode; and in an area clamped by two straight lines which pass through two end parts of each first strip-shaped common electrode and extend along the first direction, orthographic projections of the first electromagnetic wires and the data lines on the substrate body fall into orthographic projections of the first strip-shaped common electrodes on the substrate body. Therefore, the first strip-shaped common electrode can shield the first electromagnetic wire.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an array substrate, an electromagnetic touch display device and a driving method thereof. Background Art

[0002] Electromagnetic touch usually uses an electromagnetic pen and an electromagnetic touch panel to achieve touch function. The panel contains a multi-layer electromagnetic coil structure, a pressure sensor at the pen tip and an electromagnetic field sending device. When the electromagnetic pen touches the display surface, the sensor inside the panel can determine the touch point position information of the electromagnetic pen in three-dimensional space by calculating the electromagnetic changes, and achieve accurate and delicate writing experience. Summary of the invention

[0003] In order to solve the problem of liquid crystal deflection caused by the potential difference between the electromagnetic wiring and other layers of metal being greater than the threshold voltage of the liquid crystal, the embodiments of the present disclosure provide an array substrate, an electromagnetic touch display device and a driving method thereof, which can shield the electromagnetic wiring or reduce the potential difference between the electromagnetic wiring and other layers of metal, thereby improving the display effect.

[0004] At least one embodiment of the present disclosure provides an array substrate, comprising: a base substrate; a source-drain metal layer, located on the base substrate, comprising a plurality of data lines arranged in a first direction and extending in a second direction, wherein the first direction and the second direction are arranged crosswise; a common electrode layer, located on a side of the source-drain metal layer away from the base substrate, comprising a plurality of first strip-shaped common electrodes extending in the second direction, wherein the plurality of first strip-shaped common electrodes are arranged in an array on the base substrate to form a plurality of first strip-shaped common electrode columns; a plurality of first electromagnetic traces, arranged in the first direction and extending in the second direction, and located on the common electrode layer; The electrode layer faces the side of the base substrate; each of the multiple first electromagnetic routings is arranged corresponding to one of the multiple data lines, and the multiple first electromagnetic routings are arranged one-to-one with the multiple first strip common electrode columns. For the data lines, the first strip common electrode columns and the first electromagnetic routing that correspond to each other, in an area sandwiched by two straight lines passing through the two ends of each of the first strip common electrodes and extending along the first direction, the orthographic projections of the first electromagnetic routing and the data lines on the base substrate fall within the orthographic projections of the first strip common electrodes on the base substrate.

[0005] For example, in an array substrate provided by an embodiment of the present disclosure, the first strip-shaped common electrodes are continuously arranged in a direction parallel to the base substrate and perpendicular to the extending direction of the first strip-shaped common electrodes.

[0006] For example, in the array substrate provided by an embodiment of the present disclosure, for the data lines, the first strip common electrode columns and the first electromagnetic routing lines that correspond to each other, in an area sandwiched by two straight lines passing through the two ends of each of the first strip common electrodes and extending along the first direction, the orthographic projection of the interval between the first electromagnetic routing lines and the data lines on the base substrate falls within the orthographic projection of the first strip common electrode on the base substrate.

[0007] For example, in an array substrate provided by an embodiment of the present disclosure, the common electrode layer also includes a plurality of second strip common electrodes extending along the second direction, and the plurality of second strip common electrodes are arranged in an array on the base substrate to form a plurality of second strip common electrode columns, and each of the plurality of second strip common electrode columns is at least partially overlapped with one of the plurality of data lines, and the data line at least partially overlapped with the second strip common electrode column and the data line corresponding to the first electromagnetic routing are different data lines.

[0008] For example, in an array substrate provided by an embodiment of the present disclosure, at least one second strip-shaped common electrode column is disposed between every two adjacent first strip-shaped common electrode columns.

[0009] For example, in an array substrate provided by an embodiment of the present disclosure, two second strip-shaped common electrode columns are disposed between every two adjacent first strip-shaped common electrode columns.

[0010] For example, in an array substrate provided by an embodiment of the present disclosure, the width of the second strip-shaped common electrode in the first direction is smaller than the width of the first strip-shaped common electrode in the first direction.

[0011] For example, in an array substrate provided by an embodiment of the present disclosure, the plurality of first electromagnetic wirings are located in the source-drain metal layer, and each of the plurality of first electromagnetic wirings is disposed adjacent to one of the plurality of data lines.

[0012] For example, an array substrate provided by an embodiment of the present disclosure also includes: a gate layer, located between the base substrate and the source-drain metal layer, including a plurality of gate lines extending along the first direction and arranged along the second direction; a gate insulating layer, located on a side of the gate layer away from the base substrate; and a first interlayer insulating layer, located on a side of the source-drain metal layer away from the base substrate; a first conductive layer, located on a side of the first interlayer insulating layer away from the base substrate; a second interlayer insulating layer, located on a side of the first conductive layer away from the base substrate; and a plurality of second electromagnetic routing lines, located in the first conductive layer, extending along the first direction and arranged along the second direction, each of the plurality of second electromagnetic routing lines being arranged corresponding to one of the plurality of gate lines.

[0013] For example, in the array substrate provided by an embodiment of the present disclosure, the common electrode layer also includes a plurality of common electrode patterns, and the plurality of common electrode patterns are arranged in an array on the base substrate to form a plurality of common electrode pattern rows and a plurality of common electrode pattern columns, and each of the plurality of common electrode pattern columns is located between adjacent second strip common electrode columns or between adjacent first strip common electrode columns and second strip common electrode columns.

[0014] For example, in an array substrate provided by an embodiment of the present disclosure, the common electrode pattern includes a plurality of strip electrodes arranged along the first direction and extending along the second direction, a slit is provided between two adjacent strip electrodes, and an orthographic projection of at least one end of the slit of each common electrode pattern on the base substrate at least partially overlaps with an orthographic projection of the second electromagnetic trace on the base substrate.

[0015] For example, an array substrate provided by an embodiment of the present disclosure also includes: a plurality of pixel electrodes, which are arranged in an array along the first direction and the second direction, and are arranged one-to-one with the plurality of common electrode patterns; the source-drain metal layer also includes a plurality of drain electrodes, which are arranged in an array along the first direction and the second direction, and are arranged one-to-one with the plurality of pixel electrodes; the orthographic projection of the drain electrode on the base substrate overlaps with the orthographic projection of one of the plurality of gate lines on the base substrate; the drain electrode includes a connecting portion, the orthographic projection of the connecting portion on the base substrate overlaps with the orthographic projection of the corresponding pixel electrode on the base substrate to be connected to the pixel electrode; the connecting portion of the drain electrode overlapping with the same gate line and the second electromagnetic routing arranged corresponding to the gate line are respectively located on both sides of the center line of the gate line along the second direction.

[0016] For example, in an array substrate provided in an embodiment of the present disclosure, the gate layer further includes a plurality of common electrode lines extending along the first direction and arranged along the second direction, and each of the plurality of common electrode lines is disposed adjacent to one of the plurality of gate lines.

[0017] For example, in an array substrate provided by an embodiment of the present disclosure, each of the multiple second electromagnetic wires is arranged corresponding to one of the multiple common electrode lines, the second electromagnetic wire is consistent with the extension direction of the corresponding common electrode line, and the ratio of the overlapping area of ​​the orthographic projection of the second electromagnetic wire on the base substrate and the orthographic projection of the common electrode line on the base substrate to the orthographic projection area of ​​the common electrode line on the base substrate is greater than or equal to 80%.

[0018] For example, in the array substrate provided by an embodiment of the present disclosure, the orthographic projection of the common electrode line on the base substrate includes a first boundary segment that is farthest from the center line of a gate line adjacent to the common electrode line, and the orthographic projection of the second electromagnetic trace corresponding to the gate line on the base substrate includes a second boundary segment that is farthest from the center line of the gate line, and the distance between the first boundary segment and the center line of the gate line is greater than or equal to the distance between the second boundary segment and the center line of the gate line.

[0019] For example, in an array substrate provided by an embodiment of the present disclosure, the gate line includes a plurality of protrusions, the protrusions protrude toward corresponding common electrode lines, the common electrode lines include a plurality of bends, the plurality of bends are arranged in one-to-one correspondence with the protrusions and bend away from the protrusions, the common electrode lines also include a plurality of transverse connecting portions, two adjacent bends are connected by the transverse connecting portions, the plurality of bends include a plurality of first bends and a plurality of second bends, in a plane parallel to the base substrate, the first strip-shaped common electrode column passes through the first bend, the second strip-shaped common electrode column passes through the second bend, and the size of the first bend in the first direction is larger than the size of the second bend in the first direction.

[0020] For example, an array substrate provided by an embodiment of the present disclosure also includes: a gate layer, located between the base substrate and the source-drain metal layer, including a plurality of gate lines extending along the first direction and arranged along the second direction; a gate insulating layer, located on a side of the gate layer away from the base substrate; a first interlayer insulating layer, located on a side of the source-drain metal layer away from the base substrate; a second conductive layer, located on a side of the first interlayer insulating layer away from the base substrate; and a third interlayer insulating layer, located on a side of the second conductive layer away from the base substrate; the plurality of first electromagnetic routing lines are located in the second conductive layer, and each of the plurality of first electromagnetic routing lines is at least partially overlapped with one of the plurality of data lines.

[0021] For example, the array substrate provided by one embodiment of the present disclosure also includes: a first conductive layer, located on the side of the gate insulation layer away from the base substrate; a second interlayer insulation layer, located on the side of the first conductive layer away from the base substrate; and a plurality of second electromagnetic wires, located in the first conductive layer, extending along the first direction and arranged along the second direction, each of the plurality of second electromagnetic wires being arranged corresponding to one of the plurality of gate lines.

[0022] At least one embodiment of the present disclosure further provides an electromagnetic touch display device, comprising: an array substrate according to any one of the above items; an opposing substrate, arranged in a box with the array substrate; and a liquid crystal layer, arranged between the array substrate and the opposing substrate.

[0023] At least one embodiment of the present disclosure also provides a driving method for an electromagnetic touch display device, wherein the electromagnetic touch display device includes an array substrate and an opposing substrate which are arranged in a box with each other, and a liquid crystal layer sandwiched between the array substrate and the opposing substrate, the array substrate includes a plurality of first electromagnetic wirings and a common electrode layer, the first electromagnetic wirings are arranged along a first direction and extend along a second direction intersecting the first direction, the driving method includes: providing a common voltage to the common electrode layer; and providing a touch voltage to the plurality of first electromagnetic wirings; the difference between the touch voltage and the common voltage is less than a threshold voltage for rotation of liquid crystal molecules in the liquid crystal layer.

[0024] For example, in a driving method provided in an embodiment of the present disclosure, the array substrate also includes a plurality of second electromagnetic traces and a plurality of common electrode patterns located in the common electrode layer, the plurality of second electromagnetic traces are arranged along a second direction and extend along the first direction, the plurality of common electrode patterns are arranged in an array on the plane of the array substrate, the common electrode pattern includes a plurality of strip electrodes arranged along the first direction and extending along the second direction, a slit is provided between two adjacent strip electrodes, and an orthographic projection of at least one of the slits on the plane of the array substrate at least partially overlaps with an orthographic projection of the second electromagnetic trace on the plane of the array substrate, and the driving method also includes: providing the touch voltage to the plurality of second electromagnetic traces.

[0025] For example, in a driving method provided in an embodiment of the present disclosure, the difference between the touch voltage and the common voltage is less than or equal to 0.5V. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0027] Figure 1 It is a simulated diagram of liquid crystal deflection on a cross-section perpendicular to the longitudinal electromagnetic touch line direction of an electromagnetic touch display product in a normally black mode;

[0028] Figure 2 for Figure 1 The schematic diagram of the array substrate structure shown;

[0029] Figure 3 It is a simulated diagram of liquid crystal deflection on a cross-section plane perpendicular to the horizontal electromagnetic touch line direction of an electromagnetic touch display product in a normally black mode;

[0030] Figure 4 for Figure 3The schematic diagram of the array substrate structure shown;

[0031] Figure 5 A schematic structural diagram of an array substrate provided in one embodiment of the present disclosure;

[0032] Figure 6 for Figure 5 The local structure schematic diagram shown;

[0033] Figure 7 for Figure 5 Schematic diagram of the cross-sectional structure along the cutting line AB;

[0034] Figure 8 A schematic diagram of a partial structure of a first strip-shaped common electrode column provided in an embodiment of the present disclosure;

[0035] Fig. 9 A schematic diagram of a partial structure of another first strip-shaped common electrode column provided in an embodiment of the present disclosure;

[0036] Fig.10 for Figure 5 Schematic diagram of the cross-sectional structure along the cutting line CD;

[0037] Fig.11 for Figure 5 The local structure schematic diagram shown;

[0038] Fig.12 for Figure 5 A simulated diagram of liquid crystal deflection along a cross-section plane perpendicular to the first electromagnetic wiring direction;

[0039] Fig.13 A schematic structural diagram of an array substrate provided in one embodiment of the present disclosure;

[0040] Fig.14 for Fig.13 The local structure schematic diagram shown;

[0041] Fig.15 for Fig.13 Schematic diagram of the cross-sectional structure along the cutting line EF;

[0042] Fig.16 for Fig.13 A schematic diagram of the cross-sectional structure along the cutting line GH;

[0043] Fig.17 for Fig.13 Schematic diagram of the cross-sectional structure along the cutting line IJ;

[0044] Fig.18 A schematic diagram of an electromagnetic touch display device provided by an embodiment of the present disclosure;

[0045] Fig.19A schematic diagram of another electromagnetic touch display device provided by an embodiment of the present disclosure;

[0046] Fig. 20 A flowchart of a driving method of an electromagnetic touch display device provided by an embodiment of the present disclosure;

[0047] Fig.21 A structural schematic diagram of another array substrate is provided for an embodiment of the present disclosure;

[0048] Fig. 22 for Fig.21 Schematic diagram of the cross-sectional structure along the cutting line KL;

[0049] Fig.23 for Fig.21 A schematic diagram of the cross-sectional structure along the cutting line MN; and

[0050] Fig.24 for Fig.21 A simulation diagram of liquid crystal deflection along a cross-section plane perpendicular to the direction of the second electromagnetic wiring. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0052] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0053] Unless otherwise defined, the features such as "parallel", "perpendicular" and "same" used in the embodiments of the present disclosure include the situations of "parallel", "perpendicular", "same" in a strict sense, as well as the situations of "approximately parallel", "approximately perpendicular", "approximately the same", etc., which contain certain errors. For example, the above-mentioned "approximately" may mean that the difference of the compared objects is within 10% or 5% of the average value of the compared objects. When the number of a component or element is not specifically indicated in the following text of the embodiments of the present disclosure, it means that the component or element may be one or more, or may be understood as at least one. "At least one" refers to one or more, and "multiple" refers to at least two. The "same-layer arrangement" in the embodiments of the present disclosure refers to the relationship between multiple film layers formed by the same material after the same step (for example, a one-step patterning process). The "same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.

[0054] Compared with conventional display products, electromagnetic touch display products have added electromagnetic touch coils and common electrode lines in the display area. When the screen displays images, the different signals of the electromagnetic touch line and the common electrode will produce a potential difference. When the new electric field is greater than the threshold voltage of the liquid crystal, it will drive the liquid crystal to deflect, resulting in undesirable light leakage. If the light leakage problem is solved by increasing the size of the black matrix, it will affect the pixel opening rate. In addition, the electromagnetic touch display product contains a multi-layer electromagnetic coil structure, and the complex metal routing will also affect the pixel opening.

[0055] Figure 1 It is a simulated diagram of liquid crystal deflection on a cross-section perpendicular to the longitudinal electromagnetic touch line direction of an electromagnetic touch display product in a normally black mode; Figure 2 for Figure 1 The schematic diagram of the array substrate structure is shown in FIG. Figure 1 and Figure 2 As shown, the upper part of the longitudinal electromagnetic touch line 11 is not covered by the common electrode 12, and the electric field generated by the potential difference between the longitudinal electromagnetic touch line 11 and the common electrode 12 causes the liquid crystal 13 to deflect, resulting in undesirable light leakage when the screen is displaying. Figure 3 It is a simulated diagram of liquid crystal deflection on a cross-section plane perpendicular to the horizontal electromagnetic touch line direction of an electromagnetic touch display product in a normally black mode; Figure 4 for Figure 3 The schematic diagram of the array substrate structure is shown in FIG. Figure 3 and Figure 4 As shown, the upper part of the transverse electromagnetic touch line 14 is covered by the common electrode 12, and the electric field generated by the potential difference between the transverse electromagnetic touch line 13 and the common electrode 12 causes the liquid crystal to deflect, resulting in undesirable light leakage when the screen is displaying.

[0056] In this regard, the embodiments of the present disclosure provide an array substrate, an electromagnetic touch display device and a driving method thereof. The array substrate includes a base substrate, a source-drain metal layer, a common electrode layer and a plurality of first electromagnetic traces. The source-drain metal layer is located on the base substrate, and includes a plurality of data lines arranged along a first direction and extending along a second direction, and the first direction and the second direction are arranged crosswise; the common electrode layer is located on a side of the source-drain metal layer away from the base substrate, and includes a plurality of first strip-shaped common electrodes extending along the second direction, and the plurality of first strip-shaped common electrodes are arranged in an array on the base substrate to form a plurality of first strip-shaped common electrode columns; a plurality of first electromagnetic routing lines are arranged along the first direction and extending along the second direction, and are located on a side of the common electrode layer facing the base substrate; each of the plurality of first electromagnetic routing lines is arranged corresponding to one of the plurality of data lines, and the plurality of first electromagnetic routing lines are arranged one-to-one corresponding to the plurality of first strip-shaped common electrode columns, and for the corresponding data lines, first strip-shaped common electrode columns and first electromagnetic routing lines, in an area sandwiched by two straight lines passing through two ends of each first strip-shaped common electrode and extending along the first direction, the orthographic projections of the first electromagnetic routing lines and the data lines on the base substrate fall within the orthographic projections of the first strip-shaped common electrodes on the base substrate.

[0057] In the array substrate provided by the embodiment of the present disclosure, in the area sandwiched by two straight lines passing through the two ends of each first strip common electrode and extending along the first direction, the first electromagnetic wiring is covered by the first strip common electrode, and the first strip common electrode can shield the first electromagnetic wiring, thereby reducing or avoiding the electric field generated by the potential difference between the first electromagnetic wiring and the common electrode layer from affecting the liquid crystal deflection, further reducing or avoiding the occurrence of undesirable light leakage. At the same time, the first strip common electrode can also shield the data line, reducing or avoiding the electric field generated by the potential difference between the data line and the common electrode layer from affecting the liquid crystal deflection, further reducing or avoiding the occurrence of undesirable light leakage.

[0058] The array substrate, the electromagnetic touch display device and the driving method thereof provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0059] An embodiment of the present disclosure provides an array substrate. Figure 5 A schematic structural diagram of an array substrate provided in one embodiment of the present disclosure; Figure 6 for Figure 5 The local structure schematic diagram shown; Figure 7 for Figure 5 Schematic diagram of the cross-section structure along the cutting line AB. Figures 5 to 7As shown, the array substrate 100 includes a base substrate 110, a source-drain metal layer 130, a common electrode layer 160, and a plurality of first electromagnetic traces 170. The source-drain metal layer 130 is located on the base substrate 110, and includes a plurality of data lines 131 arranged along a first direction X and extending along a second direction Y, wherein the first direction X and the second direction Y are arranged crosswise; the common electrode layer 160 is located on a side of the source-drain metal layer 130 away from the base substrate 110, and includes a plurality of first strip-shaped common electrodes 161 extending along the second direction Y, wherein the plurality of first strip-shaped common electrodes 161 are arranged in an array on the base substrate 110 to form a plurality of first strip-shaped common electrode columns 161C, wherein each first strip-shaped common electrode column 161C of the plurality of first strip-shaped common electrode columns 161C extends along the second direction Y; the plurality of first electromagnetic traces 170 are arranged along the first direction X and extend along the second direction Y, and are located on a side of the common electrode layer 160 facing the base substrate 110. Figure 7 In the cross-sectional view shown, the first electromagnetic routing wire 170 is located in the source-drain metal layer 130, but the present disclosure does not limit this, as long as it is located on the side of the common electrode layer 160 facing the base substrate 110. Each of the plurality of first electromagnetic routing wires 170 is arranged corresponding to one of the plurality of data lines 131, and the plurality of first electromagnetic routing wires 170 are arranged one-to-one corresponding to the plurality of first strip-shaped common electrode columns 161C. For the corresponding data lines 131, first strip-shaped common electrode columns 161C and first electromagnetic routing wires 170, in the area sandwiched by the straight line L1 and the straight line L2 passing through the two ends of each first strip-shaped common electrode 161 and extending along the first direction X, the orthographic projections of the first electromagnetic routing wire 170 and the data line 131 on the base substrate 110 fall within the orthographic projections of the first strip-shaped common electrode 161 on the base substrate 110.

[0060] In the array substrate 100 provided in the embodiment of the present disclosure, in the area sandwiched by the straight line L1 and the straight line L2 passing through the two ends of each first strip common electrode 161 and extending along the first direction X, the first electromagnetic wiring 170 is covered by the first strip common electrode 161, and the first strip common electrode 161 can shield the first electromagnetic wiring 170, thereby reducing or avoiding the electric field generated by the potential difference between the first electromagnetic wiring 170 and the common electrode layer 160 to affect the liquid crystal deflection, further reducing or avoiding the occurrence of undesirable light leakage. At the same time, the first strip common electrode 161 can also shield the data line 131, reducing or avoiding the electric field generated by the potential difference between the data line 131 and the common electrode layer 160 to affect the liquid crystal deflection, further reducing or avoiding the occurrence of undesirable light leakage. It should be noted that the extension along the first direction X, the extension along the second direction Y or the extension along the specified direction mentioned in the present application can be either strictly extending along the direction or approximately extending along the direction. For example, extending approximately along the direction can include that the extension direction at a local position has an angle less than or equal to 10 degrees with the direction, or the local position can have a bending feature or a protruding feature, etc.

[0061] In some examples, such as Figure 5 As shown, the array substrate 100 further includes a plurality of gate lines 121 extending along the first direction X and arranged along the second direction Y, and the plurality of gate lines 121 and the plurality of data lines 131 define a plurality of sub-pixel openings 190, and the plurality of sub-pixel openings 190 are arranged in an array on the base substrate 110. Each of the plurality of first strip-shaped common electrodes 161 is arranged corresponding to one of the plurality of sub-pixel openings 190. For example, the sub-pixel opening 190 may be further defined by the black matrix layer mentioned later to form a light-transmitting area of ​​the sub-pixel corresponding to the sub-pixel opening 190. For example, the orthographic projection of the light-transmitting area on the base substrate falls within the orthographic projection of the sub-pixel opening 190 on the base substrate.

[0062] In some examples, such as Figure 5 As shown, the size of the first strip common electrode 161 in the second direction Y is greater than or equal to the size of the adjacent sub-pixel opening 190 in the second direction Y, thereby better reducing or avoiding the undesirable light leakage caused by liquid crystal deflection.

[0063] Figure 8 FIG. 1 is a partial structural diagram of a first strip common electrode column provided in an embodiment of the present disclosure. Figure 8 As shown, the plurality of first strip-shaped common electrodes 161 of the first strip-shaped common electrode column 161C may be spaced apart from each other in the second direction Y. For example, Figure 8As shown, there is a gap H1 between two adjacent first strip-shaped common electrodes 161 in the second direction Y, and the size of the gap H1 in the first direction X is greater than or equal to the size of the first strip-shaped common electrode 161 in the first direction X. For example, a plurality of first strip-shaped common electrodes 161 of the first strip-shaped common electrode column 161C may be connected through other connection structures of the common electrode layer 160, so that a common signal may be realized. For example, two ends 161a of a first strip-shaped common electrode 161 (only one end 161a of each first strip-shaped common electrode 161 is shown in the figure) are located outside the upper and lower boundaries of the corresponding sub-pixel opening 190 (only one boundary 190a of the upper and lower boundaries of each sub-pixel opening 190 is shown in the figure) in the extension direction of the first strip-shaped common electrode 161. It should be noted that in the present application, two adjacent first strip-shaped common electrodes 161 in the second direction Y refer to the situation where there is no first strip-shaped common electrode 161 between the two first strip-shaped common electrodes 161, but there may be other structures, such as a gap. Figure 8 The sub-pixel opening 190 shown in the figure is only used to exemplify the first strip-shaped common electrode column 161C and the first strip-shaped common electrode 161 , and is not intended to limit the embodiment of the present disclosure.

[0064] Fig. 9 FIG. 1 is a schematic diagram of a partial structure of another first strip common electrode array provided in an embodiment of the present disclosure. Fig. 9 As shown in (a) of FIG. 1 , the plurality of first strip common electrodes 161 of the first strip common electrode column 161C may be continuous in the second direction Y, and there is no gap between two adjacent first strip common electrodes 161 in the second direction Y. Fig. 9 As shown in (b), there is a gap H2 between two adjacent first strip common electrodes 161 in the second direction Y, but the gap H2 and the first strip common electrode column 161C are staggered in the second direction Y, and do not make the two adjacent first strip common electrodes 161 completely discontinuous.

[0065] It should be noted that in Fig. 9 In the example shown, two ends 161a of a first strip common electrode 161 (only one end 161a of each first strip common electrode 161 is shown in the figure) are located outside the upper and lower boundaries of the corresponding sub-pixel opening 190 (only one boundary 190a of the upper and lower boundaries of each sub-pixel opening 190 is shown in the figure) in the extension direction of the first strip common electrode 161. Fig. 9 As shown, every two adjacent first strip-shaped common electrodes 161 of the first strip-shaped common electrode column 161C are connected via a connecting portion 164. Of course, the embodiment of the present disclosure does not limit the structural design and arrangement of the first strip-shaped common electrode column 161C. Fig. 9The sub-pixel opening 190 shown in the figure is only used to exemplify the first strip-shaped common electrode column 161C and the first strip-shaped common electrode 161 , and is not intended to limit the embodiment of the present disclosure.

[0066] In some examples, such as Figures 5 to 7 As shown, the first strip common electrodes 161 are continuously arranged in a direction parallel to the base substrate 110 and perpendicular to the extension direction of the first strip common electrodes 161. Thus, the difficulty of manufacturing the first strip common electrodes 161 can be reduced and the yield rate can be improved.

[0067] In some examples, such as Figures 5 to 7 As shown, for the data line 131, the first strip common electrode column 161C and the first electromagnetic wiring 170 corresponding to each other, in the area sandwiched by the straight line L1 and the straight line L2 passing through the two ends of each first strip common electrode 161 and extending along the first direction X, the orthographic projection of the gap Gap between the first electromagnetic wiring 170 and the data line 131 on the base substrate 110 falls within the orthographic projection of the first strip common electrode 161 on the base substrate 110. Therefore, the electric field generated by the first electromagnetic wiring 170 or the data line 131 through the potential difference between the gap Gap and the common electrode layer 160 can be reduced or avoided to affect the liquid crystal deflection, and the occurrence of undesirable light leakage can be reduced or avoided.

[0068] In some examples, each first electromagnetic trace 170 of the plurality of first electromagnetic traces 170 may correspond to each data line 131 of the plurality of data lines 131 one by one, thereby increasing the number of first electromagnetic traces 170 and improving touch sensitivity. Of course, the disclosed embodiment does not limit the number correspondence and position correspondence between the first electromagnetic traces 170 and the data lines 131. For example, a first electromagnetic trace 170 may be provided every other data lines 131 of the same number, or a first electromagnetic trace 170 may be provided every other data lines 131 of different numbers.

[0069] For example, the array substrate further includes a plurality of sub-pixels, and the plurality of sub-pixels are arranged in a one-to-one correspondence with the plurality of sub-pixel openings. For example, the plurality of sub-pixels include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. For example, the first color, the second color, and the third color are different, for example, the first color is red, the second color is green, and the third color is blue. Of course, the present disclosure includes but is not limited to this, and the first color, the second color, and the third color mentioned above may also be other colors. For example, the plurality of sub-pixels of the array substrate are arranged in an array on the base substrate to form a first color sub-pixel column, a second color sub-pixel column, and a third color sub-pixel column adjacent to each other in sequence.

[0070] For example, the first electromagnetic wiring may be located between the first color sub-pixel column and the second color sub-pixel column. Of course, the present disclosure includes but is not limited to this. For example, the first electromagnetic wiring may be arranged between each adjacent sub-pixel column.

[0071] Fig.10 for Figure 5 Schematic diagram of the cross-section structure along the cutting line CD. Figure 5 , Figure 6 and Fig.10 As shown, the common electrode layer 160 further includes a plurality of second strip common electrodes 162 extending along the second direction Y. The plurality of second strip common electrodes 162 are arranged in an array on the base substrate 110 to form a plurality of second strip common electrode columns 162C. Each second strip common electrode column 162C of the plurality of second strip common electrode columns 162C extends along the second direction Y. Each second strip common electrode column 162C of the plurality of second strip common electrode columns 162C is at least partially overlapped with one of the plurality of data lines 131. The data line 131 at least partially overlapped with the second strip common electrode column 162C and the data line 131 corresponding to the first electromagnetic wiring 170 are different data lines 131. The second strip common electrodes 162 can shield the corresponding data line 131, thereby reducing or preventing the electric field generated by the potential difference between the data line 131 and the common electrode layer 160 from affecting the liquid crystal deflection, and reducing or preventing the occurrence of undesirable light leakage.

[0072] For example, Figure 5 , Figure 7 and Fig.10 As shown, the data line 131 corresponding to the first electromagnetic wiring 170 and the first strip common electrode column 161C is the data line 1310, and the data line 131 corresponding to the second strip common electrode column 162C is 1311. The data line 1310 and the data line 1311 are different data lines 131. The distinction between different data lines here is only to describe whether the data line is adjacent to the first strip common electrode column, and does not limit the function and role of the data line itself.

[0073] In some examples, such as Figure 5 , Figure 6 and Fig.10 As shown, for the data line 131 and the second strip common electrode column 162C corresponding to each other, in the area sandwiched by the straight line L3 and the straight line L4 passing through the two ends of each second strip common electrode 162 and extending along the first direction X, the orthographic projection of the data line 131 on the base substrate 110 falls within the orthographic projection of the second strip common electrode 162 on the base substrate 110. Thus, the electric field generated by the potential difference between the data line 131 and the common electrode layer 160 can be reduced or avoided to affect the deflection of the liquid crystal, and the occurrence of undesirable light leakage can be reduced or avoided.

[0074] In some examples, such as Figure 5 As shown, the size of the second strip common electrode column 162C in the second direction Y is greater than or equal to the size of the adjacent sub-pixel opening 190 in the second direction Y. Thus, the undesirable light leakage caused by liquid crystal deflection can be better reduced or avoided.

[0075] In some examples, the plurality of second strip-shaped common electrodes 162 of the second strip-shaped common electrode column 162C may be spaced apart from each other or may be continuous in the second direction Y. For details, please refer to the present application. Figure 8 , Fig. 9 The description of the first strip common electrode column 161C is not repeated here.

[0076] In some examples, such as Figure 5 As shown, at least one second strip common electrode column 162C is disposed between each adjacent first strip common electrode column 161C. Figure 5 As shown, two second strip common electrode columns 162C are arranged between each adjacent first strip common electrode column 161C. Of course, the disclosed embodiment does not limit the number of second strip common electrode columns 162C between each adjacent first common electrode column. It should be noted that adjacent first strip common electrode columns 161C means that there is no first strip common electrode column 161C between the two first strip common electrode columns 161C, but other structures may be arranged.

[0077] In some examples, such as Figure 5 As shown, the width of the second strip common electrode 162 in the first direction X is smaller than the width of the first strip common electrode 161 in the first direction X. Therefore, under the premise that the first electromagnetic trace 170, the data line 1310 and the data line 1311 can be shielded, the width of the second strip common electrode 162 in the first direction X is set to be smaller than the width of the first strip common electrode 161 in the first direction X, and the space occupied by the width of the second strip common electrode 162 in the first direction X can also be reduced, which is convenient for the design and arrangement of other structures of the common electrode layer 160.

[0078] In some examples, such as Figure 7 As shown, the plurality of first electromagnetic traces 170 are located in the source-drain metal layer 130, and each of the plurality of first electromagnetic traces 170 is disposed adjacent to one of the plurality of data lines 131. The first electromagnetic traces 170 and the data lines 131 are disposed in the same layer and are formed by using the same conductive material layer and the same patterning process, which can reduce the manufacturing process, reduce the thickness of the array substrate 100, and reduce the difficulty of processing.

[0079] In some examples, such as Figure 5As shown, the extending directions of the adjacently arranged first electromagnetic wiring 170 and the data line 131 are substantially consistent. The added first electromagnetic wiring 170 has an impact on the sub-pixel opening 190. By making the extending directions of the first electromagnetic wiring 170 and the data line 131 substantially consistent, the impact of the first electromagnetic wiring 170 on the sub-pixel opening 190 can be reduced as much as possible, and the size occupied by the first electromagnetic wiring 170 and the data line 131 in the first direction X can be reduced as much as possible, so that the size of the sub-pixel opening 190 can be increased as much as possible.

[0080] For example, Figure 5 As shown, the shapes of the first electromagnetic wiring 170 and the data line 131 are substantially the same. Figure 5 As shown, the first electromagnetic trace 170 and the data line 131 are substantially equally spaced. Figure 5 As shown, the data line 131 is at a position with a bending feature or a protruding feature, and the first electromagnetic wiring 170 also has basically the same bending feature or protruding feature at the same position; the data line 131 is at a position with a straight extension, and the first electromagnetic wiring 170 also has basically the same straight extension feature at the same position.

[0081] In some examples, such as Figure 5 and Figure 7 As shown, the size of the interval Gap between the adjacently arranged first electromagnetic traces 170 and the data lines 131 can be the minimum spacing that meets the process requirements, so that the influence of the first electromagnetic traces 170 on the pixel opening 190 can be minimized, the size occupied by the first electromagnetic traces 170 and the data lines 131 in the first direction X can be minimized, and the size of the pixel opening 190 can be maximized. Of course, the embodiment of the present disclosure does not specifically limit the minimum spacing that meets the process requirements and the size of the interval Gap between the first electromagnetic traces 170 and the data lines 131.

[0082] Fig.11 for Figure 5 The local structure diagram is shown in Figure 1. Figure 5 , Figure 7 and Fig.11As shown, the array substrate 100 further includes a gate layer 120, a gate insulating layer 191, a first interlayer insulating layer 192, a first conductive layer 140, a second interlayer insulating layer 193, and a plurality of second electromagnetic traces 180. The gate layer 120 is located between the base substrate 110 and the source-drain metal layer 130, and includes a plurality of gate lines 121 extending along the first direction X and arranged along the second direction Y. The gate insulating layer 191 is located on a side of the gate layer 120 away from the base substrate 110, the first interlayer insulating layer 192 is located on a side of the source-drain metal layer 130 away from the base substrate 110, the first conductive layer 140 is located on a side of the first interlayer insulating layer 192 away from the base substrate 110, the second interlayer insulating layer 193 is located on a side of the first conductive layer 140 away from the base substrate 110, and the plurality of second electromagnetic traces 180 are located in the first conductive layer 140, extending along the first direction X and arranged along the second direction Y. Each of the plurality of second electromagnetic wirings 180 is disposed corresponding to one of the plurality of gate lines 121 .

[0083] In some examples, such as Figure 5 , Figure 7 and Fig.11 As shown, each second electromagnetic wire 180 of the plurality of second electromagnetic wires 180 can correspond to each gate wire 121 of the plurality of gate wires 121 one by one, thereby increasing the number of second electromagnetic wires 180 and improving touch sensitivity. Of course, the disclosed embodiment does not limit the number correspondence and position correspondence between the second electromagnetic wires 180 and the gate wires 121. For example, a second electromagnetic wire 180 can be provided every other gate wires 121 of the same number, or a second electromagnetic wire 180 can be provided every other gate wires 121 of different numbers.

[0084] In some examples, such as Figure 5 and Fig.11 As shown, the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 does not overlap with the orthographic projection of the corresponding gate line 121 on the base substrate 110. Of course, the embodiment of the present disclosure is not limited to this.

[0085] For example, the orthographic projection of the second electromagnetic wiring 180 on the base substrate 110 may be at least partially overlapped with the orthographic projection of the corresponding gate line 121 on the base substrate 110. The added second electromagnetic wiring 180 has an impact on the pixel opening 190. By making the second electromagnetic wiring 180 at least partially overlap with the corresponding gate line 121, the impact of the second electromagnetic wiring 180 on the pixel opening 190 can be reduced as much as possible, and the size occupied by the second electromagnetic wiring 180 and the corresponding gate line 121 in the second direction Y can be reduced as much as possible, so that the size of the pixel opening 190 can be increased as much as possible.

[0086] In some examples, such as Figure 5As shown, the common electrode layer 160 also includes a plurality of common electrode patterns 163, and the plurality of common electrode patterns 163 are arranged in an array on the base substrate 110 to form a plurality of common electrode pattern rows 163R and a plurality of common electrode pattern columns 163C, and each common electrode pattern column 163C of the plurality of common electrode pattern columns 163C is located between adjacent second strip common electrode columns 162C or between adjacent first strip common electrode columns 161C and second strip common electrode columns 162C. It should be noted that in the present application, adjacent second strip common electrode columns 162C means that there will be no second strip common electrode columns 162C between the two second strip common electrode columns 162C, but other structures may be provided. Adjacent first strip common electrode columns 161C and second strip common electrode columns 162C mean that there will be no first strip common electrode columns and second strip common electrode columns 162C between the two, but other structures may be provided.

[0087] In some examples, such as Figure 5 As shown, the common electrode pattern 163 located between the adjacent second strip common electrode columns 162C is connected to the adjacent second strip common electrode columns 162C. The common electrode pattern 163 located between the adjacent first strip common electrode columns 161C and the second strip common electrode columns 162C is connected to the adjacent first strip common electrode columns 161C and the second strip common electrode columns 162C. Thus, the plurality of first strip common electrodes 161, the plurality of second strip common electrodes 162, and the plurality of common electrode patterns 163 on the common electrode layer 160 are connected.

[0088] In some examples, such as Figures 5 to 7 As shown, the common electrode pattern 163 includes a plurality of strip electrodes 1630 arranged along a first direction X and extending along a second direction Y, and a slit 1631 is provided between two adjacent strip electrodes 1630, and the orthographic projection of the end of at least one slit 1631 of each common electrode pattern 163 on the base substrate 110 at least partially overlaps with the orthographic projection of the second electromagnetic trace 180 on the base substrate 110.

[0089] In some examples, such as Figures 5 to 7 and Fig.11As shown, the array substrate 100 further includes a plurality of pixel electrodes 135, which are arranged in an array along the first direction X and the second direction Y, and are arranged one-to-one with the plurality of common electrode patterns 163. The source-drain metal layer 130 further includes a plurality of drain electrodes 132, which are arranged in an array along the first direction X and the second direction Y, and are arranged one-to-one with the plurality of pixel electrodes 135, the orthographic projection of the drain electrode 132 on the substrate substrate 110 overlaps with the orthographic projection of one of the plurality of gate lines 121 on the substrate substrate 110, the drain electrode 132 includes a connecting portion 132a, the orthographic projection of the connecting portion 132a on the substrate substrate 110 overlaps with the orthographic projection of the corresponding pixel electrode 135 on the substrate substrate 110 to connect with the pixel electrode 135, the connecting portion 132a of the drain electrode 132 overlapping with the same gate line 121 and the second electromagnetic trace 180 arranged corresponding to the gate line 121 are respectively located on both sides of the center line of the gate line 121 along the second direction Y.

[0090] In some examples, such as Figure 5 and Fig.11 As shown, the array substrate 100 further includes an active layer 195 , and the active layer 195 is located between the gate insulating layer 191 and the source-drain metal layer 130 .

[0091] In this example, the drain electrode 132, the gate line 121 (or the gate 121a, the gate 121a and the gate line 121 are integrated) overlapping the drain electrode 132, the data line 131 (or the source electrode 131c, the source electrode 131c and the data line 131 are integrated) overlapping the gate line 121, and the active layer 195 overlapping the data line 131 and the drain electrode 132 can form a driving transistor TFT, and the driving transistor is connected to the corresponding pixel electrode 135 through the connecting portion 132a of the drain electrode 132, so as to realize liquid crystal deflection driving. The second electromagnetic wiring 180 and the connecting portion 132a of the drain electrode 132 are respectively arranged on both sides of the center line of the gate line 121, which can prevent the second electromagnetic wiring 180 from affecting the driving transistor, and can also better design and arrange the structure of the driving transistor and the second electromagnetic wiring 180.

[0092] In some examples, such as Figures 5 to 7 , Fig.11 As shown, the gate layer 120 further includes a plurality of common electrode lines 122 extending along the first direction X and arranged along the second direction Y, and each of the plurality of common electrode lines 122 is disposed adjacent to one of the plurality of gate lines 121. By adding the common electrode lines 122, the resistance of the common electrode layer 160 of the array substrate 100 can be reduced, for example, the common electrode lines 122 can be connected to the common electrode layer 160 through vias.

[0093] For example, Figure 5As shown, each common electrode line 122 of the plurality of common electrode lines 122 is disposed in one-to-one correspondence with each gate line 121 of the plurality of gate lines 121. Thus, the resistance of the common electrode layer 160 of the array substrate 100 can be better reduced.

[0094] In some examples, such as Figures 5 to 7 , Fig.11 As shown, the extending directions of the adjacent common electrode lines 122 and gate lines 121 are basically consistent. The added common electrode lines 122 have an impact on the sub-pixel opening 190. By making the common electrode lines 122 and the gate lines 121 extend in basically the same direction, the impact of the common electrode lines 122 on the sub-pixel opening 190 can be reduced as much as possible, and the dimensions occupied by the common electrode lines 122 and the gate lines 121 in the first direction X can be reduced as much as possible, so that the dimensions of the sub-pixel opening 190 can be increased as much as possible.

[0095] For example, the shapes of the common electrode line 122 and the gate line 121 may be substantially the same. Figure 5 and Fig.11 As shown, the common electrode lines 122 and the gate lines 121 are substantially equidistant from each other. For example, where the gate lines 121 are at a bending feature or a protruding feature, the common electrode lines 122 at the same position also have substantially the same bending feature or protruding feature. Where the gate lines 121 are at a straight extension feature, the common electrode lines 122 at the same position also have substantially the same straight extension feature.

[0096] In some examples, such as Figure 5 and Fig.11 As shown, the spacing between the adjacent common electrode lines 122 and gate lines 121 can be the minimum spacing that meets the process requirements, so that the influence of the common electrode lines 122 on the sub-pixel openings 190 can be minimized, the dimensions occupied by the common electrode lines 122 and the gate lines 121 in the first direction X can be minimized, and the dimensions of the sub-pixel openings 190 can be maximized. Of course, the embodiments of the present disclosure do not specifically limit the minimum spacing that meets the process requirements and the spacing dimensions between the common electrode lines 122 and the gate lines 121.

[0097] In some examples, such as Figure 5 and Fig.11As shown, each of the plurality of second electromagnetic traces 180 is arranged corresponding to one of the plurality of common electrode lines 122, the second electromagnetic trace 180 and the corresponding common electrode line 122 extend in the same direction, and the ratio of the overlapping area of ​​the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 and the orthographic projection of the common electrode line 122 on the base substrate 110 to the orthographic projection area of ​​the common electrode line 122 on the base substrate 110 is greater than or equal to 80%. Thus, the second electromagnetic trace 180 can overlap with the common electrode line 122 as much as possible, and the influence of the second electromagnetic trace 180 and the common electrode line 122 on the sub-pixel opening 190 can be reduced as much as possible, so that the size of the sub-pixel opening 190 can be increased as much as possible.

[0098] For example, Figure 5 and Fig.11 As shown, the extension direction of the second electromagnetic wiring 180 and the corresponding common electrode line 122 may be substantially consistent. Figure 5 and Fig.11 As shown, the shapes of the second electromagnetic trace 180 and the common electrode line 122 are basically the same. For example, when the common electrode is at a bent position, the second electromagnetic trace 180 also has a basically consistent bending feature at the same position. When the common electrode is at a straight extension position, the second electromagnetic trace 180 also has a basically consistent straight extension feature at the same position. For example, the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 can completely fall within the orthographic projection of the common electrode line 122 on the base substrate 110.

[0099] In some examples, such as Figure 5 and Fig.11 As shown, each second electromagnetic trace 180 of the plurality of second electromagnetic traces 180 may correspond to each common electrode line 122 of the plurality of common electrode lines 122. Of course, the embodiment of the present disclosure does not limit the number correspondence and position correspondence between the second electromagnetic traces 180 and the common electrode lines 122. For example, a second electromagnetic trace 180 may be provided every other common electrode lines 122 of the same number, or a second electromagnetic trace 180 may be provided every other common electrode lines 122 of different numbers.

[0100] In some examples, such as Figure 5 and Fig.11 As shown, the line width of the second electromagnetic wiring 180 is smaller than the line width of the common electrode line 122 , so that the second electromagnetic wiring 180 and the common electrode line 122 can be overlapped as much as possible.

[0101] In some examples, such as Fig.11As shown, the orthographic projection of the common electrode line 122 on the base substrate 110 includes a first boundary segment L5 that is farthest from the center line of the gate line 121 adjacent to the common electrode line 122, and the orthographic projection of the second electromagnetic wiring 180 corresponding to the gate line 121 on the base substrate 110 includes a second boundary segment L6 that is farthest from the center line of the gate line 121, and the distance between the first boundary segment L5 and the center line of the gate line 121 is greater than or equal to the distance between the second boundary segment L6 and the center line of the gate line 121. Therefore, the farthest boundary segment of the second electromagnetic wiring 180 is closer to the gate line 121 than the farthest boundary segment of the common electrode line 122, so that the influence of the second electromagnetic wiring 180 on the sub-pixel opening 190 can be reduced, and the size of the sub-pixel opening 190 can be increased as much as possible.

[0102] In some examples, the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 is closer to the orthographic projection of the gate line 121 on the base substrate 110 than the orthographic projection of the common electrode line 122 on the base substrate 110. The second electromagnetic trace 180 and the gate line 121 are located in different layers, so that the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 can be closer to the orthographic projection of the gate line 121 on the base substrate 110, thereby reducing the influence of the second electromagnetic trace 180 on the sub-pixel opening 190, and the size of the sub-pixel opening 190 can be increased as much as possible.

[0103] In some examples, such as Figure 5 and Fig.11 As shown, the connection portion 132a of the drain electrode 132 overlapping the same gate line 121 and the common electrode line 122 arranged corresponding to the gate line 121 are respectively located on both sides of the center line of the gate line 121 along the second direction Y. Thus, the common electrode line 1220 can be prevented from affecting the driving transistor, and the structures of the driving transistor and the common electrode line 122 can be better designed and arranged.

[0104] In some examples, such as Figure 5 and Fig.11As shown, the gate line 121 includes a plurality of protrusions 1210, and the protrusions 1210 protrude toward the corresponding common electrode lines 122. The common electrode lines 122 include a plurality of bending portions 1221, and the plurality of bending portions 1221 are arranged in one-to-one correspondence with the protrusions 1210 and bend away from the protrusions 1210. The common electrode lines 122 also include a plurality of transverse connecting portions 1222, and two adjacent bending portions 1221 are connected by the transverse connecting portions 1222. The plurality of bending portions 1221 include a plurality of first bending portions 1221a and a plurality of second bending portions 1221b. In a plane parallel to the base substrate 110, the first strip common electrode column 161C passes through the first bending portion 1221a, and the second strip common electrode column 162C passes through the second bending portion 1221b. The size of the first bending portion 1221a in the first direction X is greater than the size of the second bending portion 1221b in the first direction X. The common electrode line 122 is bent only at the protruding portion 1210 of the gate line 121, so as to minimize the impact on the sub-pixel opening 190. The size of the first bent portion 1221a in the first direction X is greater than the size of the second bent portion 1221b in the first direction X, so that the sizes of the sub-pixel openings 190 are basically the same. It should be noted that in the present application, two adjacent bent portions 1221 refer to no bent portion 1221 between the two bent portions 1221, but there may be other structures, such as a transverse connecting portion 1222.

[0105] In some examples, such as Figure 5 and Fig.11 As shown, the first strip common electrode column 161C has a notch at a position corresponding to the active layer 195. The notch can be referred to as Figure 8 and Fig. 9 As shown, the first strip common electrode column 161C is not completely continuous in the second direction. The second strip common electrode column 162C has a gap at a position corresponding to the active layer 195. The gap can be referred to as Figure 8 and Fig. 9 As shown, the first strip-shaped common electrode column 161C is not completely continuous in the second direction.

[0106] Fig.12 for Figure 5 A simulation diagram of liquid crystal deflection along a cross-section plane perpendicular to the direction of the first electromagnetic wiring. Figure 5 , Figure 7 and Fig.12 As shown, the top of the first electromagnetic wiring 170 is covered by the first strip common electrode 161, and the first electromagnetic wiring 170 is shielded by the first strip common electrode 161. When a voltage signal is applied to the first electromagnetic wiring 170 and the voltage signal is different from the voltage signal of the first strip common electrode 161, the liquid crystal is basically not deflected, thereby reducing or avoiding the occurrence of unexpected light leakage.

[0107] In some examples, such as Figures 5 to 7 , Fig.10 , Fig.11 As shown, the manufacturing method of the array substrate 100 includes: forming a patterned gate layer 120 on a base substrate 110; depositing a gate insulating layer 191 on the gate layer 120; forming a patterned active layer 195 on the gate insulating layer 191; forming a patterned pixel electrode 135 on the active layer 195; forming a patterned source-drain metal layer 130 on the active layer 195, wherein the source-drain metal layer 130 overlaps with the pixel electrode 135 at a connection portion 132a of the drain electrode 132; A first interlayer insulating layer 192 is deposited on the pixel electrode 130 and the pixel electrode 135; a patterned first conductive layer 140 is formed on the first interlayer insulating layer 192, and the first conductive layer 140 includes a second electromagnetic trace 180; a patterned second interlayer insulating layer 193 is formed on the first conductive layer 140; a patterned common electrode layer 160 is formed on the second interlayer insulating layer 193, and the common electrode layer 160 includes a first strip-shaped common electrode 161, a second strip-shaped common electrode 162 and a common electrode pattern 163.

[0108] In some examples, such as Figures 5 to 7 , Fig.10 , Fig.11 As shown, the pixel electrode 135 may be a transparent conductive metal. For example, the common electrode layer 160 may be a transparent conductive metal layer. For example, the transparent conductive metal may be indium tin oxide or the like.

[0109] Fig.13 A schematic structural diagram of an array substrate provided in one embodiment of the present disclosure; Fig.14 for Fig.13 The local structure schematic diagram shown; Fig.15 for Fig.13 Schematic diagram of the cross-section structure along the cutting line EF. Figures 13 to 15As shown, the array substrate 100 includes a base substrate 110 , a gate layer 120 , a gate insulating layer 191 , a source-drain metal layer 130 , a first interlayer insulating layer 192 , a second conductive layer 150 , a third interlayer insulating layer 194 , a common electrode layer 160 and a plurality of first electromagnetic traces 170 . The gate layer 120 is located between the base substrate 110 and the source-drain metal layer 130, and includes a plurality of gate lines 121 extending along the first direction X and arranged along the second direction Y. The gate insulating layer 191 is located on a side of the gate layer 120 away from the base substrate 110. The source-drain metal layer 130 is located on the base substrate 110 and includes a plurality of data lines 131 arranged along the first direction X and extending along the second direction Y. The first interlayer insulating layer 192 is located on a side of the source-drain metal layer 130 away from the base substrate 110. The second conductive layer 150 is located on a side of the first interlayer insulating layer 192 away from the base substrate 110. The third interlayer insulating layer 194 is located on a side of the second conductive layer 150 away from the base substrate 110. The common electrode layer 160 is located on a side of the third interlayer insulating layer 194 away from the base substrate 110 and includes a plurality of first strip-shaped common electrodes 161 extending along the second direction Y. The plurality of first strip-shaped common electrodes 161 are arranged in an array on the base substrate 110. The plurality of first strip common electrode columns 161C are arranged to form a plurality of first strip common electrode columns 161C, each of the plurality of first strip common electrode columns 161C extends along the second direction Y; the plurality of first electromagnetic routing wires 170 are arranged along the first direction X and extend along the second direction Y, and are located in the second conductive layer 150; each of the plurality of first electromagnetic routing wires 170 is arranged corresponding to one of the plurality of data lines 131, and the plurality of first electromagnetic routing wires 170 are arranged one-to-one corresponding to the plurality of first strip common electrode columns 161C. For the data lines 131, the first strip common electrode columns 161C and the first electromagnetic routing wires 170 corresponding to each other, in the area sandwiched by the straight line L1 and the straight line L2 passing through the two ends of each first strip common electrode 161 and extending along the first direction X, the orthographic projections of the first electromagnetic routing wires 170 and the data lines 131 on the base substrate 110 fall within the orthographic projections of the first strip common electrodes 161 on the base substrate 110.

[0110] In the array substrate 100 provided in the embodiment of the present disclosure, in the area sandwiched by the straight line L1 and the straight line L2 passing through the two ends of each first strip common electrode 161 and extending along the first direction X, the first electromagnetic wiring 170 is covered by the first strip common electrode 161, and the first strip common electrode 161 can shield the first electromagnetic wiring 170, thereby reducing or avoiding the electric field generated by the potential difference between the first electromagnetic wiring 170 and the common electrode layer 160 to affect the liquid crystal deflection, reducing or avoiding the occurrence of undesirable light leakage. At the same time, the first strip common electrode 161 can also shield the data line 131, reducing or avoiding the electric field generated by the potential difference between the data line 131 and the common electrode layer 160 to affect the liquid crystal deflection, reducing or avoiding the occurrence of undesirable light leakage.

[0111] In some examples, such as Fig.13 As shown, a plurality of gate lines 121 and a plurality of data lines 131 define a plurality of sub-pixel openings 190 .

[0112] In some examples, such as Fig.13 As shown, the size of the first strip common electrode 161 in the second direction Y is greater than or equal to the size of the adjacent sub-pixel opening 190 in the second direction Y. Thus, the occurrence of undesirable light leakage can be better reduced or avoided.

[0113] In some examples, the plurality of first strip-shaped common electrodes 161 of the first strip-shaped common electrode column 161C may be spaced apart from each other or may be continuous in the second direction Y. For details, please refer to the present application. Figure 8 , Fig. 9 The description of the first strip common electrode column 161C is not repeated here.

[0114] In some examples, each first electromagnetic trace 170 of the plurality of first electromagnetic traces 170 may correspond to each data line 131 of the plurality of data lines 131 one by one, thereby increasing the number of first electromagnetic traces 170 and improving touch sensitivity. Of course, the disclosed embodiment does not limit the number correspondence and position correspondence between the first electromagnetic traces 170 and the data lines 131. For example, a first electromagnetic trace 170 may be provided every other data lines 131 of the same number, or a first electromagnetic trace 170 may be provided every other data lines 131 of different numbers.

[0115] In some examples, such as Fig.15As shown, in the direction perpendicular to the base substrate 110, the corresponding first electromagnetic wiring 170 and the data line 131 are at least partially overlapped. Thus, the influence of the addition of the second electromagnetic wiring 180 on the sub-pixel opening 190 can be minimized, and the size occupied by the first electromagnetic wiring 170 and the data line 131 in the first direction X can be minimized, so that the size of the sub-pixel opening 190 can be maximized. For example, Fig.15 As shown, the orthographic projection of the data line 131 on the base substrate 110 can completely fall within the orthographic projection of the first electromagnetic trace 170 on the base substrate 110. Fig.13 As shown in FIG. 1 , the corresponding first electromagnetic wiring 170 and the data line 131 extend in substantially the same direction. Fig.13 As shown, the shapes of the correspondingly arranged first electromagnetic wiring 170 and the data line 131 are substantially consistent. For example, the orthographic projection of the first electromagnetic wiring 170 on the base substrate 110 may also completely fall within the orthographic projection of the data line 131 on the base substrate 110 .

[0116] Fig.16 for Fig.13 Schematic diagram of the cross-sectional structure along the cutting line GH. Fig.13 , Fig.14 and Fig.16 As shown, the common electrode layer 160 also includes a plurality of second strip common electrodes 162 extending along the second direction Y, and the plurality of second strip common electrodes 162 are arranged in an array on the base substrate 110 to form a plurality of second strip common electrode columns 162C, and each second strip common electrode 162 of the plurality of second strip common electrode columns 162C is at least partially overlapped with one of the plurality of data lines 131, and the data line 131 at least partially overlapped with the second strip common electrode column 162C and the data line 131 corresponding to the first electromagnetic wiring 170 are different data lines 131. Differentiating different data lines here is only to describe whether the data line is arranged corresponding to the first strip common electrode column, and does not limit the function and role of the data line itself. The second strip common electrode 162 can shield the corresponding data line 131, so as to reduce or avoid the electric field generated by the potential difference between the data line 131 and the common electrode layer 160 from affecting the liquid crystal deflection, and reduce or avoid the occurrence of undesirable light leakage.

[0117] For example, Fig.13 and Fig.15 As shown, the data line 131 corresponding to the first electromagnetic wiring 170 and the first strip common electrode column 161C is the data line 1310, and the data line 131 corresponding to the second strip common electrode column 162C is the data line 1311. The data line 1310 and the data line 1311 are different data lines 131.

[0118] In some examples, such as Fig.13 , Fig.14 and Fig.16 As shown, for the data line 131 and the second strip common electrode column 162C corresponding to each other, in the area sandwiched by the straight line L3 and the straight line L4 passing through the two ends of each second strip common electrode 162 and extending along the first direction X, the orthographic projection of the data line 131 on the base substrate 110 falls within the orthographic projection of the second strip common electrode 162 on the base substrate 110. Thus, the electric field generated by the potential difference between the data line 131 and the common electrode layer 160 can be reduced or avoided to affect the deflection of the liquid crystal, and the occurrence of undesirable light leakage can be reduced or avoided.

[0119] In some examples, such as Fig.13 As shown, the size of the second strip common electrode column 162C in the second direction Y is greater than or equal to the size of the adjacent sub-pixel opening 190 in the second direction Y. Thus, the occurrence of undesirable light leakage can be better reduced or avoided.

[0120] In some examples, the plurality of second strip-shaped common electrodes 162 of the second strip-shaped common electrode column 162C may be spaced apart from each other or may be continuous in the second direction Y. For details, please refer to the present application. Figure 8 , Fig. 9 The description of the first strip common electrode column 161C is not repeated here.

[0121] In some examples, such as Fig.13 As shown, at least one second strip common electrode column 162C is disposed between each adjacent first strip common electrode column 161C. Fig.13 As shown, two second strip common electrode columns 162C are disposed between each adjacent first strip common electrode column 161C. Of course, the embodiment of the present disclosure does not limit the number of second strip common electrode columns 162C between each adjacent first common electrode column.

[0122] In some examples, such as Fig.13 and Fig.14 As shown, the width of the second strip common electrode 162 in the first direction X is equal to the width of the first strip common electrode 161 in the first direction X. Of course, the embodiment of the present disclosure is not limited to this. For example, the width of the second strip common electrode 162 in the first direction X may also be smaller than the width of the first strip common electrode 161 in the first direction X. Specifically, it can be designed according to the width of the first electromagnetic wiring 170 and the overlapping relationship between the first electromagnetic wiring 170 and the data line 131.

[0123] In some examples, such as Figures 13 to 16As shown, the base substrate 110 further includes a first conductive layer 140, a second interlayer insulating layer 193 and a plurality of second electromagnetic traces 180. The first conductive layer 140 is located on a side of the gate insulating layer 191 away from the base substrate 110, the second interlayer insulating layer 193 is located on a side of the first conductive layer 140 away from the base substrate 110, and the plurality of second electromagnetic traces 180 are located in the first conductive layer 140, and extend along the first direction X and are arranged along the second direction Y. Each second electromagnetic trace 180 of the plurality of second electromagnetic traces 180 is arranged corresponding to one of the plurality of gate lines 121.

[0124] In some examples, such as Fig.13 As shown, each second electromagnetic wire 180 of the plurality of second electromagnetic wires 180 can correspond to each gate wire 121 of the plurality of gate wires 121 one by one, thereby increasing the number of second electromagnetic wires 180 and improving touch sensitivity. Of course, the disclosed embodiment does not limit the number correspondence and position correspondence between the second electromagnetic wires 180 and the gate wires 121. For example, a second electromagnetic wire 180 can be provided every other gate wires 121 of the same number, or a second electromagnetic wire 180 can be provided every other gate wires 121 of different numbers.

[0125] In some examples, such as Fig.13 As shown, the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 does not overlap with the orthographic projection of the corresponding gate line 121 on the base substrate 110. Of course, the embodiment of the present disclosure is not limited to this.

[0126] For example, the orthographic projection of the second electromagnetic wiring 180 on the base substrate 110 may be at least partially overlapped with the orthographic projection of the corresponding gate line 121 on the base substrate 110. The added second electromagnetic wiring 180 has an impact on the sub-pixel opening 190. By making the second electromagnetic wiring 180 at least partially overlap with the corresponding gate line 121, the impact of the second electromagnetic wiring 180 on the sub-pixel opening 190 can be reduced as much as possible, and the size occupied by the second electromagnetic wiring 180 and the corresponding gate line 121 in the second direction Y can be reduced as much as possible, so that the size of the sub-pixel opening 190 can be increased as much as possible.

[0127] In some examples, such as Fig.13 As shown, the common electrode layer 160 also includes a plurality of common electrode patterns 163, and the plurality of common electrode patterns 163 are arranged in an array on the base substrate 110 to form a plurality of common electrode pattern rows 163R and a plurality of common electrode pattern columns 163C, and each common electrode pattern column 163C of the plurality of common electrode pattern columns 163C is located between adjacent second strip common electrode columns 162C or between adjacent first strip common electrode columns 161C and second strip common electrode columns 162C.

[0128] In some examples, such as Fig.13 As shown, the common electrode pattern 163 located between the adjacent second strip common electrode columns 162C is connected to the adjacent second strip common electrode columns 162C. The common electrode pattern 163 located between the adjacent first strip common electrode columns 161C and the second strip common electrode columns 162C is connected to the adjacent first strip common electrode columns 161C and the second strip common electrode columns 162C. Thus, the plurality of first strip common electrodes 161, the plurality of second strip common electrodes 162, and the plurality of common electrode patterns 163 on the common electrode layer 160 are connected.

[0129] In some examples, such as Figures 13 to 16 As shown, the common electrode pattern 163 includes a plurality of strip electrodes 1630 arranged along a first direction X and extending along a second direction Y, and a slit 1631 is provided between two adjacent strip electrodes 1630, and the orthographic projection of the end of at least one slit 1631 of each common electrode pattern 163 on the base substrate 110 at least partially overlaps with the orthographic projection of the second electromagnetic trace 180 on the base substrate 110.

[0130] Fig.17 for Fig.13 Schematic diagram of the cross-sectional structure along the cutting line IJ. Figures 13 to 17 As shown, the array substrate 100 further includes a plurality of pixel electrodes 135, which are arranged in an array along the first direction X and the second direction Y, and are arranged one-to-one with the plurality of common electrode patterns 163. The source-drain metal layer 130 further includes a plurality of drain electrodes 132, which are arranged in an array along the first direction X and the second direction Y, and are arranged one-to-one with the plurality of pixel electrodes 135, the orthographic projection of the drain electrode 132 on the substrate substrate 110 overlaps with the orthographic projection of one of the plurality of gate lines 121 on the substrate substrate 110, the drain electrode 132 includes a connecting portion 132a, the orthographic projection of the connecting portion 132a on the substrate substrate 110 overlaps with the orthographic projection of the corresponding pixel electrode 135 on the substrate substrate 110 to connect with the pixel electrode 135, the connecting portion 132a of the drain electrode 132 overlapping with the same gate line 121 and the second electromagnetic trace 180 arranged corresponding to the gate line 121 are respectively located on both sides of the center line of the gate line 121 along the second direction Y.

[0131] In this example, the drain electrode 132, the gate line 121 overlapping the drain electrode 132, the data line 131 overlapping the gate line 121, and the active layer can form a driving transistor, and the driving transistor is connected to the corresponding pixel electrode 135 through the connecting portion 132a of the drain electrode 132, so that liquid crystal deflection can be achieved. The second electromagnetic wiring 180 and the connecting portion 132a of the drain electrode 132 are respectively arranged on both sides of the center line of the gate line 121, which can prevent the second electromagnetic wiring 180 from affecting the driving transistor, and can also better design and arrange the structures of the driving transistor and the second electromagnetic wiring 180.

[0132] In some examples, such as Fig.17 As shown, the pixel electrode 135 is arranged on the second interlayer insulating layer 193, and an insulating layer is arranged between the pixel electrode 135 and the source-drain metal layer 130. The pixel electrode 135 and the source-drain metal layer 130 can be connected through an insulating layer via 196 at the position where connection is required.

[0133] In some examples, such as Fig.13 and Fig.14 As shown, the pixel electrode 135 is a plate-shaped structure. Of course, the embodiment of the present disclosure does not limit the structure of the pixel electrode 135.

[0134] In some examples, such as Figures 13 to 17 As shown, the gate layer 120 further includes a plurality of common electrode lines 122 extending along the first direction X and arranged along the second direction Y, and each of the plurality of common electrode lines 122 is disposed adjacent to one of the plurality of gate lines 121. By adding the common electrode lines 122, the resistance of the common electrode layer 160 of the array substrate 100 can be reduced, for example, the common electrode lines 122 can be connected to the common electrode layer 160 through vias.

[0135] For example, Fig.13 As shown, each common electrode line 122 of the plurality of common electrode lines 122 is disposed in one-to-one correspondence with each gate line 121 of the plurality of gate lines 121. Thus, the resistance of the common electrode layer 160 of the array substrate 100 can be better reduced.

[0136] In some examples, such as Fig.13 and Fig.14As shown, the common electrode lines 122 and gate lines 121 disposed adjacently are substantially equidistant. For example, the spacing between the common electrode lines 122 and gate lines 121 disposed adjacently can be the minimum spacing that meets the process requirements. For example, the gate line 121 is at a position of a bending feature or a protruding feature, and the common electrode line 122 also has substantially the same bending feature or protruding feature at the same position, and the gate line 121 is at a position of a straight extension, and the common electrode line 122 also has substantially the same straight extension feature at the same position. The added common electrode line 122 has an impact on the sub-pixel opening 190, and by making the common electrode line 122 and the gate line 121 substantially equidistant, the spacing is the minimum spacing that meets the process requirements, thereby reducing the impact of the common electrode line 122 on the sub-pixel opening 190 as much as possible, reducing the size occupied by the common electrode line 122 and the gate line 121 in the first direction X as much as possible, and increasing the size of the sub-pixel opening 190 as much as possible. Of course, the embodiment of the present disclosure does not impose any specific limitation on the minimum spacing that meets the process requirements and the spacing between the common electrode line 122 and the gate line 121 .

[0137] In some examples, such as Fig.13 and Fig.14 As shown, each of the plurality of second electromagnetic traces 180 is arranged corresponding to one of the plurality of common electrode lines 122, the second electromagnetic trace 180 and the corresponding common electrode line 122 extend in the same direction, and the ratio of the overlapping area of ​​the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 and the orthographic projection of the common electrode line 122 on the base substrate 110 to the orthographic projection area of ​​the common electrode line 122 on the base substrate 110 is greater than or equal to 80%. Thus, the second electromagnetic trace 180 can overlap with the common electrode line 122 as much as possible, and the influence of the second electromagnetic trace 180 and the common electrode line 122 on the sub-pixel opening 190 can be reduced as much as possible, so that the size of the sub-pixel opening 190 can be increased as much as possible.

[0138] In some examples, such as Fig.13 and Fig.14 As shown, the extension direction of the second electromagnetic wiring 180 and the corresponding common electrode line 122 may be substantially consistent. Figure 5 and Fig.11 As shown, the shapes of the second electromagnetic trace 180 and the common electrode line 122 are basically the same. For example, when the common electrode is at a bent position, the second electromagnetic trace 180 also has a basically consistent bending feature at the same position. When the common electrode is at a straight extension position, the second electromagnetic trace 180 also has a basically consistent straight extension feature at the same position. For example, the orthographic projection of the second electromagnetic trace 180 on the base substrate 110 can completely fall within the orthographic projection of the common electrode line 122 on the base substrate 110.

[0139] In some examples, each second electromagnetic trace 180 of the plurality of second electromagnetic traces 180 may correspond to each common electrode line 122 of the plurality of common electrode lines 122. Of course, the disclosed embodiment does not limit the number correspondence and position correspondence between the second electromagnetic traces 180 and the common electrode lines 122. For example, a second electromagnetic trace 180 may be provided every other common electrode lines 122 of the same number, or a second electromagnetic trace 180 may be provided every other common electrode lines 122 of different numbers.

[0140] In some examples, such as Figures 13 to 17 As shown, the manufacturing method of the array substrate 100 includes: forming a patterned gate layer 120 on a base substrate 110; depositing a gate insulating layer 191 on the gate layer 120; forming a patterned active layer on the gate insulating layer 191; forming a patterned source-drain metal layer 130 on the active layer 195; forming a patterned first interlayer insulating layer 192 on the source-drain metal layer 130; forming a patterned first conductive layer 140 on the first interlayer insulating layer 192, the first conductive layer 140 including a second electromagnetic trace 180; forming a patterned second interlayer insulating layer 193 on the first conductive layer 140; A patterned pixel electrode 135 is formed on the second interlayer insulating layer 193, and the pixel electrode 135 is connected to the source-drain metal layer 130 through a via 196; a patterned second conductive layer 150 is formed on the second interlayer insulating layer 193, and the second conductive layer 150 includes a first electromagnetic trace 170; a patterned third interlayer insulating layer 194 is formed on the second conductive layer 150 and the pixel electrode 135; a patterned common electrode layer 160 is formed on the third interlayer insulating layer 194, and the common electrode layer 160 includes a first strip-shaped common electrode 161, a second strip-shaped common electrode 162 and a common electrode pattern 163.

[0141] In some examples, the two ends of the first electromagnetic wire 170 can form a coil loop with the common electrode, and the two ends of the second electromagnetic wire 180 can form coil loops with the common electrode, and multiple first electromagnetic wires 170 and multiple second electromagnetic wires 180 form multiple coil loop arrays. The coil loop array can receive signals, for example, the position of the electromagnetic pen can be calculated based on the change in magnetic flux, thereby realizing the electromagnetic touch function. Of course, the embodiment of the present disclosure does not limit the structural design of electromagnetic touch.

[0142] An embodiment of the present disclosure further provides an electromagnetic touch display device. Fig.18 FIG. 1 is a schematic diagram of an electromagnetic touch display device provided by an embodiment of the present disclosure. Fig.18As shown, the electromagnetic touch display device 200 includes any of the above array substrates 100. Therefore, the electromagnetic touch display device 200 has the beneficial technical effects corresponding to the beneficial technical effects of the above array substrate 100, which will not be described in detail here.

[0143] Fig.19 FIG. 1 is a schematic diagram of another electromagnetic touch display device provided by an embodiment of the present disclosure. Fig.19 As shown, the electromagnetic touch display device 200 includes any of the above array substrates 100, an opposing substrate 210 arranged in a box with the array substrate 100, and a liquid crystal layer 220 arranged between the array substrate 100 and the opposing substrate 210. Figure 5 The array substrate 100 shown is taken as an example, but is not limited thereto.

[0144] In some examples, such as Fig.19 As shown, the counter substrate 210 includes a black matrix layer 211, and the orthographic projections of the first electromagnetic wiring 170 and the data line 131 on the base substrate 110 are located within the orthographic projection of the black matrix layer 201 on the base substrate 110. Through the structural design of the base substrate 110, when solving the problem of undesirable light leakage, it is not necessary to increase the size of the black matrix layer 211, thereby avoiding the influence on the sub-pixel opening. In addition, by making the first electromagnetic wiring 170 and the adjacent data line 131 matching design, and the second electromagnetic wiring 180 and the adjacent gate line 121, the common electrode line 122 matching design, it is possible to reduce the influence of the increase of the first electromagnetic wiring 170 and the second electromagnetic wiring 180 on the sub-pixel opening as much as possible, and minimize the increase in the size of the black matrix layer 211.

[0145] In some examples, a plurality of common electrode patterns arranged in an array may also be located on the counter substrate 200 .

[0146] For example, the electromagnetic touch display device may be a television, a computer, a navigator, a car computer, an electronic picture frame, a tablet computer, a mobile phone, or other electronic product with an electromagnetic touch display function.

[0147] An embodiment of the present disclosure further provides a driving method of an electromagnetic touch display device. Fig. 20 A flowchart of a driving method of an electromagnetic touch display device provided in one embodiment of the present disclosure. The electromagnetic touch display device includes an array substrate and an opposing substrate arranged in a box with each other, and a liquid crystal layer sandwiched between the array substrate and the opposing substrate. The array substrate includes a plurality of first electromagnetic traces and a common electrode layer. The first electromagnetic traces are arranged along a first direction and extend along a second direction intersecting the first direction. Fig. 20 As shown, the driving method includes:

[0148] S100: providing a common voltage to the common electrode layer;

[0149] S200: Providing a touch voltage to multiple first electromagnetic wirings; the difference between the touch voltage and the common voltage is less than the threshold voltage for the rotation of the liquid crystal molecules in the liquid crystal layer. Therefore, the electric field generated by the potential difference between the first electromagnetic wiring and the common electrode layer will not affect the deflection of the liquid crystal, thereby avoiding the occurrence of unexpected light leakage. It should be noted that the two steps of the driving method can be performed simultaneously or in a time-sharing manner, and there is no order between the two steps. For example, a common voltage can be provided to the common electrode layer first, and then a touch voltage can be provided to multiple first electromagnetic wirings, or vice versa. For example, while providing a common voltage to the common electrode layer, a touch voltage can be provided to multiple first electromagnetic wirings.

[0150] For example, when the change in brightness of the display area of ​​the electromagnetic touch display device reaches a set value of the maximum change, the effective value of the applied driving voltage is defined as the threshold voltage. For example, the set value may be 10% or 15%, etc. Of course, the embodiment of the present disclosure is not limited to this, and may also be designed to other acceptable values ​​according to the size and performance requirements of the electromagnetic touch display device.

[0151] For example, the difference between the touch voltage and the common voltage is less than or equal to 0.5 V. Of course, the embodiment of the present disclosure does not specifically limit the value range of the threshold voltage, and can be set according to the size and performance requirements of the specific electromagnetic touch display device.

[0152] In some examples, the array substrate further includes a plurality of second electromagnetic traces, the second electromagnetic traces are arranged along the second direction and extend along the first direction, and the driving method further includes: providing a touch voltage to the plurality of second electromagnetic traces. Thus, the difference between the touch voltage and the common voltage is less than the threshold voltage for the rotation of the liquid crystal molecules, and the electric field generated by the potential difference between the second electromagnetic traces and the common electrode layer will not affect the deflection of the liquid crystal, thereby avoiding the occurrence of undesirable light leakage.

[0153] In some examples, the touch voltage provided to the first electromagnetic trace and the second electromagnetic trace can be equal to the common voltage of the common electrode layer, and the first electromagnetic trace, the second electromagnetic trace and the common electrode layer share a common signal. Thus, there is no potential difference between the first electromagnetic trace and the second electromagnetic trace and the common electrode layer, avoiding the occurrence of undesirable light leakage.

[0154] Fig.21 A structural schematic diagram of another array substrate is provided for an embodiment of the present disclosure; Fig. 22 for Fig.21 Schematic diagram of the cross-section structure along the cutting line KL. Fig.21 and Fig. 22 As shown, the array substrate 100 and Figure 5The difference of the array substrate shown is that the first strip common electrode 161 in the common electrode layer 160 has an opening 197, and at least a part of the orthographic projection of the first electromagnetic trace 170 on the base substrate 110 is located within the orthographic projection of the opening 197 on the plane of the array substrate 100. Therefore, there is no need to change the structural design and opening design of the common electrode layer 160, and by making the difference between the touch voltage and the common voltage smaller than the threshold voltage of the rotation of the liquid crystal molecules, the problem of undesired light leakage can also be solved.

[0155] Fig.23 for Fig.21 Schematic diagram of the cross-sectional structure along the cutting line MN; Fig.24 for Fig.21 A simulation diagram of liquid crystal deflection along a cross-section plane perpendicular to the direction of the second electromagnetic wiring. Fig.21 , Fig.23 and Fig.24 As shown, the array substrate 100 further includes a plurality of second electromagnetic traces 180 and a plurality of common electrode patterns 163, the plurality of common electrode patterns 163 are located in the common electrode layer 160, the plurality of second electromagnetic traces 180 are arranged along the second direction Y and extend along the first direction X, the plurality of common electrode patterns 163 are arranged in an array on the plane of the array substrate 100, the common electrode pattern 163 includes a plurality of strip electrodes 1630 arranged along the first direction X and extending along the second direction Y, a slit 1631 is provided between two adjacent strip electrodes 1630, and the orthographic projection of at least one slit 1631 on the plane of the array substrate 100 at least partially overlaps with the orthographic projection of the second electromagnetic trace 180 on the base substrate 110. A touch voltage is provided to the plurality of second electromagnetic traces 180, so that the difference between the touch voltage and the common voltage is less than the threshold voltage for the rotation of the liquid crystal molecules, and the electric field generated by the potential difference between the second electromagnetic trace 180 and the common electrode layer 160 will not affect the deflection of the liquid crystal, thereby avoiding the occurrence of undesired light leakage.

[0156] For example, Fig.23 and Fig.24 As shown, the voltage signal applied to the second electromagnetic wiring 180 is the same as the voltage signal of the common electrode layer 160. At this time, there is no potential difference between the second electromagnetic wiring 180 and the common electrode layer 160, and the liquid crystal is basically not deflected. Therefore, there will be no unexpected light leakage when the screen is displayed.

[0157] For example, Fig.23 and Fig.24 The thickness of the second electromagnetic wiring 180 shown can be designed according to the requirements, and the embodiment of the present disclosure is not limited to this. For example, the thickness of the second electromagnetic wiring 180 can be increased to reduce the resistance. For example, the thickness of the second electromagnetic wiring 180 can be made substantially consistent with the thickness of the source-drain metal layer 130.

[0158] In some examples, the voltage of the common electrode layer of the electromagnetic touch display device may be a negative voltage, zero, or a positive voltage, which is not limited in the embodiments of the present disclosure.

[0159] There are a few points to note:

[0160] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0161] (2) In the absence of conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0162] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An array substrate, comprising: substrate substrate; A source-drain metal layer, located on the base substrate, includes a plurality of data lines arranged along a first direction and extending along a second direction, wherein the first direction and the second direction are arranged to intersect each other; A common electrode layer, located on a side of the source-drain metal layer away from the base substrate, comprising a plurality of first strip-shaped common electrodes extending along the second direction, wherein the plurality of first strip-shaped common electrodes are arranged in an array on the base substrate to form a plurality of first strip-shaped common electrode columns; a plurality of first electromagnetic traces, arranged along the first direction and extending along the second direction, and located on a side of the common electrode layer facing the base substrate; Each of the plurality of first electromagnetic wirings is arranged corresponding to one of the plurality of data lines, and the plurality of first electromagnetic wirings are arranged one-to-one corresponding to the plurality of first strip-shaped common electrode columns. For the data lines, the first strip common electrode columns and the first electromagnetic routing lines that correspond to each other, in an area sandwiched by two straight lines passing through the two ends of each of the first strip common electrodes and extending along the first direction, the orthographic projections of the first electromagnetic routing lines and the data lines on the base substrate fall within the orthographic projections of the first strip common electrodes on the base substrate.

2. The array substrate according to claim 1, wherein: The first strip-shaped common electrodes are continuously arranged in a direction parallel to the base substrate and perpendicular to an extending direction of the first strip-shaped common electrodes.

3. The array substrate according to claim 1, wherein: For the data lines, the first strip common electrode columns and the first electromagnetic routing wires that correspond to each other, in an area sandwiched by two straight lines passing through the two ends of each of the first strip common electrodes and extending along the first direction, the orthographic projection of the interval between the first electromagnetic routing wires and the data lines on the base substrate falls within the orthographic projection of the first strip common electrode on the base substrate.

4. The array substrate according to any one of claims 1 to 3, wherein: The common electrode layer also includes a plurality of second strip common electrodes extending along the second direction, and the plurality of second strip common electrodes are arranged in an array on the base substrate to form a plurality of second strip common electrode columns, and each of the plurality of second strip common electrode columns is at least partially overlapped with one of the plurality of data lines, and the data line at least partially overlapped with the second strip common electrode column and the data line corresponding to the first electromagnetic routing are different data lines.

5. The array substrate according to claim 4, wherein: At least one second strip-shaped common electrode column is disposed between every two adjacent first strip-shaped common electrode columns.

6. The array substrate according to claim 5, wherein: Two second strip-shaped common electrode columns are disposed between every two adjacent first strip-shaped common electrode columns.

7. The array substrate according to claim 4, wherein: The width of the second strip-shaped common electrode in the first direction is smaller than the width of the first strip-shaped common electrode in the first direction.

8. The array substrate according to claim 4, wherein: The plurality of first electromagnetic routing lines are located in the source-drain metal layer, and each of the plurality of first electromagnetic routing lines is disposed adjacent to one of the plurality of data lines.

9. The array substrate according to claim 8, further comprising: A gate layer, located between the base substrate and the source-drain metal layer, comprising a plurality of gate lines extending along a first direction and arranged along the second direction; A gate insulating layer, located on a side of the gate layer away from the substrate; as well as A first interlayer insulating layer is located on a side of the source / drain metal layer away from the substrate; A first conductive layer, located on a side of the first interlayer insulating layer away from the substrate; A second interlayer insulating layer is located on a side of the first conductive layer away from the substrate; as well as A plurality of second electromagnetic traces are located in the first conductive layer, extending along a first direction and arranged along the second direction, Wherein, each of the plurality of second electromagnetic wires is arranged corresponding to one of the plurality of gate wires.

10. The array substrate according to claim 9, wherein: The common electrode layer also includes a plurality of common electrode patterns, which are arranged in an array on the base substrate to form a plurality of common electrode pattern rows and a plurality of common electrode pattern columns, and each of the plurality of common electrode pattern columns is located between adjacent second strip common electrode columns or between adjacent first strip common electrode columns and second strip common electrode columns.

11. The array substrate according to claim 10, wherein: The common electrode pattern includes a plurality of strip electrodes arranged along the first direction and extending along the second direction, a slit is provided between two adjacent strip electrodes, and an orthographic projection of an end portion of at least one slit of each common electrode pattern on the base substrate at least partially overlaps with an orthographic projection of the second electromagnetic trace on the base substrate.

12. The array substrate according to claim 10, further comprising: A plurality of pixel electrodes are arranged in an array along the first direction and the second direction and are arranged one-to-one corresponding to the plurality of common electrode patterns. The source-drain metal layer further includes a plurality of drain electrodes, which are arranged in an array along the first direction and the second direction and are arranged one-to-one with the plurality of pixel electrodes, and the orthographic projection of the drain electrode on the base substrate overlaps with the orthographic projection of one of the plurality of gate lines on the base substrate. The drain electrode comprises a connecting portion, the orthographic projection of the connecting portion on the base substrate overlaps with the orthographic projection of the corresponding pixel electrode on the base substrate to be connected to the pixel electrode, The connection portion of the drain electrode overlapping the same gate line and the second electromagnetic wiring arranged corresponding to the gate line are respectively located on both sides of the center line of the gate line along the second direction.

13. The array substrate according to claim 12, wherein: The gate layer further includes a plurality of common electrode lines extending along the first direction and arranged along the second direction, and each of the plurality of common electrode lines is disposed adjacent to one of the plurality of gate lines.

14. The array substrate according to claim 13, wherein: Each of the plurality of second electromagnetic wirings is arranged corresponding to one of the plurality of common electrode wires, The second electromagnetic trace is consistent with the corresponding common electrode line in extension direction, and the ratio of the overlapping area of ​​the orthographic projection of the second electromagnetic trace on the substrate and the orthographic projection of the common electrode line on the substrate to the orthographic projection area of ​​the common electrode line on the substrate is greater than or equal to 80%.

15. The array substrate according to claim 14, wherein: The orthographic projection of the common electrode line on the substrate includes a first boundary segment that is farthest from the center line of a gate line adjacent to the common electrode line, and the orthographic projection of the second electromagnetic trace corresponding to the gate line on the substrate includes a second boundary segment that is farthest from the center line of the gate line, and the distance between the first boundary segment and the center line of the gate line is greater than or equal to the distance between the second boundary segment and the center line of the gate line.

16. The base substrate according to claim 14, wherein: The gate line includes a plurality of protrusions, and the protrusions protrude toward the corresponding common electrode lines. The common electrode line includes a plurality of bending portions, which are arranged in one-to-one correspondence with the protruding portions and are bent away from the protruding portions. The common electrode line also includes a plurality of transverse connecting portions, and two adjacent bending portions are connected by the transverse connecting portions. The plurality of bending portions include a plurality of first bending portions and a plurality of second bending portions. In a plane parallel to the base substrate, the first strip-shaped common electrode column passes through the first bending portion, and the second strip-shaped common electrode column passes through the second bending portion. The size of the first bending portion in the first direction is larger than the size of the second bending portion in the first direction.

17. The array substrate according to claim 4, further comprising: A gate layer, located between the base substrate and the source-drain metal layer, comprising a plurality of gate lines extending along a first direction and arranged along the second direction; A gate insulating layer, located on a side of the gate layer away from the substrate; A first interlayer insulating layer is located on a side of the source / drain metal layer away from the substrate; A second conductive layer is located on a side of the first interlayer insulating layer away from the substrate; as well as A third interlayer insulating layer is located on a side of the second conductive layer away from the substrate; The plurality of first electromagnetic wirings are located in the second conductive layer, and each of the plurality of first electromagnetic wirings at least partially overlaps with one of the plurality of data lines.

18. The array substrate according to claim 17, further comprising: A first conductive layer is located on a side of the gate insulating layer away from the substrate; A second interlayer insulating layer is located on a side of the first conductive layer away from the substrate; as well as A plurality of second electromagnetic traces are located in the first conductive layer, extending along a first direction and arranged along the second direction, Wherein, each of the plurality of second electromagnetic wires is arranged corresponding to one of the plurality of gate wires.

19. An electromagnetic touch display device, comprising: The array substrate according to any one of claims 1 to 18; An opposing substrate is arranged in a box with the array substrate; as well as The liquid crystal layer is arranged between the array substrate and the counter substrate.

20. A driving method for an electromagnetic touch display device, the electromagnetic touch display device comprising an array substrate and an opposing substrate arranged opposite to each other and a liquid crystal layer sandwiched between the array substrate and the opposing substrate, the array substrate comprising a plurality of first electromagnetic traces and a common electrode layer, the first electromagnetic traces being arranged along a first direction and extending along a second direction intersecting the first direction, the driving method comprising: Providing a common voltage to the common electrode layer; as well as Providing a touch voltage to the plurality of first electromagnetic wirings; Wherein, the difference between the touch voltage and the common voltage is smaller than a threshold voltage for the rotation of liquid crystal molecules in the liquid crystal layer.

21. The driving method according to claim 20, wherein: The array substrate further includes a plurality of second electromagnetic traces and a plurality of common electrode patterns located in the common electrode layer, the plurality of second electromagnetic traces are arranged along a second direction and extend along the first direction, the plurality of common electrode patterns are arranged in an array on the plane of the array substrate, the common electrode pattern includes a plurality of strip electrodes arranged along the first direction and extending along the second direction, a slit is provided between two adjacent strip electrodes, and an orthographic projection of at least one of the slits on the plane of the array substrate at least partially overlaps with an orthographic projection of the second electromagnetic trace on the plane of the array substrate, and the driving method further includes: The touch voltage is provided to the plurality of second electromagnetic traces.

22. The driving method according to claim 20 or 21, wherein: A difference between the touch voltage and the common voltage is less than or equal to 0.5V.

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