Parameter value optimization in memory subsystem

Abstract

The invention relates to parameter value optimization in a memory subsystem. A processing device operatively coupled with a memory device determines a current workload characteristic of the memory device. The processing device further determines a first set of one or more parameter values that satisfy a threshold workload criterion associated with the memory device by processing a trainable classifier of the current workload characteristics. The processing device further configures a firmware component of the memory device with the first set of one or more parameter values.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to parameter value optimization in memory subsystems. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present disclosure relates to a system comprising: a memory device; and a processing device operatively coupled to the memory device to perform operations comprising: determining current workload characteristics of the memory device; determining a first set of one or more parameter values ​​that satisfy a threshold workload criterion associated with the memory device by processing a trainable classifier of the current workload characteristics; and configuring a firmware component of the memory device with the first set of one or more parameter values.

[0004] In another aspect, the present disclosure relates to a method comprising: determining current workload characteristics of a memory device; determining a first set of one or more parameter values ​​that satisfy a threshold workload criterion associated with the memory device by processing a trainable classifier of the current workload characteristics; and configuring a firmware component of the memory device with the first set of one or more parameter values.

[0005] In another aspect, the present disclosure relates to a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: determining a current workload characteristic of a memory device, wherein the current workload characteristic comprises a number of memory access operations performed on the memory device; identifying a record of a data structure, wherein the record is associated with a workload characteristic corresponding to the current workload characteristic of the memory device; identifying a first set of one or more parameter values ​​associated with the identified record, wherein the first set of one or more parameter values ​​satisfies a threshold workload criterion; and configuring a firmware component of the memory device with the first set of one or more parameter values. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An exemplary computing system including a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2 For illustrating some embodiments of the present disclosure, reference Figures 3 to 4 A block diagram of an exemplary data structure is described.

[0009] Figure 3 A flow chart of an exemplary method for performing parameter value optimization in a memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 4 A flow chart of an exemplary method for performing parameter value optimization in a memory subsystem according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of an exemplary computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure relate to parameter value optimization in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0013] The memory subsystem may include a high density non-volatile memory device where data retention is required when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die includes one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. Each block includes a set of pages. Each page includes a set of memory cells. A memory cell is an electronic circuit that stores information. Depending on the memory cell type, a memory cell can store one or more bits of binary information and have various logical states related to the number of bits stored. The logical state can be represented by a binary value such as "0" and "1" or a combination of such values.

[0014] Certain memory devices have memory device specifications set by industry standards, customer standards, device performance requirements, etc. For example, certain memory devices will achieve certain performance metrics, such as target read operation latency, target write operation latency, target read operation bandwidth, target write operation bandwidth, etc. In order to achieve those performance metrics / device specifications, the firmware components of the memory device typically use a set of pre-configured parameter values ​​that may affect the performance of the memory device. These parameter values ​​may include, for example, the number of read operations performed during program suspension and / or erase suspension operations; the number of suspension operations performed during program and / or erase operations, etc. However, the set of parameter values ​​may be determined during the design phase of the memory device (before manufacturing), where offline testing (e.g., directly on the memory device or in a simulation environment) is performed using various workload characteristics (e.g., various conditions of memory device operation, such as a specific number of memory access operations performed on the memory device, etc.). Therefore, a set of parameter values ​​can be identified to achieve the performance metrics / device specifications of the memory device operating with any of the various workload characteristics used during the design phase. However, when the memory device is operated after manufacturing, the memory device may experience workload characteristics that are different from the various workload characteristics used during the design phase. For example, the temperature of the memory device may affect the workload characteristics, different uses of the memory device may be required (e.g., lighter workload characteristics versus higher workload characteristics), etc. Therefore, customizable parameter values ​​that are optimized based on the current workload characteristics may be required in order to achieve better performance and meet the performance metrics / device requirements assigned to the memory device.

[0015] Aspects of the present disclosure address the above and other deficiencies by performing parameter value optimization in a memory subsystem. In some embodiments, a memory subsystem controller determines a current workload characteristic of a memory device (e.g., the number of memory access operations performed on the memory device). The memory subsystem controller may input the current workload characteristic into a trainable classifier (e.g., a machine learning model). In some embodiments, the trainable classifier may be, for example, a decision tree machine learning model, a regression machine learning model, etc. In some embodiments, the memory subsystem controller may store the trainable classifier on the memory device. The trainable classifier may generate an output. The output may be a set of parameter values ​​that meet a target performance characteristic (e.g., a threshold workload criterion, which may be specified by a memory device specification). The set of parameter values ​​may be one or more parameter values ​​used by a memory device (e.g., by a firmware component of a memory device) to achieve a target performance characteristic. For example, a parameter value may include the number of read operations allowed during a program suspension and / or erase suspension operation, the number of suspension operations allowed during a program and / or erase operation, etc. The target performance characteristic may be a desired read and / or write operation latency, a read and / or write operation bandwidth, etc. Thus, a firmware component of a memory device may use a set of parameter values ​​to achieve a threshold workload criterion.A memory subsystem controller may configure a firmware component of a memory device with a set of parameter values.

[0016] In some embodiments, the memory subsystem controller may use the current workload characteristics to identify a record of a data structure (e.g., a lookup table). The data structure may have one or more records. Each record contains a set of parameter values ​​corresponding to a particular workload characteristic, wherein the set of parameter values ​​satisfies a target performance characteristic. The memory subsystem controller may store the data structure on the memory device. The memory subsystem controller may configure a firmware component of the memory device with the identified set of parameter values.

[0017] Performing parameter value optimization can produce customizable parameter values ​​that are optimized based on current workload characteristics rather than using a preconfigured set of constant parameter values ​​that are used across various workload characteristics. By considering the current workload characteristics of the memory device and identifying a set of parameter values ​​that can be used under the current workload characteristics to achieve the desired performance metric / device requirement, the performance and quality of service (QoS) of the memory device as a whole can be improved. In addition, it can help achieve specific performance metrics / device requirements assigned to the memory device.

[0018] Figure 1An exemplary computing system 100 including a memory subsystem 110 is shown according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0019] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0020] The computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0021] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0022] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0023] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access a memory component (e.g., the memory device 130). The physical host interface may provide an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0024] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0025] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. A cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0026] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, for example, a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such memory cell arrays. In some embodiments, a particular memory device may include an SLC portion of a memory cell, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0027] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 can be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-(NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0028] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the described operations. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0029] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0030] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include a read-only memory (ROM) for storing microcode. Figure 1 The exemplary memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0031] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), name space) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and convert responses associated with the memory device 130 into information for the host system 120.

[0032] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive an address from the memory subsystem controller 115 and decode the address to access the memory device 130.

[0033] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., the local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] In some embodiments, the memory subsystem 110 includes a parameter value optimization component 113, which can be used to perform parameter value optimization in the memory device 130 or the memory device 140. The parameter value optimization component 113 determines the current workload characteristics of the memory device (e.g., the number of memory access operations performed on the memory device). The parameter value optimization component 113 can input the current workload characteristics into a trainable classifier (e.g., a machine learning model). In some embodiments, the trainable classifier can be, for example, a decision tree machine learning model, a regression machine learning model, etc. In some embodiments, the parameter value optimization component 113 can store the trainable classifier on the memory device. In some embodiments, in order to train the classifier, a subject matter expert can provide a set of features (e.g., parameter values) that can be measured on the memory device. For example, the memory device can be operated with a set of known workloads (also referred to herein as workload characteristics), and when the memory device is operated with each known workload in the set of known workloads, a set of parameter values ​​can be measured. The set of known workloads can be a read and / or write operation latency of the memory device, a read and / or write operation bandwidth of the memory device, etc. A data set may be created that may store each parameter value in a measured parameter value set as an input and each known workload in the set of known workloads as an output. The classifier may then be trained to discover (e.g., predict) a relationship between the measured parameter value set and the set of known workloads. The classifier may be used on a memory device to classify the workload currently being experienced by the memory device according to the parameter value set. In some embodiments, the classifier may be trained with a parameter value set as an input and a set of optimal firmware parameter values ​​as an output, so that the classifier may directly output the optimal parameter values ​​for the memory device. In some embodiments, in response to inputting the current workload characteristics into the trainable classifier, the trainable classifier may generate an output. The output may be a parameter value set that satisfies a target performance characteristic (e.g., a threshold workload criterion, which may be specified by a memory device specification). The parameter value set may be one or more parameter values ​​(e.g., firmware, NAND, ASIC parameter values, etc.) used by a memory device (e.g., by a firmware component of a memory device) to achieve a target performance characteristic. For example, the parameter value may include the number of read operations allowed during a program suspend and / or erase suspend operation, the number of pause operations allowed during a program and / or erase operation, etc. The target performance characteristic may be a desired read and / or write operation latency, a read and / or write operation bandwidth, etc. Therefore, the firmware component of the memory device may use a set of parameter values ​​to achieve a threshold workload criterion. The parameter value optimization component 113 may configure the firmware component of the memory device with the set of parameter values.

[0035] In some embodiments, the parameter value optimization component 113 may use the current workload characteristics to identify a record of a data structure (e.g., a lookup table). The data structure may have one or more records. Each record contains a set of parameter values ​​corresponding to a specific workload characteristic, wherein the set of parameter values ​​satisfies the target performance characteristic. The parameter value optimization component 113 may store the data structure on a memory device. The parameter value optimization component 113 may configure a firmware component of the memory device with the identified set of parameter values.

[0036] As an example, a current workload characteristic of a memory device may be 100,000 read operations performed on the memory device. A target performance characteristic of a memory device may be, for example, a read operation bandwidth of 5,000 MB / s (megabytes per second). The current workload characteristic of 100,000 read operations may be input into a trainable classifier. The trainable classifier may generate an output that is a set of parameter values ​​that satisfies the target performance characteristic. For example, the set of parameter values ​​may be a maximum number of read operations allowed to be performed during a programming suspension operation, such as 1,000 read operations. A data structure may include a record that includes a set of parameter values ​​generated as an output from a trainable classifier (e.g., a maximum of 1,000 read operations allowed to be performed during a programming suspension operation) and an identifier of a corresponding workload characteristic (e.g., 100,000 read operations).

[0037] Additional details regarding the operation of parameter value optimization component 113 are described below.

[0038] Figure 2 For illustrating some embodiments of the present disclosure, reference Figures 3 to 4 A block diagram of an exemplary data structure is described.

[0039] Figure 3 Flowchart of an exemplary method for performing parameter value optimization in a memory subsystem according to some embodiments of the present disclosure. Method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 300 is performed by Figure 1Parameter value optimization component 113 is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, it should be understood that the illustrated embodiment is only an example, and the illustrated process can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0040] At block 305, processing logic determines a memory subsystem (e.g., Figure 1 10) of the memory subsystem 110) of the memory device (e.g., Figure 1 The processing logic may measure and / or identify and / or retrieve the current workload characteristic of the memory device while the memory device is in operation (e.g., after manufacturing). The current workload characteristic may be the current number of memory access operations (e.g., read operations, write operations, etc.) performed on the memory device within a certain period (e.g., within a certain number of program / erase cycles and / or within the life cycle of the memory device).

[0041] At block 310, processing logic determines a set of one or more parameter values ​​that satisfy a target performance characteristic (e.g., a threshold workload criterion). In some embodiments, processing logic determines the set of one or more parameter values ​​using a trainable classifier for processing the current workload characteristic determined at block 305. For example, processing logic may input the current workload characteristic into a trainable classifier. In some embodiments, the trainable classifier may be, for example, a machine learning model, such as a decision tree machine learning model, a regression machine learning model, etc. The trainable classifier may be trained so that for each workload characteristic input into the trainable classifier, a set of one or more parameter values ​​that may be used to satisfy the target performance characteristic (e.g., a threshold workload criterion) may be predicted. For example, in some embodiments, to train the classifier, (e.g., a subject matter expert) may provide a set of features (e.g., parameter values) that may be measured on a memory device. For example, the memory device may be operated with a set of known workload characteristics, and the set of parameter values ​​may be measured when the memory device is operated with each of the known workload characteristics in the set of known workload characteristics. A data set may be created that may store each parameter value in a measured parameter value set as an input and each known workload characteristic in the set of known workload characteristics as an output. The classifier may then be trained to discover (e.g., predict) a relationship between the measured parameter value set and the set of known workload characteristics. The classifier may then be used in a memory device to classify the workload characteristics currently being experienced by the memory device according to the parameter value set. In some embodiments, the classifier may be trained with a parameter value set as an input and a set of optimal firmware parameter values ​​as an output, so that the classifier may directly output the optimal parameter values ​​for the memory device. The processing logic may identify an output of a trainable classifier, wherein the output is a set of one or more parameter values. The one or more parameter values ​​may be parameter values ​​used by a memory device (e.g., by a firmware component of a memory device) to implement a threshold workload criterion. For example, the one or more parameter values ​​may include at least one of the following: a maximum number of read operations allowed to be performed during a program suspend and / or erase suspend operation, a maximum number of suspend operations allowed to be performed during a program and / or erase operation, a threshold time period for completing a program and / or erase operation, or a threshold time period for limiting a program suspend and / or erase suspend operation, etc. In some embodiments, the threshold workload criterion may be a specification for a memory device, such as a target read operation latency, a target write operation latency, a target read operation bandwidth, a target write operation bandwidth, etc.

[0042] In some embodiments, the trainable classifier may be generated during the design phase of the memory device. The processing logic may use a simulation environment (e.g., an agent-based modeling simulator framework) external to the memory device to generate the trainable classifier. In some embodiments, the processing logic may generate the trainable classifier directly on the memory device. In some embodiments, generating the trainable classifier may be performed using one or more workload characteristics. The one or more workload characteristics may be the number of memory access operations (e.g., read operations, write operations, etc.) to be performed on the memory device within a certain period (e.g., within a specific number of program / erase cycles and / or within the life cycle of the memory device).

[0043] In some embodiments, processing logic identifies a data structure (e.g. Figure 2 The data structure 200 includes a record (e.g., a lookup table) of the memory device, wherein the record includes a workload characteristic corresponding to the current workload characteristic of the memory device determined at block 305. In some embodiments, the data structure includes one or more records (e.g., Figure 2 In some embodiments, processing logic may retrieve a data structure stored on a memory device. Processing logic may identify a record of the data structure that includes another (e.g., a second) set of one or more parameter values ​​corresponding to a current workload characteristic of the memory device. For example, processing logic may compare the current workload characteristic to each of the workload characteristics listed in each record of the data structure. For example, using Figure 2 As an example, processing logic may identify that the current workload characteristic is equivalent to workload characteristic 23 b of entry 2 of data structure 200 .

[0044] In some embodiments, each record of the data structure may include one or more parameter values ​​(e.g., Figure 2 Each set of one or more parameter values ​​may correspond to a particular workload characteristic. For example, Figure 2The parameter value 22a of the record 1 of the data structure in can correspond to the workload characteristic 23a. The parameter value 22a can be a set of one or more parameter values ​​that can be used by the firmware component of the memory device to achieve a target performance characteristic (e.g., a threshold workload criterion) when the memory device is running and experiencing a current workload characteristic equivalent to the workload characteristic 23a. In some embodiments, the second set of one or more parameter values ​​can include at least one of the following: a maximum number of read operations allowed to be performed during a program suspend and / or erase suspend operation, a maximum number of suspend operations allowed during a program and / or erase operation, a threshold time period for completing a program and / or erase operation, or a threshold time period for limiting a program suspend and / or erase suspend operation, etc. In some embodiments, the threshold workload criterion can be a specification for the memory device, such as a target read operation latency, a target write operation latency, a target read operation bandwidth, a target write operation bandwidth, etc.

[0045] In some embodiments, the data structure may be generated during the design phase of the memory device. The processing logic may generate the data structure using a simulation environment (e.g., an agent-based modeling simulator framework) external to the memory device. In some embodiments, the processing logic may generate the data structure directly on the memory device. In some embodiments, generating the data structure may be performed using one or more workload characteristics. The one or more workload characteristics may be the number of memory access operations (e.g., read operations, write operations, etc.) to be performed on the memory device within a certain period (e.g., within a specific number of program / erase cycles and / or within the life cycle of the memory device).

[0046] At block 320, processing logic configures a firmware component of the memory device. In some embodiments, processing logic configures the firmware component with the set of one or more parameter values ​​identified at block 310 (e.g., a first set of one or more parameter values ​​determined using a trainable classifier and / or a second set of one or more parameter values ​​associated with an identified record of a data structure described with respect to block 310). In some embodiments, configuring the firmware component includes setting a configuration setting of the firmware component to the set of one or more parameter values ​​such that the firmware component uses the set of one or more parameter values ​​to achieve a target performance characteristic.

[0047] Figure 4 4 is a flowchart of an exemplary method for performing parameter value optimization in a memory subsystem according to some embodiments of the present disclosure. Method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 400 is performed by Figure 1 Parameter value optimization component 113 is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, it should be understood that the illustrated embodiment is only an example, and the illustrated process can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0048] At block 405, processing logic determines a memory subsystem (e.g., Figure 1 10) of the memory subsystem 110) of the memory device (e.g., Figure 1 The processing logic may measure and / or identify and / or retrieve the current workload characteristic of the memory device while the memory device is in operation (e.g., after manufacturing). The current workload characteristic may be the current number of memory access operations (e.g., read operations, write operations, etc.) performed on the memory device within a certain period (e.g., within a certain number of program / erase cycles and / or within the life cycle of the memory device).

[0049] At block 410, processing logic identifies a data structure (e.g. Figure 2 The data structure 200 includes a record (e.g., a lookup table) of the memory device, wherein the record includes a workload characteristic corresponding to the current workload characteristic of the memory device determined at block 405. In some embodiments, the data structure includes one or more records (e.g., Figure 2 In some embodiments, processing logic may retrieve a data structure stored on a memory device. Processing logic may identify a record of the data structure that includes a set of one or more parameter values ​​corresponding to a current workload characteristic of the memory device. For example, processing logic may compare the current workload characteristic to each of the workload characteristics listed in each record of the data structure. For example, using Figure 2 As an example, processing logic may identify that the current workload characteristic is equivalent to workload characteristic 23 b of record 2 of data structure 200 .

[0050] In some embodiments, each record of the data structure may include one or more parameter values ​​(e.g., Figure 2 Each set of one or more parameter values ​​may correspond to a particular workload characteristic. For example, Figure 2The parameter value 22a of the record 1 of the data structure in may correspond to the workload characteristic 23a. The parameter value 22a may be a set of one or more parameter values ​​that may be used by a firmware component of the memory device to achieve a target performance characteristic (e.g., a threshold workload criterion) when the memory device is running and experiencing a current workload characteristic equivalent to the workload characteristic 23a. In some embodiments, the set of one or more parameter values ​​may include at least one of the following: a maximum number of read operations allowed during a program suspend and / or erase suspend operation, a maximum number of suspend operations allowed during a program and / or erase operation, a threshold time period for completing a program and / or erase operation, or a threshold time period for limiting a program suspend and / or erase suspend operation, etc. In some embodiments, the threshold workload criterion may be a specification for a memory device, such as a target read operation latency, a target write operation latency, a target read operation bandwidth, a target write operation bandwidth, etc.

[0051] In some embodiments, processing logic determines a set of one or more parameter values ​​using a trainable classifier for processing the current workload characteristics determined at block 405. For example, processing logic may input the current workload characteristics into the trainable classifier. In some embodiments, the trainable classifier may be, for example, a machine learning model, such as a decision tree machine learning model, a regression machine learning model, etc. The trainable classifier may be trained so that for each workload characteristic input into the trainable classifier, a set of one or more parameter values ​​that may be used to meet a target performance characteristic (e.g., a threshold workload criterion) may be predicted. For example, in some embodiments, to train the classifier, (e.g., a subject matter expert) may provide a set of features (e.g., parameter values) that may be measured on a memory device. For example, the memory device may be operated with a set of known workload characteristics, and a set of parameter values ​​may be measured when the memory device is operated with each known workload characteristic in the set of known workload characteristics. A data set may be created that may store each parameter value in the measured set of parameter values ​​as input and store each known workload characteristic in the set of known workload characteristics as output. The classifier can then be trained to discover (e.g., predict) a relationship between a set of measured parameter values ​​and the set of known workload characteristics. The classifier can then be used in a memory device to classify the workload characteristics currently being experienced by the memory device based on the set of parameter values. In some embodiments, the classifier can be trained with a set of parameter values ​​as input and a set of optimal firmware parameter values ​​as output, so that the classifier can directly output the optimal parameter values ​​for the memory device.

[0052] In some embodiments, the data structure may be generated during the design phase of the memory device. The processing logic may generate the data structure using a simulation environment (e.g., an agent-based modeling simulator framework) external to the memory device. In some embodiments, the processing logic may generate the data structure directly on the memory device. In some embodiments, generating the data structure may be performed using one or more workload characteristics. The one or more workload characteristics may be the number of memory access operations (e.g., read operations, write operations, etc.) to be performed on the memory device within a certain period (e.g., within a specific number of program / erase cycles and / or within the life cycle of the memory device).

[0053] At block 415, the processing logic identifies a set of one or more parameter values ​​listed within the record identified at block 410. For example, the processing logic may identify a set of one or more parameter values ​​(e.g., parameter value 22b) listed within the same record 2 of the data structure 200. The processing logic may use the set of one or more parameter values ​​as the one or more parameter values ​​that satisfy the threshold workload criteria.

[0054] At block 420, processing logic configures a firmware component of the memory device. In some embodiments, the processing logic configures the firmware component with the set of one or more parameter values ​​identified at operation 415. In some embodiments, configuring the firmware component includes setting a configuration setting of the firmware component to the set of one or more parameter values ​​such that the firmware component achieves a target performance characteristic using the set of one or more parameter values.

[0055] Figure 5 An exemplary machine of computer system 500 is shown, in which a set of instructions for causing the machine to perform any one or more of the methodologies discussed may be executed. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network connection) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0056] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed.

[0057] The exemplary computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0058] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, and the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, and the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed. Computer system 500 may additionally include a network interface device 508 to communicate over a network 520.

[0059] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methods or functions described. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, with the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0060] In one embodiment, instructions 526 include instructions for implementing the Figure 1The parameter value optimization component 113 of the embodiment of the present invention is provided with instructions for the functionality of the component 113. Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0061] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are a means by which those skilled in the art of data processing can most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that produces a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven to be convenient at times, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0062] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0063] The present disclosure also relates to an apparatus for performing an operation. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0064] The algorithms and displays presented are not inherently related to any particular computer or other device. Various general purpose systems may be used with the programs according to the teachings, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various such systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure described may be implemented using a variety of programming languages.

[0065] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0066] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A system comprising: Memory device; as well as A processing device operatively coupled to the memory device to perform operations comprising: determining a current workload characteristic of the memory device; determining, by processing a trainable classifier of the current workload characteristics, a first set of one or more parameter values ​​that satisfy a threshold workload criterion associated with the memory device; as well as A firmware component of the memory device is configured with the first set of one or more parameter values.

2. The system according to claim 1, further comprising: identifying a record of a data structure, wherein the record is associated with a workload characteristic corresponding to the current workload characteristic of the memory device; as well as A second set of one or more parameter values ​​associated with the identified record is identified, wherein the second set of one or more parameter values ​​satisfies the threshold workload criteria. 3 . The system of claim 1 , wherein the current workload characteristic comprises a number of memory access operations performed on the memory device.

4. The system of claim 1, wherein the threshold workload criterion comprises at least one of: a target read operation latency, a target write operation latency, a target read operation bandwidth, or a target write operation bandwidth.

5. The system of claim 1 , wherein the first set of one or more parameter values ​​comprises at least one of: a maximum number of read commands to be executed during a program suspend and / or erase suspend operation, a maximum number of suspend commands to be executed during a program and / or erase operation, a threshold time period for completing the program and / or erase operation, or a threshold time period for limiting the program suspend and / or erase suspend operation.

6. The system of claim 1, further comprising: The current workload characteristics are input into the trainable classifier.

7. The system of claim 1, wherein the trainable classifier is a decision tree machine learning model and / or a regression machine learning model.

8. A method comprising: determining current workload characteristics of the memory device; determining, by processing a trainable classifier of the current workload characteristics, a first set of one or more parameter values ​​that satisfy a threshold workload criterion associated with the memory device; as well as A firmware component of the memory device is configured with the first set of one or more parameter values.

9. The method according to claim 8, further comprising: identifying a record of a data structure, wherein the record is associated with a workload characteristic corresponding to the current workload characteristic of the memory device; as well as A second set of one or more parameter values ​​associated with the identified record is identified, wherein the second set of one or more parameter values ​​satisfies the threshold workload criteria.

10. The method of claim 8, wherein the current workload characteristic comprises a number of memory access operations performed on the memory device.

11. The method of claim 8, wherein the threshold workload criterion comprises at least one of: a target read operation latency, a target write operation latency, a target read operation bandwidth, or a target write operation bandwidth.

12. The method of claim 8, wherein the first set of one or more parameter values ​​comprises at least one of: a maximum number of read commands to be executed during a program suspend and / or erase suspend operation, a maximum number of suspend commands to be executed during a program and / or erase operation, a threshold time period for completing the program and / or erase operation, or a threshold time period for limiting the program suspend and / or erase suspend operation.

13. The method according to claim 8, further comprising: The current workload characteristics are input into the trainable classifier.

14. The method of claim 8, wherein the trainable classifier is a decision tree machine learning model and / or a regression machine learning model.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: determining a current workload characteristic of a memory device, wherein the current workload characteristic comprises a number of memory access operations performed on the memory device; identifying a record of a data structure, wherein the record is associated with a workload characteristic corresponding to the current workload characteristic of the memory device; identifying a first set of one or more parameter values ​​associated with the identified record, wherein the first set of one or more parameter values ​​satisfies a threshold workload criterion; and A firmware component of the memory device is configured with the first set of one or more parameter values.

16. The non-transitory computer-readable storage medium of claim 15, wherein the processing device is to perform operations further comprising: A second set of one or more parameter values ​​that satisfies the threshold workload criterion is determined by processing the trainable classifier of the current workload characteristics.

17. The non-transitory computer-readable storage medium of claim 15, wherein the threshold workload criterion comprises at least one of: a target read operation latency, a target write operation latency, a target read operation bandwidth, or a target write operation bandwidth.

18. The non-transitory computer-readable storage medium of claim 15, wherein the first set of one or more parameter values ​​comprises at least one of: a maximum number of read commands to be executed during a program suspend and / or erase suspend operation, a maximum number of suspend operations to be performed during a program and / or erase operation, a threshold time period for completing the program and / or erase operation, or a threshold time period for limiting the program suspend and / or erase suspend operation.

19. The non-transitory computer-readable storage medium of claim 16, wherein the processing device is to perform operations further comprising: The current workload characteristics are input into the trainable classifier.

20. The non-transitory computer-readable storage medium of claim 16, wherein the trainable classifier is a decision tree machine learning model and / or a regression machine learning model.

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