Method and device for generating test case for verifying return address stack and electronic equipment

Abstract

The embodiment of the invention discloses a method and a device for generating a test case for verifying a return address stack, and electronic equipment, relates to the technical field of processors, and can effectively improve the test capability of the test case of the return address stack. The method comprises the steps that an instruction sequence with multiple instructions is generated according to the maximum depth of a return address stack, and the multiple instructions comprise a Call instruction and a Return instruction; generating a jump direction of each instruction in the plurality of instructions, wherein the jump direction represents an address value change direction of a to-be-assigned target address of the instruction relative to a to-be-assigned instruction address; determining a to-be-assigned instruction address of each instruction and a position sequence of a to-be-assigned target address of each instruction based on the instruction sequence and the jump direction of each instruction; according to the position sequence, assigning address values to the to-be-assigned instruction address of each instruction and the to-be-assigned target address of each instruction; and respectively writing each instruction into the instruction address of each instruction. The method and device are suitable for the scene of verifying the return address stack.

Description

Technical Field

[0001] The present application relates to the field of processor technology, and in particular to a method, device and electronic device for generating a test case for verifying a return address stack. Background Art

[0002] A stack is a serial data structure with a first-in, last-out feature, that is, the content put into the stack last is taken out first, and the first content put into the stack is always taken out last. The input and output operations on the stack are called push and pop.

[0003] In the processor architecture, when a program calls a sub-function or interrupts a save, the current process status information is saved in the stack, and the process is restored after the sub-function or interrupt program is executed. In order to improve processor performance, a separate cache is often used inside the processor branch prediction module to store the stack used for prediction. The cache is not visible to instructions. From a hardware perspective, the depth of the stack is limited, and predictions will not be possible beyond the stack depth range. This stack is called Ras (Return address stack).

[0004] For the test verification of Ras, since address conflicts may occur between the instructions of the test cases, it is difficult for general test cases to test the call and return combinations of each instruction according to the depth of the stack, including complex scenarios such as recursive calls and recursive returns. It is also difficult to quickly reach its saturation performance according to the depth of the stack. Summary of the invention

[0005] In view of this, the present application provides a method, device and electronic device for generating a test case for verifying a return address stack, so as to improve the testing capability of the test case for the return address stack.

[0006] In a first aspect, an embodiment of the present invention provides a method for generating a test case for verifying a return address stack, comprising: generating an instruction sequence having multiple instructions according to the maximum depth of the return address stack, the multiple instructions including Call instructions and Return instructions; generating a jump direction for each of the multiple instructions, the jump direction indicating the direction of change in the address value of the target address to be assigned of the instruction relative to the address of the instruction to be assigned; determining a position sequence of the instruction address to be assigned of each instruction and the target address to be assigned of each instruction based on the instruction sequence and the jump direction of each instruction; assigning address values ​​to the instruction address to be assigned of each instruction and the target address to be assigned of each instruction according to the position sequence; and writing each instruction into the instruction address of each instruction respectively.

[0007] In a specific implementation scheme, the step of generating an instruction sequence having multiple instructions according to the maximum depth of the return address stack includes: assigning an initial value of zero to the depth count value of the return address stack; querying the depth count value; if the depth count value is zero, generating a Call instruction, adding 1 to the depth count value, and returning to the step of querying the depth count value; if the depth count value is greater than zero and the depth count value has not reached the maximum depth, generating a Call instruction or a Return instruction, and returning to the step of querying the depth count value, wherein if a Call instruction is generated, the depth count value is added 1, and if a Return instruction is generated, the depth count value is subtracted by 1; if the depth count value reaches the maximum depth, then terminating the step of generating an instruction sequence having multiple instructions according to the maximum depth of the return address stack.

[0008] In a specific implementation, if the depth count value is greater than zero and the depth count value has not reached the maximum depth, a Call instruction or a Return instruction is generated, including: if the depth count value is greater than zero and the depth count value is less than or equal to a preset threshold, a Call instruction is generated with a first probability and a Return instruction is generated with a second probability; if the depth count value has not reached the maximum depth and the depth count value is greater than the preset threshold, a Call instruction is generated with a third probability and a Return instruction is generated with a fourth probability, wherein the third probability is greater than the fourth probability.

[0009] In a specific implementation scheme, the determining of the position sequence of the instruction address to be assigned and the target address to be assigned of each instruction based on the instruction sequence and the jump direction of each instruction comprises: selecting instructions from the instruction sequence in sequence as instructions to be arranged; if the instruction to be arranged is the first instruction in the instruction sequence, determining the corresponding sequence of the instruction address to be assigned and the target address to be assigned of the instruction to be arranged in the position sequence according to the jump direction of the instruction to be arranged; if the instruction to be arranged is the instruction after the first instruction in the instruction sequence, and the instruction to be arranged is a Call instruction, determining the corresponding sequence of the instruction address to be assigned of the instruction to be arranged in the position sequence; , placed after the sequence corresponding to the target address to be assigned of the previous instruction of the to-be-arranged instruction, and according to the jump direction of the to-be-arranged instruction, determine the sequence corresponding to the target address to be assigned of the to-be-arranged instruction in the position sequence; if the to-be-arranged instruction is the instruction after the first instruction in the instruction sequence, and the to-be-arranged instruction is a Return instruction, then the sequence corresponding to the instruction address to be assigned of the to-be-arranged instruction in the position sequence is placed after the sequence corresponding to the target address to be assigned of the previous instruction of the to-be-arranged instruction, and the sequence corresponding to the target address to be assigned of the to-be-arranged instruction in the position sequence is placed after the sequence corresponding to the instruction address to be assigned of the previous Call instruction that has not been returned of the to-be-arranged instruction.

[0010] In a specific implementation scheme, the rank corresponding to the to-be-assigned instruction address of the to-be-assigned instruction in the position sequence is the rank corresponding to the to-be-assigned instruction address that is closest to the rank corresponding to the to-be-assigned target address of the previous instruction of the to-be-assigned instruction along the sorting direction of the position sequence.

[0011] In a specific implementation scheme, the target addresses to be assigned values ​​of each instruction and the instruction addresses to be assigned values ​​of each instruction are assigned address values ​​respectively according to the position sequence, including: according to the sequence positions corresponding to the target addresses to be assigned values ​​of each instruction and the instruction addresses to be assigned values ​​of each instruction in the position sequence, the target addresses to be assigned values ​​of each instruction and the instruction addresses to be assigned values ​​of each instruction are assigned address values ​​that increase in sequence.

[0012] In a specific implementation, it also includes: if the to-be-arranged instruction is an instruction after the first instruction in the instruction sequence, and the to-be-arranged instruction is a Call instruction of an indirect jump, then selecting a first reusable instruction from the instructions before the to-be-arranged instruction as the reusable instruction, wherein the first reusable instruction is a Call instruction of an indirect jump, and the output position of the to-be-assigned target address of the first reusable instruction is the same as the output position of the to-be-assigned target address of the to-be-arranged instruction; if the to-be-arranged instruction is an instruction after the first instruction in the instruction sequence, and the to-be-arranged instruction is a Return instruction, then selecting a first reusable instruction from the instructions before the to-be-arranged instruction as the reusable instruction, wherein the first reusable instruction is a Call instruction of an indirect jump, and the output position of the to-be-assigned target address of the first reusable instruction is the same as the output position of the to-be-assigned target address of the to-be-arranged instruction. A second reusable instruction is selected from the instructions before the to-be-arranged instruction as the multiplexed instruction, wherein the second reusable instruction is a Return instruction; the sequence position corresponding to the to-be-assigned instruction address of the to-be-assigned instruction in the position sequence and the sequence position corresponding to the to-be-assigned instruction address of the multiplexed instruction are the same sequence position; according to the position sequence, address values ​​are respectively assigned to the to-be-assigned instruction address of each instruction and the to-be-assigned target address of each instruction, and also includes: if the sequence positions corresponding to more than two to-be-assigned instruction addresses in the position sequence are the same sequence position, the more than two to-be-assigned instruction addresses are assigned the same address value.

[0013] In a specific implementation scheme, according to the position sequence, address values ​​are assigned to the target address to be assigned of each instruction and the instruction address to be assigned of each instruction, including: assigning the target address to be assigned of each Return instruction in the instructions and the instruction address to be assigned of the previous non-returned Call instruction of each Return instruction to: the target address of each Return instruction is adjacent to the instruction address of the previous non-returned Call instruction of each Return instruction.

[0014] In a specific implementation scheme, it also includes: reserving a gap address between the instruction address of each Return instruction in the instructions and the instruction address of another instruction adjacent to the previous or next instruction or the target address of another instruction; and / or reserving a gap address between the instruction address of each Call instruction in the instructions and the instruction address of another instruction adjacent to the previous or next instruction or the target address of another Call instruction; and / or reserving a gap address between the target address of each Call instruction in the instructions and the instruction address of another instruction adjacent to the previous or next instruction or the target address of another instruction.

[0015] In a specific implementation, it also includes: writing a non-jump instruction in the gap address, and / or writing a non-jump instruction in the target address of each instruction.

[0016] In a second aspect, an embodiment of the present invention further provides a device for generating a test case for verifying a return address stack, the device for generating a test case for verifying a return address stack comprising: an instruction sequence generating unit, for generating an instruction sequence having a plurality of instructions according to the maximum depth of the return address stack, the plurality of instructions comprising a Call instruction and a Return instruction; a jump direction generating unit, for generating a jump direction of each instruction in the plurality of instructions, the jump direction indicating a direction in which the address value of the target address to be assigned of the instruction is changed relative to the address of the instruction to be assigned; a position sequence determining unit, for determining the position sequence of the instruction address to be assigned of each instruction and the target address to be assigned of each instruction based on the instruction sequence and the jump direction of each instruction; an address value assigning unit, for assigning address values ​​to the instruction address to be assigned of each instruction and the target address to be assigned of each instruction according to the position sequence; and an instruction writing unit, for writing each instruction into the instruction address of each instruction respectively.

[0017] In a specific implementation scheme, the instruction sequence generation unit includes: an initialization module, used to assign an initial value of zero to the depth count value of the return address stack; a query module, used to query the depth count value; a first judgment module, used to generate a Call instruction if the depth count value is zero, add 1 to the depth count value, and return to the step of querying the depth count value; a second judgment module, used to generate a Call instruction or a Return instruction if the depth count value is greater than zero and the depth count value has not reached the maximum depth, and return to the step of querying the depth count value, and if a Call instruction is generated, add 1 to the depth count value, and if a Return instruction is generated, subtract 1 from the depth count value; a third judgment module, used to end the step of generating an instruction sequence with multiple instructions according to the maximum depth of the return address stack if the depth count value reaches the maximum depth.

[0018] In a specific implementation scheme, the second judgment module is used to: if the depth count value is greater than zero and the depth count value is less than or equal to a preset threshold, generate a Call instruction with a first probability and generate a Return instruction with a second probability; if the depth count value does not reach the maximum depth and the depth count value is greater than the preset threshold, generate a Call instruction with a third probability and generate a Return instruction with a fourth probability, wherein the third probability is greater than the fourth probability.

[0019] In a specific implementation scheme, the position sequence determination unit includes: a to-be-arranged instruction selection module, which is used to select instructions from the instruction sequence in sequence as to-be-arranged instructions; a first sorting module, which is used to determine the corresponding order of the to-be-assigned instruction address of the to-be-arranged instruction and the to-be-assigned target address of the to-be-arranged instruction in the position sequence according to the jump direction of the to-be-arranged instruction if the to-be-arranged instruction is the first instruction in the instruction sequence; and a second sorting module, which is used to place the corresponding order of the to-be-assigned instruction address of the to-be-arranged instruction in the position sequence to the previous instruction of the to-be-arranged instruction if the to-be-arranged instruction is the instruction after the first instruction in the instruction sequence and the to-be-arranged instruction is a Call instruction. The third sorting module is used for placing the sequence corresponding to the target address to be assigned of the instruction to be arranged in the position sequence after the sequence corresponding to the target address to be assigned of the instruction to be arranged, and determining the sequence corresponding to the target address to be assigned of the instruction to be arranged in the position sequence according to the jump direction of the instruction to be arranged; if the instruction to be arranged is the instruction after the first instruction in the instruction sequence, and the instruction to be arranged is a Return instruction, then placing the sequence corresponding to the instruction address to be assigned of the instruction to be arranged in the position sequence after the sequence corresponding to the target address to be assigned of the previous instruction to be arranged, and placing the sequence corresponding to the target address to be assigned of the instruction to be arranged in the position sequence after the sequence corresponding to the instruction address to be assigned of the previous Call instruction that has not been returned of the instruction to be arranged.

[0020] In a specific implementation scheme, the address value assignment unit is used to assign successively increasing address values ​​to the target addresses to be assigned and the instruction addresses to be assigned of each instruction in the position sequence, respectively, according to the order positions corresponding to the target addresses to be assigned and the instruction addresses to be assigned of each instruction in the position sequence.

[0021] In a specific implementation scheme, the position sequence determination unit also includes a fourth sorting module, and the fourth sorting module is used to: if the instruction to be arranged is an instruction after the first instruction in the instruction sequence, and the instruction to be arranged is a Call instruction of an indirect jump, then select a first reusable instruction from the instructions before the instruction to be arranged as a multiplexed instruction, wherein the first reusable instruction is a Call instruction of an indirect jump, and the output position of the target address to be assigned of the first reusable instruction is the same as the output position of the target address to be assigned of the instruction to be arranged; if the instruction to be arranged is the instruction sequence The instruction after the first instruction in the sequence, and the instruction to be arranged is a Return instruction, then a second reusable instruction is selected from the instructions before the instruction to be arranged as the multiplexed instruction, wherein the second reusable instruction is a Return instruction; the sequence corresponding to the address of the instruction to be assigned of the instruction to be arranged in the position sequence and the sequence corresponding to the address of the instruction to be assigned of the multiplexed instruction are set to the same sequence; the address value assigning unit is also used for: if the sequence corresponding to two or more addresses of the instruction to be assigned in the position sequence are the same sequence, then the same address value is assigned to the two or more addresses of the instruction to be assigned.

[0022] In a specific implementation scheme, the address value assignment unit is also used to: assign the target address to be assigned of each Return instruction in the instructions and the instruction address to be assigned of the previous non-returned Call instruction of each Return instruction as follows: the target address of each Return instruction is adjacent to the instruction address of the previous non-returned Call instruction of each Return instruction.

[0023] In a specific implementation scheme, it also includes a reserved gap address unit, which is used to reserve a gap address between the instruction address of each Return instruction in the instructions and the instruction address of another instruction adjacent to the previous or next instruction or the target address of another instruction; and / or to reserve a gap address between the instruction address of each Call instruction in the instructions and the instruction address of another instruction adjacent to the previous or next instruction or the target address of another Call instruction; and / or to reserve a gap address between the target address of each Call instruction in the instructions and the instruction address of another instruction adjacent to the previous or next instruction or the target address of another instruction.

[0024] In a specific implementation, it also includes a non-jump instruction writing unit, which is used to write non-jump instructions in the gap address and / or write non-jump instructions in the target address of each instruction.

[0025] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising: a shell, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is arranged inside the space enclosed by the shell, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute any one of the test case generation methods for verifying the return address stack provided in the embodiments of the present invention.

[0026] The embodiment of the present invention provides a method, device and electronic device for generating a test case for verifying a return address stack. According to the maximum depth of the return address stack, an instruction sequence with multiple instructions is generated, and the multiple instructions include a Call instruction and a Return instruction; the jump direction of each instruction in the multiple instructions is generated, and the jump direction indicates the direction of change in the address value of the target address to be assigned of the instruction relative to the address of the instruction to be assigned; based on the instruction sequence and the jump direction of each instruction, the position sequence of the instruction address to be assigned of each instruction and the target address to be assigned of each instruction is determined; according to the position sequence, the instruction address to be assigned of each instruction and the target address to be assigned of each instruction are respectively assigned address values; and each instruction is respectively written into the instruction address of each instruction. The method for generating a test case can quickly reach its saturation capacity according to the maximum depth of the return address stack when verifying the return address stack, and can avoid the overlap of the instruction address and the target address of each instruction in the test case, thereby improving the test capacity of the test case of the return address stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 A flow chart of a method for generating a test case for verifying a return address stack provided in an embodiment of the present application; Figure 2 A flow chart of an instruction sequence generation method for a test case for verifying a return address stack provided in an embodiment of the present application; Figure 3 A schematic diagram of another instruction sequence generation method for a test case for verifying a return address stack provided in an embodiment of the present application; Figure 4A flowchart of a position determination sequence for a test case for verifying a return address stack provided in an embodiment of the present application; Figure 5 A schematic diagram of another determining position sequence of a test case for verifying a return address stack provided by an embodiment of the present application; Figure 6 A schematic diagram of the structure of a device for generating a test case for verifying a return address stack provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of an instruction sequence generation unit for a test case for verifying a return address stack provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of a position sequence determination unit for verifying a test case of a return address stack provided in an embodiment of the present application; Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] For the test verification of Ras, since address conflicts may occur between the instructions of the test case, it is difficult for general test cases to test the call and return combinations of each instruction according to the depth of the stack, including complex scenarios such as recursive calls and recursive returns. It is also difficult to quickly reach its saturation performance according to the depth of the stack. In order to solve this problem, on the one hand, Figure 1 As shown, an embodiment of the present invention provides a method for generating a test case for verifying a return address stack, and the method may include: S11. Generate an instruction sequence having multiple instructions according to the maximum depth of the return address stack, where the multiple instructions include a Call instruction and a Return instruction.

[0032] In this embodiment, the execution order of multiple instructions is determined according to the instruction sequence generated by the maximum depth of the return address stack, so as to execute the multiple instructions in sequence according to the instruction sequence and fill the return address stack with the instruction return addresses generated during the execution of the multiple instructions. Among them, the maximum depth is used to characterize the maximum number of instruction return addresses that the return address stack can store. The multiple instructions include Call instructions and Return instructions. The instruction return address generated during the execution of the Call instruction is input to the top of the return address stack. During the execution of the Return instruction, the instruction return address at the top of the return address stack is output. Each of the multiple instructions is executed in sequence according to their respective order in the instruction sequence. In this way, the return address stack can be input and filled with the instruction return addresses generated during the execution of the multiple instructions, so that the return address stack can be tested and verified at the maximum saturation capacity. For example, the maximum depth of the return address stack is 2 and the return address stack is empty at this time. Assuming that the randomly generated multiple instructions are 4, and the instructions in the instruction sequence are 1-Call instruction, 2-Return instruction, 3-Call instruction, and 4-Call instruction, then after the 1-Call instruction is executed, the instruction return generated The address adr1 is input to the top of the return address stack; 2-After the Return instruction is executed, the instruction return address adr1 at the top of the return address stack is output again, and the return address stack is empty again; 3-After the Call instruction is executed, the generated instruction return address adr3 is input to the top of the return address stack; 4-After the Call instruction is executed, the generated instruction return address adr4 is input to the top of the return address stack again. At this time, the return address stack reaches the maximum depth, and the return address stack stores the instruction return address adr3 and the instruction return address adr4 from the bottom to the top.

[0033] Since the multiple instructions include not only Call instructions that can generate instruction return addresses to fill the return address stack, but also Return instructions for outputting the instruction return addresses in the return address stack, when verifying the return address stack, the instruction return addresses generated by the multiple instructions during execution can be dynamically filled to fill the return address stack. It is easy to understand that compared with only generating instruction return addresses through Call instructions to fill the return address stack, the method of this embodiment is more in line with the actual situation and can verify the use status of the return address stack in complex scenarios such as recursive calls and recursive returns. In order to verify the return address stack, the instruction sequence of this embodiment can be randomly generated or set based on preset rules to meet the corresponding test requirements.

[0034] S12. Generate a jump direction of each instruction in the plurality of instructions, where the jump direction indicates a direction in which the address value of the target address to be assigned of the instruction changes relative to the address of the instruction to be assigned.

[0035] During the actual execution of the instruction, it is necessary to assign an instruction address and a target address to the instruction. The instruction address and the target address of the instruction have different address values ​​in the memory. When the instruction is executed, the instruction address of the instruction jumps to the target address of the instruction. For example, if the instruction address and the target address of instruction one have been assigned, and the address value of the target address of instruction one is greater than the address value of the instruction address of instruction one, then during the execution of instruction one, the instruction one jumps from the instruction address with a smaller address value to the target address with a larger address value, that is, the jump direction of instruction one is to jump in the direction of increasing address value; if the instruction address and the target address of instruction two have been assigned, and the address value of the target address of instruction two is less than the address value of the instruction address of instruction two, then during the execution of instruction two, the instruction two jumps from the instruction address with a larger address value to the target address with a smaller address value, that is, the jump direction of instruction two is to jump in the direction of decreasing address value. Therefore, the jump direction indicates the direction of change in the address value of the target address of the instruction relative to the instruction address.

[0036] In this embodiment, in the instruction sequence generated in step S11, the instruction address and the target address of each instruction have not been assigned, but the jump direction of each instruction in the multiple instructions can be generated first, and the jump direction also indicates the direction of the change of the address value of the target address to be assigned of the instruction relative to the address of the instruction to be assigned. For example, if the instruction sequence generated in step S11 includes instruction Ins1 and instruction Ins2, and the instruction addresses to be assigned and the target addresses to be assigned of instruction Ins1 and instruction Ins2 have not been assigned, in step S12, if the jump direction of instruction Ins1 is randomly generated, The jump direction is to jump in the direction of increasing address value, that is, the target address to be assigned of instruction Ins1 is greater than the instruction address to be assigned of instruction Ins1, and at this time, it is not necessary to assign actual address values ​​to the instruction address to be assigned and the target address to be assigned of instruction Ins1; if the jump direction of the randomly generated instruction Ins2 is to jump in the direction of decreasing address value, that is, the target address to be assigned of instruction Ins2 is less than the instruction address to be assigned of instruction Ins2, and at this time, it is not necessary to assign actual address values ​​to the instruction address to be assigned and the target address to be assigned of instruction Ins2. Similarly, in order to verify the return address stack, the jump directions of multiple instructions in this embodiment can be randomly generated or set based on preset rules to meet corresponding test requirements.

[0037] S13. Based on the instruction sequence and the jump direction of each instruction, determine the position sequence of the instruction address to be assigned of each instruction and the target address to be assigned of each instruction.

[0038] After determining an instruction sequence including multiple instructions and the jump direction of each instruction in the multiple instructions, the relative position relationship between the target address to be assigned of each instruction and the instruction address to be assigned of each instruction can be sorted to obtain a position sequence, and the position sequence can reflect the relative relationship between the address values ​​of the target address to be assigned of each instruction and the instruction address to be assigned of each instruction in the memory. For example, the target address to be assigned of each instruction and the instruction address to be assigned of each instruction can be sorted according to the order of address value from small to large. In this way, based on the jump direction of each instruction, if the jump direction of instruction Ins1 is to jump in the direction of increasing address value, then In the position sequence, the sequence corresponding to the instruction address to be assigned of instruction Ins1 is located before the sequence corresponding to the target address to be assigned of instruction Ins1; if the jump direction of instruction Ins2 is to jump in the direction of decreasing address value, then in the position sequence, the sequence corresponding to the instruction address to be assigned of instruction Ins2 is located after the sequence corresponding to the target address to be assigned of instruction Ins2; based on the execution order of the instruction sequence, if instruction Ins1 precedes instruction Ins2 in the instruction sequence, then in the position sequence, the sequence corresponding to the instruction address to be assigned of instruction Ins2 is located after the sequence corresponding to the target address to be assigned of instruction Ins1. Therefore, the position sequence determined by this scheme not only represents the relative relationship between the address values ​​of the target addresses to be assigned of each instruction and the instruction addresses to be assigned of each instruction in the memory, but also represents the jump direction of each instruction, that is, the direction of change of the address values ​​of the target addresses to be assigned of each instruction and the instruction addresses to be assigned of each instruction, and also represents the execution order of each instruction.

[0039] S14. According to the position sequence, address values ​​are respectively assigned to the instruction address to be assigned of each instruction and the target address to be assigned of each instruction.

[0040] Since the position sequence represents the relative relationship between the address values ​​of the target addresses to be assigned of each instruction and the instruction addresses to be assigned of each instruction in the memory, after determining the position sequence, address values ​​can be assigned to the target addresses to be assigned of each instruction and the instruction addresses to be assigned of each instruction, so as to avoid the overlap of the address values ​​of the target addresses of each instruction and the instruction addresses of each instruction, thereby ensuring that multiple instructions are executed correctly.

[0041] S15, writing each instruction into the instruction address of each instruction. After assigning the instruction address and the target address to each instruction, each instruction can be written into the instruction address corresponding to each instruction to generate a test case and verify the return address stack.

[0042] The method for generating a test case for verifying a return address stack provided by an embodiment of the present invention generates an instruction sequence with multiple instructions according to the maximum depth of the return address stack, wherein the multiple instructions include a Call instruction and a Return instruction; generates a jump direction of each instruction in the multiple instructions, wherein the jump direction indicates the direction of change in the address value of the target address to be assigned of the instruction relative to the address of the instruction to be assigned; based on the instruction sequence and the jump direction of each instruction, determines the position sequence of the instruction address to be assigned of each instruction and the target address to be assigned of each instruction; according to the position sequence, assigns address values ​​to the instruction address to be assigned of each instruction and the target address to be assigned of each instruction; and writes each instruction into the instruction address of each instruction respectively. The method for generating a test case can quickly reach the saturation capacity of the return address stack according to the maximum depth of the return address stack when verifying the return address stack, and can avoid the overlap of the instruction address and the target address of each instruction in the test case, thereby improving the test capacity of the test case of the return address stack.

[0043] Optional, such as Figure 2 As shown, in one embodiment of the present invention, step S11 generates an instruction sequence having multiple instructions according to the maximum depth of the return address stack, including: S111, initializing the depth count value of the return address stack to zero; S112, querying the depth count value; S113, if the depth count value is zero, generate a Call instruction, add 1 to the depth count value, and return to step S112 of querying the depth count value; S114, if the depth count value is greater than zero and the depth count value has not reached the maximum depth, a Call instruction or a Return instruction is generated, and the process returns to step S112 of querying the depth count value, wherein if a Call instruction is generated, the depth count value is increased by 1, and if a Return instruction is generated, the depth count value is decreased by 1; S115 . If the depth count value reaches the maximum depth, then the step S11 of generating an instruction sequence having a plurality of instructions according to the maximum depth of the return address stack ends.

[0044] Through the above steps, an instruction sequence for filling the return address stack can be generated. The method is easy to implement in programming and improves the generation efficiency of test cases. In order to further improve the generation quality of test cases, optionally, in one embodiment of the present invention, if the depth count value is greater than zero and the depth count value does not reach the maximum depth, a Call instruction or a Return instruction is generated in step S114, including: if the depth count value is greater than zero and the depth count value is less than or equal to the preset threshold, a Call instruction is generated with a first probability and a Return instruction is generated with a second probability; if the depth count value does not reach the maximum depth and the depth count value is greater than the preset threshold, a Call instruction is generated with a third probability and a Return instruction is generated with a fourth probability, wherein the third probability is greater than the fourth probability. The preset threshold can be set according to the test requirements to achieve the corresponding test efficiency or reflect the corresponding nested call or nested return combination in multiple instructions. The Call instruction and the Return instruction can also be randomly generated. The first probability and the second probability can be set according to the actual test situation; the third probability is greater than the fourth probability. After the depth count value is greater than the preset threshold, the probability of the Return instruction can be reduced and the probability of the Call instruction can be increased to tend to reach the maximum depth. The generation method of the instruction sequence can not only make the return address stack reach dynamic saturation according to the maximum depth of the return address stack, but also adjust the relative proportion of Call instructions and Return instructions through different generation probabilities, and simulate multiple nested call and nested return combinations in a single test case, thereby improving the test verification capability of the return address stack.

[0045] For example Figure 3 As shown, the embodiment of the present application specifically provides an example of generating an instruction sequence: In step P100, the depth count value is initialized to zero, and the depth count value is queried in step P101. The following execution options are made according to the depth count value: if step P102 determines that the depth count value satisfies the maximum depth of Ras, the instruction sequence generation step is terminated; if step P103 determines that the depth count value is zero, step P105 is sequentially executed to randomly generate a Call instruction, step P110 increases the depth count value by 1, and step P101 is repeatedly executed to query the depth count value; if step P104 determines that the depth count value is greater than the preset threshold, step P106 is sequentially executed to randomly generate a Call instruction with a high probability and a Return instruction with a low probability, and then step P108 is determined to randomly generate a Return instruction. Whether the instruction is a Call instruction, if it is a Call instruction, go to step P110 to add 1 to the depth count value, if it is not a Call instruction, go to step P109 to subtract 1 from the depth count value, and then loop again to execute step P101 to query the depth count value; if step P104 determines that the depth count value is not greater than the preset threshold, execute step P107 to randomly generate a Return instruction or a Call instruction, and then determine whether the randomly generated instruction is a Call instruction according to step P108, if it is a Call instruction, go to step P110 to add 1 to the depth count value, if it is not a Call instruction, go to step P109 to subtract 1 from the depth count value, and then loop again to execute step P101 to query the depth count value.

[0046] Optional, such as Figure 4 As shown, in one embodiment of the present invention, step S13 determines the position sequence of the instruction address to be assigned and the target address to be assigned of each instruction based on the instruction sequence and the jump direction of each instruction, including: S131, sequentially selecting instructions from the instruction sequence as instructions to be queued; S132, if the instruction to be queued is the first instruction in the instruction sequence, determine the corresponding positions of the instruction address to be assigned and the target address to be assigned of the instruction to be queued in the position sequence according to the jump direction of the instruction to be queued; according to the aforementioned instruction sequence generation method, the first instruction in the instruction sequence is a Call instruction; S133, if the instruction to be arranged is the instruction after the first instruction in the instruction sequence, and the instruction to be arranged is a Call instruction, then the sequence corresponding to the instruction address to be assigned of the instruction to be arranged in the position sequence is placed after the sequence corresponding to the target address to be assigned of the previous instruction to be arranged, and the sequence corresponding to the target address to be assigned of the instruction to be arranged in the position sequence is determined according to the jump direction of the instruction to be arranged; preferably, the sequence corresponding to the instruction address to be assigned of the instruction to be arranged in the position sequence is the sequence corresponding to the instruction address to be assigned which is closest to the sequence corresponding to the target address to be assigned of the previous instruction to be arranged along the sorting direction of the position sequence; S134, if the instruction to be arranged is the instruction after the first instruction in the instruction sequence, and the instruction to be arranged is a Return instruction, then the sequence corresponding to the instruction address to be assigned of the instruction to be arranged in the position sequence is placed after the sequence corresponding to the target address to be assigned of the previous instruction to be arranged, and the sequence corresponding to the target address to be assigned of the instruction to be arranged in the position sequence is placed after the sequence corresponding to the instruction address to be assigned of the previous Call instruction that has not been returned; preferably, the sequence corresponding to the instruction address to be assigned of the instruction to be arranged in the position sequence is the sequence corresponding to the instruction address to be assigned that is closest to the sequence corresponding to the target address to be assigned of the previous instruction to be arranged along the sorting direction of the position sequence; In some embodiments, the process further includes step S135 : if the instruction to be queued is neither a Call instruction nor a Return instruction, the process proceeds to step S11 of generating an instruction sequence having multiple instructions according to the maximum depth of the return address stack.

[0047] After the instruction sequence and the jump direction of each instruction are generated, the position sequence of the relative positions between the target address to be assigned of each instruction and the instruction address to be assigned of each instruction can be obtained through the above-mentioned sorting method. For example, the instruction sequence is 1-Call instruction, 2-Return instruction, 3-Call instruction, 4-Call instruction, if the jump direction of the 1-Call instruction is to jump from a smaller address value to a larger address value, the jump direction of the 3-Call instruction is to jump from a larger address value to a smaller address value, the jump direction of the 4-Call instruction is to jump from a smaller address value to a larger address value, and the jump direction of the 2-Return instruction is determined by the previous Call instruction that has not returned, that is, the target address to be assigned of the 2-Return instruction is the instruction address to be assigned of the next instruction after the previous Call instruction that has not returned, regarding the position sequence of the multiple instructions, the first instruction, that is, the 1-Call instruction, can be selected as the instruction to be arranged, and according to the jump direction of the 1-Call instruction, the sequence a corresponding to the instruction address to be assigned of the 1-Call instruction can be selected. The sequence A corresponding to the target address to be assigned of the instruction to be arranged is sorted as a, A in the position sequence; then the second instruction, namely the 2-Return instruction, is selected from the instruction sequence as the instruction to be arranged, and along the sorting direction of the position sequence, the sequence b corresponding to the instruction address to be assigned of the 2-Return instruction can be arranged after the sequence A corresponding to the target address to be assigned of the previous instruction, namely the 1-Call instruction, in the position sequence, to obtain the position sequence a, A, b, and then according to the jump direction of the 2-Return instruction, the target address to be assigned of the 2-Return instruction is the instruction address to be assigned of the next instruction of the previous 1-Call instruction that has not returned, so the sequence B corresponding to the target address to be assigned of the 2-Return instruction can be placed after the sequence a corresponding to the instruction address to be assigned of the previous 1-Call instruction that has not returned in the position sequence, to obtain the position sequence a, B, A, b.

[0048] Similarly, for the third instruction selected from the instruction sequence, that is, the 3-Call instruction, in the position sequence, the sequence c corresponding to the instruction address to be assigned of the 3-Call instruction can be placed after the sequence B corresponding to the target address to be assigned of the previous instruction, that is, the 2-Return instruction, to obtain the position sequence a, B, c, A, b. Then, according to the jump direction of the 3-Call instruction, since the jump direction of the 3-Call instruction is from a larger address value to a smaller address value, that is, in the opposite direction of the sorting direction of the position sequence of this embodiment, the sequence C corresponding to the target address to be assigned of the 3-Call instruction can be placed in the position sequence before the sequence c corresponding to the instruction address to be assigned of the 3-Call instruction. For example, in this example, the position sequence can be a, B, C, c, A, b.

[0049] It can be seen that for the 1-Call instruction, the 2-Return instruction, and the 3-Call instruction, the position sequence not only represents the relative relationship between the target address to be assigned of each instruction and the address value size of the instruction address to be assigned of each instruction in the memory, but also represents the jump direction of each instruction, that is, the direction of change of the address value size of the target address to be assigned of each instruction and the instruction address to be assigned of each instruction, and also represents the execution order of each instruction.

[0050] Optionally, in one embodiment of the present invention, step S14 assigns address values ​​to the target address to be assigned of each instruction and the instruction address to be assigned of each instruction according to the position sequence, including: assigning successively increasing address values ​​to the target address to be assigned of each instruction and the instruction address to be assigned of each instruction according to the sequence positions corresponding to the target address to be assigned of each instruction and the instruction address to be assigned of each instruction in the position sequence.

[0051] According to the determined position sequence, the instruction address and target address of each instruction are assigned from small to large according to the corresponding order of the target address to be assigned and the instruction address to be assigned of each instruction in the position sequence, which can ensure that there is no address overlap between instructions. In this way, multiple instructions are executed in sequence according to the execution order of the instruction sequence. When the return address stack is tested and verified, the correctness of the execution program flow can be ensured, and the debugging time is avoided to increase due to program running away, thereby improving the test verification capability of the test case of the return address stack.

[0052] In the actual execution process of the instruction, since the Call instruction is divided into two types: direct jump and indirect jump, the target address of the direct jump Call instruction is fixed, and its target address information is directly reflected in the Call instruction code. The target address of the indirect jump Call instruction is variable. Usually, the target address of the indirect jump Call instruction or the memory location where the target address is located is stored in a general register, and the encoding information of the general register is stored in the Call instruction code. Different function calls are implemented by changing the content in the general register. The target address of the Return instruction is the instruction after the previous Call instruction that has not returned. When it is actually executed, the target address of the Return instruction is output from the return address stack, and there is no need to specify the target address in the Return instruction code. It can be seen that the Return instruction can also be regarded as an indirect jump instruction. Since both the indirect jump Call instruction and the Return instruction have reusable scenarios, therefore, optionally, in one embodiment of the present invention, it also includes: if the instruction to be arranged is the instruction after the first instruction in the instruction sequence, and the instruction to be arranged is the indirect jump Call instruction, then select the first reusable instruction from the instructions before the instruction to be arranged as the reusable instruction, wherein the first reusable instruction is the indirect jump Call instruction, and the output position of the target address to be assigned of the first reusable instruction is the same as the output position of the target address to be assigned of the instruction to be arranged; if the instruction to be arranged is the instruction after the first instruction in the instruction sequence , and the instruction to be arranged is a Return instruction, then a second reusable instruction is selected from the instructions before the instruction to be arranged as the multiplexed instruction, wherein the second reusable instruction is a Return instruction; the sequence corresponding to the instruction address to be assigned of the instruction to be arranged in the position sequence and the sequence corresponding to the instruction address to be assigned of the multiplexed instruction are the same sequence; step S14 assigns address values ​​to the instruction address to be assigned of each instruction and the target address to be assigned of each instruction according to the position sequence, and also includes: if the sequence corresponding to two or more instruction addresses to be assigned in the position sequence are the same sequence, then the same address value is assigned to the two or more instruction addresses to be assigned.

[0053] Still taking the multiple instructions of the aforementioned instruction sequence 1-Call instruction, 2-Return instruction, 3-Call instruction, and 4-Call instruction as an example, if the 3-Call instruction and the 4-Call instruction are indirect jumps, and the output positions of the target addresses to be assigned of the 3-Call instruction and the 4-Call instruction are the same, such as the same general register, since the jump direction of the 3-Call instruction is opposite to the sorting direction of the position sequence, then for the sorting of the 4-Call instruction in the position sequence, the 3-Call instruction can be used as a multiplexing instruction, and the sequence d corresponding to the instruction address to be assigned of the 4-Call instruction is compared with The sequence c corresponding to the address of the instruction to be assigned of the 3-Call instruction is set to the same sequence, and the position sequence a, B, C, c (d), A, b is obtained. Then according to the jump direction of the 4-Call instruction, since the jump direction of the 4-Call instruction is from a smaller address value to a larger address value, that is, along the sorting direction of the position sequence of this embodiment, the sequence D corresponding to the target address to be assigned of the 4-Call instruction can be set in the position sequence after the sequence c corresponding to the address of the instruction to be assigned of the 4-Call instruction. For example, in this example, the position sequence can be a, B, C, c (d), A, b, D.

[0054] Preferably, the jump direction of the first reusable instruction is opposite to the sorting direction of the position sequence, that is, the jump direction of the first reusable instruction jumps in the direction of decreasing address value; for example, the position sequence a, B, C, c (d), A, b, D obtained in the above example, since the 4-Call instruction can reuse the 3-Call instruction, and the execution order of the 4-Call instruction is immediately after the 3-Call instruction, that is, the instruction to be arranged is immediately after the first reusable instruction, therefore, the jump direction of the first reusable instruction is opposite to the sorting direction of the position sequence, which can ensure that the instruction to be arranged can reuse the instruction in the instruction sequence immediately before the instruction to be arranged. In some other embodiments, in the instruction sequence, there may be other instructions between the instruction to be arranged and the first reusable instruction. The jump direction of these other instructions may cause the sequence corresponding to the address of the instruction to be assigned of the instruction to be arranged to be arranged at the sequence corresponding to the address of the instruction to be assigned of the first reusable instruction, so that the instruction to be arranged can reuse the first reusable instruction. Therefore, for the case where the instruction to be arranged in the instruction sequence is not immediately adjacent to the first reusable instruction, the jump direction of the first reusable instruction can be along the sorting direction of the position sequence or in the opposite direction of the sorting direction of the position sequence, that is, the jump direction of the first reusable instruction can jump in the direction of increasing address value or in the direction of decreasing address value.

[0055] Similarly, the Return instruction can also be used as a reusable instruction. For example, take the instruction sequence of 5-Call instruction, 6-Call instruction, 7-Return instruction, and 8-Return instruction as an example. If the jump direction of the 5-Call instruction and the 6-Call instruction is to jump from a smaller address value to a larger address value, then in the position sequence, for the sequence e corresponding to the instruction address to be assigned of the 5-Call instruction, the sequence E corresponding to the target address to be assigned of the 5-Call instruction, the sequence f corresponding to the instruction address to be assigned of the 6-Call instruction, and the sequence F corresponding to the target address to be assigned of the 6-Call instruction, the position sequence is determined to be e, E, f, and F. When the 7-Return instruction is used as the instruction to be arranged, since the target address to be assigned of the 7-Return instruction is the address to be assigned of the next instruction after the previous 6-Call instruction that has not returned. Assignment instruction address, therefore, for the position sequence, the rank g corresponding to the instruction address to be assigned of the 7-Return instruction and the rank G corresponding to the target address to be assigned of the 7-Call instruction can be determined as e, E, f, G, F, g. After the execution of the 7-Return instruction is completed, the 6-Call instruction has returned. Therefore, when the 8-Return instruction is used as the instruction to be arranged, the target address to be assigned of the 8-Return instruction is the instruction address to be assigned of the next instruction of the previous 5-Call instruction that has not returned, and the 8-Return instruction can reuse the 7-Return instruction. Therefore, the 7-Return instruction can be used as a multiplexed instruction. For the position sequence, the rank h corresponding to the instruction address to be assigned of the 8-Return instruction and the rank H corresponding to the target address to be assigned of the 8-Call instruction can be determined as e, H, E, f, G, F, g (h).

[0056] In this way, when assigning address values ​​to the instruction address to be assigned of each instruction and the target address to be assigned of each instruction respectively, if there are more than two instruction addresses to be assigned in the position sequence and the corresponding positions are the same, then the two or more instruction addresses to be assigned are assigned the same address value, that is, since the instructions can be reused, the two or more instruction addresses to be assigned are equivalent to a shared memory address value, thereby saving storage space and improving the utilization rate of the memory.

[0057] This embodiment specifically provides an example of sorting the corresponding order of the instruction addresses to be assigned and the target addresses to be assigned in the position sequence of each instruction in the instruction sequence, such as Figure 5 As shown: Step P201 selects instructions from the instruction sequence in turn as the instructions to be arranged, and step P202 determines whether the instruction to be arranged is the first instruction. If it is the first instruction in the instruction sequence, step P203 determines the order of the instruction address to be assigned and the target address to be assigned of the instruction to be arranged in the position sequence, and then step P201 is executed again in a loop; if step P201 determines that the instruction to be arranged is not the first instruction in the instruction sequence, step P204 determines whether the previous instruction is a Call instruction. If it is a Call instruction, step P205 determines the order of the instruction address to be assigned and the target address to be assigned of the instruction to be arranged according to the order of the instruction to be assigned of the previous Call instruction in the position sequence, or the same order corresponding to the multiplexed instruction. Specifically, step P205 can be executed according to step S133, step S134 and the method for determining the multiplexed instruction in this embodiment, and then step P201 is executed again. Execute step P201 in the next loop; if step P204 determines that the previous instruction is not a Call instruction, step P206 determines whether the previous instruction is a Return instruction. If it is a Return instruction, step P207 determines the sequence corresponding to the instruction address to be assigned and the target address to be assigned of the instruction to be arranged or the same sequence corresponding to the multiplexed instruction according to the sequence corresponding to the instruction address to be assigned of the previous Return instruction and its corresponding returned Call instruction in the position sequence. Specifically, step P207 can be executed according to step S133, step S134 and the method for determining the multiplexed instruction in this embodiment, and then step P201 is executed again in a loop; if step P206 determines that the previous instruction is not a Return instruction, go to step P208 to check the generation constraints of the instruction sequence, and restart the step of generating an instruction sequence with multiple instructions according to the maximum depth of the return address stack.

[0058] When the instruction is actually running, the target address of the Return instruction is always the instruction address of the next instruction of the last unreturned Call instruction. Therefore, optionally, in one embodiment of the present invention, according to the position sequence, the target address to be assigned of each instruction and the instruction address to be assigned of each instruction are respectively assigned address values, including: assigning the target address to be assigned of each Return instruction in each instruction and the instruction address to be assigned of the last unreturned Call instruction of each Return instruction to: the target address of each Return instruction is adjacent to the instruction address of the last unreturned Call instruction of each Return instruction, which can improve the utilization of storage space and improve execution efficiency. Optionally, in one embodiment of the present invention, it also includes: reserving a gap address between the instruction address of each Return instruction in each instruction and the instruction address of another instruction that is adjacent to it or the target address of another instruction; and / or reserving a gap address between the instruction address of each Call instruction in each instruction and the instruction address of another instruction that is adjacent to it or the target address of another Call instruction; and / or reserving a gap address between the target address of each Call instruction in each instruction and the instruction address of another instruction that is adjacent to it or the target address of another instruction. In this way, the target address of the Return instruction is adjacent to the instruction address of the previous Call instruction that has not been returned, and gap addresses can be reserved between other addresses. The gap addresses can be used to write other instructions, which can avoid the situation where address overlap occurs when assigning instruction addresses to other instructions due to the lack of reserved gap addresses after the Call instruction that has not been returned.

[0059] Optionally, in one embodiment of the present invention, the method further includes: writing a non-jump instruction in the gap address, and / or writing a non-jump instruction in the target address of each instruction. Since the gap address is reserved in this embodiment, other instructions such as non-jump instructions can be written in the gap address, and non-jump instructions can also be written in the target address of each instruction, thereby further improving the test flexibility and test capability of the test case.

[0060] In a second aspect, an embodiment of the present invention further provides a device for generating a test case for verifying a return address stack, which can effectively improve the testing capability of the test case for the return address stack.

[0061] like Figure 6As shown, the test case generation device for verifying the return address stack provided by the embodiment of the present application may include: an instruction sequence generation unit 31, which is used to generate an instruction sequence with multiple instructions according to the maximum depth of the return address stack, and the multiple instructions include Call instructions and Return instructions; a jump direction generation unit 32, which is used to generate the jump direction of each instruction in the multiple instructions, and the jump direction indicates the direction of change in the address value of the target address to be assigned of the instruction relative to the address of the instruction to be assigned; a position sequence determination unit 33, which is used to determine the position sequence of the instruction address to be assigned of each instruction and the target address to be assigned of each instruction based on the instruction sequence and the jump direction of each instruction; an address value assignment unit 34, which is used to assign address values ​​to the instruction address to be assigned of each instruction and the target address to be assigned of each instruction according to the position sequence; an instruction writing unit 35, which is used to write each instruction into the instruction address of each instruction respectively.

[0062] The test case generation device for verifying the return address stack provided by the embodiment of the present invention can quickly reach its saturation capacity according to the maximum depth of the return address stack when verifying the return address stack, and can avoid the overlap of the instruction address and the target address of each instruction in the test case, thereby improving the test capability of the test case of the return address stack.

[0063] Optional, such as Figure 7 As shown, the instruction sequence generation unit 31 includes: 311 an initialization module, which is used to initialize the depth count value of the return address stack to zero; 312 a query module, which is used to query the depth count value; 313 a first judgment module, which is used to generate a Call instruction if the depth count value is zero, add 1 to the depth count value, and return to the step of querying the depth count value; 314 a second judgment module, which is used to generate a Call instruction or a Return instruction if the depth count value is greater than zero and the depth count value has not reached the maximum depth, and return to the step of querying the depth count value, and if a Call instruction is generated, add 1 to the depth count value, and if a Return instruction is generated, subtract 1 from the depth count value; 315 a third judgment module, which is used to end the step of generating an instruction sequence with multiple instructions according to the maximum depth of the return address stack if the depth count value reaches the maximum depth.

[0064] Optionally, the second judgment module 315 is used to: if the depth count value is greater than zero and the depth count value is less than or equal to a preset threshold, generate a Call instruction with a first probability and generate a Return instruction with a second probability; if the depth count value does not reach the maximum depth and the depth count value is greater than the preset threshold, generate a Call instruction with a third probability and generate a Return instruction with a fourth probability, wherein the third probability is greater than the fourth probability.

[0065] Optional, such as Figure 8As shown, the position sequence determination unit 33 includes: a to-be-arranged instruction selection module 331, which is used to select instructions from the instruction sequence in sequence as to-be-arranged instructions; a first sorting module 332, which is used to determine the corresponding sequences of the to-be-assigned instruction address of the to-be-arranged instruction and the to-be-assigned target address of the to-be-arranged instruction in the position sequence according to the jump direction of the to-be-arranged instruction if the to-be-arranged instruction is the first instruction in the instruction sequence; a second sorting module 333, which is used to place the sequence corresponding to the to-be-assigned instruction address of the to-be-arranged instruction in the position sequence after the sequence corresponding to the to-be-assigned target address of the previous instruction of the to-be-arranged instruction if the to-be-arranged instruction is the instruction after the first instruction in the instruction sequence and the to-be-arranged instruction is a Call instruction, and determine the to-be-assigned target address of the to-be-arranged instruction in the position sequence according to the jump direction of the to-be-arranged instruction. The sequence corresponding to the address in the position sequence; the third sorting module 334 is used for placing the sequence corresponding to the address of the instruction to be assigned of the instruction to be arranged in the position sequence after the sequence corresponding to the target address to be assigned of the previous instruction to be arranged, and placing the sequence corresponding to the target address to be assigned of the instruction to be arranged in the position sequence after the sequence corresponding to the address to be assigned of the previous non-returned Call instruction of the instruction to be arranged if the instruction to be arranged is the instruction after the first instruction in the instruction sequence, and the instruction to be arranged is the Return instruction; in some embodiments, it also includes a trigger module 335, which is used for jumping to the step of generating an instruction sequence with multiple instructions according to the maximum depth of the return address stack if the instruction to be arranged is neither a Call instruction nor a Return instruction.

[0066] Optionally, the address value assignment unit 34 is used to assign successively increasing address values ​​to the target address to be assigned and the instruction address to be assigned of each instruction according to the corresponding order positions of the target address to be assigned and the instruction address to be assigned of each instruction in the position sequence.

[0067] Optionally, the position sequence determination unit 33 also includes a fourth sorting module, which is used to: if the instruction to be arranged is the instruction after the first instruction in the instruction sequence, and the instruction to be arranged is an indirect jump Call instruction, then select a first reusable instruction from the instruction before the instruction to be arranged as the multiplexing instruction, wherein the first reusable instruction is an indirect jump Call instruction, and the output position of the target address to be assigned of the first reusable instruction is the same as the output position of the target address to be assigned of the instruction to be arranged; if the instruction to be arranged is the instruction after the first instruction in the instruction sequence, and the instruction to be arranged is a Return instruction, then select a second reusable instruction from the instruction before the instruction to be arranged as the multiplexing instruction, wherein the second reusable instruction is a Return instruction; set the sequence position corresponding to the instruction address to be assigned of the instruction to be arranged in the position sequence and the sequence position corresponding to the instruction address to be assigned of the multiplexing instruction to the same sequence position; the address value assignment unit 34 is also used to: if the sequence positions corresponding to more than two instruction addresses to be assigned in the position sequence are the same sequence position, assign the same address value to the two or more instruction addresses to be assigned.

[0068] Optionally, the address value assignment unit 34 is also used to assign the target address to be assigned of each Return instruction in each instruction and the instruction address to be assigned of the previous non-returned Call instruction of each Return instruction as follows: the target address of each Return instruction is adjacent to the instruction address of the previous non-returned Call instruction of each Return instruction.

[0069] Optionally, it also includes a reserved gap address unit, which is used to reserve a gap address between the instruction address of each Return instruction in each instruction and the instruction address of another adjacent instruction before and after or the target address of another instruction; and / or to reserve a gap address between the instruction address of each Call instruction in each instruction and the instruction address of another adjacent instruction before and after or the target address of another Call instruction; and / or to reserve a gap address between the target address of each Call instruction in each instruction and the instruction address of another adjacent instruction before and after or the target address of another instruction.

[0070] Optionally, a non-jump instruction writing unit is also included, which is used to write non-jump instructions in the gap address and / or write non-jump instructions in the target address of each instruction.

[0071] In a third aspect, an embodiment of the present invention further provides an electronic device.

[0072] like Fig. 9As shown, the electronic device provided in the embodiment of the present application includes: a shell 51, a processor 52, a memory 53, a circuit board 54 and a power supply circuit 55, wherein the circuit board 54 is arranged inside the space enclosed by the shell 51, and the processor 52 and the memory 53 are arranged on the circuit board 54; the power supply circuit 55 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 53 is used to store executable program codes; the processor 52 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 53, so as to execute any one of the test case generation methods for verifying the return address stack provided in the embodiment of the present invention.

[0073] The specific execution process of the above steps by the processor 52 and the steps further executed by the processor 52 by running the executable program code can be found in the description of the previous embodiment, which will not be repeated here.

[0074] The above electronic devices exist in many forms, including but not limited to: (1) Mobile communication devices: These devices are characterized by their mobile communication functions and their main purpose is to provide voice and data communications. These terminals include: smart phones (such as iPhone), multimedia phones, feature phones, and low-end phones.

[0075] (2) Ultra-mobile personal computer devices: These devices fall into the category of personal computers, have computing and processing capabilities, and generally also have mobile Internet access features. These terminals include: PDA, MID and UMPC devices, such as iPad.

[0076] (3) Portable entertainment devices: These devices can display and play multimedia content. They include audio and video players (such as iPods), handheld game consoles, e-books, smart toys, and portable car navigation devices.

[0077] (4) Server: A device that provides computing services. The server consists of a processor, hard disk, memory, system bus, etc. The server is similar to a general-purpose computer architecture, but because it needs to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0078] (5) Other electronic devices with data interaction functions.

[0079] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0080] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0081] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0082] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0083] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0084] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for generating a test case for verifying a return address stack, characterized in that: include: Generate an instruction sequence having a plurality of instructions according to a maximum depth of a return address stack, wherein the plurality of instructions include a Call instruction and a Return instruction; Generate a jump direction of each instruction in the plurality of instructions, wherein the jump direction indicates a direction in which the address value of the target address to be assigned of the instruction changes relative to the address of the instruction to be assigned; Based on the instruction sequence and the jump direction of each instruction, determine the position sequence of the instruction address to be assigned of each instruction and the target address to be assigned of each instruction; According to the position sequence, address values ​​are respectively assigned to the instruction addresses to be assigned of the instructions and the target addresses to be assigned of the instructions; The instructions are written into the instruction addresses of the instructions respectively.

2. The method for generating a test case for verifying a return address stack according to claim 1, wherein: The generating of an instruction sequence having a plurality of instructions according to the maximum depth of the return address stack comprises: Initialize the depth count value of the return address stack to zero; Query the depth count value; If the depth count value is zero, generate a Call instruction, add 1 to the depth count value, and return to the step of querying the depth count value; If the depth count value is greater than zero and the depth count value has not reached the maximum depth, a Call instruction or a Return instruction is generated, and the process returns to the step of querying the depth count value, wherein if a Call instruction is generated, the depth count value is increased by 1, and if a Return instruction is generated, the depth count value is decreased by 1; If the depth count value reaches the maximum depth, the step of generating an instruction sequence having a plurality of instructions according to the maximum depth of the return address stack ends.

3. The method for generating a test case for verifying a return address stack according to claim 2, wherein: If the depth count value is greater than zero and the depth count value does not reach the maximum depth, generating a Call instruction or a Return instruction includes: If the depth count value is greater than zero and the depth count value is less than or equal to a preset threshold, a Call instruction is generated with a first probability and a Return instruction is generated with a second probability; If the depth count value does not reach the maximum depth and the depth count value is greater than the preset threshold, a Call instruction is generated with a third probability and a Return instruction is generated with a fourth probability, wherein the third probability is greater than the fourth probability.

4. The method for generating a test case for verifying a return address stack according to claim 1, wherein: The determining, based on the instruction sequence and the jump direction of each instruction, a position sequence of instruction addresses to be assigned and target addresses to be assigned of each instruction, comprises: Selecting instructions from the instruction sequence in sequence as instructions to be arranged; If the instruction to be queued is the first instruction in the instruction sequence, determining the corresponding positions of the instruction address to be assigned and the target address to be assigned of the instruction to be queued in the position sequence according to the jump direction of the instruction to be queued; If the instruction to be queued is an instruction after the first instruction in the instruction sequence, and the instruction to be queued is a Call instruction, the sequence corresponding to the instruction address to be assigned of the instruction to be queued in the position sequence is placed after the sequence corresponding to the target address to be assigned of the previous instruction of the instruction to be queued, and the sequence corresponding to the target address to be assigned of the instruction to be queued in the position sequence is determined according to the jump direction of the instruction to be queued; If the instruction to be queued is the instruction after the first instruction in the instruction sequence, and the instruction to be queued is a Return instruction, then the sequence corresponding to the instruction address to be assigned of the instruction to be queued in the position sequence is placed after the sequence corresponding to the target address to be assigned of the previous instruction to be queued, and the sequence corresponding to the target address to be assigned of the instruction to be queued in the position sequence is placed after the sequence corresponding to the instruction address to be assigned of the previous Call instruction that has not been returned before the instruction to be queued.

5. The method for generating a test case for verifying a return address stack according to claim 1, wherein: The assigning address values ​​to the target addresses to be assigned of each instruction and the instruction addresses to be assigned of each instruction respectively according to the position sequence includes: According to the corresponding order positions of the target addresses to be assigned and the instruction addresses to be assigned of each instruction in the position sequence, the target addresses to be assigned and the instruction addresses to be assigned of each instruction are respectively assigned successively increasing address values.

6. The method for generating a test case for verifying a return address stack according to claim 4, wherein: Also includes: If the instruction to be arranged is an instruction after the first instruction in the instruction sequence, and the instruction to be arranged is a Call instruction of an indirect jump, then a first reusable instruction is selected from the instructions before the instruction to be arranged as the reusable instruction, wherein the first reusable instruction is a Call instruction of an indirect jump, and the output position of the target address to be assigned of the first reusable instruction is the same as the output position of the target address to be assigned of the instruction to be arranged; If the instruction to be queued is an instruction after the first instruction in the instruction sequence, and the instruction to be queued is a Return instruction, then selecting a second reusable instruction from the instructions before the instruction to be queued as the reusable instruction, wherein the second reusable instruction is a Return instruction; Set the sequence position corresponding to the instruction address to be assigned of the instruction to be arranged in the position sequence and the sequence position corresponding to the instruction address to be assigned of the multiplexed instruction to the same sequence position; The method of assigning address values ​​to the instruction addresses to be assigned and the target addresses to be assigned of each instruction respectively according to the position sequence also includes: if the order positions corresponding to more than two instruction addresses to be assigned in the position sequence are the same, assigning the same address value to the more than two instruction addresses to be assigned.

7. The method for generating a test case for verifying a return address stack according to claim 5, wherein: The assigning address values ​​to the target addresses to be assigned of each instruction and the instruction addresses to be assigned of each instruction respectively according to the position sequence includes: The target address to be assigned of each Return instruction in the instructions and the instruction address to be assigned of the previous Call instruction that has not been returned before each Return instruction are assigned values: the target address of each Return instruction is adjacent to the instruction address of the previous Call instruction that has not been returned before each Return instruction.

8. The method for generating a test case for verifying a return address stack according to claim 1, wherein: Also includes: A gap address is reserved between the instruction address of each Return instruction in the instructions and the instruction address of another instruction adjacent to it or the target address of another instruction; and / or A gap address is reserved between the instruction address of each Call instruction in the instructions and the instruction address of another instruction adjacent to it or the target address of another Call instruction; and / or A gap address is reserved between the target address of each Call instruction in the instructions and the instruction address of another instruction adjacent to the previous or next instruction or the target address of another instruction.

9. The method for generating a test case for verifying a return address stack according to claim 8, wherein: Also includes: A non-jump instruction is written into the gap address, and / or a non-jump instruction is written into the target address of each instruction.

10. A device for generating a test case for verifying a return address stack, characterized in that: include: An instruction sequence generating unit, used for generating an instruction sequence having a plurality of instructions according to the maximum depth of the return address stack, wherein the plurality of instructions include a Call instruction and a Return instruction; A jump direction generating unit, used to generate a jump direction of each instruction in the plurality of instructions, wherein the jump direction indicates a direction in which the address value of the target address to be assigned of the instruction changes relative to the address of the instruction to be assigned; A position sequence determining unit, used to determine the position sequence of the instruction address to be assigned of each instruction and the target address to be assigned of each instruction based on the instruction sequence and the jump direction of each instruction; an address value assigning unit, used for assigning address values ​​to the instruction addresses to be assigned of the instructions and the target addresses to be assigned of the instructions respectively according to the position sequence; The instruction writing unit is used to write the instructions into the instruction addresses of the instructions respectively.

11. The device for generating a test case for verifying a return address stack according to claim 10, characterized in that: The instruction sequence generating unit comprises: The initialization module is used to initialize the depth count value of the return address stack to zero; A query module, used for querying the depth count value; A first judgment module is used to generate a Call instruction if the depth count value is zero, add 1 to the depth count value, and return to the step of querying the depth count value; A second judgment module is used for generating a Call instruction or a Return instruction if the depth count value is greater than zero and the depth count value has not reached the maximum depth, and returning to the step of querying the depth count value, and if a Call instruction is generated, adding 1 to the depth count value, and if a Return instruction is generated, subtracting 1 from the depth count value; The third judgment module is used for ending the step of generating an instruction sequence having a plurality of instructions according to the maximum depth of the return address stack if the depth count value reaches the maximum depth.

12. The device for generating a test case for verifying a return address stack according to claim 11, characterized in that: The second judgment module is used for: If the depth count value is greater than zero and the depth count value is less than or equal to a preset threshold, a Call instruction is generated with a first probability and a Return instruction is generated with a second probability; If the depth count value does not reach the maximum depth and the depth count value is greater than the preset threshold, a Call instruction is generated with a third probability and a Return instruction is generated with a fourth probability, wherein the third probability is greater than the fourth probability.

13. The device for generating a test case for verifying a return address stack according to claim 10, characterized in that: The position sequence determining unit comprises: A module for selecting instructions to be arranged, used for selecting instructions from the instruction sequence in sequence as instructions to be arranged; A first sorting module is used to determine, if the instruction to be arranged is the first instruction in the instruction sequence, the corresponding order of the instruction address to be assigned of the instruction to be arranged and the target address to be assigned of the instruction to be arranged in the position sequence according to the jump direction of the instruction to be arranged; a second sorting module, for placing the sequence corresponding to the instruction address to be assigned of the instruction to be arranged in the position sequence after the sequence corresponding to the target address to be assigned of the previous instruction of the instruction to be arranged, if the instruction to be arranged is the instruction after the first instruction in the instruction sequence, and the instruction to be arranged is a Call instruction, and determining the sequence corresponding to the target address to be assigned of the instruction to be arranged in the position sequence according to the jump direction of the instruction to be arranged; The third sorting module is used to place the sequence corresponding to the instruction address to be assigned of the instruction to be arranged in the position sequence after the sequence corresponding to the target address to be assigned of the previous instruction of the instruction to be arranged, and to place the sequence corresponding to the target address to be assigned of the instruction to be arranged in the position sequence after the sequence corresponding to the instruction address to be assigned of the previous Call instruction that has not been returned before the instruction to be arranged, if the instruction to be arranged is the instruction after the first instruction in the instruction sequence, and the instruction to be arranged is the Return instruction.

14. The device for generating a test case for verifying a return address stack according to claim 10, characterized in that: The address value assigning unit is used for: According to the corresponding order positions of the target addresses to be assigned and the instruction addresses to be assigned of each instruction in the position sequence, the target addresses to be assigned and the instruction addresses to be assigned of each instruction are respectively assigned successively increasing address values.

15. The device for generating a test case for verifying a return address stack according to claim 13, characterized in that: The position sequence determination unit further includes a fourth sorting module, and the fourth sorting module is used to: if the instruction to be arranged is an instruction after the first instruction in the instruction sequence, and the instruction to be arranged is a Call instruction of an indirect jump, select a first reusable instruction from the instructions before the instruction to be arranged as a reusable instruction, wherein the first reusable instruction is a Call instruction of an indirect jump, and the output position of the target address to be assigned of the first reusable instruction is the same as the output position of the target address to be assigned of the instruction to be arranged; If the instruction to be queued is an instruction after the first instruction in the instruction sequence, and the instruction to be queued is a Return instruction, then selecting a second reusable instruction from the instructions before the instruction to be queued as the reusable instruction, wherein the second reusable instruction is a Return instruction; Set the sequence position corresponding to the instruction address to be assigned of the instruction to be arranged in the position sequence and the sequence position corresponding to the instruction address to be assigned of the multiplexed instruction to the same sequence position; The address value assigning unit is further used for: if there are more than two instruction addresses to be assigned values ​​in the position sequence and the corresponding positions are the same, then assigning the same address value to the more than two instruction addresses to be assigned values.

16. The device for generating a test case for verifying a return address stack according to claim 14, characterized in that: The address value assignment unit is also used to assign the target address to be assigned of each Return instruction in the instructions and the instruction address to be assigned of the previous Call instruction that has not been returned before each Return instruction, such that the target address of each Return instruction is adjacent to the instruction address of the previous Call instruction that has not been returned before each Return instruction.

17. The device for generating a test case for verifying a return address stack according to claim 10, characterized in that: It also includes a gap address reservation unit, which is used to reserve a gap address between the instruction address of each Return instruction in the instructions and the instruction address of another adjacent instruction before and after or the target address of another instruction; and / or A gap address is reserved between the instruction address of each Call instruction in the instructions and the instruction address of another instruction adjacent to it or the target address of another Call instruction; and / or A gap address is reserved between the target address of each Call instruction in the instructions and the instruction address of another instruction adjacent to the previous or next instruction or the target address of another instruction.

18. The device for generating a test case for verifying a return address stack according to claim 17, characterized in that: It also includes a non-jump instruction writing unit, which is used to write non-jump instructions in the gap address and / or write non-jump instructions in the target address of each instruction.

19. An electronic device, characterized in that: The electronic device comprises: a shell, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the shell, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute the method for generating a test case for verifying the return address stack described in any one of claims 1 to 9.

Images