A chip layout pattern topology representation and hotspot detection method

Abstract

The present invention discloses a chip layout pattern topological representation and hotspot detection method, the steps include: converting layout data into binary image data for storage; converting polygons in the layout data into geometric sequence data for storage; saving polygon topological relationship data in the layout data; constructing a hotspot detection model based on contrastive learning, constructing a layout training set and a validation set according to the saved data, inputting the hotspot detection model and performing model training; respectively calculating the hotspot geometric sequence representation and non-hotspot geometric sequence representation of the test layout, inputting the trained hotspot detection model for testing, obtaining the probability values ​​of the hotspot geometric sequence and the non-hotspot geometric sequence, and judging whether the current test layout is a hotspot. The method of the present invention introduces the global topological representation information of the layout through serialized representation, and combines contrastive learning to solve the problem of traditional supervised learning in constructing a single decision boundary on an unbalanced data set.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit computer-aided design, and in particular to a chip layout pattern topology representation and hotspot detection method. Background Art

[0002] With the rapid development of semiconductor technology, the reduction of transistor feature size and the increase of chip size have brought great challenges to manufacturability design. Hotspot detection is a key step in manufacturability design, which can detect potential defect modes early. Traditional hotspot detection methods are mainly divided into two schemes: lithography simulation and layout retrieval. After each chip design, lithography simulation technology needs to simulate the entire lithography manufacturing process for the entire chip to accurately detect hotspots. However, simulation takes a lot of time and is not suitable for the current large-scale integrated circuit manufacturing; layout retrieval methods are based on matching or clustering to identify hotspot layout slices with similar patterns. However, this type of method relies on a large-scale layout pattern hotspot library and cannot retrieve hotspots outside the current library.

[0003] In order to solve the problems existing in traditional hotspot detection methods, machine learning-based methods have been applied to layout hotspot detection and achieved good results. Most of these methods convert layout files into binary images and use supervised learning methods to classify hotspots and non-hotspots. For example, Chinese invention patent application CN109522905A proposes a hotspot detection method based on FFT feature extraction. However, these methods are limited by the information extraction receptive field and cannot fully utilize the global topological information when distinguishing layout hotspots. In order to represent the global topological structure, another type of method uses polygons in the layout to construct graph structure data and uses graph neural networks for graph classification. For example, Chinese invention patent application CN116401999A provides a hotspot detection method based on graph neural networks. However, they decompose polygons into multiple rectangular nodes, which brings additional complexity. In addition, this type of method will cause the loss of polygon shape information to a certain extent. In general, existing methods based on convolutional neural networks and graph neural networks rely on supervised learning. When supervised learning constructs a single decision boundary on the entire data set, it is affected by the small number of hotspot data and often has a high false alarm rate.

[0004] Therefore, it is necessary to study a topological map representation method that is different from binary images and graph structures to solve the problem of traditional supervised learning constructing a single decision boundary on an imbalanced data set. Summary of the invention

[0005] The problem to be solved by the present invention is to provide a chip layout pattern topological representation and hotspot detection method, introduce the global topological representation information of the layout through serialized representation, and combine it with comparative learning to solve the problem of traditional supervised learning in constructing a single decision boundary on an unbalanced data set.

[0006] The present invention adopts the following technical solution: a chip layout pattern topology representation and hotspot detection method, comprising the following steps:

[0007] Step 1, convert the chip layout data into binary image data and save it;

[0008] Step 2: Convert the polygons in the chip layout data into geometric sequence data and save them;

[0009] Step 3, saving the polygon topological relationship data in the chip layout data;

[0010] Step 4: Build a hotspot detection model based on contrastive learning, build a layout training set and a validation set based on the data saved in steps 1 to 3, and input the hotspot detection model for model training;

[0011] Step 5. Calculate the hotspot geometry sequence representation and non-hotspot geometry sequence representation of the current test layout according to steps 2 and 3 respectively, input the hotspot detection model trained in step 4 for testing, and output the probability values ​​of the hotspot geometry sequence and non-hotspot geometry sequence respectively to determine whether the current test layout is a hotspot.

[0012] Preferably, step 2 converts the polygons in the chip layout data into geometric sequence data in the following manner:

[0013] Step 2.1: Extract the coordinates of each polygon in the layout and calculate the image moment of each polygon. ;

[0014] Step 2.2: Calculate the central moment of the polygon based on the image moment ;

[0015] Step 2.3: Calculate the regularized moment of the image moment based on the center distance ;

[0016] Step 2.4: Use as the first 7 items of the serialized representation;

[0017] Step 2.5, calculate the geometric invariant Hu moments of the polygon, and use the 7 invariant Hu moments as 7 vectors of serialized representation;

[0018] Step 2.6, respectively calculate the area-perimeter ratio, the minimum enclosing rectangle, and the concavity of the polygon as the last three vectors of the serialized representation;

[0019] Step 2.7: Fill the polygon serialization representation according to the hotspot or non-hotspot label of the chip layout until the preset serialization representation context length is reached.

[0020] Preferably, step 3 converts the polygon topological relationship data in the chip layout data into the following method:

[0021] Step 3.1, based on the central moment, calculate the centroid of the polygon and obtain the horizontal and vertical coordinate values ​​of the centroid of the kth polygon;

[0022] Step 3.2: Obtain the relative position relationship of the polygons in the layout based on the centroid coordinate values ​​of the polygons to obtain the topological structure in the layout.

[0023] Preferably, step 4 constructs a hotspot detection model based on contrastive learning and performs model training, the method is as follows:

[0024] Step 4.1, input chip version Figure 2 Value images and serialized representations;

[0025] Step 4.2: Calculate the topological information embedding through a multi-layer perceptron ;

[0026] Step 4.3, embedding the topological information and fusing it with the sequence representation;

[0027] Step 4.4, using a deep learning feature extractor to extract binary image features;

[0028] Step 4.5: Use a serialization Transformer model to extract serialization features;

[0029] Step 4.6, calculate the similarity between the image features and the serialized features, and normalize them;

[0030] Step 4.7: Calculate the similarity loss from image features to serialized features ;

[0031] Step 4.8: Calculate the similarity loss from serialized features to image features ;

[0032] Step 4.9: Calculate the total loss .

[0033] Preferably, step 5 determines whether the current test layout is a hotspot, and the method is as follows:

[0034] Step 5.1, assuming that the current test layout is a hotspot, calculate the hotspot sequence representation according to step 2;

[0035] Step 5.2, assuming that the current test layout is a non-hotspot, calculate the non-hotspot sequence representation according to step 2;

[0036] Step 5.3, based on the current test layout, calculate the polygon topology relationship information according to step 3;

[0037] Step 5.4, input the contrastive learning model trained in step 4, and output the similarity between the current test pattern and the hotspot sequence and the non-hotspot sequence;

[0038] Step 5.5: Select the result with the largest similarity as the final output to determine whether the current test layout is a hotspot.

[0039] The technical solution of the present invention also provides: an electronic device, comprising:

[0040] one or more processors;

[0041] a storage device having one or more programs stored thereon;

[0042] When the one or more programs are executed by the one or more processors, the one or more processors implement any of the above-mentioned chip layout pattern topology representation and hotspot detection methods.

[0043] The technical solution of the present invention also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps in any of the above-mentioned chip layout pattern topology representation and hotspot detection methods are implemented.

[0044] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0045] The present invention proposes a chip layout pattern topological representation method that is different from binary images and graph structures. The global topological representation information of the chip layout is introduced through serialized representation, and then the topological representation is combined with the binary image. The hotspot representation and non-hotspot representation are distinguished through comparative learning, which effectively solves the problem of traditional supervised learning in constructing a single decision boundary on an imbalanced data set. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a flow chart of the chip layout pattern topology representation and hot spot detection method of the present invention;

[0047] Figure 2 A schematic diagram showing the comparison results between an embodiment of the present invention and a classification network based on deep learning;

[0048] Figure 3 This is a schematic diagram of the comparison results of the algorithm accuracy and efficiency of the embodiment of the present invention;

[0049] Figure 4 Schematic diagram of comparison results between an embodiment of the present invention and a current advanced method. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the application is further elaborated in detail below in conjunction with the accompanying drawings. The described embodiments are only a part of the embodiments involved in the present invention. All non-innovative embodiments of other researchers in the field on this embodiment belong to the protection scope of the present invention. At the same time, for the step numbering in the embodiment of the present invention, it is only set for the convenience of explanation, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0051] In one embodiment of the present invention, a chip layout pattern topology representation and hot spot detection method, such as Figure 1 As shown, the following steps are included:

[0052] Step 1, converting the layout data into binary image data and saving it;

[0053] Step 2: Convert the polygons in the layout data into a geometric sequence format and save it;

[0054] Step 3, save the polygon topological relationship in the layout data;

[0055] Step 4: construct a hotspot detection model based on contrastive learning, and construct a layout training set and a validation set according to the obtained data, and input the constructed hotspot detection model for training;

[0056] Step 5: Test the layout. Calculate the hotspot sequence representation and non-hotspot sequence representation according to steps 2 and 3 respectively, and input the hotspot detection model trained in step 4 for testing. Output the probability values ​​of the hotspot geometry sequence and non-hotspot geometry sequence respectively to determine whether it is a hotspot.

[0057] In this embodiment, the specific implementation process of step 2 is as follows:

[0058] 1) Extract the coordinates of each polygon in the layout and calculate the image moment of each polygon :

[0059]

[0060] In the formula, k Indicates k polygons, p and q represents the order of the image moment, I Represents the image that the polygon is rendered into, x and y Represents the spatial coordinate value of the rendered image, W and H Indicates the width and height of the rendered image. Indicates k The order of the polygon is pq The image moment.

[0061] 2) Calculate the central moment of the polygon based on the image moment :

[0062] ;

[0063] In the formula, , , Respectively represent k The image moments of order 00, 01, 10 in the polygons are Indicates k The order of the polygon is pq The central moment of the image.

[0064] 3) In order to adapt the regularized distribution of the model input, the regularized moment of the image moment is calculated based on the center distance :

[0065] ;

[0066] In the formula, Indicates k The order of the polygon is pq The regularized image moment of .

[0067] 4) Use As the first 7 items of the serialized representation.

[0068] 5) Calculate the geometric invariance Hu moment of the polygon:

[0069]

[0070] Among them, f i represents a nonlinear transformation function of the regularized moment. In this embodiment, 7 invariant Hu moments are used as 7 vectors of serialization representation.

[0071] 6) Calculate the area-perimeter ratio, minimum enclosing rectangle, and concavity of the polygon as the last three vectors of the serialized representation.

[0072] 7) Fill the polygon serialization representation according to the layout label (hotspot or non-hotspot) until the context length acceptable to the model.

[0073] In this embodiment, step 3 needs to calculate the centroid of the polygon based on the central moment:

[0074]

[0075] In the formula, , Respectively represent k The horizontal and vertical coordinate values ​​of the centroid of each polygon; further, the relative position relationship of the polygons in the layout is obtained according to the coordinate values ​​of the centroid of the polygon, and the topological structure in the layout is obtained.

[0076] In this embodiment, step 4 constructs a hotspot detection model based on contrastive learning and performs model training. The process is as follows:

[0077] 1) Input a batch of versions Figure 2 Value images and serialized representations;

[0078] 2) Calculate the topological information embedding through a layer of multi-layer perceptron:

[0079] ;

[0080] In the formula, represents the activation function, represents a fully connected network. Indicates the number of polygons in the layout, subscript i Indicates i A map.

[0081] 3) Fusion of topological embedding and sequence representation:

[0082] ;

[0083] In the formula, represents the i-th layout sequence calculated in step 2;

[0084] 4) Extract binary image features using a deep learning feature extractor;

[0085] 5) Extract serialization features using a serialization Transformer model;

[0086] 6) Calculate the similarity between image features and serialized features and normalize them:

[0087]

[0088] ;

[0089] In the formula, The function represents a layer of neural network as feature projection, For the i Version Figure 2 The value image represents, represents a deep learning feature extractor for extracting binary image features, Represents the Transformer model for extracting serialized features, Respectively represent the binary image and the deep features extracted from the serialized representation, and the superscript T represents transposition. Represents feature similarity calculation.

[0090] 7) Calculate the similarity loss from image features to serialized features:

[0091] ;

[0092] In the formula, represents the hyperparameters of the cross entropy function, represents the natural exponential function.

[0093] 8) Calculate the similarity loss from serialized features to image features:

[0094] ;

[0095] 9) Calculate the total loss:

[0096] .

[0097] In this embodiment, the specific implementation process of step 5 is as follows:

[0098] 1) Assuming that the current test sample is a hotspot, calculate the hotspot sequence representation according to step 2;

[0099] 2) Assuming that the current test sample is a non-hotspot, calculate the non-hotspot sequence representation according to step 2;

[0100] 3) Calculate the topology information according to step 3 based on the current test sample;

[0101] 4) Input the model trained in step 4 and output its similarity with the hotspot sequence and the non-hotspot sequence;

[0102] 5) Select the result with the largest similarity as the final output of the model.

[0103] In an embodiment of the present invention, an electronic device is also provided, including: one or more processors; a storage device on which one or more programs are stored; when the one or more programs are executed by the one or more processors, the one or more processors implement any of the chip layout pattern topology representation and hotspot detection methods described above.

[0104] In an embodiment of the present invention, a computer-readable storage medium is further provided, on which a computer program is stored. When the program is executed by a processor, the steps in any of the above-mentioned chip layout pattern topology representation and hotspot detection methods are implemented.

[0105] Furthermore, the inventive method is compared with a classification network based on deep learning, and the results are as follows: Figure 2As shown. It can be seen that compared with the classification networks based on deep learning ResNet50 (R-50), MobileNetV2 (M-V2), VisionTransformer (ViT-16), and SwinTransformer-Tiny (Swin-T), the method of the present invention can achieve the best accuracy and computational efficiency.

[0106] In order to test the flexibility of the contrastive learning method of the present invention, the image features obtained by contrastive learning training of the present invention are fine-tuned in a supervised manner (marked as the present invention in the figure). ), using only one layer of linear neural network to achieve performance comparable to existing deep neural networks.

[0107] Furthermore, the method of the present invention is compared with the above method in terms of computational efficiency. Figure 3 As shown in FIG. 1 , the method of the present invention can achieve the optimal inference speed (FPS) under the premise of reducing a certain degree of accuracy; as shown in FIG. Figure 4 As shown, compared with the current advanced hotspot detection method on ICCAD2019, the method of the present invention can achieve the best accuracy and the lowest false alarm rate.

[0108] In summary, the chip layout pattern topological representation and hotspot detection method of the present invention introduces the global topological representation information of the layout through serialized representation, and combines it with comparative learning, which effectively solves the problem of traditional supervised learning in constructing a single decision boundary on an unbalanced data set.

[0109] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A chip layout pattern topology representation and hotspot detection method, characterized in that: The steps include: Step 1, convert the chip layout data into binary image data and save it; Step 2: Convert the polygons in the chip layout data into geometric sequence data and save them as follows: Step 2.1: Extract the coordinates of each polygon in the layout and calculate the image moment of each polygon. : ； In the formula, k Indicates k polygons, p and q represents the order of the image moment, I Represents the image that the polygon is rendered into, x and y Represents the spatial coordinate value of the rendered image, W and H Indicates the width and height of the rendered image; Indicates k The order of the polygon is pq The image moment of Step 2.2: Calculate the central moment of the polygon based on the image moment : ； In the formula, , , Respectively represent k The image moments of order 00, 01, 10 in the polygons are Indicates k The order of the polygon is pq The image center moment of Step 2.3: Calculate the regularized image moment based on the center distance : ； In the formula, Indicates k The order of the polygon is pq The regularized image moment of ; Step 2.4: Use as the first 7 items of the serialized representation; Step 2.5, calculate the geometric invariance Hu moment of the polygon: ； In the formula, Represents the nonlinear transformation function of the regularized moment, using 7 invariant Hu moments as 7 vectors of serialization representation; Step 2.6, respectively calculate the area-perimeter ratio, the minimum enclosing rectangle, and the concavity of the polygon as the last three vectors of the serialized representation; Step 2.7, filling the polygon serialization representation according to the hotspot or non-hotspot label of the chip layout until the preset serialization representation context length; Step 3: Save the polygon topological relationship data in the chip layout data as follows: Step 3.1, calculate the center of mass of the polygon based on the central moment: ； In the formula, , Respectively represent k The horizontal and vertical coordinate values ​​of the centroid of each polygon; Step 3.2, obtaining the relative position relationship of the polygons in the layout according to the centroid coordinate values ​​of the polygons, and obtaining the topological structure in the layout; Step 4: Build a hotspot detection model based on contrastive learning. Build a layout training set and a validation set based on the data saved in steps 1 to 3. Input the hotspot detection model for model training. The method is as follows: Step 4.1, input the binary image and serialized representation of the chip layout; Step 4.2: Calculate the topological information embedding through a multi-layer perceptron : ； In the formula, represents the activation function, represents a fully connected network. Indicates the number of polygons in the layout, subscript i Indicates i a map; Step 4.3: Fusion of topological information embedding and sequence representation: ； In the formula, represents the first i A sequence of layouts is represented; Step 4.4, using a deep learning feature extractor to extract binary image features; Step 4.5: Use a serialization Transformer model to extract serialization features; Step 4.6: Calculate the similarity between the image features and the serialized features and normalize them: ； In the formula, The function represents a layer of neural network as feature projection, For the i A binary image representation of the map, represents a deep learning feature extractor for extracting binary image features, Represents the Transformer model for extracting serialized features, Respectively represent the binary image and the deep features extracted from the serialized representation, and the superscript T represents transposition. Indicates feature similarity calculation; Step 4.7: Calculate the similarity loss from image features to serialized features : ； In the formula, represents the hyperparameters of the cross entropy function, represents the natural exponential function; Step 4.8: Calculate the similarity loss from serialized features to image features : ； Step 4.9: Calculate the total loss : ； Step 5. Calculate the hotspot geometry sequence representation and non-hotspot geometry sequence representation of the current test layout according to steps 2 and 3 respectively, input the hotspot detection model trained in step 4 for testing, and output the probability values ​​of the hotspot geometry sequence and non-hotspot geometry sequence respectively to determine whether the current test layout is a hotspot.

2. The chip layout pattern topology representation and hotspot detection method according to claim 1, characterized in that: Step 5 determines whether the current test layout is a hotspot, as follows: Step 5.1, assuming that the current test layout is a hotspot, calculate the hotspot sequence representation according to step 2; Step 5.2, assuming that the current test layout is a non-hotspot, calculate the non-hotspot sequence representation according to step 2; Step 5.3, based on the current test layout, calculate the polygon topology relationship information according to step 3; Step 5.4, input the contrastive learning model trained in step 4, and output the similarity between the current test pattern and the hotspot sequence and the non-hotspot sequence; Step 5.5: Select the result with the largest similarity as the final output to determine whether the current test layout is a hotspot.

3. An electronic device, characterized in that: include: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the chip layout pattern topology representation and hotspot detection method as described in any one of claims 1 to 2.

4. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the program is executed by a processor, the steps in the chip layout pattern topology representation and hotspot detection method described in any one of claims 1 to 2 are implemented.

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