Driving method of display panel and display device

Abstract

The application discloses a driving method of a display panel and a display device. The driving method comprises the following steps: providing a subarea enabling signal to a subarea enabling signal line, so that a shift register outputs a scanning signal to a corresponding connected pixel circuit according to the subarea enabling signal, to control the refresh frequency of the corresponding connected pixel circuit, thereby realizing a subarea multi-frequency display mode; and in at least one frame of the subarea multi-frequency display mode, providing a driving signal corresponding to the driving mode of a second display subarea to a driving signal line, before the scanning signal output by a first shift register corresponding to the second display subarea is controlled to be a first conduction level. The embodiment of the application can improve the phenomenon of display unevenness and improve the display effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a driving method of display panel and display device. BACKGROUND

[0002] In use, many application scenarios of electronic products (such as mobile phones, tablet computers, etc.) will use split-screen display, for example, a user watches a video while playing a game or reading a novel, etc. The required frequencies of two scenes of split-screen display are not the same in most cases, for example, reading a novel may only need 10Hz refresh or lower, watching a video needs 36Hz or 60Hz, and playing a game needs 60Hz or higher. At present, there is a problem of display abnormality near the split line when split-screen display, which affects the display effect. SUMMARY

[0003] The present application provides a driving method of display panel and display device, which can improve the phenomenon of display abnormality near the split line when split-screen display, and improve the display effect.

[0004] In a first aspect, the present application provides a driving method of display panel, the display panel comprising at least two display partitions, the at least two display partitions comprising a first display partition and a second display partition, the first display partition and the second display partition being adjacent along a data line extension direction, each display partition comprising a plurality of pixel circuits, the pixel circuits being electrically connected with the data line; the display panel further comprising a gate drive circuit and at least one partition enable signal line, the gate drive circuit comprising a plurality of cascaded shift registers, the shift registers being electrically connected with the partition enable signal line in correspondence; the driving method comprising: providing a partition enable signal to the partition enable signal line, so that the shift registers output a scan signal to the corresponding connected pixel circuits according to the partition enable signal, to control the refresh frequency of the corresponding connected pixel circuits, thereby realizing a partition multi-frequency display mode; wherein the scan signal output by at least one shift register comprises a first conduction level; within at least one frame of the partition multi-frequency display mode, before controlling the scan signal output by the first shift register corresponding to the second display partition to be the first conduction level, a driving signal corresponding to the driving mode of the second display partition is provided to the driving signal line; wherein the driving signal line comprises the partition enable signal line and / or the data line; wherein in the partition multi-frequency display mode, the refresh frequency of the second display partition is greater than the refresh frequency of the first display partition; the first shift register corresponding to the second display partition is the shift register connected with the first row of pixel circuits in the second display partition; the pixel circuit is used for writing a data signal on the data line according to the received first conduction level; wherein in the driving mode of the second display partition, the level on the partition enable signal line is an enable level, and the data line transmits a data signal.

[0005] In a second aspect, the embodiments of the present application provide a driving method of a display panel. The display panel comprises at least two display partitions, the at least two display partitions comprising a first display partition and a second display partition, the first display partition and the second display partition being adjacent along a data line extension direction, each display partition comprising a plurality of pixel circuits, the pixel circuits being electrically connected with the data lines; the display panel further comprises a gate driving circuit and at least one partition enable signal line, the gate driving circuit comprising a plurality of cascaded shift registers, the shift registers being electrically connected with the partition enable signal line in correspondence; the driving method comprises: providing a partition enable signal to the partition enable signal line, so that the shift registers output a scanning signal to the corresponding connected pixel circuits according to the partition enable signal, to control the refresh frequency of the corresponding connected pixel circuits, thereby realizing a partition multi-frequency display mode; wherein the scanning signal output by at least one shift register comprises a first conduction level of the partition enable signal; within at least one frame of the partition multi-frequency display mode, before controlling the scanning signal output by a first shift register corresponding to the second display partition to be the first conduction level, a first conduction level is provided to a set partition enable signal line; wherein the set partition enable signal line is a partition enable signal line connected with the first shift register corresponding to the second display partition; wherein in the partition multi-frequency display mode, the refresh frequency of the second display partition is greater than the refresh frequency of the first display partition; the first shift register corresponding to the second display partition is a shift register connected with a first row of pixel circuits in the second display partition; the pixel circuit is used for writing a data signal on the data line according to the received first conduction level.

[0006] In a third aspect, an embodiment of the present application provides a display device, comprising a display panel and a display driving module, the display panel comprising at least two display partitions, the at least two display partitions comprising a first display partition and a second display partition, the first display partition and the second display partition being adjacent along a data line extension direction, each display partition comprising a plurality of pixel circuits, the pixel circuits being electrically connected with the data lines; the display panel further comprising a gate driving circuit and at least one partition enable signal line, the gate driving circuit comprising a plurality of cascaded shift registers, the shift registers being electrically connected with the partition enable signal line in correspondence, the shift registers being configured to control refresh frequencies of the corresponding connected pixel circuits according to partition enable signals of the partition enable signal line; the display driving module being configured to provide the partition enable signal line with the partition enable signal, so that the shift registers output scan signals to the corresponding connected pixel circuits according to the partition enable signal, to control refresh frequencies of the corresponding connected pixel circuits, thereby realizing a partition multi-frequency display mode; wherein the scan signal output by at least one shift register comprises a first conduction level; within at least one frame of the partition multi-frequency display mode, before the scan signal output by a first shift register corresponding to the second display partition is controlled to be the first conduction level, a driving signal corresponding to a driving mode of the second display partition is provided to a driving signal line; wherein the driving signal line comprises the partition enable signal line and / or the data line; wherein in the partition multi-frequency display mode, a refresh frequency of the second display partition is greater than a refresh frequency of the first display partition; the first shift register corresponding to the second display partition is a shift register connected with a first row of pixel circuits in the second display partition; the pixel circuits are configured to write data signals on the data line according to the received first conduction level; wherein in the driving mode of the second display partition, a level on the partition enable signal line is an enable level, and the data line transmits the data signal.

[0007] The driving method of the display panel provided by the embodiment of the present application is to provide a partition enable signal to a partition enable signal line, so that the shift register outputs a scanning signal to the pixel circuit connected thereto according to the partition enable signal, to control the refresh frequency of the pixel circuit connected thereto, thereby realizing the partition multi-frequency display mode. In at least one frame of the partition multi-frequency display mode, before the scanning signal output by the first shift register corresponding to the second display partition is controlled to be at the first conduction level, a driving signal corresponding to the refresh frequency of the second display partition is provided to the driving signal line, the driving signal including the partition enable signal on the partition enable signal line and / or the data signal on the data line, so that the pixel circuit connected to the first shift register corresponding to the second display partition has the data signal accessed thereto in a state matched with the driving mode of the pixel circuit before the pixel circuit starts to write the data signal; and / or, before the scanning signal output by the first shift register of the second display partition is at the first conduction level, the partition enable signal on the partition enable signal line connected to the first shift register of the second display partition is already in a state matched with the driving mode of the second display partition, so that the process of jumping from the off level to the first conduction level of the partition enable signal is completed before the first shift register corresponding to the second display partition outputs the scanning signal at the first conduction level, and then when the first shift register corresponding to the second display partition outputs the scanning signal at the first conduction level, that is, when the pixel circuit starts to write the data, the first conduction level has reached a stable state, so that the pixel circuit can normally write the data. In this way, the brightness of the pixels in the border area of the second display partition and the first display partition can be switched more smoothly, the phenomenon of display abnormality near the boundary line during split-screen display can be improved, and the display effect can be improved.

[0008] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0010] Figure 1 is a schematic diagram of a scene where display abnormality exists at the boundary line during split-screen display of the display panel;

[0011] Figure 2 is Figure 1 is a voltage waveform diagram of the corresponding signal;

[0012] Figure 3 is a structural schematic diagram of a display device provided by an embodiment of the present application;

[0013] Figure 4 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0014] Figure 5 is a flowchart of a driving method of a display panel provided by an embodiment of the present application;

[0015] Figure 6 is a schematic diagram of another driving method of a display panel provided by an embodiment of the present application;

[0016] Figure 7 is a structural schematic diagram of a gate driving circuit provided by an embodiment of the present application;

[0017] Figure 8 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0018] Figure 9 is a schematic diagram of a first display frame and a second display frame partition enabling signal jump provided by an embodiment of the present application;

[0019] Figure 10 is a flowchart of another driving method of a display panel provided by an embodiment of the present application;

[0020] Figure 11 is a flowchart of another driving method of a display panel provided by an embodiment of the present application;

[0021] Figure 12 is a flowchart of another driving method of a display panel provided by an embodiment of the present application;

[0022] Figure 13 is a working timing diagram of a display panel provided by an embodiment of the present application;

[0023] Figure 14 is a structural schematic diagram of a shift register provided by an embodiment of the present application;

[0024] Figure 15 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0025] Figure 16 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0026] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application, so that those skilled in the art can better understand the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to include only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0028] As described in the background, in the related art, when the display panel is split-screen displayed, there is an abnormal display problem near the boundary line, for example, the display area is divided into a low refresh frequency area and a high refresh frequency area in the column direction in turn, and a bright line may be generated near the boundary line between the low refresh frequency area and the high refresh frequency area, affecting the display effect.

[0029] Based on the above technical problems, the inventors have found the causes of the above technical problems after long-term research, Figure 1 is a schematic diagram of a scenario of display abnormality of a display panel in split-screen display. Figure 2 is Figure 1 is a voltage waveform diagram of the corresponding signal. In the following, Figure 1 and Figure 2 The causes of the above technical problems are described.

[0030] As shown in Figure 1 , for example, the display area of the display panel is divided into a first display partition AA1, a second display partition AA2 and a third display partition AA3 in the column direction in turn. For example, the refresh frequency of the first display partition AA1 and the third display partition AA3 is 1Hz, and the refresh frequency of the second display partition AA2 is 120Hz.

[0031] For a display panel capable of switching display frequency, the display frame of a sub-pixel can be divided into an active frame and an idle frame. In the active frame, the shift register provides a turn-on potential to the pixel circuit, so that the data voltage is written into the pixel circuit; in the idle frame, the shift register provides an off potential to the pixel circuit, and the pixel circuit no longer performs data writing.

[0032] The refresh frequency can be understood as the number of active frames contained in a unit of time. Exemplarily, in high-frequency display, only active frames can be included. With continued reference to Figure 1 , it is assumed that, at a refresh frequency f, the display frame of the second display partition AA2 only includes active frames, and the refresh frequency of the first display partition AA1 and the third display partition AA3 is lower than that of the second display partition AA2. Exemplarily, when f = 60 Hz, the second display partition AA2 refreshes 60 display frames in 1 second. The low-frequency refresh implementation of the first display partition AA1 and the third display partition AA3 is as follows: a keep frame is inserted between adjacent active frames of the second display partition AA2, the total number of display frames contained in a unit of time remains unchanged, and the display duration of each display frame also remains unchanged. Exemplarily, when the refresh frequency of the first display partition AA1 and the third display partition AA3 is f / 2, 1 keep frame is inserted between every two adjacent active frames. When the refresh frequency of the first display partition AA1 and the third display partition AA3 is f / 3, 2 keep frames are inserted between every two adjacent active frames. By analogy, when the refresh frequency of the first display partition AA1 and the third display partition AA3 is f / (N+1), N keep frames are inserted between every two adjacent active frames.

[0033] The display device includes a display driving module and a display panel, the display driving module includes a data driver, and the display panel includes a pixel circuit. The function of the data driver is to transmit data signals to the pixel circuit to realize the correct display of the pixels.

[0034] The load size of the data driver is related to the refresh frequency, and the greater the refresh frequency, the greater the load of the data driver. It is assumed that there are two display partitions, the refresh frequency of partition A is 1 Hz, and the refresh frequency of partition B is 60 Hz. In partition A, because the refresh frequency is low, the data needs to be updated only once per second, the voltage jump frequency of the data transmitted by the data driver is low, and the load is relatively small. In partition B, the refresh frequency is 60 Hz, and the data needs to be updated 60 times per second, the voltage jump frequency of the data transmitted by the data driver is much higher than that of partition A, so the load thereof will be much larger than that of partition A.

[0035] In the process of partition multi-frequency display of the display device, in some display frames, the sub-pixels in some display partitions do not perform data refreshing, and the sub-pixels in other display partitions perform data refreshing, that is, the display frame for local refreshing of the display panel is referred to as a first display frame. For example, in the first display frame, the sub-pixels in the first display partition AA1 do not perform data refreshing, and the sub-pixels in the second display partition AA2 perform data refreshing. Since in the first display frame, each sub-pixel in the second display partition AA2 needs to perform a data writing process to complete data refreshing, and each sub-pixel in the first display partition AA1 performs data maintaining and does not need to perform data refreshing again, at this time, the load of the data line is small, and by setting the data voltage transmitted on the data line to be in a high resistance state (Hiz) or a fixed voltage, energy consumption can be effectively saved. That is, in the first display partition AA1, since the refresh frequency is low, the update frequency of the pixel circuit to data is also low, and the demand for electric energy is relatively small, so the data driver does not need to frequently provide a large amount of electric energy, and thus is in a light load state. When entering a high refresh area (that is, the second display partition AA2), the load of the data driver changes. The refresh frequency of the high refresh area is high, and the pixel circuit needs to update data more frequently. For example, the high refresh area may need to update pixel data tens or even hundreds of times per second, which requires the data driver to provide more electric energy to meet the demand for data transmission and pixel refreshing, so the data driver enters a heavy load state.

[0036] The transition from the light load state of the low refresh area to the heavy load state of the high refresh area can couple other driving signals or power signals. For example, in the case of a sudden change in the voltage on the data line, the driving power signal changes, the partition enable signal for controlling the refresh frequency of the pixel circuit in the display panel is generated according to the driving power signal, and thus the partition enable signal is affected. In this case, the charging degree of the storage capacitor in the pixel circuit is affected, and finally display abnormalities occur. Figure 2 As shown in FIG. 1, for example, when the refresh frequency of the first display partition AA1 changes from 1 Hz to 120 Hz of the second display partition AA2, the load of the data driver changes, so that the first conduction level NVGH1 of the partition enable signal VFE falls, the level stability fluctuates, the front rows of pixels in the second display partition AA2 are different from other rows in charging, and abnormal display occurs. When the first conduction level NVGH1 is concave, the partition enable signal VFE gradually rises from a low level to a high level, and in this process, near the boundary between the first display partition AA1 and the second display partition AA2, the part of the rows of the second display partition AA2 close to the first display partition AA1 produce a bright band.

[0037] In view of the above research findings of the inventors, in order to solve the problems in the prior art, embodiments of the present application provide a display panel driving method and a display device. First, a display device to which the display panel driving method provided by the embodiments of the present application can be applied is introduced.

[0038] Figure 3 is a structural schematic diagram of a display device provided by an embodiment of the present application. Referring to Figure 3 , the display device includes a display panel 01 and a display driving module 02. The display driving module 02 can be a display driver integrated circuit (DDIC) or a touch and display driver integration (TDDI) chip, etc.

[0039] The display panel 01 can include a display area AA and a non-display area NAA. The display area AA includes at least two display sub-areas. Each display sub-area includes a plurality of pixel circuits PX arranged in an array.

[0040] The display panel 11 further includes a plurality of scan lines GL and a gate driving circuit 11. The plurality of scan lines GL extend along a first direction X and are arranged in sequence along a second direction Y. Each scan line GL is connected to pixel circuits PX of a corresponding row (which can be one or more rows). The gate driving circuit 11 is connected to the plurality of scan lines GL. The gate driving circuit 11 can be located in the non-display area NAA. The display panel 01 further includes a plurality of data lines DL extending along the second direction Y and arranged along the first direction X. Each data line DL is connected to pixel circuits PX of a corresponding column (which can be one or more columns). The first direction X (which can be a row direction) and the second direction Y (which can be a column direction) intersect, for example, can be perpendicular. A column of pixel circuits PX can also be connected to two corresponding data lines, which is not specifically limited in the embodiments of the present application.

[0041] Figure 4 is a structural schematic diagram of a display panel provided by an embodiment of the present application. Referring to Figure 3 and Figure 4 , the at least two display sub-areas include a first display sub-area AA1 and a second display sub-area AA2. Along a data line extension direction (for example, the second direction Y of Figure 3 , the first display sub-area AA1 and the second display sub-area AA2 are adjacent. The first display sub-area AA1 is a previous display sub-area of the second display sub-area AA2. The refresh frequency of the second display sub-area AA2 is greater than that of the first display sub-area AA1. The pixel circuits PX are located in the display area. Each display sub-area includes a plurality of rows of pixel circuits PX. The pixel circuits PX are configured to receive a scan signal output by the gate driving circuit 12. The refresh frequency refers to the number of times a screen is refreshed per second.

[0042] Reference Figure 4 The gate drive circuit 11 includes a plurality of shift registers 10, when the display panel 01 includes a plurality of rows of pixel circuits PX, the plurality of shift registers 10 are connected in cascade, and each of the plurality of shift registers 10 provides a scan signal to the corresponding row (for example, at least one row) of pixel circuits PX. The first stage shift register is connected to the input signal EIN. The display panel further includes at least one partition enable signal line ENL, and the shift register 10 is electrically connected to the partition enable signal line ENL.

[0043] Figure 5 is a flowchart of a display panel driving method provided by an embodiment of the present application. As shown in Figure 5 The display panel driving method includes the following steps.

[0044] S101, a partition enable signal is provided to the partition enable signal line, so that the shift register outputs a scan signal to the corresponding connected pixel circuit according to the partition enable signal, to control the refresh frequency of the corresponding connected pixel circuit, thereby realizing a partition multi-frequency display mode.

[0045] Specifically, the partition multi-frequency display mode is a mode in which at least two display partitions have different refresh frequencies. The scan signal output by the at least one shift register includes a first conduction level NVGH1.

[0046] Optionally, the partition enable signal VFE includes an enable level and a non-enable level. By controlling the time period of the enable level and the non-enable level of the partition enable signal VFE on the partition enable signal line in a frame, the scan signal output by different shift registers is controlled to be the first conduction level NVGH1 or the off level NVGL, so as to control the refresh frequency of the corresponding connected pixel circuit, thereby realizing the partition multi-frequency display mode.

[0047] In some optional embodiments of the present application, the enable level of the partition enable signal VFE can be the first conduction level NVGH1 of the scan signal output by the shift register. When the shift register meets the condition of outputting the partition enable signal VFE, and the partition enable signal VFE is the first conduction level NVGH1, the shift register can output the enable level of the partition enable signal VFE, that is, the first conduction level NVGH1. When the shift register meets the condition of outputting the partition enable signal VFE, and the partition enable signal VFE is the non-enable level, the shift register can output the non-enable level of the partition enable signal VFE, that is, the off level NVGL.

[0048] In some optional embodiments of the present application, the partition enabling signal VFE can serve as a control signal for the first conducting level output module of the shift register to output the first conducting level NVGH1. The input terminal of the first conducting level output module can be connected to the first conducting level NVGH1. The potential at the control terminal of the first conducting level output module can be controlled by the partition enabling signal VFE and other control signals. When the partition enabling signal VFE is at the enabling level, the first conducting level output module can output the first conducting level NVGH1 if the other control signals all satisfy the condition for the first conducting level output module to output the first conducting level. When the partition enabling signal VFE is at the non-enabling level, the first conducting level output module cannot output the first conducting level NVGH1 but outputs the off level from the off level output module in the shift register if the other control signals all satisfy the condition for the first conducting level output module to output the first conducting level.

[0049] For example, the scan signals output by the shift registers 10 are transmitted to the functional modules in the pixel circuits PX in each row through the scan lines in each row. When the scan signal output by a certain shift register 10 contains the first conducting level, the pixel circuit PX in the corresponding row can be controlled to refresh data, so that the current frame of the pixel circuit PX in the row is a refresh frame. When the scan signal output by a certain shift register 10 does not contain the first conducting level, the pixel circuit PX in the corresponding row cannot refresh data, so that the current frame of the pixel circuit PX in the row is a hold frame. Based on this, the potential of the partition enabling signal VFE can be controlled to jump, so that in one display frame, the data writing stage of some pixel circuits PX is realized, the first conducting level is output by the corresponding shift register 10, and the high-frequency display of the display partition where the pixel circuit PX is located is realized. The data writing stage of some pixel circuits PX is realized, the off level is output by the corresponding shift register 10, and the low-frequency display of the display partition where the pixel circuit PX is located is realized, so as to realize the display of different frequencies in the column direction of the display device.

[0050] S102、in at least one frame of the partition multi-frequency display mode, before controlling the scan signal output by the first shift register corresponding to the second display partition to be the first conducting level, providing a driving signal corresponding to the driving mode of the second display partition to the driving signal line.

[0051] The driving signal line includes a partition enable signal line and / or a data line. In the partition multi-frequency display mode, the refresh frequency of the second display partition AA2 is greater than the refresh frequency of the first display partition AA1. The first shift register corresponding to the second display partition AA2 is a shift register connected to the first row of pixel circuits in the second display partition AA2. The pixel circuit is configured to write a data signal on the data line according to a received first conduction level. In the driving mode of the second display partition, the level on the partition enable signal line is an enable level, and the data line transmits a data signal.

[0052] Specifically, the driving signal includes a partition enable signal VFE and a data signal Vdata. The partition enable signal VFE indirectly affects the writing of the data signal Vdata by controlling the output of the scan signal of the shift register. For example, when the partition enable signal VFE causes the shift register to output a corresponding scan signal (such as a first conduction level), the pixel circuit will write the data signal Vdata on the data line according to this scan signal.

[0053] The data line transmits a data signal, that is, the data signal on the data line can change according to different display pictures, or in other words, the data signal on the data line can be different according to the display gray scale corresponding to the pixel, and can not be a direct current level or not transmit a signal. For example, different frames of data lines can correspond to different data signals for the same pixel, and the same frame of data lines can transmit different data signals to different pixels.

[0054] Optionally, the first display partition AA1 is a display partition adjacent to the second display partition AA2 in the refresh direction of the display panel (i.e., the extension direction of the data line, for example Figure 2 the second direction Y), and in a full brushing frame (i.e., a display frame in which each display partition of the display panel performs data writing), the first display partition AA1 writes data before the second display partition AA2. For further reference Figure 4, the driving signal line is provided with a driving signal corresponding to the refresh frequency of the second display partition AA2 before the scan signal output by the first shift register corresponding to the second display partition AA2 is at the first conductive level. This enables the data signal to be prepared in advance according to the refresh frequency and timing requirements of the second display partition AA2. For example, for the second display partition AA2, the data signal can be prepared in advance at a higher frequency and with appropriate data volume. Due to the advance preparation and orderly transmission of the data signal, the load of the data driver will not suddenly increase. Instead, it is more evenly distributed in time, avoiding the problem of overload caused by the concentration of load in a certain time period during partition switching. For example, during the process of switching from the first display partition AA1 to the second display partition AA2, the load of the data driver gradually transitions from a low load state to a load state suitable for the second display partition AA2, achieving load averaging. When the data driver load is averaged, it can more stably provide data signals to different display partitions. Near the boundary line, the data signal transmission will not be unstable due to excessive load on one side, thereby reducing the possibility of display abnormalities. Before the scan signal output by the first shift register corresponding to the second display partition AA2 is at the first conductive level, the partition enable signal of the partition enable signal line connected to the first shift register of the second display partition AA2 is already in a state matched with the refresh frequency of the second display partition AA2. In this way, the process of jumping from the off level to the first conductive level of the partition enable signal can be completed before the first conductive level of the scan signal output by the first shift register corresponding to the second display partition AA2, and thus when the first conductive level of the scan signal output by the first shift register corresponding to the second display partition AA2, i.e., when the pixel circuit starts to write data, the first conductive level has already reached a stable first conductive level, enabling the pixel circuit to normally write data. This allows the brightness of the pixels in the border area of the second display partition AA2 and the first display partition AA1 to switch more smoothly, and can improve the display abnormality phenomenon near the boundary line during split-screen display, improving the display effect.

[0055] The display panel driving method provided by the embodiment of the present application controls the refresh frequency of the pixel circuit connected to the corresponding shift register by providing the partition enable signal to the partition enable signal line, so that the shift register outputs the scan signal to the pixel circuit connected to the corresponding shift register according to the partition enable signal, thereby realizing the partition multi-frequency display mode. In at least one frame of the partition multi-frequency display mode, the scan signal output by the first shift register corresponding to the second display partition is controlled to be the first conduction level, and the driving signal corresponding to the refresh frequency of the second display partition is provided to the driving signal line before that. The driving signal includes the partition enable signal on the partition enable signal line and / or the data signal on the data line. The pixel circuit connected to the first shift register of the second display partition can have the data signal accessed by the pixel circuit in a state matched with the driving mode of the pixel circuit before the data signal starts to be written. In addition, the partition enable signal on the partition enable signal line connected to the first shift register of the second display partition is in a state matched with the driving mode of the second display partition before the scan signal output by the first shift register of the second display partition is the first conduction level. In this way, the process of jumping from the off level to the first conduction level of the partition enable signal can be completed before the first conduction level of the scan signal output by the first shift register corresponding to the second display partition. Therefore, when the first conduction level of the scan signal output by the first shift register corresponding to the second display partition is reached, that is, when the pixel circuit starts to write data, the first conduction level has reached a stable first conduction level, so that the pixel circuit can normally write data. In this way, the brightness of the pixels in the border area of the second display partition and the first display partition can be switched more smoothly, the display abnormality phenomenon near the division line during split-screen display can be improved, and the display effect can be improved.

[0056] Optionally, the enable level is the first conduction level NVGH1; in the partition multi-frequency display mode, the scan signal output by the at least one shift register includes the first conduction level NVGH1 of the partition enable signal VFE. Figure 6 FIG. 6 is a schematic diagram of another display panel driving method provided by the embodiment of the present application. Referring to FIG. 6, Figure 3 to Figure 6 The display panel driving method includes the following steps.

[0057] S201, a partition enable signal is provided to a partition enable signal line, so that a shift register outputs a scan signal to a pixel circuit connected to the corresponding shift register according to the partition enable signal, to control the refresh frequency of the pixel circuit connected to the corresponding shift register, thereby realizing a partition multi-frequency display mode.

[0058] S202, in at least one frame of the partition multi-frequency display mode, a first conduction level is provided to the partition enable signal line before the scan signal output by the first shift register corresponding to the second display partition is controlled to be the first conduction level.

[0059] The set partition enable signal line is a partition enable signal line connected to the first shift register corresponding to the second display partition AA2.

[0060] Specifically, the output of the shift register 10 is affected by the partition enable signal VFE. The partition enable signal VFE indirectly affects the writing of the data signal Vdata by controlling the output of the shift register 10. When the partition enable signal line provides the first conduction level, the shift register 10 can output the first conduction level under the appropriate conditions, so that the pixel circuit writes the data signal on the data line according to the scan signal.

[0061] The pixel circuit writes the data signal on the data line according to the received scan signal (such as the first conduction level NVGH1). Providing the first conduction level NVGH1 to the partition enable signal line in advance can make the partition enable signal jump from the off level to the first conduction level before the first conduction level is output from the first shift register corresponding to the second display partition AA2, so that even in the case of load change of the first display partition AA1 and the second display partition AA2 caused by voltage change on the data line, the time of the first conduction level jumping from the off level to the first conduction level is advanced, and the first conduction level is less affected by the load change on the data line, and the data voltage writing of the pixel circuit is less affected, thereby improving the display abnormality phenomenon.

[0062] Optionally, in at least part of the frames in the partition multi-frequency display mode, the time of providing the first conduction level to the set partition enable signal line is gradually increased or gradually decreased compared to the time of outputting the first conduction level from the first shift register corresponding to the second display partition AA2.

[0063] Specifically, in at least part of the frames in the partition multi-frequency display mode, the time of providing the first conduction level to the partition enable signal line connected to the first shift register corresponding to the second display partition AA1 is advanced compared to the time of outputting the first conduction level from the first shift register corresponding to the second display partition AA2, and the advanced time is gradually increased or gradually decreased.

[0064] For example, assuming that the display panel is divided into two display partitions, the refresh frequency of the first display partition AA1 is 1Hz, and the refresh frequency of the second display partition AA2 is 120Hz, and now the first display partition AA1 is switched to the second display partition AA2.

[0065] In the partition multi-frequency display mode, the second frame, the third frame and the fourth frame perform the gradual change operation. In the second frame, the time for providing the first display partition AA2 corresponding first shift register connected partition enable signal line with the first conduction level is 1 unit time (here the unit time can be microsecond or other time scale, only for example, set conveniently) earlier than the time for the second display partition AA2 corresponding first shift register outputting the scanning signal with the first conduction level. In the third frame, the advanced time becomes 2 unit times. In the fourth frame, the advanced time becomes 3 unit times. Through such a gradual change mode, the load change of the first display partition AA1 and the second display partition AA2 is gradually averaged to the multi-line pixel circuit, reduces the influence of the load change of the display partition due to the different refresh frequencies on the display effect, and improves the display abnormality in the boundary area of the first display partition AA1 and the second display partition AA2.

[0066] Optionally, in at least part of the frames in the partition multi-frequency display mode, the time for providing the first display partition AA2 corresponding first shift register connected partition enable signal line with the first conduction level is gradually increased or gradually decreased in a manner of changing every d frames compared with the time for the second display partition AA2 corresponding first shift register outputting the scanning signal with the first conduction level, wherein d is greater than or equal to 0.

[0067] Specifically, the gradual change mode of the time for providing the first display partition AA2 corresponding first shift register connected partition enable signal line with the first conduction level is changed every d frames compared with the time for the second display partition AA2 corresponding first shift register outputting the scanning signal with the first conduction level. In the case of d=0, the change of the advanced time can be performed every frame. In the case of d being greater than or equal to 1, the advanced time is not changed every frame, but is changed according to a certain interval d frames. When the advanced time is gradually changed according to a certain interval, the sudden increase of the load on the data driver can be avoided, and the load is gradually increased, so that the load is averaged.

[0068] Optionally, in at least part of the frames in the partitioned multi-frequency display mode, the time for which the first conductive level provided to the set partition enable signal line is advanced compared to the first conductive level output by the first shift register corresponding to the second display partition AA2 is gradually increased. The time for advancement can vary in steps at equal intervals. For example, the time for advancement is increased by a fixed value in jumps every few frames. Assuming that the time for advancement is increased once every 3 frames, and the fixed value for each increase is t. If the time for advancement is t0 in the first frame, then in the 4th frame the time for advancement becomes t0+t, in the 7th frame the time for advancement becomes t0+2t, and so on. The time for advancement can also vary in steps at unequal intervals. For example, the time for advancement is not changed in the first two frames, and then the time for advancement is increased by different values every different number of frames starting from the 3rd frame. For example, the time for advancement is increased by t1 in the 3rd frame, the time for advancement is increased by t2 in the 6th frame, and so on. Here, t2 is greater than t1.

[0069] The partitioned multi-frequency display mode includes a first display frame and a second display frame. The first display frame is a holding frame for at least part of the row pixel circuits in the first display partition AA1, and is a refresh frame for the second display partition AA2. The second display frame is a refresh frame for both the first display partition AA1 and the second display partition AA2.

[0070] Here, in the refresh frame of the pixel circuit, the pixel circuit writes data voltage, and in the holding frame of the pixel circuit, the pixel circuit does not write data voltage.

[0071] Optionally, the n first display frames between adjacent second display frames are divided into a plurality of display sub-periods. n is less than or equal to the difference between the refresh frequency of the second display partition AA2 and the refresh frequency of the first display partition AA1. A display sub-period includes a plurality of first display frames.

[0072] In at least one display sub-period, the time for which the first conductive level provided to the set partition enable signal line is advanced compared to the first conductive level output by the first shift register corresponding to the second display partition AA2 is gradually increased or gradually decreased in a manner that changes every d frames. Here, a display sub-period includes a plurality of first display frames, and d is less than n.

[0073] Specifically, the first display frame is a holding frame for at least part of the row pixel circuits in the first display partition AA1, meaning that these pixel circuits maintain the previous data state in the first display frame and do not perform new data writing or refreshing. At the same time, the first display frame is also a refresh frame for the second display partition AA2, meaning that the second display partition AA2 performs data updating in this frame. The second display frame is a frame in which both the first display partition AA1 and the second display partition AA2 perform refreshing. In the second display frame, the pixel circuits of both partitions receive new data and update the display content.

[0074] For example, at a certain time period, the second display sub-area AA2 is in the process of refreshing the 10th frame, while at least part of the row pixel circuits in the first display sub-area AA1 are in the hold frame state, keeping the data display of the previous frame and not performing new data writing. The second display sub-area AA2 receives new data signals and updates the display content of the corresponding pixels, and the 10th frame is a refresh frame for the second display sub-area AA2, but is a hold frame for part of the pixel circuits in the first display sub-area AA1.

[0075] In the second display frame, all pixel circuits in the first display sub-area AA1 (including the odd-numbered row pixel circuits in the hold state in the first display frame) perform refreshing operations, receive new data signals, and update the display. At the same time, the second display sub-area AA2 also performs refreshing operations. For example, this can be a key frame in which the first display sub-area AA1 and the second display sub-area AA2 update the display content simultaneously to present a complete picture, such as when displaying a large image spanning two sub-areas or switching a video scene, in which case the two sub-areas need to refresh simultaneously, and the frame is the second display frame.

[0076] It is assumed that there are 10 first display frames (i.e., n = 10) in a certain display sub-period, and d can take a value less than 10, such as 3. This means that every 3 frames, the time when the first display sub-area AA1 is provided with the first conductive level of the set sub-area enable signal line changes, which can gradually increase (for example, the time when the first display sub-area AA1 is provided with the first conductive level of the set sub-area enable signal line is 1 ms, 2 ms, 3 ms, etc.) or gradually decrease (for example, the time when the first display sub-area AA1 is provided with the first conductive level of the set sub-area enable signal line is 3 ms, 2 ms, 1 ms, etc.). This control mode can make the sub-area enable signal of the second display sub-area AA2 more smoothly switch from the off level to the first conductive level when entering the refreshing stage, reduce the load change that can be caused by the level switching moment, thereby optimizing the effect of the entire sub-area multi-frequency display, and making the display transition of the two sub-areas at the boundary area more smooth.

[0077] Optionally, in the previous display sub-period in the adjacent display sub-period, the time when the first display sub-area AA1 is provided with the first conductive level of the set sub-area enable signal line compared to the first conductive level output by the corresponding first shift register of the second display sub-area AA2 is gradually increased or gradually decreased in a manner of changing every d frames.

[0078] For example, assuming d=3, and there are 12 first display frames in the previous display sub-period, the time of providing the first conductive level to the set partition enable signal line is gradually increased (e.g., 1ms, 2ms, 3ms, 4ms in turn) or gradually decreased (e.g., 4ms, 3ms, 2ms, 1ms in turn) at the 1st frame, 4th frame, 7th frame, and 10th frame. The purpose of this control mode is to gradually adjust the level state of the set partition enable signal line before the second display partition AA2 starts refreshing, so that the partition enable signal can be switched from the off level to the first conductive level more smoothly, avoiding signal interference or display abnormalities caused by level mutation. By gradually increasing or decreasing the advance time, the pixel circuit of the second display partition AA2 can adapt to the new data writing more smoothly when entering the refreshing stage, reducing the brightness fluctuation or image flicker caused by the change of refreshing frequency, especially in the partition boundary area, which can make the display transition more natural.

[0079] In the latter display sub-period in the adjacent display sub-period, the time of providing the first conductive level to the set partition enable signal line compared to the first conductive level output by the first shift register corresponding to the second display partition AA2 is gradually decreased or gradually increased in a manner of changing every d frames.

[0080] For example, if the latter display sub-period also has 12 first display frames, and d is still 3, the time of providing the first conductive level to the set partition enable signal line will change in a trend opposite to that of the previous display sub-period (if the previous one is gradually increased, this one is gradually decreased; vice versa) at the 1st frame, 4th frame, 7th frame, and 10th frame. The reason for this is that the partition enable signal has been preliminarily adjusted in the previous display sub-period, and the latter display sub-period can further optimize the stability of the signal by reverse adjustment, so that the second display partition AA2 can maintain a more stable state during refreshing, and at the same time, it is also helpful to balance the display difference between the two partitions, ensure the continuity and consistency of the entire display picture at the partition boundary, and avoid obvious visual fragmentation or display abnormal phenomena. This control mode with different trends in adjacent display sub-periods can more effectively adapt to the cooperative work between different frequency partitions in the partition multi-frequency display, and improve the display quality.

[0081] Optionally, the number of first display frames included in the plurality of display sub-periods is equal.

[0082] In some other optional embodiments of the present application, in the plurality of frames in the partition multi-frequency display mode, the time of providing the first conductive level to the set partition enable signal line compared to the first conductive level output by the first shift register corresponding to the second display partition AA2 is equal.

[0083] Specifically, in each frame of the partitioned multi-frequency display mode, the time when the partition enable signal line is provided with the first conductive level is earlier than the time when the first shift register corresponding to the second display partition AA2 outputs the scanning signal with the first conductive level, and the time difference is fixed. For example, assuming that the time difference is fixed as t (which can be a unit of time such as a microsecond), in the first frame, the partition enable signal line is provided with the first conductive level at time point T1, and the first shift register outputs the scanning signal with the first conductive level at time point T1+t; in the second frame, the partition enable signal line is provided with the first conductive level at time point T2, and the first shift register outputs the scanning signal with the first conductive level at time point T2+t. With the fixed time difference, the partition enable signal can reach the first shift register corresponding to the second display partition AA2 in a stable rhythm. The scanning signal output by the first shift register also becomes more regular. Because the time difference of the partition enable signal is fixed, the time when the scanning signal is output with the first conductive level is also fixed. For example, when switching from one display partition to another display partition, the scanning signal can be output with the first conductive level at a fixed time point, so that the pixel circuit can receive the scanning signal in a stable timing, perform data writing and refreshing operations, and thus ensure the stability of the display.

[0084] Figure 7 is a structural schematic diagram of a gate drive circuit provided by an embodiment of the present application. As shown in Figure 7 Optionally, each shift register 10 includes a stage transmission unit 220 and an output unit 230, the stage transmission unit 220 is configured to transmit the second conductive level NVGH2 stage by stage; the output unit 230 is connected to the partition enable signal VFE and is configured to transmit the partition enable signal VFE to the output end of the shift register 10 when the stage transmission unit 220 outputs the second conductive level NVGH2, and the output end of the shift register 10 is configured to output the scanning signal.

[0085] Optionally, continuing to refer to Figure 7 In at least one frame of the partitioned multi-frequency display mode, the first conductive level NVGH1 of the partition enable signal VFE is provided to the partition enable signal line before the second conductive level NVGH2 of the stage transmission unit 220 is output. The stage transmission unit 220 is the stage transmission unit 220 of the shift register 10 connected to the first row of pixel circuits in the second display partition AA2. The size of the first conductive level NVGH1 can be the same as or different from the potential size of the second conductive level NVGH2.

[0086] Specifically, the output unit 230 can output the partition enable signal when the stage transmission unit 220 outputs the second conduction level, and before the stage transmission unit 220 outputs the second conduction level NVGH2, the first conduction level NVGH1 of the partition enable signal VFE is provided to the setting partition enable signal line, so that the output unit 230 of the first shift register corresponding to the second display partition AA2 outputs the partition enable signal, and the first conduction level NVGH1 of the partition enable signal VFE is provided to the setting partition enable signal line, so that the partition enable signal VFE can be prepared in advance. Providing the partition enable signal VFE in advance makes the subsequent signal transmission more orderly. In this way, even if the voltage change on the data line causes the load change of the first display partition AA1 and the second display partition AA2, the first conduction level is changed from the off level to the first conduction level in advance, and the first conduction level is less affected by the load change on the data line, so that the data voltage writing of the pixel circuit is less affected, and the display abnormality phenomenon can be improved. When the partition enable signal VFE reaches the first shift register 10 in advance, the shift register 10 can output the scan signal in the correct order and rhythm, and the pixel circuit can write the data signal on the data line in order according to the scan signal.

[0087] When the refresh frequency of the second display partition AA2 is higher than that of the first display partition AA1, at the switching moment, if the partition enable signal is not prepared in advance, the pixel circuit may suddenly require higher load from the data driver, resulting in sudden increase of the data driver load. By providing the partition enable signal in advance, the data driver can gradually adjust the load during the partition switching process. When the data driver load is averaged, the possibility of display abnormality can be reduced.

[0088] Figure 8 is another structure diagram of a display panel provided by an embodiment of the present application. Referring to Figure 8 Optionally, the display panel includes k partition enable signal lines, the gate drive circuit includes a plurality of cascaded shift register groups 20, each shift register group includes k cascaded shift register units 21, k is an integer greater than or equal to 2, each shift register unit 21 includes m shift registers 10, m is an integer greater than or equal to 1, different shift register units 21 in the same shift register group 20 are electrically connected with different partition enable signal lines, and different shift register groups 20 are connected with the same k partition enable signal lines.

[0089] The display partition includes a plurality of pixel circuit groups 12; the pixel circuit group 12 includes k sub-pixel circuit groups 121, the sub-pixel circuit group 121 includes a plurality of rows of pixel circuits PX; the sub-pixel circuit group 121 is electrically connected with the shift register unit 21 in one-to-one correspondence; the output end of the first-stage shift register 10 is electrically connected with r rows of pixel circuits PX, and r is an integer greater than or equal to 1.

[0090] wherein, Figure 8 The case where k = 4 is schematically shown in FIG. 2. For example, m can be 16, and r can be 1. Each shift register group 20 can control the display of k*m*r rows of pixel circuits. Figure 8 The shift register group 20 of the first gate drive circuit in the display panel shown can be regarded as including four cascaded shift register units 21, and including four partition enable signal lines, namely ENL1, EN2, ENL3 and ENL4. One partition enable signal line is connected with m shift registers 10 in one shift register unit 21. Each partition enable signal line can drive m*r rows of pixel circuits driven by one shift register unit 21, and the number of rows driven by the four partition enable signal lines is one period.

[0091] Optionally, Figure 9 is a schematic diagram of the partition enable signal jump in the first display frame and the second display frame provided by the embodiment of the present application, referring to Figure 9 In the first display frame F1, the time points of pulse jump of the signals on the k partition enable signal lines to the first conduction level NVGH1 are sequentially delayed (in combination with Figure 8 and Figure 9 VFE1 is the partition enable signal on the partition enable signal line ENL1, VFE2 is the partition enable signal on the partition enable signal line ENL2, VFE3 is the partition enable signal on the partition enable signal line ENL3, and VFE4 is the partition enable signal on the partition enable signal line ENL4); in the second display frame F2, the signals on the k partition enable signal lines are at the first conduction level NVGH1. Wherein, the first display frame is the holding frame of at least part of the rows of pixel circuits in the first display partition AA1, and is the refresh frame of the second display partition AA2; the second display frame is the refresh frame of the first display partition AA1 and the second display partition AA2. In the second display frame, the first display partition is refreshed before the second display partition.

[0092] Specifically, in the first display frame F1, it is the refresh frame of at least one display partition, and it is the holding frame of at least one display partition, so as to Figure 9In the case shown, the pixel circuit connected to the shift register corresponding to the off level NVGL works in the holding frame, and the pixel circuit connected to the shift register corresponding to the first on level NVGH works in the refreshing frame. In this case, the time when the pulse jump of the signal on the k partition enable signal lines is set to the enable level is sequentially delayed, facilitating the completion of the partition multi-frequency control. The second display frame F2 is the refreshing frame of each display partition, and the signal on the k partition enable signal lines is set to the first on level in the second display frame, so that each display partition can be refreshed in the second display frame, and the signal on the partition enable signal line does not need to be jumped. The first partition enable signal line ENL1 transmits the first partition enable signal VFE1 to the corresponding shift register. The second partition enable signal line ENL2 transmits the second partition enable signal VFE2 to the corresponding shift register. The third partition enable signal line ENL3 transmits the third partition enable signal VFE3 to the corresponding shift register. The fourth partition enable signal line ENL4 transmits the fourth partition enable signal VFE4 to the corresponding shift register.

[0093] Optionally, k-1 shift register units 21 are connected between the two adjacent shift register units 21 connected to the same partition enable signal line.

[0094] Specifically, the sub-pixel rows connected to the k partition enable signal lines are periodically arranged. For example, the first partition enable signal line ENL1 is connected to 1-16 rows, 65-80 rows, … of sub-pixel rows. The second partition enable signal line ENL2 is connected to 17-32 rows, 81-96 rows, … of sub-pixel rows. The third partition enable signal line ENL3 is connected to 33-48 rows, 97-112 rows, … of sub-pixel rows. The fourth partition enable signal line ENL4 is connected to 49-64 rows, 98-128 rows, … of sub-pixel rows.

[0095] Optionally, m is greater than or equal to 8, and k is greater than or equal to 4.

[0096] Continuing to refer to Figure 7 and Figure 8 Optionally, in at least one frame of the partition multi-frequency display mode, before the control setting level transmission unit 220 outputs the second on level NVGH2, and after the second on level output by the level transmission unit 220 of the shift register connected to the setting partition enable signal line jumps to the off level NVGL in the pixel circuit group 12 corresponding to the second display partition AA2 adjacent to the first display partition AA1, the first on level of the partition enable signal is provided to the setting partition enable signal line.

[0097] For example, the partition enabling signal line is set as the first partition enabling signal line ENL1, and the first sub-pixel circuit group 121 corresponding to the first display partition AA1 is connected to the first partition enabling signal line ENL1. Only after the first sub-pixel circuit group 121 corresponding to the first display partition AA1 outputs the off level NVGL from the stage transfer unit 220 of the shift register 10, the first conductive level NVGH1 of the partition enabling signal is provided to the first partition enabling signal line ENL1, so as not to affect the output of the scanning signal of the first sub-pixel circuit group 121 corresponding to the first display partition AA1.

[0098] Optionally, the number of rows of the pixel circuits in each pixel circuit group is the same.

[0099] Optionally, the time for providing the first conductive level to the partition enabling signal line is less than or equal to k*c*b, compared with the time for the first conductive level output by the first shift register corresponding to the second display partition AA2, wherein c is the number of rows of the pixel circuits included in one pixel circuit group 12, and b is equal to the sum of the first conductive level pulse width time corresponding to one row of pixel circuits and the preset time interval, wherein the preset time interval is equal to the time interval for the first conductive level output by adjacent two shift registers. Optionally, the preset time interval is greater than or equal to 0.

[0100] Specifically, for example, k=4 and c=16. Then k*c*b=64b, that is, the time for providing the first conductive level to the partition enabling signal line is less than or equal to 64b, compared with the time for the first conductive level output by the first shift register corresponding to the second display partition AA2. This limitation can ensure that the signal transmission and display process can proceed normally under this specific display panel setting, and avoid display abnormalities of the first display partition AA1 caused by excessive time advance. Since the writing of the data voltage requires a certain time, if the time for providing the first conductive level to the partition enabling signal line is too long compared with the time for the first conductive level output by the first shift register corresponding to the second display partition AA2, the data writing time of some rows of pixel circuits in the display panel will be insufficient. In some optional embodiments, the time for providing the first conductive level to the partition enabling signal line can be less than or equal to (k-1)*c*b, compared with the time for the first conductive level output by the first shift register corresponding to the second display partition AA2, so as to ensure that the pixel circuits in the display panel can normally write the data voltage.

[0101] Optionally, in at least part of the first n frames in the multi-frequency display mode, the time for providing the first conductive level NVGH1 to the set partition enable signal line is gradually increased or gradually decreased compared to the time for providing the second conductive level NVGH2 to the set stage transmission unit; n is greater than or equal to 2.

[0102] Specifically, assuming n = 5, the display panel is divided into two display partitions, the refresh frequency of the first display partition AA1 is 1 Hz, and the refresh frequency of the second display partition AA2 is 60 Hz. In the first 5 frames in the multi-frequency display mode, it is assumed that only the 2nd frame, the 3rd frame and the 4th frame perform the gradual change operation.

[0103] In the 2nd frame, the time for providing the first conductive level to the partition enable signal line corresponding to the first shift register of the second display partition AA2 is 1 unit time earlier than the time for providing the second conductive level to the first stage transmission unit of the second display partition AA2. In the 3rd frame, the time is 2 unit times. In the 4th frame, the time is 3 unit times. Through such a gradual change mode, the load of the data driver is more evenly distributed in time. In at least part of the first n frames in the multi-frequency display mode, as the time for providing the partition enable signal gradually changes, the data driver can gradually adjust its data output according to the gradually changing working state of the shift register. For example, in some frames, the data driver can steadily increase the amount of data provided according to the gradual increase in the data demand of the pixel circuit, rather than suddenly increasing a large amount of data in a frame, so that the load is more evenly distributed in these frames, achieving load averaging, enabling the shift register corresponding to the second display partition AA2 to output the scanning signal more smoothly, thereby avoiding display abnormalities in the boundary area between the first display partition AA1 and the second display partition AA2.

[0104] Optionally, in at least part of the first n frames in the multi-frequency display mode, the time for providing the first conductive level NVGH1 to the set partition enable signal line is gradually increased compared to the time for providing the second conductive level NVGH2 to the set stage transmission unit. In this way, the load change caused by the change of the data signal can be gradually averaged to more rows of pixel circuits, and the display abnormality can be further improved.

[0105] Optionally, the time for providing the first conductive level of the partition enable signal to the set partition enable signal line compared to the time for providing the second conductive level to the set stage transmission unit is equal to an integer multiple of the sum of the first conductive level pulse width time output by the shift register and the preset time interval.

[0106] Specifically, the first on-time of the first on-level output by the shift register is equal to the sum of the first on-time of the first on-level of the input signal EIN accessed by the shift register and the preset time interval. Since the display panel is refreshed row by row, the first on-time of the first on-level output by the shift register is equal to the sum of the first on-time of the first on-level of the input signal EIN accessed by the shift register and the preset time interval. By setting the first on-time of the first on-level of the partition enabling signal provided to the partition enabling signal line to be earlier than the second on-time of the second on-level output by the level shifting unit, the first on-time of the first on-level output by the shift register is equal to the sum of the first on-time of the first on-level of the input signal EIN accessed by the shift register and the preset time interval. The driving control of the display panel is more convenient and easy to implement.

[0107] Figure 10 is a flowchart of another driving method of a display panel provided by an embodiment of the present application. As shown in Figure 10 the driving method of the display panel comprises:

[0108] S301, providing a partition enabling signal to a partition enabling signal line, so that the shift register outputs a scan signal to a corresponding pixel circuit according to the partition enabling signal to control the refresh frequency of the corresponding pixel circuit, thereby realizing a partition multi-frequency display mode.

[0109] S302, in at least one frame of the partition multi-frequency display mode, outputting a data signal to a data line in a first output mode before controlling the first shift register corresponding to the second display partition to output the first on-level of the partition enabling signal.

[0110] Specifically, the data signal output to the data line in the first output mode has a jump. In at least one frame of the partition multi-frequency display mode, the data signal provided to the data line before controlling the first shift register corresponding to the second display partition AA2 to output the first on-level of the partition enabling signal creates conditions for the data signal of the second display partition AA2. Although the first shift register corresponding to the second display partition AA2 has not yet output the first on-level of the partition enabling signal at this time, the data signal has been output in the first output mode corresponding to the second display partition AA2. When the refresh frequency of the second display partition AA2 is higher than that of the first display partition AA1, the demand for data of the pixel circuit suddenly increases at the switching moment, and the data driver may not be able to provide sufficient data signal in time, resulting in display abnormalities. By providing the data signal to the data line in advance, the data driver can gradually adjust the provision of the data signal according to the refresh frequency and timing requirements of the second display partition AA2, so that the change of the load is averaged in the scanning time corresponding to multiple rows of pixel circuits, avoiding the impact of load mutation on the display, thereby improving the abnormal display of the partition boundary.

[0111] Optionally, continuing to refer to Figure 7 andFigure 8 In at least one frame of the partition multi-frequency display mode, before controlling the first stage transfer unit 220 corresponding to the second display partition AA2 to output the second conduction level NVGH2, the data signal is output to the data line in the first output mode. Wherein, the first stage transfer unit 220 corresponding to the second display partition AA2 is the stage transfer unit 220 of the shift register 10 connected to the first row of pixel circuits in the second display partition AA2.

[0112] Specifically, before the first stage transfer unit 220 corresponding to the second display partition AA2 outputs the second conduction level NVGH2, the data signal is provided to the data line in the first output mode. First, if the data signal is not provided in advance during the partition switching process, a data conflict situation may occur. When switching from the first display partition AA1 to the second display partition AA2, the requirements of the second display partition AA2 for the data signal may be different from those of the first display partition AA1. Providing the data signal to the data line in advance can be adjusted according to the refresh frequency and related requirements of the second display partition AA2, so that at the moment of partition switching, the data signal can meet the requirements of the second display partition AA2, avoiding display abnormalities such as flickering, bright lines, etc. caused by mismatched data signals, thereby improving the situation of display abnormalities at the partition boundary. Second, providing the data signal to the data line in advance can make the load of the data driver more stable. When the partition is switched, if the data signal suddenly changes, the data driver will face the problem of load mutation. By providing the data signal in advance, the data driver can gradually adjust the provision of the data signal according to the refresh frequency and timing requirements of the second display partition AA2, so that the load is more evenly distributed in time, avoiding display abnormalities caused by load mutation, and thereby improving the situation of display abnormalities at the partition boundary.

[0113] Figure 11 is a flowchart of another display panel driving method provided by an embodiment of the present application. As shown in Figure 11 the display panel driving method comprises:

[0114] S401, providing a partition enable signal to a partition enable signal line, so that the shift register outputs a scan signal to the corresponding connected pixel circuit according to the partition enable signal, to control the refresh frequency of the corresponding connected pixel circuit, thereby realizing a partition multi-frequency display mode.

[0115] S402, in at least one frame of the partition multi-frequency display mode, before controlling the first stage transfer unit corresponding to the second display partition to output the second conduction level, the data signal is output to the data line in the first output mode.

[0116] S403. In at least one frame of the partition multi-frequency display mode, when the cascade unit of the shift register corresponding to the first display partition outputs the second conduction level, a DC level is output to the data line in the second output mode, or no signal is output to the data line; and / or, in at least one frame of the partition multi-frequency display mode, when the cascade unit corresponding to the first display partition outputs the second conduction level, a shutdown level is provided to the partition enable signal line.

[0117] Specifically, in the second output mode, the signal output to the data line is at a DC level, eliminating the need for frequent value changes. This stable data signal transmission reduces the workload of the data driver, as it doesn't require continuously providing data signals of varying values, thus lowering the driver's power consumption. Furthermore, not outputting a signal to the data line directly avoids energy consumption during data transmission, as no voltage flows on the data line, and the data driver doesn't need to provide power for this data transmission, further reducing its power consumption. Providing a shutdown level to the partition enable signal line turns off the relevant shift registers or other circuit components. When these components are off, they do not consume power, thus reducing the overall power consumption of the display system. For example, the relevant transistors may be cut off due to the shutdown level of the partition enable signal line, preventing current flow and further reducing power consumption.

[0118] Optionally, the time by which the drive signal for the second display partition AA2 is provided to the drive signal line relative to the first on-level of the enable signal for the first shift register output partition corresponding to the second display partition AA2 is positively correlated with the difference in refresh rates between the second display partition AA2 and the first display partition AA1. This means that the greater the difference in refresh rates between the second display partition AA2 and the first display partition AA1, the longer the time required to provide the drive signal to the drive signal line. This setting is to better adapt to the switching between partitions with different refresh rates, ensuring that the data signal and scan signal can cooperate more effectively during partition switching to achieve better display results.

[0119] Assume the refresh rate of the first display partition AA1 is 10Hz, and the refresh rate of the second display partition AA2 is 60Hz, with a difference of 50Hz. Based on the positive correlation, the drive signal providing the drive signal corresponding to the refresh rate of the second display partition AA2 will precede the first on-level of the enable signal controlling the first shift register output partition of the second display partition AA2 by a relatively long time. Now assume the refresh rate of the first display partition AA1 is 30Hz, and the refresh rate of the second display partition AA2 is 40Hz, with a difference of 10Hz. In this case, the precedence time will be shorter than in the previous scenario.

[0120] When the refresh frequency difference is large, providing the driving signal in advance for a long time can give the data driver enough time to prepare the data signal according to the refresh frequency and timing requirements of the second display partition AA2. For example, for the second display partition AA2 with a high refresh frequency, the data driver can prepare the data signal in advance at a high frequency and with a suitable data amount, avoiding display abnormalities caused by sudden changes in the data signal when the partition is switched.

[0121] Optionally, in at least one first display frame in the partition multi-frequency mode, the driving signal corresponding to the driving mode of the second display partition is provided to the driving signal line before the control of the first on level of the scan signal output by the first shift register corresponding to the second display partition.

[0122] Specifically, the driving signal includes the partition enable signal on the partition enable signal line and / or the data signal on the data line. For example, providing the partition enable signal matching the driving mode of the second display partition AA2 in advance can make the process of jumping from the off level to the first on level of the partition enable signal complete before the first on level of the scan signal output by the first shift register, thereby ensuring that the first on level is stable when the pixel circuit starts to write data, so that the pixel circuit can normally write data. For the data signal on the data line, providing the signal corresponding to the driving mode of the second display partition AA2 in advance can give the data driver enough time to prepare the data signal according to the refresh frequency and timing requirements of the second display partition AA2, avoiding display abnormalities such as flickering, bright lines, etc. caused by sudden changes in the data signal when the partition is switched, thereby improving the abnormal display of the partition boundary, making the pixel brightness switching of the second display partition AA2 and the first display partition AA1 at the border area more smooth, and improving the overall display effect.

[0123] Optionally, the first display frame and the second display frame each include a first period, a second period and a third period; in the first period of the first display frame, the scan signal output to the N rows of pixel circuits of the first display partition is continuously at the off level, the non-enable level is provided to the partition enable signal line, and the direct current level is provided to the data line, or no signal is output to the data line; in the second period of the first display frame, the scan signal output to the M rows of pixel circuits of the first display partition includes the on level, the enable level is provided to the partition enable signal line, and the data signal is provided to the data line; in the third period of the first display frame, the scan signal output to the pixel circuits of the second display partition includes the on level, the enable level is provided to the partition enable signal line, and the data signal is provided to the data line; the M rows of pixel circuits are between the N rows of pixel circuits and the second display partition; wherein the M corresponding to at least two first display frames are not equal.

[0124] Specifically, in the first time period of the first display frame, the scan signals output to the N rows of pixel circuits in the first display sub-region are continuously at the off level, which means that these pixel circuits are in the inactive state and do not perform data update operation in this time period. Meanwhile, the non-enable level is provided to the sub-region enable signal line, which further ensures that these pixel circuits will not be mistakenly started for data writing due to unnecessary interference. As for the data lines, a direct current level (e.g., setting the data lines to high impedance state or providing a fixed direct current voltage) or no signal is output to the data lines, because these pixel circuits do not need new data in this time period. In this way, the energy consumption of the data driver can be reduced, and unnecessary data transmission can be avoided. For example, when displaying a relatively static part (e.g., a background area) of a picture, the pixel circuits corresponding to this area can be in this low-power-consumption holding state in the first time period, thereby saving energy and maintaining the stability of the display.

[0125] In the second time period of the first display frame, the scan signals output to the M rows of pixel circuits in the first display sub-region between the N rows of pixel circuits and the second display sub-region include the on level, which causes the M rows of pixel circuits to be activated and can receive data signals. Meanwhile, the enable level is provided to the sub-region enable signal line to create conditions for data writing, and the data signals are provided to the data lines, and at this time, the pixel circuits start to perform data update operation. This time-period and row-specific control method can more finely manage the pixel circuits in different areas of the display sub-region, and perform data update according to the requirements of the display content. For example, when some areas of the picture need to update data in the second time period of the first display frame, this method can be used to achieve this. Moreover, since the M corresponding to at least two first display frames are not equal, which means that in different first display frames, the range of M rows of pixel circuits that perform data update can be different, which can further optimize the display effect, make the dynamic change of the picture more natural and smooth, and avoid the appearance of abrupt update areas.

[0126] In the third period of the first display frame, the scan signal output to the pixel circuits of the second display partition AA2 includes a turn-on level, the partition enable signal line also provides an enable level, and the data line provides a data signal, which causes the pixel circuits of the second display partition AA2 to perform a data refresh operation in this period. Since the first display frame is a refresh frame of the second display partition AA2, it is crucial to ensure that the second display partition AA2 can normally update data in this period to maintain the smoothness and accuracy of its display. For example, when playing a video, the second display partition may need to update the dynamic part in the video picture in the third period of each first display frame to achieve a continuous video playing effect. While the first display partition AA1 may continue to maintain stable display of part of the pixel circuits (such as N rows of pixel circuits) in this period, and the M rows of pixel circuits that have completed data update also maintain the updated state. Through the cooperative control of the partitions and periods, efficient and stable operation of the entire display panel in the partition multi-frequency display mode is achieved, and the display transition between different frequency partitions and the overall display effect are optimized.

[0127] Optionally, in the first period of the second display frame, the scan signal output to the N rows of pixel circuits of the first display partition includes a turn-on level, the partition enable signal line is provided with an enable level, and the data line is provided with a data signal; in the second period of the second display frame, the scan signal output to the M rows of pixel circuits of the first display partition includes a turn-on level, the partition enable signal line is provided with an enable level, and the data line is provided with a data signal; in the third period of the second display frame, the scan signal output to the pixel circuits of the second display partition includes a turn-on level, the partition enable signal line is provided with an enable level, and the data line is provided with a data signal; among a plurality of first display frames between two adjacent second display frames, the M corresponding to at least two first display frames are not equal, and the M corresponding to the first display frame in the time sequence in front is smaller than the M corresponding to the first display frame in the time sequence in back.

[0128] Specifically, in the first period of the second display frame, the scan signal output to the N rows of pixel circuits of the first display partition AA1 includes a turn-on level, which causes these pixel circuits to be in an active state and ready for data update. At the same time, the partition enable signal line is provided with an enable level, which creates the necessary conditions for data writing, and the data line is provided with a data signal, so that the N rows of pixel circuits can receive new data and perform update operation. This step ensures that part of the pixel circuits of the first display partition can respond and update the display content in time at the beginning of the second display frame, which helps to maintain the coherence and dynamics of the entire display picture. For example, when displaying a picture containing dynamic elements, these N rows of pixel circuits may correspond to the area that needs to be updated first in the picture, such as the foreground elements in the animation or the key information area in the interactive interface.

[0129] The second display frame second period, for the first display partition in the M row pixel circuit output conduction level of the scanning signal, the partition enable signal and the data signal, make the M row pixel circuit also carries out data update. Such time period, the control of different rows can be more accurate according to the specific requirements of display content, the update order and timing of the pixel circuit in the first display partition. For example, in the process of displaying an image gradually unfolding, M row pixel circuit may correspond to the subsequent part in the process of image unfolding, update according to the predetermined timing, to present the natural and smooth display effect.

[0130] The second display frame third period is to operate the pixel circuit of the second display partition. Similarly, the output conduction level of the scanning signal, the partition enable signal and the data signal ensure that the pixel circuit of the second display partition can carry out data refresh. Since the second display frame is the frame that both partitions are refreshed, it is very important to ensure the normal refresh of the second display partition in this period to maintain the consistency and accuracy of the whole picture. For example, in the multi-window display or split screen application scenario, the second display partition may be used to display real-time updated video, dynamic chart and other content, and the update operation in the third period can ensure the smooth playing and accurate display of these contents.

[0131] Figure 12 is another flowchart of a driving method of a display panel provided by an embodiment of the present application. As shown in the figure, the driving method comprises: Figure 12

[0132] S501, providing a partition enable signal to the partition enable signal line, so that the shift register outputs the scanning signal to the corresponding connected pixel circuit according to the partition enable signal, to control the refresh frequency of the corresponding connected pixel circuit, thereby realizing the partition multi-frequency display mode.

[0133] Among them, the scanning signal output by at least one shift register includes the first conduction level of the partition enable signal;

[0134] S502, in at least one frame of the partition multi-frequency display mode, before controlling the first conduction level of the scanning signal output by the first shift register corresponding to the second display partition, providing the first conduction level to the set partition enable signal line.

[0135] Among them, the set partition enable signal line is the partition enable signal line connected with the first shift register corresponding to the second display partition; in the partition multi-frequency display mode, the refresh frequency of the second display partition is greater than that of the first display partition; the first shift register corresponding to the second display partition is the shift register connected with the first row pixel circuit in the second display partition; the pixel circuit is used to write the data signal on the data line according to the received first conduction level. ​

[0136] Optionally, in at least part of the frames in the multi-frequency display mode of the sub-areas, the time for providing the first conductive level to the set sub-area enable signal line is gradually increased or gradually decreased compared with the first conductive level output by the first shift register corresponding to the second display sub-area.

[0137] Optionally, the multi-frequency display mode of the sub-areas includes a first display frame and a second display frame, the first display frame is a holding frame of at least part of the row pixel circuits in the first display sub-area and is a refreshing frame of the second display sub-area; and the second display frame is a refreshing frame of the first display sub-area and the second display sub-area.

[0138] Optionally, the n first display frames between adjacent second display frames are divided into a plurality of display sub-periods; n is less than or equal to the difference between the refreshing frequency of the second display sub-area and the refreshing frequency of the first display sub-area; and each display sub-period includes a plurality of first display frames. In at least one display sub-period, the time for providing the first conductive level to the set sub-area enable signal line is gradually increased or gradually decreased in a manner of changing every d frames compared with the first conductive level output by the first shift register corresponding to the second display sub-area; wherein each display sub-period includes a plurality of first display frames; and d is less than n.

[0139] Optionally, in a former one of the adjacent display sub-periods, the time for providing the first conductive level to the set sub-area enable signal line is gradually increased or gradually decreased in a manner of changing every d frames compared with the first conductive level output by the first shift register corresponding to the second display sub-area; and in a latter one of the adjacent display sub-periods, the time for providing the first conductive level to the set sub-area enable signal line is gradually decreased or gradually increased in a manner of changing every d frames compared with the first conductive level output by the first shift register corresponding to the second display sub-area.

[0140] Optionally, the number of the first display frames included in each display sub-period is equal.

[0141] Optionally, in at least part of the frames in the multi-frequency display mode of the sub-areas, the time for providing the first conductive level to the set sub-area enable signal line is gradually increased or gradually decreased in a manner of changing every d frames compared with the first conductive level output by the first shift register corresponding to the second display sub-area, wherein d is greater than or equal to 0.

[0142] Optionally, in at least part of the frames in the multi-frequency display mode of the sub-areas, the time for providing the first conductive level to the set sub-area enable signal line is gradually increased compared with the first conductive level output by the first shift register corresponding to the second display sub-area.

[0143] Figure 13 is a working timing diagram of a display panel provided by an embodiment of the present application. As shown in FIG. 1, the display panel includes a first display sub-area and a second display sub-area. Figure 13As shown, the partition enable signal VFE and the data signal Vdata corresponding to the refresh frequency of the display partition are provided to the driving signal line in the first frame F01 of the partition multi-frequency display mode. Figure 13 The first frame of the display partition is taken as a refresh frame.

[0144] Optionally, in at least part of the first n frames of the partition multi-frequency display mode, the time for the partition enable signal line connected to the first shift register corresponding to the second display partition to provide the first conductive level NVGH1 is gradually increased in advance of the time for the scan signal output by the first shift register corresponding to the second display partition to be the first conductive level NVGH1. For example, n=5, in the first 5 frames of the partition multi-frequency display mode, the time for the partition enable signal line connected to the first shift register corresponding to the second display partition to provide the first conductive level NVGH1 is gradually increased in advance of the time for the scan signal output by the first shift register corresponding to the second display partition to be the first conductive level NVGH1. The second display partition starts from the 960th row of pixel circuits. At the second frame F2, the time for the partition enable signal line connected to the first shift register corresponding to the second display partition to provide the first conductive level NVGH1 is the same as the time for the scan signal output by the first shift register corresponding to the second display partition to be the first conductive level NVGH1. At the third frame, the time for the partition enable signal line connected to the first shift register corresponding to the second display partition to provide the first conductive level NVGH1 is 8 rows of pixel circuits ahead of the time for the scan signal output by the first shift register corresponding to the second display partition to be the first conductive level NVGH1, that is, at the third frame F3, the first conductive level NVGH1 is provided to the partition enable signal line connected to the first shift register corresponding to the second display partition at the 952nd row of pixel circuits. At the fourth frame F4, the time for the partition enable signal line connected to the first shift register corresponding to the second display partition to provide the first conductive level NVGH1 is 16 rows of pixel circuits ahead of the time for the scan signal output by the first shift register corresponding to the second display partition to be the first conductive level NVGH1, that is, at the fourth frame F4, the first conductive level NVGH1 is provided to the partition enable signal line connected to the first shift register corresponding to the second display partition at the 944th row of pixel circuits. This gradual adjustment can effectively reduce display abnormalities near the partition boundary. When the second display partition starts to be activated, the pixel circuits near the boundary are prone to flickering, bright lines and other problems if they receive suddenly changing signals. Through this gradual increase in the advance time, the pixel circuits near the boundary can more smoothly transition from the display mode of one partition to the display mode of the second display partition. For example, when switching from a low refresh frequency partition to the second display partition, the boundary pixel circuits can gradually adapt to the change in the new refresh frequency over multiple frames, thereby improving display quality.

[0145] Optionally, in at least one frame of the partitioned multi-frequency display mode, the data signal Vdata is output to the data line in the first output mode before the first conductive level NVGH1 of the partition enable signal VFE output by the first shift register corresponding to the second display partition is controlled; wherein the data signal Vdata output to the data line in the first output mode has a jump. For example, in the first 5 frames of the partitioned multi-frequency display mode, the third frame F3 and the fourth frame F4 output the data signal Vdata to the data line in the first output mode before the first conductive level NVGH1 of the partition enable signal VFE output by the first shift register corresponding to the second display partition is controlled. Early output of the data signal Vdata with a jump can make the load of the data driver more balanced. In the partition switching process, if the data signal is not prepared in advance or suddenly changes, the data driver may face the problem of sudden load. For example, in the partitioned multi-frequency display mode, the data driver needs to adjust the output according to the refresh frequency and data requirements of different partitions. By early output of the data signal Vdata with a jump, the data driver can gradually adjust the output power within multiple frames, avoid excessive load in a certain frame, and ensure stable operation of the data driver. The jump of the data signal, in combination with the early adjustment of the partition enable signal and the scan signal, can make the data signal better match the refresh frequency and scan mode of the second display partition. In the partition switching, the data signal needs to adapt to the new partition display requirements. For example, in the case of a higher refresh frequency of the second display partition, the jump of the data signal can better meet the data writing requirements of the pixel circuit in the second display partition in terms of frequency, amplitude, etc., thereby improving the display effect.

[0146] Based on the same inventive concept, the embodiment of the present application also provides a display device, which refers to Figure 3 and Figure 4 The display device includes a display panel 01 and a display driving module 02, the display panel 01 includes at least two display partitions, the at least two display partitions include a first display partition AA1 and a second display partition AA2, the first display partition AA1 and the second display partition AA2 are adjacent along a data line extension direction (i.e. Figure 3 the second direction Y in the figure), each display partition includes a plurality of pixel circuits PX, the pixel circuit PX is electrically connected with the data line DL; the display panel further includes a gate drive circuit 11 and at least one partition enable signal line ENL, the gate drive circuit 11 includes a plurality of cascaded shift registers 10, the shift register 10 is electrically connected with the partition enable signal line ENL in correspondence, and the shift register 10 is used for controlling the refresh frequency of the corresponding connected pixel circuit PX according to the partition enable signal of the partition enable signal line ENL.

[0147] The display driving module 02 is configured to provide a partition enable signal to the partition enable signal line ENL, so that the shift register 10 outputs a scan signal to the corresponding connected pixel circuit PX according to the partition enable signal, to control the refresh frequency of the corresponding connected pixel circuit PX, so as to realize the partition multi-frequency display mode.

[0148] The scan signal output by at least one shift register 10 includes a first conduction level; in at least one frame of the partition multi-frequency display mode, before the scan signal output by the first shift register 10 corresponding to the second display partition is controlled to be the first conduction level, a driving signal corresponding to the driving mode of the second display partition is provided to the driving signal line; wherein the driving signal line includes the partition enable signal line ENL and / or the data line DL.

[0149] In the partition multi-frequency display mode, the refresh frequency of the second display partition AA2 is greater than the refresh frequency of the first display partition AA1; the first shift register 10 corresponding to the second display partition AA2 is the shift register 10 connected to the first row of pixel circuits PX in the second display partition AA2; the pixel circuit PX is configured to write the data signal on the data line DL according to the received first conduction level; wherein in the driving mode of the second display partition AA2, the level on the partition enable signal line ENL is an enable level, and the data line DL transmits the data signal.

[0150] Optionally, the display device can be a mobile phone, or a computer, a television, a smart wearable display device, etc., and the present application is not limited to the above. The display device has similar technical principles and effects to the driving method of the display panel provided by any embodiment of the present application, and the same parts can be referred to the explanation of the driving method of the display panel, which will not be repeated here.

[0151] Optionally, continuing to refer to Figure 3The enable level is the first conduction level; in the partitioned multi-frequency display mode, the scan signal output by the at least one shift register comprises the first conduction level of the partition enable signal; the display driving module 02 comprises a first driving unit 021, and the first driving unit 021 is configured to, in at least one frame in the partitioned multi-frequency display mode, provide the first conduction level to the set partition enable signal line before controlling the first scan signal output by the corresponding first shift register of the second display partition AA2 to be the first conduction level; wherein the set partition enable signal line is the partition enable signal line ENL connected to the corresponding first shift register of the second display partition AA2. And / or, the display driving module 02 comprises a second driving unit 022, and the second driving unit 022 is configured to, in at least one frame in the partitioned multi-frequency display mode, output a data signal to the data line DL in a first output mode before controlling the first shift register corresponding to the second display partition AA2 to output the first conduction level of the partition enable signal; wherein the data signal output to the data line DL in the first output mode has a jump.

[0152] With reference to Figure 7 Optionally, the shift register 10 comprises a stage transmission unit 220 and an output unit 230, the stage transmission unit 220 is configured to transmit the second conduction level NVGH2 stage by stage. The control end of the output unit 230 is electrically connected to the intermediate node of the stage transmission unit 220, and the potential of the intermediate node is used to control the stage transmission unit 220 to output the second conduction level NVGH2 or the off level NVGL. The control end of the output unit 230 is electrically connected to the intermediate node of the stage transmission unit 220, and the potential of the intermediate node is used to control the stage transmission unit 220 to output the second conduction level NVGH2 or the off level NVGL; the control end of the output unit 230 is electrically connected to the intermediate node, the first input end of the output unit 230 is electrically connected to the partition enable signal line, the second input end of the output unit 230 is connected to the off level NVGL, and the output end of the output unit 230 is electrically connected to at least one row of pixel circuits.

[0153] Specifically, the intermediate node comprises a first intermediate node N1 and a second intermediate node N2. In any stage shift register 10, the stage transmission unit 220 is electrically connected to the first intermediate node N1 and the second intermediate node N2, respectively, for outputting the second conduction level NVGH2 or the off level NVGL as a stage transmission signal according to the potentials of the first intermediate node N1 and the second intermediate node N2. The stage transmission signal is used as an input signal of the next stage shift register 10. The cascade mode between the shift registers 10 can be as shown in Figure 6As shown, the first stage shift register 101 receives the input signal EIN, and outputs the first stage carry signal Carryl and the first stage scan signal GOUTl according to the input signal EIN, the clock signal ECK and the partition enable signal VFE. The first stage carry signal Carryl is transmitted to the second stage input signal EIN2 as the second stage input signal EIN2, and the second stage shift register 102 outputs the second stage carry signal Carry2 (as the third stage input signal EIN3) and the second stage scan signal GOUT2 according to the second stage input signal EIN2, the clock signal ECK and the partition enable signal VFE, and so on.

[0154] Exemplarily, the output unit 230 can include a first control terminal, a second control terminal, a first input terminal, a second input terminal and an output terminal. The first control terminal is electrically connected with the first intermediate node N1, the second control terminal is electrically connected with the second intermediate node N2, the first input terminal is electrically connected with the partition enable signal line for receiving the partition enable signal VFE, the second input terminal receives the off level NVGL, and the output terminal outputs the scan signal. Then, the output unit 230 can control whether the first input terminal and the output terminal are connected according to the electric potential of the first control terminal (i.e. the first intermediate node N1), so as to control whether the level of the partition enable signal VFE is output as the scan signal; and control whether the second input terminal and the output terminal are connected according to the electric potential of the second control terminal (i.e. the second intermediate node N2), so as to control whether the off level NVGL is output as the scan signal.

[0155] Exemplarily, the first on level NVGH1 is the on potential of the functional module in the pixel circuit receiving the scan signal, and the off level NVGL is the off potential of the functional module in the pixel circuit receiving the scan signal. The functional module can be, for example, a functional module for controlling the data voltage writing process of the gate of the driving transistor in the pixel circuit. The first on level NVGH1 and the off level NVGL can both be direct current voltage signals. Exemplarily, the transistor receiving the scan signal is an N-type transistor, then the first on level NVGH1 is a high potential, and the off level NVGL is a low potential.

[0156] Specifically, when the output unit 230 controls the connection between the second input terminal and the output terminal according to the potential of the second control terminal, if the level of the partition enable signal VFE is the first on level NVGH1, then the scan signal is also at a high potential, which is equivalent to the scan signal including a conduction pulse in this display frame; if the level of the partition enable signal VFE is the off level NVGL, then the partition enable signal VFE cannot provide a high potential to the output terminal of the output unit 230, and the scan signal remains at a low potential, which is equivalent to the scan signal not including a conduction pulse in this display frame. Therefore, by controlling the potential jump of the partition enable signal VFE, the output unit 230 is controlled to output a conduction pulse, thereby controlling the refresh frequency of the pixel circuit.

[0157] Optionally, the shift register 10 further includes a drive control unit 210, which controls the potentials of the first intermediate node N1 and the second intermediate node N2 based on the clock signal ECK and the input signal. The first intermediate node N1 and the second intermediate node N2 are respectively the first output terminal and the second output terminal of the drive control unit 210. The clock signal ECK can be understood as the general term for all clock signals input to the drive control unit 210, and may include multiple clock signals with alternating high and low potentials.

[0158] It should be noted that the partition enable signal VFE plays a role during the time period when the transmission unit 220 outputs the second conduction level NVGH2. Controlling the potential of the partition enable signal VFE during this time period can control whether the output terminal of the shift register can output a conduction potential in a frame of display.

[0159] Figure 14 This is a schematic diagram of a shift register provided in an embodiment of the present invention. (Reference) Figure 7 and Figure 14 Optionally, the output unit 230 includes a first transistor M1 and a second transistor M2. The gate of the first transistor M1 serves as a first control terminal, and the gate of the second transistor M2 serves as a second control terminal; the first electrode of the first transistor M1 serves as a first input terminal, and the first electrode of the second transistor M2 serves as a second input terminal. The second electrodes of the first transistor M1 and the second electrode of the second transistor M2 are electrically connected to the output terminal of the output unit 230. In this embodiment, the output unit 230 includes two transistors, which respectively control whether the partition enable signal VFE and the off level NVGL are output as the scan signal GOUT, making the structure of the output unit 230 simple and easy to implement.

[0160] Optionally, the stage transmission unit 220 comprises a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 is electrically connected to the second intermediate node N2 as the first control terminal of the stage transmission unit 220; the first pole of the third transistor M3 is connected to the off level NVGL as the first input / output terminal of the stage transmission unit 220, and the second pole of the third transistor M3 is the output terminal of the stage transmission unit 220 for outputting the stage transmission signal Carry. The gate of the fourth transistor M4 is electrically connected to the first intermediate node N1 as the second control terminal of the stage transmission unit 220; the first pole of the fourth transistor M4 is connected to the second on level NVGH2 as the second input terminal of the stage transmission unit 220; and the second pole of the fourth transistor M4 is electrically connected to the second pole of the third transistor M3. In this embodiment, the stage transmission unit 220 comprises two transistors, which control whether the second on level NVGH2 and the off level NVGL are outputted as the stage transmission signal Carry, respectively, so that the stage transmission unit 220 has a simple structure and is easy to implement.

[0161] The drive control unit 210 comprises some or all of the thirteenth transistor M13 to the twenty-third transistor M23, the first capacitor C1, the second capacitor C2 and the third capacitor C3. The first terminal of the eighteenth transistor M18, the control terminal of the seventeenth transistor M17, the control terminal of the sixteenth transistor M16 and the control terminal of the thirteenth transistor M13 are connected to the off level NVGL; the control terminal of the eighteenth transistor M18 and the control terminal of the twentieth transistor M20 are electrically connected to the first clock signal terminal ECK1; the first terminal of the fifteenth transistor M15, the control terminal of the fourteenth transistor M14, the control terminal of the twenty-second transistor M22 and the first terminal of the second capacitor C2 are electrically connected to the second clock signal terminal ECK2; the first terminal of the twenty-first transistor M21 and the first terminal of the twenty-third transistor M23 are connected to the second on level NVGH2; the first terminal of the twentieth transistor M20 is connected to the input signal EIN; the first terminal of the eleventh transistor M11 is connected to the second on level NVGH2; the second terminal of the eleventh transistor M11 outputs the stage transmission signal Carry; and the first terminal of the twelfth transistor M12 is connected to the off level NVGL.

[0162] For example, the first clock signal terminals of the odd-numbered stage shift registers and the second clock signal terminals of the even-numbered stage shift registers are connected to the first clock signal line, and the second clock signal terminals of the odd-numbered stage shift registers and the first clock signal terminals of the even-numbered stage shift registers are connected to the second clock signal line.

[0163] Optionally, the first conductive level NVGH1 of the partition enable signal VFE is provided to the partition enable signal line before the second conductive level NVGH2 of the control setting level transfer unit is output, in at least one frame of the partition multi-frequency display mode. The setting level transfer unit is the level transfer unit 220 of the shift register 10 connected to the first row of pixel circuits in the second display partition AA2.

[0164] Figure 15 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application, referring to Figure 15 Optionally, the pixel circuit PX comprises a driving module 110 and a threshold compensation module 160, the threshold compensation module 160 is connected between the control end G and the first end D of the driving module 110, the control end of the threshold compensation module 160 is electrically connected with the output end of the shift register, and the threshold compensation module 160 is used for compensating the threshold voltage of the driving module 110 in the compensation stage.

[0165] The pixel circuit PX further comprises a first initialization module 130, the first initialization module 130 is connected between the first end of the light emitting module 140 and the first initialization signal line, and the first initialization module 130 is used for transmitting the first initialization voltage Vref1 on the first initialization signal line to the first end of the light emitting module 140 in response to the pulse signal of the first scanning signal S1 on the first scanning line.

[0166] Optionally, the pixel circuit PX further comprises a data writing module 150, the data writing module 150 is connected between the data line and the second end S of the driving module 110. The data writing module 150 is used for writing the data signal Vdata to the control end G of the driving module 110 in the data writing stage.

[0167] In some optional embodiments of the present application, the first conductive level NVGH1 is a signal for turning on the threshold compensation module 160 in the pixel circuit PX; in another optional embodiment of the present application, the first conductive level NVGH1 is a signal for turning on the data writing module 150 and the threshold compensation module 160 in the pixel circuit PX.

[0168] Optionally, the pixel circuit PX further comprises a first light emitting control module 181 connected between the first power supply line L1 and the second terminal S of the driving module 110, and / or a second light emitting control module 182 connected between the first terminal D of the driving module 110 and the first terminal of the light emitting module 140. The first light emitting control module 181 and the second light emitting control module 182 are configured to be turned on in a light emitting stage to enable the driving module 110 to drive the light emitting module 140 to emit light, and the second terminal of the light emitting module 140 is electrically connected to the second power supply line L2. The driving module 110 is connected between the first power supply line L1 and the first terminal of the light emitting module 140. The driving module 110 is configured to generate a driving current in the light emitting stage to drive the light emitting module 140 in the sub-pixel to emit light.

[0169] The control end of the threshold compensation module 160 is electrically connected with the output end of the output unit 230. When the output unit 230 of the shift register outputs the first conduction level to the threshold compensation module 160, the threshold compensation module 160 is turned on, and in the case that the data writing module 150 is also turned on, the data voltage can be written to the control end of the driving module 110 through the data writing module 150, the driving module 110 and the threshold compensation module 160. When the output unit 230 of the shift register outputs the off level to the threshold compensation module 160, the threshold compensation module 160 is turned off, and the data voltage cannot be written to the control end of the driving module 110. In this way, the refresh frequency of the pixel circuit can be controlled. The threshold compensation module 160 is connected between the second end D and the control end G of the driving module 110, and the threshold compensation module 160 is used for threshold compensation of the driving module 110 in response to the third scan signal S3 on the third scan line. It should be noted that in some optional embodiments of the present application, in the refresh frame and the holding frame of the pixel circuit, the scan line connected with the data writing module 150 is an effective level, so that the data writing module is turned on; and in the refresh frame of the pixel circuit, the output unit 230 of the shift register connected with the pixel circuit outputs the first conduction level, so that the threshold compensation module 160 is turned on to write the data voltage; in the holding frame of the pixel circuit, the output unit 230 of the shift register connected with the pixel circuit outputs the off level, so that the threshold compensation module 160 is turned off, in this case, the threshold compensation module 160 mainly controls the data writing frequency of the pixel circuit, that is, the refresh frequency. In other optional embodiments, in the refresh frame of the pixel circuit, the scan line connected with the data writing module 150 is an effective level, so that the data writing module 150 is turned on; in the holding frame of the pixel circuit, the scan line connected with the data writing module 150 is an off level, so that the data writing module 150 is turned off, and the data writing module 150 and the threshold compensation module 160 jointly control the data writing frequency of the pixel circuit, that is, the refresh frequency of the pixel circuit. Optionally, the pixel circuit PX further comprises a storage module 170, which is connected between the first power supply line L1 and the control end G of the driving module 110.

[0170] Specifically, the first power supply line L1 is used for transmitting a first power supply voltage VDD, and the second power supply line L2 is used for transmitting a second power supply voltage VSS, the first power supply voltage VDD can be greater than the second power supply voltage VSS, and when the connection path between the first power supply line L1 and the second power supply line L2 is turned on, the driving module 110 drives the light emitting module 140 to emit light. The working process of the pixel circuit at least includes a first initialization stage, a data writing stage and a light emitting stage.

[0171] In the first initialization stage, the first initialization module 130 is turned on in response to the first scan signal S1, and transmits the first initialization voltage Vref1 to the first end of the light-emitting module 140 to initialize the potential of the first end of the light-emitting module 140. In the data writing stage, the data writing module 150 is turned on in response to the second scan signal S2, and transmits the data signal Vdata on the data line DL to the second end S of the driving module 110, and writes the data signal Vdata to the control end G of the driving module 110 through the threshold compensation module 160. In the light-emitting stage, the connection path between the first power line L1 and the second power line L2 is turned on through the first light-emitting control module 181 and the second light-emitting control module 182, so that the driving module 110 can drive the light-emitting module 140 to emit light.

[0172] Figure 16 is another structure diagram of a pixel circuit provided by the embodiment of the application. Referring to Figure 16 On the basis of the above technical solution, optionally, the pixel circuit PX further comprises a second initialization module 120, and the display device further comprises a second initialization signal line, the second initialization module 120 being connected between the second initialization signal line and the first end D of the driving module 110, the control end of the second initialization module 120 being electrically connected with the first scan line, and the second initialization module 120 being configured to transmit a second initialization voltage Vref2 on the second initialization signal line to the first end D of the driving module 110 in response to a pulse signal of the first scan signal S1 on the first scan line. In the second initialization stage, the second initialization module 120 is turned on in response to the first scan signal S1 to reset the first end D of the driving module 110.

[0173] Optionally, the pixel circuit PX further comprises a third initialization module 190, and optionally, the scan line GL further comprises a plurality of fourth scan lines, the control end of the third initialization module 190 in the pixel circuit PX of a corresponding row being connected with the fourth scan line.

[0174] Optionally, the display device further comprises a third initialization signal line, and a third initialization module 190 is connected between the third initialization signal line and the first end D of the driving module 110, and the third initialization module 190 is configured to transmit a third initialization voltage Vref3 on the third initialization signal line to the control end G of the driving module 110 through the threshold compensation module 160 in response to a fourth scanning signal S4 on the fourth scanning line. Optionally, the third initialization module 190 can also be directly electrically connected with the control end G of the driving module 110, and the third initialization module 190 is connected between the third initialization signal line and one end of the threshold compensation module 160 connected with the control end G of the driving module 110. The third initialization module 190 is configured to directly transmit the third initialization voltage Vref3 on the third initialization signal line to the control end G of the driving module 110 in response to the fourth scanning signal S4 on the fourth scanning line. In the third initialization stage, the third initialization module 190 is turned on in response to the fourth scanning signal S4 to reset the control end G of the driving module 110.

[0175] Specifically, the first initialization module 130 comprises a fifth transistor M5, the gate of the fifth transistor M5 is connected with the first scanning line G1, the first electrode of the fifth transistor M5 is connected with the first initialization signal line, and the second electrode of the fifth transistor M5 is connected with the first end of the light-emitting module 140. The fifth transistor M5 is configured to transmit the first initialization voltage Vref1 on the first initialization signal line to the first end of the light-emitting module 140 in the first initialization stage.

[0176] Optionally, the second initialization module 120 comprises a sixth transistor M6, the gate of the sixth transistor M6 is connected with the first scanning line, the first electrode of the sixth transistor M6 is connected with the second initialization signal line, and the second electrode of the sixth transistor M6 is connected with the first end D of the driving module 110. The sixth transistor M6 is configured to transmit the second initialization voltage Vref2 on the second initialization signal line to the first end D of the driving module 110 in the second initialization stage.

[0177] Optionally, the driving module 110 comprises a seventh transistor M7 (i.e. a driving transistor), the data writing module 150 comprises an eighth transistor M8, the threshold compensation module 160 comprises a ninth transistor M9, the third initialization module 190 comprises a tenth transistor M10, the first light emitting control module 181 comprises an eleventh transistor M11, the second light emitting control module 182 comprises a twelfth transistor M12, the light emitting module 140 comprises a light emitting diode D1, and the storage module 170 comprises a storage capacitor Cst. The gate of the twelfth transistor M12 is connected with a second scan line, the first pole of the twelfth transistor M12 is connected with a data line, the second pole of the twelfth transistor M12 is connected with the first pole of the eleventh transistor M11, the gate of the ninth transistor M9 is connected with a third scan line, the first pole of the ninth transistor M9 is connected with the second pole of the eleventh transistor M11, and the second pole of the ninth transistor M9 is connected with the gate of the eleventh transistor M11; the gate of the tenth transistor M10 is connected with a fourth scan line, the first pole of the tenth transistor M10 is connected with a second initialization signal line, and the second pole of the tenth transistor M10 is connected with the first pole of the ninth transistor M9; the gate of the eleventh transistor M11 and the gate of the twelfth transistor M12 are both connected with a light emitting control signal line, the first pole of the eleventh transistor M11 is connected with a first power line L1, the second pole of the eleventh transistor M11 is connected with the first pole of the eleventh transistor M11, the first pole of the twelfth transistor M12 is connected with the second pole of the eleventh transistor M11, the second pole of the twelfth transistor M12 is connected with the first pole of the light emitting diode D1, and the second pole of the light emitting diode D1 is connected with a second power line L2; the first pole of the capacitor C is connected with the first power line L1, and the second pole of the capacitor C is connected with the gate of the eleventh transistor M11. Here, the first pole of the light emitting diode D1 can be an anode, and the second pole can be a cathode. The ninth transistor M9 and the tenth transistor M10 can be N-type transistors, or can be P-type transistors, and the rest of the transistors are P-type transistors. Figure 15 Only the case where the ninth transistor M9 and the tenth transistor M10 are N-type transistors is shown, for example, the ninth transistor M9 and the tenth transistor M10 can both be metal oxide transistors, and the advantage of this arrangement is that it can reduce the leakage problem of the gate of the eleventh transistor M11, and is conducive to maintaining the stability of the gate voltage of the eleventh transistor M11.

[0178] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A driving method of a display panel, characterized by, The display panel comprises at least two display partitions, at least two display partitions comprise a first display partition and a second display partition, along the data line extension direction, the first display partition and the second display partition are adjacent, each display partition comprises a plurality of pixel circuits, the pixel circuit is electrically connected with the data line;The display panel further comprises a gate drive circuit and at least one partition enable signal line, the gate drive circuit comprises a plurality of cascaded shift registers, the shift register is connected with the partition enable signal line; The driving method comprises: The partition enable signal line is provided with a partition enable signal, so that the shift register outputs a scanning signal to the corresponding connected pixel circuit according to the partition enable signal, to control the refresh frequency of the corresponding connected pixel circuit, so as to realize the partition multi-frequency display mode;Wherein, the partition multi-frequency display mode is a mode that at least two display partitions have different refresh frequencies, and the scanning signal output by at least one shift register comprises a first conduction level; In at least one frame of the partition multi-frequency display mode, before controlling the scanning signal output by the first shift register corresponding to the second display partition to be the first conduction level, a driving signal corresponding to the driving mode of the second display partition is provided to the driving signal line;Wherein, the driving signal line comprises the partition enable signal line and / or the data line; Wherein, in the partition multi-frequency display mode, the refresh frequency of the second display partition is greater than that of the first display partition;The first shift register corresponding to the second display partition is the shift register connected to the first row of pixel circuits in the second display partition;The pixel circuit is used for writing the data signal on the data line according to the received first conduction level;Wherein, in the driving mode of the second display partition, the level of the partition enable signal line is the enable level, and the data line transmits the data signal; The enable level is the first conduction level;In the partition multi-frequency display mode, the scanning signal output by at least one shift register comprises the first conduction level of the partition enable signal;Before the scanning signal output by the first shift register corresponding to the second display partition is controlled to be the first conduction level in at least one frame of the partition multi-frequency display mode, a driving signal corresponding to the driving mode of the second display partition is provided to the driving signal line, comprising: Before the scanning signal output by the first shift register corresponding to the second display partition is controlled to be the first conduction level in at least one frame of the partition multi-frequency display mode, the first conduction level is provided to the set partition enable signal line;Wherein, the set partition enable signal line is the partition enable signal line connected to the first shift register corresponding to the second display partition; In the first frame of the partition multi-frequency display mode, a driving signal corresponding to the refresh frequency of the second display partition is provided to the driving signal line. The step of providing the first conductive level to the set division enable signal line before the first scanning signal outputted by the first shift register corresponding to the second display division is controlled to be the first conductive level in at least one frame of the division multi-frequency display mode comprises: In at least part of the frames of the division multi-frequency display mode, the time for providing the first conductive level to the set division enable signal line is gradually increased or gradually decreased compared to the time for the first scanning signal outputted by the first shift register corresponding to the second display division to be the first conductive level.

2. The driving method of a display panel according to claim 1, wherein In at least part of the frames of the division multi-frequency display mode, the time for providing the first conductive level to the set division enable signal line is gradually increased or gradually decreased compared to the time for the first scanning signal outputted by the first shift register corresponding to the second display division to be the first conductive level.

3. The driving method of a display panel according to claim 1, wherein In at least part of the frames of the division multi-frequency display mode, the time for providing the first conductive level to the set division enable signal line is gradually increased compared to the time for the first scanning signal outputted by the first shift register corresponding to the second display division to be the first conductive level. The division multi-frequency display mode comprises a first display frame and a second display frame, the first display frame is a holding frame of at least part of the row pixel circuits in the first display division and is a refreshing frame of the second display division; the second display frame is a refreshing frame of the first display division and the second display division.

4. The driving method of a display panel according to claim 1, wherein n first display frames between adjacent second display frames are divided into a plurality of display sub-periods; n is less than or equal to the difference between the refreshing frequency of the second display division and the refreshing frequency of the first display division; the display sub-period comprises a plurality of the first display frames; In at least one of the display sub-periods, the time for providing the first conductive level to the set division enable signal line is gradually increased or gradually decreased compared to the time for the first scanning signal outputted by the first shift register corresponding to the second display division to be the first conductive level in a manner of changing every d frames; wherein the display sub-period comprises a plurality of the first display frames; and wherein d is less than n.

5. The driving method of a display panel according to claim 1, wherein In the former one of the adjacent display sub-periods, the time for providing the first conductive level to the set division enable signal line is gradually increased or gradually decreased compared to the time for the first scanning signal outputted by the first shift register corresponding to the second display division to be the first conductive level in a manner of changing every d frames; In the latter one of the adjacent display sub-periods, the time for providing the first conductive level to the set division enable signal line is gradually decreased or gradually increased compared to the time for the first scanning signal outputted by the first shift register corresponding to the second display division to be the first conductive level in a manner of changing every d frames.

6. The driving method of the display panel according to claim 5, wherein The number of the first display frames comprised by the plurality of the display sub-periods is equal.

7. The driving method of the display panel according to claim 1, wherein The step of providing the first conductive level to the set division enable signal line before the first scanning signal outputted by the first shift register corresponding to the second display division is controlled to be the first conductive level in at least one frame of the division multi-frequency display mode comprises: In at least one frame of the subfield multi-frequency display mode, the first conductive level is provided to the set subfield enable signal line before the first conductive level output by the first shift register corresponding to the second display subfield is controlled.

8. The driving method of the display panel according to claim 1, wherein The shift register comprises a stage transmission unit and an output unit, the stage transmission unit is used for transmitting the second conductive level stage by stage; and the output unit accesses the subfield enable signal and is used for transmitting the subfield enable signal to the output end of the shift register when the stage transmission unit outputs the second conductive level, and the output end of the shift register is used for outputting the scanning signal. In at least one frame of the subfield multi-frequency display mode, the first conductive level is provided to the set subfield enable signal line before the first conductive level output by the first shift register corresponding to the second display subfield is controlled. In at least one frame of the subfield multi-frequency display mode, the first conductive level of the subfield enable signal is provided to the set subfield enable signal line before the second conductive level output by the set stage transmission unit is controlled; wherein the set stage transmission unit is the stage transmission unit of the shift register connected to the first row of pixel circuits in the second display subfield.

9. The driving method of the display panel according to claim 8, wherein The display panel comprises k subfield enable signal lines, the gate drive circuit comprises a plurality of cascaded shift register groups, each shift register group comprises k cascaded shift register units, k is an integer greater than or equal to 2, each shift register unit comprises m shift registers, m is an integer greater than or equal to 1, different shift register units in the same shift register group are electrically connected to different subfield enable signal lines, and different shift register groups are connected to the same k subfield enable signal lines. The display subfield comprises a plurality of pixel circuit groups; each pixel circuit group comprises k sub-pixel circuit groups, each sub-pixel circuit group comprises a plurality of rows of pixel circuits; each sub-pixel circuit group is electrically connected to one shift register unit; and the output end of each shift register is electrically connected to r rows of pixel circuits, r is an integer greater than or equal to 1.

10. The driving method of the display panel according to claim 9, wherein In the first display frame, the time of pulse jump of the signals of the k subfield enable signal lines to the first conductive level is delayed in turn; in the second display frame, the signals on the k subfield enable signal lines are the first conductive level; wherein the first display frame is the holding frame of at least part of the rows of pixel circuits in the first display subfield and is the refresh frame of the second display subfield; the second display frame is the refresh frame of the first display subfield and the second display subfield; in the second display frame, the first display subfield is refreshed before the second display subfield.

11. The driving method of the display panel according to claim 10, wherein K-1 shift register units are connected between two adjacent shift register units connected to the same subfield enable signal line.

12. The driving method of the display panel according to claim 11, wherein, m is greater than or equal to 8, and k is greater than or equal to 4. The first conductive level of the partition enable signal is provided to the set partition enable signal line before the second conductive level output by the stage transfer unit of the shift register connected with the set partition enable signal line jumps to the off level after the second conductive level output by the stage transfer unit of the shift register connected with the set partition enable signal line in the pixel circuit group adjacent to the second display partition in the first display partition jumps to the off level and before the second display partition corresponding first shift register outputs the second conductive level in at least one frame of the partition multi-frequency display mode.

13. The driving method of the display panel according to claim 12, wherein The number of rows of the pixel circuits in each of the pixel circuit groups is the same.

14. The driving method of the display panel according to claim 13, wherein The time for providing the first conductive level to the set partition enable signal line is less than or equal to k*c*b, wherein c is the number of rows of the pixel circuits included in one of the pixel circuit groups, b is the sum of the first conductive level pulse width time corresponding to one row of the pixel circuits and the preset time interval, and the preset time interval is equal to the time interval of the first conductive level output by adjacent two stages of the shift register.

15. The driving method of the display panel according to claim 14, wherein The preset time interval is greater than or equal to 0.

16. The driving method of the display panel according to claim 15, wherein In at least part of the first n frames of the partition multi-frequency display mode, the time for providing the first conductive level to the set partition enable signal line gradually increases or gradually decreases compared with the time for the set stage transfer unit to output the second conductive level; n is greater than or equal to 2.

17. The driving method of the display panel according to claim 15, wherein In at least part of the first n frames of the partition multi-frequency display mode, the time for providing the first conductive level to the set partition enable signal line gradually increases compared with the time for the set stage transfer unit to output the second conductive level.

18. The driving method of the display panel according to claim 15, wherein The time for providing the first conductive level of the partition enable signal to the set partition enable signal line compared with the time for the set stage transfer unit to output the second conductive level is equal to an integer multiple of the sum of the first conductive level pulse width time output by the shift register and the preset time interval.

19. The driving method of the display panel according to any one of claims 1 to 18, wherein The method comprises the following steps: In at least one frame of the partition multi-frequency display mode, before the first conductive level of the partition enable signal output by the first shift register corresponding to the second display partition is controlled to be the first conductive level, the driving signal corresponding to the driving mode of the second display partition is provided to the driving signal line.

20. The driving method of the display panel according to claim 19, wherein The shift register comprises a stage transfer unit and an output unit, the stage transfer unit is used for transferring the second conductive level stage by stage, and the output unit is connected with the partition enable signal and is used for transmitting the partition enable signal to the output end of the shift register when the stage transfer unit outputs the second conductive level, and the output end of the shift register is used for outputting the scan signal. The first output mode is used to output data signals to the data line before the first conductive level of the partition enable signal output by the first shift register corresponding to the second display partition is controlled in at least one frame of the partition multi-frequency display mode. The first output mode is used to output data signals to the data line before the first conductive level of the partition enable signal output by the first shift register corresponding to the second display partition is controlled in at least one frame of the partition multi-frequency display mode.

21. The driving method of the display panel according to claim 20, wherein Further comprising: The first output mode is used to output data signals to the data line before the first conductive level of the partition enable signal output by the first shift register corresponding to the second display partition is controlled in at least one frame of the partition multi-frequency display mode. And / or, The first output mode is used to output data signals to the data line before the first conductive level of the partition enable signal output by the first shift register corresponding to the second display partition is controlled in at least one frame of the partition multi-frequency display mode.

22. The driving method of the display panel according to claim 1, wherein The time difference between the time when the driving signal corresponding to the second display partition is provided to the driving signal line and the time when the first conductive level of the partition enable signal output by the first shift register corresponding to the second display partition is controlled is positively correlated with the difference in refresh frequency between the second display partition and the first display partition.

23. The driving method of the display panel according to claim 1, wherein The partition enable signal is provided to the partition enable signal line to enable the shift register to output a scanning signal to the pixel circuit connected thereto according to the partition enable signal, so as to control the refresh frequency of the pixel circuit connected thereto, thereby realizing the partition multi-frequency display mode. The first conductive level and the off level of the partition enable signal on the partition enable signal line in a frame are controlled to control the scanning signal output by different shift registers to be the first conductive level or the off level, so as to control the refresh frequency of the pixel circuit connected thereto, thereby realizing the partition multi-frequency display mode.

24. The driving method of the display panel according to claim 1, wherein The partition multi-frequency display mode includes a first display frame and a second display frame, the first display frame is a retention frame of at least part of the row pixel circuits in the first display partition, and is a refresh frame of the second display partition; the second display frame is a refresh frame of the first display partition and the second display partition. The driving signal corresponding to the driving mode of the second display partition is provided to the driving signal line before the scanning signal output by the first shift register corresponding to the second display partition is controlled to be the first conductive level in at least one frame of the partition multi-frequency display mode. The driving signal corresponding to the driving mode of the second display partition is provided to the driving signal line before the scanning signal output by the first shift register corresponding to the second display partition is controlled to be the first conductive level in at least one frame of the partition multi-frequency display mode.

25. The driving method of the display panel according to claim 1, wherein The first display frame and the second display frame respectively include a first period, a second period and a third period; In the first period of the first display frame, the scan signal output to the N rows of pixel circuits of the first display area is continuously off, the non-enabled level is provided to the area enable signal line, and the direct current level is provided to the data line, or no signal is output to the data line; In the second period of the first display frame, the scan signal output to the M rows of pixel circuits of the first display area includes the on level, the enabled level is provided to the area enable signal line, and the data signal is provided to the data line; In the third period of the first display frame, the scan signal output to the pixel circuits of the second display area includes the on level, the enabled level is provided to the area enable signal line, and the data signal is provided to the data line; The M rows of pixel circuits are located between the N rows of pixel circuits and the second display area; The M corresponding to at least two first display frames is not equal.

26. The driving method of the display panel according to claim 25, wherein The data signal provided to the data line in the second period of the first display frame is the same as the data signal corresponding to the M rows of pixel circuits of the second display frame before the second display frame.

27. The driving method of the display panel according to claim 25, wherein In the first period of the second display frame, the scan signal output to the N rows of pixel circuits of the first display area includes the on level, the enabled level is provided to the area enable signal line, and the data signal is provided to the data line; In the second period of the second display frame, the scan signal output to the M rows of pixel circuits of the first display area includes the on level, the enabled level is provided to the area enable signal line, and the data signal is provided to the data line; In the third period of the second display frame, the scan signal output to the pixel circuits of the second display area includes the on level, the enabled level is provided to the area enable signal line, and the data signal is provided to the data line; In the plurality of first display frames between the two adjacent second display frames, the M corresponding to at least two first display frames is not equal, and the M corresponding to the first display frame in the front timing is smaller than the M corresponding to the first display frame in the rear timing.

28. A driving method of a display panel, comprising: The display panel includes at least two display areas, at least two display areas include a first display area and a second display area, along the data line extension direction, the first display area and the second display area are adjacent, each display area includes a plurality of pixel circuits, the pixel circuit is electrically connected with the data line; the display panel further includes a gate drive circuit and at least one area enable signal line, the gate drive circuit includes a plurality of cascaded shift registers, the shift register is correspondingly connected with the area enable signal line; The driving method comprises: The area enable signal is provided to the area enable signal line, so that the shift register outputs the scan signal to the corresponding connected pixel circuit according to the area enable signal, to control the refresh frequency of the corresponding connected pixel circuit, so as to realize the multi-frequency display mode of the area; wherein the scan signal output by at least one shift register includes the first on level of the area enable signal; The first conductive level is provided to a set partition enable signal line before a first scan signal output by a first shift register corresponding to the second display partition is controlled to be the first conductive level in at least one frame of the partitioned multi-frequency display mode; the set partition enable signal line is a partition enable signal line to which the first shift register corresponding to the second display partition is connected; In the partitioned multi-frequency display mode, a refresh frequency of the second display partition is greater than a refresh frequency of the first display partition; the first shift register corresponding to the second display partition is a shift register connected to a first row of pixel circuits in the second display partition; and the pixel circuit is configured to write a data signal on the data line according to the first conductive level received. The first conductive level is provided to a set partition enable signal line before a first scan signal output by a first shift register corresponding to the second display partition is controlled to be the first conductive level in at least one frame of the partitioned multi-frequency display mode; the set partition enable signal line is a partition enable signal line to which the first shift register corresponding to the second display partition is connected; In at least part of the frames of the partitioned multi-frequency display mode, a time for providing the first conductive level to the set partition enable signal line is gradually increased or gradually decreased compared to a time for the first shift register corresponding to the second display partition to output the first conductive level. The partitioned multi-frequency display mode includes a first display frame and a second display frame; the first display frame is a retention frame of at least part of the rows of pixel circuits in the first display partition and is a refresh frame of the second display partition; and the second display frame is a refresh frame of the first display partition and the second display partition.

29. The driving method of the display panel according to claim 28, wherein n adjacent first display frames between adjacent second display frames are divided into a plurality of display sub-periods; n is less than or equal to a difference between a refresh frequency of the second display partition and a refresh frequency of the first display partition; and each display sub-period includes a plurality of first display frames. In at least one display sub-period, a time for providing the first conductive level to the set partition enable signal line is gradually increased or gradually decreased compared to a time for the first shift register corresponding to the second display partition to output the first conductive level in a manner of changing every d frames; each display sub-period includes a plurality of first display frames; and d is less than n.

30. The driving method of the display panel according to claim 28, wherein In a previous one of adjacent display sub-periods, a time for providing the first conductive level to the set partition enable signal line is gradually increased or gradually decreased compared to a time for the first shift register corresponding to the second display partition to output the first conductive level in a manner of changing every d frames. In a later one of adjacent display sub-periods, a time for providing the first conductive level to the set partition enable signal line is gradually decreased or gradually increased compared to a time for the first shift register corresponding to the second display partition to output the first conductive level in a manner of changing every d frames.

31. The driving method of the display panel according to any one of claims 29-30, wherein, The number of first display frames included in each of the plurality of display sub-periods is equal.

32. The driving method of claim 28, wherein, in at least part of the frames in the subfield multi-frequency display mode, a time for providing the first conductive level to the set subfield enable signal line compared with a time for the first subfield corresponding first shift register to output the first conductive level is gradually increased or gradually decreased in a manner of changing every d frames, where d is greater than or equal to 0. In at least part of the frames in the subfield multi-frequency display mode, a time for providing the first conductive level to the set subfield enable signal line compared with a time for the first subfield corresponding first shift register to output the first conductive level is gradually increased.

33. The driving method of the display panel according to claim 28, wherein The display panel comprises at least two display subfields, at least two display subfields comprise a first display subfield and a second display subfield, along the data line extension direction, the first display subfield and the second display subfield are adjacent, each display subfield comprises a plurality of pixel circuits, and the pixel circuits are electrically connected with the data line; the display panel further comprises a gate drive circuit and at least one subfield enable signal line, the gate drive circuit comprises a plurality of cascaded shift registers, the shift registers are correspondingly electrically connected with the subfield enable signal line, and the shift registers are used for controlling the refresh frequency of the corresponding connected pixel circuits according to the subfield enable signal of the subfield enable signal line; 34. A display device for performing the driving method of the display panel according to any one of claims 1 to 27, characterized by The display driving module is used for providing a subfield enable signal to the subfield enable signal line, so that the shift register outputs a scanning signal to the corresponding connected pixel circuit according to the subfield enable signal, to control the refresh frequency of the corresponding connected pixel circuit, thereby realizing a subfield multi-frequency display mode; wherein, the scanning signal output by at least one shift register comprises a first conductive level; in at least one frame in the subfield multi-frequency display mode, before controlling the scanning signal output by the first shift register corresponding to the second display subfield to be the first conductive level, a driving signal corresponding to the driving mode of the second display subfield is provided to the driving signal line; wherein, the driving signal line comprises the subfield enable signal line and / or the data line; In the subfield multi-frequency display mode, the refresh frequency of the second display subfield is greater than the refresh frequency of the first display subfield; the first shift register corresponding to the second display subfield is the shift register connected with the first row of pixel circuits in the second display subfield; the pixel circuit is used for writing the data signal on the data line according to the received first conductive level; wherein, in the driving mode of the second display subfield, the level on the subfield enable signal line is an enable level, and the data line transmits a data signal. ​ 35. The display device of claim 34, wherein, The enable level is the first conduction level; in the subfield multi-frequency display mode, the scan signal output by at least one of the shift registers comprises the first conduction level of the subfield enable signal; the display driving module comprises a first driving unit, which is configured to provide the first conduction level to a set subfield enable signal line before controlling the first shift register corresponding to the second display subfield to output the scan signal of the first conduction level in at least one frame of the subfield multi-frequency display mode; wherein the set subfield enable signal line is the subfield enable signal line connected to the first shift register corresponding to the second display subfield. And / or, the display driving module comprises a second driving unit, which is configured to output a data signal to the data line in a first output mode before controlling the first shift register corresponding to the second display subfield to output the first conduction level of the subfield enable signal in at least one frame of the subfield multi-frequency display mode; wherein the data signal output to the data line in the first output mode has a jump.

36. A display device according to claim 34 or 35, wherein, The shift register comprises a stage transmission unit and an output unit, the stage transmission unit is configured to transmit the second conduction level stage by stage; the control end of the output unit is electrically connected with the intermediate node of the stage transmission unit, and the potential of the intermediate node is used to control the stage transmission unit to output the second conduction level or an off level; the control end of the output unit is electrically connected with the intermediate node, the first input end of the output unit is electrically connected with the subfield enable signal line, and the second input end of the output unit is connected to the off level; the output end of the output unit is electrically connected with at least one row of pixel circuits.

37. The display device of claim 36, wherein, The intermediate node comprises a first intermediate node and a second intermediate node, and the control end of the output unit comprises a first control end and a second control end; the first control end is electrically connected with the first intermediate node, and the second control end is electrically connected with the second intermediate node; the output unit comprises a first transistor and a second transistor; the gate of the first transistor serves as the first control end, and the gate of the second transistor serves as the second control end; the first electrode of the first transistor serves as the first input end, the first electrode of the second transistor serves as the second input end, and the second electrode of the first transistor and the second electrode of the second transistor are electrically connected with the output end of the output unit.

38. The display device of claim 37, wherein, The pixel circuit comprises a driving module and a threshold compensation module, the threshold compensation module is connected between the control end and the first end of the driving module, and the control end of the threshold compensation module is electrically connected with the output end of the shift register.

39. The display device of claim 38, wherein, The pixel circuit further comprises a data writing module, which is connected between the data line and the second end of the driving module.

40. The display device of claim 39, wherein, The pixel circuit further comprises a first light-emitting control module and a second light-emitting control module, the first light-emitting control module is connected between the second end of the driving module and the first power supply line, the second light-emitting control module is connected between the first end of the driving module and the first end of the light-emitting module, and the second end of the light-emitting module is electrically connected with the second power supply line.

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