Processing method and device for automatically adjusting sampling of asynchronous data
By using bit length counter and sampling pulse technology in asynchronous communication, the problem of data reception errors caused by error accumulation in asynchronous communication is solved, and higher data sampling accuracy and lower bit error rate are achieved.
Patent Information
- Application Number
- CN202411360100.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-27
- Publication Date
- 2025-01-21
AI Technical Summary
In asynchronous communication mode, since the working clocks of both parties of the communication are different sources and frequencies, the accumulation of errors during data transmission is caused, which in turn affects the accuracy of data reception.
By obtaining the asynchronous data, determine whether the comparison of the special length counter is accumulated based on the position of the data edge. When the accumulation is added to the preset length value, the sampling pulse is generated for sampling to obtain the sampling data.
This method can effectively reduce the code rate and improve the accuracy of data sampling, and does not require the local clock to work at a high frequency, suitable for embedding into integrated circuit chips such as FPGA or MCU/SOC.
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Figure CN119341718A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit design, and in particular to a processing method, device and electronic device for automatically adjusting sampling of asynchronous data. Background Art
[0002] Communication in a broad sense refers to the process in which two or more parties use any method and any medium to exchange information. Communication can be divided into many categories. From the perspective of whether the clocks of the two communicating parties are from the same source, communication is divided into synchronous communication and asynchronous communication. Synchronous communication requires that the working clocks of the two communicating parties are from the same source and that both parties are completely synchronized, so the allowable error is very small. In asynchronous communication mode, the receiving end clock and the sending end clock are not required to be from the same source, and a certain error is allowed. In this mode, after the sending end sends a byte, it can send the next byte after any long time interval. In order to distinguish between idle data and actual valid data, the transmission of asynchronous communication starts with a frame header mark (such as the "start bit" of UART) and ends with a frame end mark (such as the "stop bit" of UART), and the load data is transmitted between the two.
[0003] In the asynchronous communication mode, although the baud rates of both parties are the same, the working clocks of both parties are local clocks, so the clock frequencies of both parties are from different sources and frequencies. Due to the frequency difference caused by the above reasons, if the transmitted data is large, it is easy to cause the accumulation of errors, resulting in data reception errors during the transmission process. On the other hand, when the receiver performs asynchronous sampling, the oversampling method is used for sampling positioning. The purpose of oversampling is to lock its sampling at the middle moment of the data bit according to the preset baud rate, thereby reducing the probability of sampling errors. In order to make the local reception follow the clock of the sending side as much as possible, the receiver will use the edge of the data to extract the clock information and follow the clock. However, due to the existence of interference, there will be redundant data edges, which will cause the receiver's oversampling to be offset, affecting the sampling of the input data. Summary of the invention
[0004] In view of this, the present application proposes a processing method for automatically adjusting sampling of asynchronous data to solve the problems embodied in the above-mentioned background technology.
[0005] According to one aspect of the present application, a method for processing asynchronous data automatic adjustment sampling is provided, comprising:
[0006] Get asynchronous data;
[0007] Determining whether to accumulate a bit length count of a digital signal duration of the asynchronous data in a bit length counter according to a position of a data edge of the asynchronous data;
[0008] When the bit length counter accumulates to a preset length value, a sampling pulse is generated, and the asynchronous data is sampled using the sampling pulse to obtain sampled data.
[0009] As an optional implementation scheme of the present application, determining whether to accumulate the bit length count of the digital signal duration of the asynchronous data in the bit length counter according to the position of the data edge of the asynchronous data includes:
[0010] When the data edge is located within a preset time window or a frame header, the bit length counter is reset to zero;
[0011] When the data edge is not located within the preset time window or the frame header, the bit length counter is counted and accumulated.
[0012] As an optional implementation scheme of the present application, when the bit length counter accumulates to a preset length value, a sampling pulse is generated, and the asynchronous data is sampled using the sampling pulse to obtain the sampled data, including:
[0013] Preset sampling position of sampling pulse;
[0014] The asynchronous data is sampled using the sampling pulse according to the sampling position to obtain sampled data.
[0015] As an optional implementation scheme of the present application, the bit length counter is reset to zero, further comprising:
[0016] When the bit length counter accumulates to a preset maximum bit length value, the bit length counter is reset to zero.
[0017] As an optional implementation scheme of the present application, according to the sampling position, the asynchronous data is sampled using the sampling pulse to obtain the sampled data, further comprising:
[0018] Counting the count value before the bit length counter is cleared;
[0019] In a cycle of counting the count value, if the count value is outside a preset count value range for a consecutive preset number of times, it is determined that the asynchronous data contains a bit error.
[0020] As an optional implementation scheme of the present application, within a counting cycle, if the count value is outside the preset count value range for a consecutive preset number of times, after determining that the asynchronous data contains a bit error, the method further includes:
[0021] The asynchronous data is resampled using the sampling pulse, and when a data edge of the asynchronous data is detected, the bit length count of the bit length counter continues to accumulate until a preset maximum bit length value is reached.
[0022] As an optional implementation scheme of the present application, before determining whether to accumulate the bit length count of the digital signal duration of the asynchronous data in the bit length counter according to the position of the data edge of the asynchronous data, the method further includes:
[0023] Preset glitch threshold;
[0024] The level signal whose pulse width in the asynchronous data is smaller than the glitch threshold is filtered.
[0025] As an optional implementation scheme of the present application, according to the sampling position, the asynchronous data is sampled using the sampling pulse to obtain the sampled data, and further includes:
[0026] The bit size of the sampled data is determined according to the principle of large numbers.
[0027] The present application also provides a processing device for automatically adjusting sampling of asynchronous data, comprising:
[0028] Get data module, used to get asynchronous data;
[0029] A determination counter working module, used for determining whether to accumulate the bit length count of the digital signal duration of the asynchronous data in the bit length counter according to the position of the data edge of the asynchronous data;
[0030] The sampling module is used to generate a sampling pulse when the bit length counter accumulates to a preset length value, and use the sampling pulse to sample the asynchronous data to obtain sampled data.
[0031] The present application also provides an electronic device, including:
[0032] processor;
[0033] a memory for storing processor-executable instructions;
[0034] Wherein, the processor is configured to implement the above-mentioned processing method for automatically adjusting sampling of asynchronous data when executing the executable instructions.
[0035] Beneficial effects of this application:
[0036] The present invention obtains asynchronous data, and determines whether to accumulate the bit length count of the digital signal duration of the asynchronous data in the bit length counter according to the position of the data edge of the asynchronous data. When the bit length counter accumulates to a preset length value, a sampling pulse is generated, and the asynchronous data is sampled using the sampling pulse to obtain the sampled data. Through this method, it is possible to configure to filter burrs of different widths, so that the environmental adaptability of the signal is better, the data edge can be monitored, the sampling of the asynchronous data can be reconstructed, and the sampling effect caused by the erroneous data can be effectively reduced, thereby reducing the bit error rate. In addition, the local clock does not need to work at a very high frequency, so it can be well embedded in digital designs such as FPGA or integrated circuit chips such as MCU / SOC, and the resource occupancy rate is low.
[0037] Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present application and, together with the description, serve to explain the principles of the present application.
[0039] Figure 1 A flowchart showing a method for processing asynchronous data automatic adjustment sampling according to an embodiment of the present application;
[0040] Figure 2 A bit length counter workflow diagram showing the processing method for automatically adjusting sampling of asynchronous data according to an embodiment of the present application;
[0041] Figure 3 A diagram showing a delayed asynchronous data reception situation of the asynchronous data automatic adjustment sampling processing method according to an embodiment of the present application;
[0042] Figure 4 A diagram showing a situation of asynchronous data reception with delay and bit error in the method for automatically adjusting sampling of asynchronous data according to an embodiment of the present application;
[0043] Figure 5 A diagram showing a situation of receiving asynchronous data with delay and glitches in a processing method for automatically adjusting sampling of asynchronous data according to an embodiment of the present application;
[0044] Figure 6 A block diagram of a processing device for automatically adjusting sampling of asynchronous data according to an embodiment of the present application is shown. DETAILED DESCRIPTION
[0045] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.
[0046] Among them, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application or simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0047] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0048] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.
[0049] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.
[0050] Example 1
[0051] Figure 1 FIG. 1 is a flow chart showing a method for automatically adjusting sampling of asynchronous data according to an embodiment of the present application. Figure 1 As shown, the flow chart includes:
[0052] S100, obtaining asynchronous data;
[0053] In this embodiment, the asynchronous data is mainly a low-speed asynchronous signal. This method does not require a very high-frequency clock, that is, it does not exceed 16 times the baud rate of the low-speed asynchronous signal. Taking a serial port with a baud rate of 115200 as an example, the local clock operating frequency ≥ 1.8432M is sufficient, and the timing requirement is not high, which is more conducive to engineering implementation.
[0054] After receiving the asynchronous data, the asynchronous data is synchronized to the local clock domain, and the glitches in the asynchronous data are filtered through the configured registers.
[0055] S200, determining whether to accumulate a bit length count of a digital signal duration of the asynchronous data in a bit length counter according to a position of a data edge of the asynchronous data;
[0056] In this embodiment, the bit length counter is the bit length counter. By default, after the bit length counter is powered on, when the position of the data edge of the asynchronous data after glitch filtering is within the [MAX-bit_window_offset_set, bit_window_offset_set] window or the frame header indication signal is valid, the bit length counter will be cleared.
[0057] Among them, the [MAX-bit_window_offset_set, bit_window_offset_set] window can be configured through a register. In this embodiment, the window is used to mark the boundary of the bit. During the communication process, the boundary position of each bit of the asynchronous signal at different rates is not fixed. Therefore, by configuring the register, when the boundary of the asynchronous signal bit is reached, the bit length counter is cleared to mark the boundary position of the next bit. The register is used to be compatible with the bit width error caused by different sources and frequencies of the communicating parties. In practical applications, it can be set to 0 in most cases.
[0058] S300, when the bit length counter accumulates to a preset length value, a sampling pulse is generated, and the asynchronous data is sampled using the sampling pulse to obtain sampled data.
[0059] In this embodiment, the preset length value is Sample_pulse_set, and the default value is Sample_pulse_set=MAX / 2, that is, when the count value in the bit length counter reaches MAX / 2, the sampling pulse is valid, and the sampling pulse can be used to sample the asynchronous data.
[0060] Similarly, Sample_pulse_set can be configured through a register. In this embodiment, the default value is MAX / 2, that is, sampling is performed at the middle position of the bit. Furthermore, the position of the sampling point can be adjusted by modifying the value of the register.
[0061] As an optional implementation scheme of the present application, according to the position of the data edge of the asynchronous data, it is determined whether to accumulate the bit length count of the digital signal duration of the asynchronous data in the bit length counter, including: when the data edge is located within a preset time window or a frame header, the bit length counter is cleared to zero; when the data edge is not located within the preset time window or the frame header, the bit length counter is accumulated.
[0062] In this embodiment, the preset time window is [MAX-bit_window_offset_set, bit_window_offset_set], where MAX = Tbit / Tclk_period, Tclk_period is the current local clock period, and Tbit is the pulse width of one bit of asynchronous data. For example, assuming that the current clock period is 10ns and the pulse width of one data bit is 200ns, then MAX = 200 / 10 = 20. Figure 2 The bit length counter workflow shown in Figure 3 The asynchronous data reception under the condition of delay is shown. After the asynchronous signal is transmitted through the channel, there is a delay. In this embodiment, it is assumed that the receiving end can accept the influence of the delay. Figure 3 It can be obtained that the upper part is an ideal asynchronous signal, and the lower part is an asynchronous signal with actual reception delay. After receiving the asynchronous signal with delay, when the data edge of the asynchronous signal is within [MAX-bit_window_offset_set, bit_window_offset_set] or the frame header, the count in the bit length counter is cleared; if the data edge of the asynchronous signal is not within [MAX-bit_window_offset_set, bit_window_offset_set] or is not at the frame header, the bit length counter keeps counting.
[0063] As an optional implementation scheme of the present application, when the bit length counter accumulates to a preset length value, a sampling pulse is generated, and the asynchronous data is sampled using the sampling pulse to obtain sampled data, including: a sampling position of a preset sampling pulse; according to the sampling position, the asynchronous data is sampled using the sampling pulse to obtain sampled data.
[0064] In this embodiment, when the count value in the bit length counter reaches MAX / 2, the sampling pulse is valid, and in the local clock cycle, the asynchronous data is sampled three times at the three positions of the -1, 0, and +1 levels of the sampling pulse, that is, the asynchronous data at the -1 level, the asynchronous data at the 0 level, and the asynchronous data at the +1 level are sampled. The sampled data is sorted to obtain sampled data.
[0065] As an optional implementation scheme of the present application, the bit length counter is reset to zero, further comprising: when the bit length counter is accumulated to a preset maximum bit length value, the bit length counter is reset to zero.
[0066] like Figure 2 As shown, in addition to clearing the bit length counter when the detected data edge is within [MAX-bit_window_offset_set, bit_window_offset_set] or the frame header, the bit length counter is cleared when the bit length counter counts to the MAX value.
[0067] As an optional implementation scheme of the present application, according to the sampling position, the asynchronous data is sampled using the sampling pulse to obtain the sampled data, and it also includes: counting the count value before the bit length counter is cleared; within a cycle of counting the count value, if the count value is outside the preset count value range for a consecutive preset number of times, it is determined that the asynchronous data contains bit errors.
[0068] In this embodiment, the preset counting value range is [MAX-Δ, MAX+Δ], where Δ=Bit_window_offset_set, and the counting value before the bit length counter is cleared is continuously counted. When it is detected that within a statistical counting cycle, there are two consecutive counting values outside the range of [MAX-Δ, MAX+Δ], it means that a bit error event has occurred, that is, the asynchronous data contains bit errors.
[0069] As an optional implementation scheme of the present application, within a counting cycle, if the count value is outside the preset count value range for a preset number of consecutive times, after determining that the asynchronous data contains bit errors, it also includes: re-sampling the asynchronous data using the sampling pulse, and when the data edge of the asynchronous data is detected, the bit length count of the bit length counter continues to accumulate until the preset maximum bit length value.
[0070] like Figure 4As shown in the figure, the upper part is asynchronous data with bit errors. Due to the existence of bit errors during sampling, the data edge of the bit error in the time window will be captured, triggering the clearing of the bit length counter in advance, resulting in sampling errors. After determining that a bit error event has occurred, the sampling process is rebuilt. The asynchronous data is resampled. At this time, during the sampling process, when a data edge is detected, the data edge is prohibited from clearing the bit length counter. When the bit length counter reaches the MAX value, the data edge is re-enabled to clear the bit length counter.
[0071] As an optional implementation scheme of the present application, before determining whether to accumulate the bit length count of the digital signal duration of the asynchronous data in the bit length counter based on the position of the data edge of the asynchronous data, it also includes: presetting a glitch threshold; filtering the level signal in the asynchronous data whose pulse width is less than the glitch threshold.
[0072] In this embodiment, the glitch threshold is Burr_filter_set value*local clock cycle, and a high level or a low level of an asynchronous data pulse width smaller than the glitch threshold will be regarded as a glitch and filtered.
[0073] The working principle of glitch filtering is as follows: when the local clock continuously samples '1' for Burr_filter_set cycles, it is considered to be a true '1'. Similarly, when the local clock continuously samples '0' for Burr_filter_set cycles, it is considered to be a true '0'. Otherwise, the change is ignored.
[0074] like Figure 5 As shown in the figure, when the asynchronous signal is delayed and contains glitches, the bit length counter will capture the glitch edge within the window during sampling, which will trigger the bit length counter to be cleared in advance. After eliminating the glitches, the bit length counter captures the data edge outside the time window during sampling. At this time, the data edge will be discarded and will not trigger the bit length counter to be cleared.
[0075] As an optional implementation scheme of the present application, according to the sampling position, the asynchronous data is sampled using the sampling pulse to obtain the sampled data, and the method further includes: determining the bit size of the sampled data according to the principle of large numbers.
[0076] The asynchronous data is sampled three times at the three positions of the sampling pulse level -1, 0, +1 to obtain the sampled data, and the number of bits quantized by the sampled data is determined using the principle of large numbers.
[0077] This method can be configured to filter glitches of different widths, making the signal more adaptable to the environment, monitoring the data edge, reconstructing the sampling of asynchronous data, and effectively reducing the sampling impact of erroneous data, thereby reducing the bit error rate. In addition, the local clock does not need to work at a very high frequency, so it can be well embedded in digital designs such as FPGA or integrated circuit chips such as MCU / SOC, with low resource occupancy.
[0078] Example 2
[0079] Based on the same principle as the above method, a processing device for automatically adjusting sampling of asynchronous data is also proposed, see Figure 6 , an asynchronous data automatic adjustment sampling processing device 100 according to an embodiment of the present disclosure includes:
[0080] A data acquisition module 110 is used to acquire asynchronous data;
[0081] A determination counter working module 120, configured to determine whether to accumulate a bit length count of a digital signal duration of the asynchronous data in a bit length counter according to a position of a data edge of the asynchronous data;
[0082] The sampling module 130 is used to generate a sampling pulse when the bit length counter accumulates to a preset length value, and use the sampling pulse to sample the asynchronous data to obtain sampled data.
[0083] Obviously, those skilled in the art should understand that all or part of the processes in the above-mentioned embodiment method can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned control methods. The modules or steps of the present invention can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. Optionally, they can be implemented by program codes executable by computing devices, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules respectively, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. In this way, the present invention is not limited to any specific combination of hardware and software.
[0084] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment method can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned control methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated as: HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.
[0085] Example 3
[0086] Furthermore, an electronic device is proposed, comprising:
[0087] processor;
[0088] a memory for storing processor-executable instructions;
[0089] The processor is configured to implement the processing method for automatically adjusting sampling of asynchronous data as described in Example 1 when executing the executable instructions.
[0090] The electronic device of the embodiment of the present disclosure includes a processor and a memory for storing processor executable instructions, wherein the processor is configured to implement any of the above-mentioned asynchronous data automatic adjustment sampling processing methods when executing the executable instructions.
[0091] It should be noted that the number of processors may be one or more. At the same time, the electronic device of the embodiment of the present disclosure may also include an input device and an output device. The processor, memory, input device, and output device may be connected via a bus or in other ways, which are not specifically limited here.
[0092] The memory is a computer-readable storage medium for the method for automatically adjusting sampling of asynchronous data, and can be used to store software programs, computer executable programs, and various modules, such as the program or module corresponding to the method for automatically adjusting sampling of asynchronous data in the embodiment of the present disclosure. The processor executes various functional applications and data processing of the electronic device by running the software program or module stored in the memory.
[0093] The input device can be used to receive input numbers or signals. The signal can be a key signal related to user settings and function control of the device / terminal / server. The output device can include a display device such as a display screen.
[0094] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.
Claims
1. A method for processing asynchronous data automatic adjustment sampling, characterized in that: include: Get asynchronous data; Determining whether to accumulate a bit length count of a digital signal duration of the asynchronous data in a bit length counter according to a position of a data edge of the asynchronous data; When the bit length counter accumulates to a preset length value, a sampling pulse is generated, and the asynchronous data is sampled using the sampling pulse to obtain sampled data.
2. The method for processing asynchronous data automatic adjustment sampling according to claim 1, characterized in that: Determining whether to accumulate a bit length count of a digital signal duration of the asynchronous data in a bit length counter according to a position of a data edge of the asynchronous data comprises: When the data edge is located within a preset time window or a frame header, the bit length counter is reset to zero; When the data edge is not located within the preset time window or the frame header, the bit length counter is counted and accumulated.
3. The method for processing asynchronous data automatic adjustment sampling according to claim 1, characterized in that: When the bit length counter accumulates to a preset length value, a sampling pulse is generated, and the asynchronous data is sampled using the sampling pulse to obtain sampled data, including: Preset sampling position of sampling pulse; The asynchronous data is sampled using the sampling pulse according to the sampling position to obtain sampled data.
4. The method for processing asynchronous data automatic adjustment sampling according to claim 2, characterized in that: The bit length counter is counted and cleared, further comprising: When the bit length counter accumulates to a preset maximum bit length value, the bit length counter is reset to zero.
5. The method for processing asynchronous data automatic adjustment sampling according to claim 3, characterized in that: According to the sampling position, the asynchronous data is sampled using the sampling pulse to obtain the sampled data, and further comprising: Counting the count value before the bit length counter is cleared; In a cycle of counting the count value, if the count value is outside a preset count value range for a consecutive preset number of times, it is determined that the asynchronous data contains a bit error.
6. The method for processing asynchronous data automatic adjustment sampling according to claim 5, characterized in that: In a counting cycle, if the count value is outside the preset count value range for a continuous preset number of times, after determining that the asynchronous data contains a bit error, the method further includes: The asynchronous data is resampled using the sampling pulse, and when a data edge of the asynchronous data is detected, the bit length count of the bit length counter continues to accumulate until a preset maximum bit length value is reached.
7. The method for processing asynchronous data automatic adjustment sampling according to any one of claims 1 to 6, characterized in that: Before determining whether to accumulate the bit length count of the digital signal duration of the asynchronous data in the bit length counter according to the position of the data edge of the asynchronous data, the method further comprises: Preset glitch threshold; The level signal whose pulse width in the asynchronous data is smaller than the glitch threshold is filtered.
8. The method for processing asynchronous data automatic adjustment sampling according to claim 3, characterized in that: According to the sampling position, the asynchronous data is sampled by using the sampling pulse to obtain the sampled data, and the method further includes: The bit size of the sampled data is determined according to the principle of large numbers.
9. A processing device for automatically adjusting sampling of asynchronous data, characterized in that: include: Get data module, used to get asynchronous data; A determination counter working module, used for determining whether to accumulate the bit length count of the digital signal duration of the asynchronous data in the bit length counter according to the position of the data edge of the asynchronous data; The sampling module is used to generate a sampling pulse when the bit length counter accumulates to a preset length value, and use the sampling pulse to sample the asynchronous data to obtain sampled data.
10. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; Wherein, the processor is configured to implement the processing method for automatically adjusting sampling of asynchronous data as described in any one of claims 1 to 8 when executing the executable instructions.