Signature generation method of physical unclonable function multiplexing LBIST structure

Abstract

The invention discloses a signature generation method for a physical unclonable function (PUF) of a multiplexing LBIST structure. The signature generation method comprises an excitation decoding stage, a capture clock period calibration stage, a response generation stage and a signature correction stage. According to the invention, the PUF circuit can be realized on the basis of not changing the original LBIST main body structure of the circuit, so that enough reliability of the PUF can be ensured while low resource overhead is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of information security, and in particular is a signature generation method of a physical unclonable function PUF of a multiplexed LBIST structure. Background Art

[0002] With the exponential growth of IoT and edge computing devices, the demand for secure identity authentication of hardware devices is becoming increasingly urgent. As a core technology in the field of hardware security, Physical Unclonable Function (PUF) generates a unique "fingerprint" by extracting the inherent process deviations generated during chip manufacturing, and has demonstrated unique advantages in areas such as device authentication and key generation.

[0003] With the exponential growth of IoT devices, PUF technology must not only adapt to the stringent resource constraints of edge devices, but also maintain stable response characteristics under complex working conditions, which poses a double challenge to traditional implementation solutions. In the current mainstream silicon-based PUF implementation solution, the architecture based on SRAM storage units has mature process compatibility, but in order to achieve sufficient entropy sources, a large area of ​​storage arrays needs to be configured, resulting in a simultaneous increase in static power consumption and chip area. The auxiliary calibration circuit introduced to solve the problem of response stability often increases the number of transistors in the overall module by more than 30%, which is particularly inappropriate in scenarios such as resource-constrained sensor nodes. On the other hand, the ring oscillator PUF architecture based on timing competition, although it alleviates the area expansion problem to a certain extent, its response generation process is extremely sensitive to temperature drift and power supply noise, and the bit error rate is high. In order to compensate for the reliability degradation caused by environmental disturbances, the existing solution has to introduce a complex error correction codec module, which not only leads to a step-by-step increase in system power consumption, but also essentially forms a vicious cycle of "reliability improvement depends on additional resource investment". This antagonistic relationship between resource efficiency and reliability has become a key bottleneck restricting the penetration of PUF technology into ultra-low power IoT nodes, especially in industrial sensor networks that require long-term maintenance-free operation. The contradiction between the error accumulation risk and energy consumption budget of the existing architecture during the life cycle is becoming increasingly irreconcilable.

[0004] Therefore, there is an urgent need for a PUF implementation method that can reuse existing hardware resources to reduce overhead and improve reliability through software-hardware co-design. Summary of the invention

[0005] The present invention aims to solve the deficiencies of the above-mentioned prior art and proposes a signature generation method of a physical unclonable function PUF that reuses the LBIST structure, so as to realize a low-overhead PUF circuit without changing the chip circuit to be tested and the scan chain structure, while ensuring the stability of the PUF, thereby effectively improving the overall security of the Internet of Things system and providing support for building a more reliable information infrastructure.

[0006] In order to achieve the above-mentioned purpose, the present invention adopts the following technical scheme:

[0007] The invention discloses a method for generating a signature of a physical unclonable function PUF with a multiplexed LBIST structure. The circuit of the physical unclonable function PUF comprises: a main controller, a compensation circuit, a clock generator, a clock delay line, a clock switching circuit, and a clock shielding circuit; wherein the main controller is composed of an excitation decoding module, a control module, and a calibration module; the clock generator is composed of a module for generating a reference clock. and offset clock The multiplexed LBIST structure comprises: a pseudo-random pattern generator, a circuit to be tested, and a multi-input feature register; wherein the circuit to be tested comprises M scan chains, each scan chain has N triggers, and the signature generation method is performed according to the following steps:

[0008] Step 1: In the excitation decoding stage of the physical unclonable function PUF, the excitation decoding module of the main controller receives an excitation signal Challenge input from the outside, and outputs a seed seed to the pseudo-random pattern generator for initializing its initial state. At the same time, it outputs the capture time CM and the initial feedback coefficient fc of the multi-input feature register to the control module, and sets the excitation decoding completion signal decoder_fin to 1;

[0009] Step 2: During the calibration phase of the physical unclonable function PUF, the control module controls the calibration module to adjust the period T of the capture clock output by the clock switching circuit. capture Perform calibration and generate calibration completion signal adjust_fin;

[0010] Step 3: In the response generation phase of the physical unclonable function PUF, an original response and a redundant response are generated:

[0011] Step 4: In the signature correction stage of the physical unclonable function PUF, the redundant excitation response pair consisting of the excitation signal Challenge and the redundant response is compared with the redundant excitation response pair registered in the server, and the comparison result is used to list the linear equations and then solve them to obtain the trigger of the inversion in the circuit to be tested, which is used to correct the original response and obtain the final signature for the security authentication of the Internet of Things.

[0012] The method for generating a signature of a physical unclonable function PUF of a multiplexed LBIST structure according to the present invention is also characterized in that step 2 comprises:

[0013] Step 2.1: If the control module detects that the excitation decoding completion signal decoder_fin is 1, the delayed reference clock of the clock delay line is initialized. The rising edge count is 0;

[0014] Step 2.2: Delayed Reference Clock of Clock Delay Line When the first rising edge of the clock arrives, the left endpoint left and the right endpoint right of the interval are defined and initialized to 0 and 31 respectively, and an array variable Array_Tcapture

[32] is defined, and the array variable Array_Tcapture

[32] stores the interval values ​​between 90% and 110% of the median of the transient response time of all test paths of the circuit under test;

[0015] The control module controls the offset clock of the clock generator The phase of the clock delay line and the clock path selection signal sel1 are used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2-1];

[0016] The control module stores the initial feedback coefficient fc of the multi-input feature register in the first row Array_c[0] of the feedback coefficient array Array_c[M][N] of the multi-input feature register, and the second row Array_c[1], the third row Array_c[2], the fourth row Array_c[3], ..., the Mth row Array_c[M-1] of the feedback coefficient array Array_c[M][N] store the initial feedback coefficient fc of the multi-input feature register in the first row Array_c[0] of the feedback coefficient array Array_c[M][N] in sequence. , , ,……, ;

[0017] The control module sets the clock switching signal sel2 of the clock switching circuit to 1, so that the global clock CLK switches to the phase-shifted clock , and at the same time, the calibration start signal adjust_flag is set to 1, and the current state of the output signal CCO of the compensation circuit is recorded;

[0018] The excitation decoding module clears the excitation decoding completion signal decoder_fin;

[0019] Step 2.3: Delay the base clock When the second rising edge of the clock arrives, if the calibration module detects that the calibration start signal adjust_flag is 1, the clock enable signal sel3 of the compensation circuit is set to 1 to enable the clock of the compensation circuit; at the same time, the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock At the same time, the calibration start signal adjust_flag is cleared and the offset clock of the clock generator is controlled The phase of the clock path selection signal sel1 is used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2];

[0020] Step 2.4: Delay the base clock When the third clock rising edge arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to disable the clock of the compensation circuit, and the control module sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shifted clock , and record the current state of the output signal CCO of the compensation circuit at the same time. If the current state of the output signal CCO of the compensation circuit is opposite to the previous state, set the output state array variable CCO_state[0] of the compensation circuit to 1; otherwise, set the output state array variable CCO_state[0] of the compensation circuit to 0;

[0021] Step 2.5: Delay the base clock When the fourth clock rising edge arrives, the calibration module sets the clock enable signal sel3 of the compensation circuit to 1 to enable the clock of the compensation circuit. At the same time, the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock. , and controls the offset clock of the clock generator The phase of the clock path selection signal sel1 is used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2+1];

[0022] Step 2.6: Delay the base clock When the fifth clock rising edge arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to disable the clock of the compensation circuit, and the control module sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shifted clock , and record the current state of the output signal CCO of the compensation circuit at the same time. If the current state of the output signal CCO of the compensation circuit is opposite to the previous state, set the output state array variable CCO_state[1] of the compensation circuit to 1; otherwise, set the output state array variable CCO_state[1] of the compensation circuit to 0;

[0023] Step 2.7: Delay the Base Clock When the sixth clock rising edge arrives, the calibration module sets the compensation circuit clock enable signal sel3 to 1 to enable the clock of the compensation circuit, and the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock ;

[0024] Step 2.8: Delay the base clock When the 7th rising edge of the clock arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to disable the clock of the compensation circuit. At the same time, if the output state array variable CCO_state[0] of the compensation circuit is 1 and CCO_state[1] is 1, the calibration module sets the calibration completion signal adjust_fin to 3; if the output state array variable CCO_state[0] of the compensation circuit is 0, CCO_state[1] is 0 and the current state of the output signal CCO of the compensation circuit is opposite to the previous clock state, the calibration module sets the calibration completion signal adjust_fin to 3; otherwise, the calibration module sets the calibration completion signal adjust_fin to 2 CCO_state[0] ;

[0025] Step 2.9: Delay the base clock When the 8th clock rising edge arrives, if the calibration completion signal adjust_fin is 3, the control module sets the left endpoint left and the right endpoint right of the interval to 0 and 31 respectively. At the same time, the calibration module clears the output state array variables CCO_state[0] and CCO_state[1] of the compensation circuit and the calibration completion signal adjust_fin, and then executes step 3.

[0026] If the calibration completion signal adjust_fin is 2, the control module sets the left endpoint of the interval left to (left+right) / 2, and controls the offset clock of the clock generator The phase of the clock path selection signal sel1 is used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2-1], and the clock switching signal sel2 is set to 1, so that the global clock CLK switches to the phase-shifted clock At the same time, the calibration module clears the output state array variables CCO_state[0], CCO_state[1] of the compensation circuit and the calibration completion signal adjust_fin, and initializes the delayed reference clock of the clock delay line After the rising edge count is 0, return to step 2.3 and execute sequentially;

[0027] If the calibration completion signal adjust_fin is 1, the control module sets the right endpoint of the interval right to (left+right) / 2, and controls the offset clock of the clock generator The phase of the clock path selection signal sel1 is used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2-1], and the clock switching signal sel2 is set to 1, so that the global clock CLK switches to the phase-shifted clock At the same time, the calibration module clears the output state array variables CCO_state[0], CCO_state[1] of the compensation circuit and the calibration completion signal adjust_fin, and initializes the delayed reference clock of the clock delay line After the rising edge count reaches 0, the process returns to step 2.3 and executes sequentially.

[0028] Furthermore, the step 3 comprises:

[0029] Step 3.1: The number of generated responses cnt of the physical unclonable function PUF, the row index c_index of the feedback coefficient array Array_c[M][N] and the delay reference clock of the clock delay line are The number of rising edges is initialized to 0;

[0030] Step 3.2: Delay the base clock When the first rising edge of the clock arrives, the control module clears the reset signal rst_prpg of the pseudo-random pattern generator to prevent the trigger in the pseudo-random pattern generator from being reset all the time;

[0031] Step 3.3: Delay the base clock When the CMth clock rising edge arrives, if the generated response number cnt is 0, the control module sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shifted clock , and set the clock enable signal sel4 of the clock shielding circuit to 1 to disable the clock of the multi-input feature register, and clear the scan enable signal SCAN_EN of the multiplexed LBIST structure to zero, so that the scan chain works in the functional mode;

[0032] If the number of generated responses cnt is not 0, the control module sets the reset signal rst_misr of the multi-input feature register to 1, which is used to reset the trigger in the multi-input feature register, and sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shifted clock , setting the clock enable signal sel4 of the clock shielding circuit to 1 to disable the clock of the multi-input feature register, and clearing the scan enable signal SCAN_EN to zero, so that the scan chain works in the functional mode;

[0033] Step 3.4: Delay the base clock When the falling edge of arrives, the control module sets the scan enable signal SCAN_EN to 1, so that the scan chain works in the scan mode;

[0034] Step 3.5: Delay the Base Clock When the CM+1th clock rising edge arrives, the control module clears the reset signal rst_misr of the multi-input feature register to prevent the flip-flops in the multi-input feature register from being reset all the time, and clears the clock switching signal sel2 to switch the global clock CLK to the original clock , clear the clock enable signal sel4 to enable the clock of the multi-input feature register. At the same time, if the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register starts to output the first bit of the redundant response and When the next rising edge of the clock arrives, the next bit of the redundant response is output in sequence until the M-1 bit of the redundant response is output;

[0035] Step 3.6: Delay the Base Clock When the CM+Mth clock rising edge arrives, if the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register starts to output the Mth bit of the redundant response and When the next rising edge of the clock arrives, the next bit of the redundant response is output in sequence until the M+N-2 bits of the redundant response are output;

[0036] If the number of generated responses cnt is 0, the output terminal OUT of the multi-input characteristic register starts to output the first bit of the original response and When the next rising edge of the clock arrives, the next bit of the original response is output in sequence until the N-1 bit of the original response is output;

[0037] Step 3.7: Delay the Base Clock When the CM+M+N-1th clock rising edge arrives, if the number of generated responses cnt is 0, the output terminal OUT of the multi-input feature register outputs the Nth bit of the original response, that is, the last bit;

[0038] If the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register outputs the M+N-1th bit, i.e., the last bit, of the redundant response;

[0039] If the number of generated responses cnt is equal to M, the control module clears the number of generated responses cnt to zero and sets the completion signal finish to 1, and delays the reference clock When the CM+M+Nth clock rising edge arrives, the control module clears the completion signal finish and executes step 4;

[0040] If the number of generated responses cnt is less than M, the controller adds 1 to the number of generated responses cnt and sets the reset signal rst_prpg of the pseudo-random pattern generator to 1 to reset the trigger in the pseudo-random pattern generator, and sets the row index c_index of the feedback coefficient array Array_c[M][N] to , and initialize the delayed reference clock of the clock delay line After the rising count reaches 0, the sequence returns to step 3.2.

[0041] An electronic device of the present invention includes a memory and a processor, wherein the memory is used to store a program that supports the processor to execute the signature generation method, and the processor is configured to execute the program stored in the memory.

[0042] The present invention provides a computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and the computer program executes the steps of the signature generation method when the computer program is executed by a processor.

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] 1. The present invention reuses the structure of LBIST without affecting the normal operation of LBIST. While achieving low resource overhead, there are many stimulus-response pairs, which significantly reduces the hardware cost of resource-sensitive devices such as the Internet of Things and edge computing.

[0045] 2. The present invention first uses a compensation circuit to calibrate the capture clock period, and then uses a signature correction algorithm to reduce the error when capturing transient response, thereby improving the reliability of PUF and ensuring the security of the Internet of Things.

[0046] 3. The present invention uses a high-frequency adjustable clock to capture the transient response in the circuit to be tested, forming the original "fingerprint" of the chip, which is easy to integrate into the existing system and has high compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a structural diagram of the overall framework of the present invention;

[0048] Figure 2 This is an interface diagram of the main controller of the present invention;

[0049] Figure 3 is a structural diagram of a clock circuit of the present invention;

[0050] Figure 4 is a structural diagram of the compensation circuit of the present invention;

[0051] Figure 5 is a schematic diagram of a test path structure in a circuit to be tested of the present invention;

[0052] Figure 6 It is a structural diagram of the multi-input feature register of the present invention. DETAILED DESCRIPTION

[0053] In this embodiment, a signature generation method of a physical unclonable function PUF of a multiplexed LBIST structure is provided. Figure 1 As shown, it is characterized in that the circuit of the physical unclonable function PUF includes: a main controller, a compensation circuit, a clock generator, a clock delay line, a clock switching circuit, and a clock shielding circuit; wherein, Figure 2 As shown, the main controller consists of an excitation decoding module, a control module and a calibration module; Figure 3 As shown, the clock generator consists of a clock that can generate a reference clock and offset clock The phase-locked loop is composed of Figure 1 As shown, the multiplexed LBIST structure includes: a pseudo-random pattern generator, a circuit to be tested, and a multi-input signature register; wherein the circuit to be tested includes M scan chains, each scan chain has N triggers, and the signature generation method is performed in the following steps:

[0054] Step 1: In the excitation decoding stage of the physical unclonable function PUF, the excitation decoding module of the main controller receives the external input excitation signal Challenge and outputs the seed seed to the pseudo-random pattern generator to initialize its initial state. At the same time, it outputs the capture moment CM and the initial feedback coefficient fc of the multi-input feature register to the control module, and sets the excitation decoding completion signal decoder_fin to 1.

[0055] Step 2: During the calibration phase of the physical unclonable function PUF, the control module controls the calibration module to adjust the period T of the capture clock output by the clock switching circuit. capture For calibration, the physical unclonable function PUF generates a response by capturing the transient response in the circuit under test, so the capture clock period T captureThe relative relationship between the capture clock period T and the transient response time determines the response result. However, changes in voltage and temperature can significantly change the delay of units or interconnects in the circuit, thereby affecting the transient response time. Therefore, in order to obtain stable results, it is necessary to capture the clock period T capture The basic principle of calibration is to make the capture clock period T capture Approximately equal to the total delay of the calibration circuit delay = t clk-to-q +d invs +t setup ,like Figure 4 As shown, t clk-to-q is the clk-to-q delay of the trigger, d invs is the delay of the inverter chain, t setup is the setup time of the trigger. The total delay of the calibration circuit is approximately equal to the average transient response time of the circuit under test. When the voltage and temperature change, the total delay of the calibration circuit will change synchronously with the average transient response time of the circuit under test. The compensation circuit is used to calibrate the capture clock period T capture After that, the capture clock period T capture Always approximately equal to the average transient response time of the circuit under test:

[0056] Step 2.1: If the control module detects that the excitation decoding completion signal decoder_fin is 1, the delayed reference clock of the clock delay line is initialized. The rising edge count is 0;

[0057] Step 2.2: Delayed Reference Clock of Clock Delay Line When the first rising edge of the clock arrives, the left endpoint left and the right endpoint right of the interval are defined and initialized to 0 and 31 respectively, and the array variable Array_Tcapture

[32] is defined, and the array variable Array_Tcapture

[32] stores the interval values ​​between 90% and 110% of the median of the transient response time of all test paths of the circuit to be tested, such as Figure 5 As shown, the transient response time of the test path is the time it takes for the clock signal to pass through the first trigger, then pass through the test path, and finally reach the input of the second trigger.

[0058] The control module controls the offset clock of the clock generator The phase of the clock delay line and the clock path selection signal sel1 are used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2-1];

[0059] The control module stores the initial feedback coefficient fc of the multi-input feature register in the first row Array_c[0] of the feedback coefficient array Array_c[M][N] of the multi-input feature register, and the second row Array_c[1], the third row Array_c[2], the fourth row Array_c[3], ..., the Mth row Array_c[M-1] of the feedback coefficient array Array_c[M][N] store the initial feedback coefficient fc of the multi-input feature register in the first row Array_c[0] of the feedback coefficient array Array_c[M][N] in sequence. , , ,……, ;

[0060] The control module sets the clock switching signal sel2 of the clock switching circuit to 1, so that the global clock CLK switches to the phase-shifted clock , and at the same time, the calibration start signal adjust_flag is set to 1, and the current state of the output signal CCO of the compensation circuit is recorded;

[0061] The excitation decoding module clears the excitation decoding completion signal decoder_fin.

[0062] Step 2.3: Delay the base clock When the second rising edge of the clock arrives, if the calibration module detects that the calibration start signal adjust_flag is 1, the clock enable signal sel3 of the compensation circuit is set to 1 to enable the clock of the compensation circuit; at the same time, the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock At the same time, the calibration start signal adjust_flag is cleared and the offset clock of the clock generator is controlled The phase and clock path selection signal sel1 is used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2].

[0063] Step 2.4: Delay the base clock When the third clock rising edge arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to disable the clock of the compensation circuit, and the control module sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shifted clock , and record the current state of the output signal CCO of the compensation circuit. If the current state of the output signal CCO of the compensation circuit is opposite to the previous state, set the output state array variable CCO_state[0] of the compensation circuit to 1; otherwise, set the output state array variable CCO_state[0] of the compensation circuit to 0. The output state of the compensation circuit satisfies the following relationship (1):

[0064] (1)

[0065] In formula (1), t clk-to-q is the clk-to-q delay of the trigger, d invs is the delay of the inverter chain, t setup is the setup time of the trigger, t hold is the hold time of the trigger.

[0066] Step 2.5: Delay the base clock When the fourth clock rising edge arrives, the calibration module sets the clock enable signal sel3 of the compensation circuit to 1 to enable the clock of the compensation circuit. At the same time, the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock. , and controls the offset clock of the clock generator The phase and clock path selection signal sel1 is used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2+1];

[0067] Step 2.6: Delay the base clock When the fifth clock rising edge arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to disable the clock of the compensation circuit, and the control module sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shifted clock , and record the current state of the output signal CCO of the compensation circuit at the same time. If the current state of the output signal CCO of the compensation circuit is opposite to the previous state, set the output state array variable CCO_state[1] of the compensation circuit to 1; otherwise, set the output state array variable CCO_state[1] of the compensation circuit to 0.

[0068] Step 2.7: Delay the Base Clock When the sixth clock rising edge arrives, the calibration module sets the compensation circuit clock enable signal sel3 to 1 to enable the clock of the compensation circuit, and the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock ;

[0069] Step 2.8: Delay the base clock When the 7th rising edge of the clock arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to disable the clock of the compensation circuit. At the same time, if the output state array variable CCO_state[0] of the compensation circuit is 1 and CCO_state[1] is 1, the calibration module sets the calibration completion signal adjust_fin to 3. At this time, the current state of the output signal CCO of the compensation circuit recorded twice before is opposite to the previous state, indicating that the reference clock is delayed. The second clock adjusts the capture clock period T capture Before capture < t clk-to-q +d invs -t hold , in the delayed reference clock The second clock adjusts the capture clock period T capture After T capture > t clk-to-q +d invs +t setup ; If the output state array variables CCO_state[0]=0, CCO_state[1]=0 of the compensation circuit and the current state of the output signal CCO of the compensation circuit is opposite to the previous clock state, the calibration module sets the calibration completion signal adjust_fin to 3. At this time, the current state of the output signal CCO of the compensation circuit recorded twice before and the previous state are opposite, opposite, and the reference clock is delayed. At the 7th clock of the compensation circuit, the current state of the output signal CCO is opposite to the previous state, indicating that the reference clock is delayed. The fourth clock adjusts the capture clock period T capture Before capture <t clk-to-q +d invs -t hold , in the delayed reference clock The fourth clock adjusts the capture clock period T capture After T capture >t clk-to-q +d invs +t setup ; Otherwise, the calibration module sets the calibration completion signal adjust_fin to 2 CCO_state[0] When CCO_state[0]=0, it indicates the capture clock period T capture Too large, need to further reduce the capture clock period T capture ; When CCO_state[0]=1, it indicates the capture clock period T capture Too small, need to further increase the capture clock period T capture .

[0070] Step 2.9: Delay the base clock When the 8th clock rising edge arrives, if the calibration completion signal adjust_fin is 3, the control module sets the left endpoint left and the right endpoint right of the interval to 0 and 31 respectively. At the same time, the calibration module clears the output state array variables CCO_state[0] and CCO_state[1] of the compensation circuit and the calibration completion signal adjust_fin, and then executes step 3.

[0071] If the calibration completion signal adjust_fin is 2, the control module sets the left endpoint of the interval to (left+right) / 2, narrows the interval range to the right half, and controls the offset clock of the clock generator. The phase and clock path selection signal sel1 is used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2-1], and the clock switching signal sel2 is set to 1, so that the global clock CLK switches to the phase-shifted clock At the same time, the calibration module clears the output state array variables CCO_state[0] and CCO_state[1] of the compensation circuit and the calibration completion signal adjust_fin, and initializes the delayed reference clock of the clock delay line. After the rising edge count is 0, return to step 2.3 and execute sequentially;

[0072] If the calibration completion signal adjust_fin is 1, the control module sets the right endpoint of the interval right to (left+right) / 2, narrows the interval range to the left half, and controls the offset clock of the clock generator at the same time. The phase and clock path selection signal sel1 is used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2-1], and the clock switching signal sel2 is set to 1, so that the global clock CLK switches to the phase-shifted clock At the same time, the calibration module clears the output state array variables CCO_state[0] and CCO_state[1] of the compensation circuit and the calibration completion signal adjust_fin, and initializes the delayed reference clock of the clock delay line. After the rising edge count reaches 0, the process returns to step 2.3 and executes sequentially.

[0073] Step 3: In the response generation phase of the physical unclonable function PUF, the original response and redundant response are generated. This phase will generate 1 original response and M redundant responses:

[0074] Step 3.1: The number of generated responses cnt of the physical unclonable function PUF, the row index c_index of the feedback coefficient array Array_c[M][N], and the delay reference clock of the clock delay line are The number of rising edges is initialized to 0;

[0075] Step 3.2: Delay the base clock When the first rising edge of the clock arrives, the control module clears the reset signal rst_prpg of the pseudo-random pattern generator to prevent the trigger in the pseudo-random pattern generator from being reset all the time.

[0076] Step 3.3: Delay the base clock When the CMth clock rising edge arrives, if the number of generated responses cnt is 0, the control module sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shifted clock , and set the clock enable signal sel4 of the clock shielding circuit to 1 to disable the clock of the multi-input feature register, and clear the scan enable signal SCAN_EN of the multiplexed LBIST structure to zero, so that the scan chain works in the functional mode;

[0077] If the number of generated responses cnt is not 0, the control module sets the reset signal rst_misr of the multi-input feature register to 1 to reset the flip-flop in the multi-input feature register and sets the clock switching signal sel2 to 1 so that the global clock CLK switches to the phase-shifted clock , set the clock enable signal sel4 of the clock shielding circuit to 1 to disable the clock of the multi-input feature register, and clear the scan enable signal SCAN_EN to zero, so that the scan chain works in the functional mode;

[0078] Step 3.4: Delay the base clock When the falling edge of arrives, the control module sets the scan enable signal SCAN_EN to 1, so that the scan chain works in the scan mode.

[0079] Step 3.5: Delay the Base Clock When the CM+1th clock rising edge arrives, the control module clears the reset signal rst_misr of the multi-input feature register to prevent the flip-flops in the multi-input feature register from being reset all the time, and clears the clock switching signal sel2 to switch the global clock CLK to the original clock , clear the clock enable signal sel4 to enable the clock of the multi-input feature register. At the same time, if the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register starts to output the first bit of the redundant response and When the next rising edge of the clock arrives, the next bit of the redundant response is output in sequence until the M-1 bit of the redundant response is output;

[0080] Step 3.6: Delay the Base Clock When the CM+Mth clock rising edge arrives, if the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register starts to output the Mth bit of the redundant response and When the next rising edge of the clock arrives, the next bit of the redundant response is output in sequence until the M+N-2 bits of the redundant response are output;

[0081] If the number of generated responses cnt is 0, the output terminal OUT of the multi-input characteristic register starts to output the first bit of the original response and When the next clock rising edge arrives, the next bit of the original response is output in sequence until the N-1 bit of the original response is output. The structure of the multi-input feature register is as follows: Figure 6 As shown, where c0, c1, …, c m-1 (c m-1 =1) is the feedback coefficient of the multi-input feature register, M bits of data are input in parallel in each cycle, and the state transfer equation of the scan trigger is formula (2):

[0082] (2)

[0083] In formula (2), Y(L) is the state vector of the trigger at the Lth clock cycle, Y(0) is the initial state vector of the trigger, A is the transformation matrix, and D i is the M-bit vector input to the trigger in the i-th cycle, then in the first M clock cycles, the output of the multi-input feature register is formula (3):

[0084] (3)

[0085] It can be noted from equation (3) that in the first M-1 clock cycles, the output does not depend on the feedback coefficient. Therefore, if the first M-1 bits of the output are retained, this part of the original response can be easily predicted by the attacker. To avoid this, the first bit of the original response is delayed from the reference clock The first bit of the redundant response starts from the rising edge of the CM+Mth clock. For the redundant response, since it does not involve the problem of leaking the original response, there is no need to remove the first M-1 bits. The first bit of the redundant response starts from the delayed reference clock It starts with the rising edge of the CM+1th clock.

[0086] Step 3.7: Delay the Base Clock When the CM+M+N-1th clock rising edge arrives, if the number of generated responses cnt is 0, the output terminal OUT of the multi-input feature register outputs the Nth bit of the original response, that is, the last bit;

[0087] If the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register outputs the M+N-1th bit, i.e., the last bit, of the redundant response;

[0088] If the number of generated responses cnt is equal to M, the control module clears the number of generated responses cnt to zero and sets the completion signal finish to 1, and delays the reference clock When the CM+M+Nth clock rising edge arrives, the control module clears the completion signal finish and executes step 4;

[0089] If the number of generated responses cnt is less than M, the controller adds 1 to the number of generated responses cnt and sets the reset signal rst_prpg of the pseudo-random pattern generator to 1 to reset the trigger in the pseudo-random pattern generator, and sets the row index c_index of the feedback coefficient array Array_c[M][N] to , and initialize the delayed reference clock of the clock delay line After the rising count reaches 0, the sequence returns to step 3.2.

[0090] Step 4: In the signature correction phase of the physical unclonable function PUF, the redundant excitation response pair consisting of the excitation signal Challenge and the redundant response is compared with the redundant excitation response pair registered in the server, and the comparison result is used to list the linear equation group and then solve it, because the multi-input feature register is reset before generating the redundant response in step 3.5. Combined with formula (3), it can be seen that the first M bits of the M redundant responses are the same, so there are M*(M+N-1)-M*(M-1)=MN valid equations in this linear equation group, and the number of scan triggers is MN, so the number of unknowns is also MN, so the equation group has and has a unique solution, and the flip-flop that is reversed in the circuit to be tested is obtained, which is used to correct the original response and obtain the final signature for the security authentication of the Internet of Things. The redundant excitation response pair registered in the server refers to the redundant excitation response pair generated by the physical unclonable function PUF at room temperature, standard atmospheric pressure and standard voltage and stored in the server.

[0091] In this embodiment, an electronic device includes a memory and a processor, wherein the memory is used to store a program that supports the processor to execute the above method, and the processor is configured to execute the program stored in the memory.

[0092] In this embodiment, a computer-readable storage medium stores a computer program on the computer-readable storage medium, and the computer program executes the steps of the above method when executed by a processor.

Claims

1. A method for generating a signature of a physical unclonable function PUF of a multiplexed LBIST structure, characterized in that: The circuit of the physical unclonable function PUF includes: a main controller, a compensation circuit, a clock generator, a clock delay line, a clock switching circuit, and a clock shielding circuit; wherein the main controller is composed of an excitation decoding module, a control module, and a calibration module; the clock generator is composed of a module for generating a reference clock. and offset clock The multiplexed LBIST structure comprises: a pseudo-random pattern generator, a circuit to be tested, and a multi-input feature register; wherein the circuit to be tested comprises M scan chains, each scan chain has N triggers, and the signature generation method is performed according to the following steps: Step 1: In the excitation decoding stage of the physical unclonable function PUF, the excitation decoding module of the main controller receives an excitation signal Challenge input from the outside, and outputs a seed seed to the pseudo-random pattern generator for initializing its initial state. At the same time, it outputs the capture time CM and the initial feedback coefficient fc of the multi-input feature register to the control module, and sets the excitation decoding completion signal decoder_fin to 1; Step 2: During the calibration phase of the physical unclonable function PUF, the control module controls the calibration module to adjust the period T of the capture clock output by the clock switching circuit. capture Perform calibration and generate calibration completion signal adjust_fin; Step 3: In the response generation phase of the physical unclonable function PUF, an original response and a redundant response are generated: Step 4: In the signature correction stage of the physical unclonable function PUF, the redundant excitation response pair consisting of the excitation signal Challenge and the redundant response is compared with the redundant excitation response pair registered in the server, and the comparison result is used to list the linear equations and then solve them to obtain the trigger of the inversion in the circuit to be tested, which is used to correct the original response and obtain the final signature for the security authentication of the Internet of Things.

2. The method for generating a signature of a physical unclonable function PUF of a multiplexing LBIST structure according to claim 1, wherein: The step 2 comprises: Step 2.1: If the control module detects that the excitation decoding completion signal decoder_fin is 1, the delayed reference clock of the clock delay line is initialized. The rising edge count is 0; Step 2.2: Delaying the Reference Clock with the Clock Delay Line When the first rising edge of the clock arrives, the left endpoint left and the right endpoint right of the interval are defined and initialized to 0 and 31 respectively, and an array variable Array_Tcapture[32] is defined, and the array variable Array_Tcapture[32] stores the interval values ​​between 90% and 110% of the median of the transient response time of all test paths of the circuit under test; The control module controls the offset clock of the clock generator The phase of the clock delay line and the clock path selection signal sel1 are used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2-1]; The control module stores the initial feedback coefficient fc of the multi-input feature register in the first row Array_c[0] of the feedback coefficient array Array_c[M][N] of the multi-input feature register, and the second row Array_c[1], the third row Array_c[2], the fourth row Array_c[3], ..., the Mth row Array_c[M-1] of the feedback coefficient array Array_c[M][N] store the initial feedback coefficient fc of the multi-input feature register in the first row Array_c[0] of the feedback coefficient array Array_c[M][N] in sequence. , , ,……, ; The control module sets the clock switching signal sel2 of the clock switching circuit to 1, so that the global clock CLK switches to the phase-shifted clock , and at the same time, the calibration start signal adjust_flag is set to 1, and the current state of the output signal CCO of the compensation circuit is recorded; The excitation decoding module clears the excitation decoding completion signal decoder_fin; Step 2.3: Delay the base clock When the second rising edge of the clock arrives, if the calibration module detects that the calibration start signal adjust_flag is 1, the clock enable signal sel3 of the compensation circuit is set to 1 to enable the clock of the compensation circuit; at the same time, the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock At the same time, the calibration start signal adjust_flag is cleared and the offset clock of the clock generator is controlled The phase of the clock path selection signal sel1 is used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2]; Step 2.4: Delay the base clock When the third clock rising edge arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to disable the clock of the compensation circuit, and the control module sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shifted clock , and record the current state of the output signal CCO of the compensation circuit at the same time. If the current state of the output signal CCO of the compensation circuit is opposite to the previous state, set the output state array variable CCO_state[0] of the compensation circuit to 1; otherwise, set the output state array variable CCO_state[0] of the compensation circuit to 0; Step 2.5: Delay the base clock When the fourth clock rising edge arrives, the calibration module sets the clock enable signal sel3 of the compensation circuit to 1 to enable the clock of the compensation circuit. At the same time, the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock. , and controls the offset clock of the clock generator The phase of the clock path selection signal sel1 is used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2+1]; Step 2.6: Delay the base clock When the fifth clock rising edge arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to disable the clock of the compensation circuit, and the control module sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shifted clock , and record the current state of the output signal CCO of the compensation circuit at the same time. If the current state of the output signal CCO of the compensation circuit is opposite to the previous state, set the output state array variable CCO_state[1] of the compensation circuit to 1; otherwise, set the output state array variable CCO_state[1] of the compensation circuit to 0; Step 2.7: Delay the Base Clock When the sixth clock rising edge arrives, the calibration module sets the compensation circuit clock enable signal sel3 to 1 to enable the clock of the compensation circuit, and the control module clears the clock switching signal sel2 to zero, so that the global clock CLK switches to the original clock ; Step 2.8: Delay the base clock When the 7th rising edge of the clock arrives, the calibration module clears the clock enable signal sel3 of the compensation circuit to disable the clock of the compensation circuit. At the same time, if the output state array variable CCO_state[0] of the compensation circuit is 1 and CCO_state[1] is 1, the calibration module sets the calibration completion signal adjust_fin to 3; if the output state array variable CCO_state[0] of the compensation circuit is 0, CCO_state[1] is 0 and the current state of the output signal CCO of the compensation circuit is opposite to the previous clock state, the calibration module sets the calibration completion signal adjust_fin to 3; otherwise, the calibration module sets the calibration completion signal adjust_fin to 2 CCO_state[0] ; Step 2.9: Delay the base clock When the 8th clock rising edge arrives, if the calibration completion signal adjust_fin is 3, the control module sets the left endpoint left and the right endpoint right of the interval to 0 and 31 respectively. At the same time, the calibration module clears the output state array variables CCO_state[0] and CCO_state[1] of the compensation circuit and the calibration completion signal adjust_fin, and then executes step 3. If the calibration completion signal adjust_fin is 2, the control module sets the left endpoint of the interval left to (left+right) / 2, and controls the offset clock of the clock generator The phase of the clock path selection signal sel1 is used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2-1], and the clock switching signal sel2 is set to 1, so that the global clock CLK switches to the phase-shifted clock At the same time, the calibration module clears the output state array variables CCO_state[0], CCO_state[1] of the compensation circuit and the calibration completion signal adjust_fin, and initializes the delayed reference clock of the clock delay line After the rising edge count is 0, return to step 2.3 and execute sequentially; If the calibration completion signal adjust_fin is 1, the control module sets the right endpoint of the interval right to (left+right) / 2, and controls the offset clock of the clock generator The phase of the clock path selection signal sel1 is used to change the capture clock period T capture The value of is Array_Tcapture[(left+right) / 2-1], and the clock switching signal sel2 is set to 1, so that the global clock CLK switches to the phase-shifted clock At the same time, the calibration module clears the output state array variables CCO_state[0], CCO_state[1] of the compensation circuit and the calibration completion signal adjust_fin, and initializes the delayed reference clock of the clock delay line After the rising edge count reaches 0, the process returns to step 2.3 and executes sequentially.

3. The signature generation method of a physical unclonable function PUF of a multiplexing LBIST structure according to claim 2, characterized in that, The step 3 comprises: Step 3.1: The number of generated responses cnt of the physical unclonable function PUF, the row index c_index of the feedback coefficient array Array_c[M][N] and the delay reference clock of the clock delay line are The number of rising edges is initialized to 0; Step 3.2: Delay the base clock When the first rising edge of the clock arrives, the control module clears the reset signal rst_prpg of the pseudo-random pattern generator to prevent the trigger in the pseudo-random pattern generator from being reset all the time; Step 3.3: Delay the base clock When the CMth clock rising edge arrives, if the generated response number cnt is 0, the control module sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shifted clock , and set the clock enable signal sel4 of the clock shielding circuit to 1 to disable the clock of the multi-input feature register, and clear the scan enable signal SCAN_EN of the multiplexed LBIST structure to zero, so that the scan chain works in the functional mode; If the number of generated responses cnt is not 0, the control module sets the reset signal rst_misr of the multi-input feature register to 1, which is used to reset the trigger in the multi-input feature register, and sets the clock switching signal sel2 to 1, so that the global clock CLK switches to the phase-shifted clock , setting the clock enable signal sel4 of the clock shielding circuit to 1 to disable the clock of the multi-input feature register, and clearing the scan enable signal SCAN_EN to zero, so that the scan chain works in the functional mode; Step 3.4: Delay the base clock When the falling edge of arrives, the control module sets the scan enable signal SCAN_EN to 1, so that the scan chain works in the scan mode; Step 3.5: Delay the Base Clock When the CM+1th clock rising edge arrives, the control module clears the reset signal rst_misr of the multi-input feature register to prevent the flip-flops in the multi-input feature register from being reset all the time, and clears the clock switching signal sel2 to switch the global clock CLK to the original clock , clear the clock enable signal sel4 to enable the clock of the multi-input feature register. At the same time, if the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register starts to output the first bit of the redundant response and When the next rising edge of the clock arrives, the next bit of the redundant response is output in sequence until the M-1 bit of the redundant response is output; Step 3.6: Delay the Base Clock When the CM+Mth clock rising edge arrives, if the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register starts to output the Mth bit of the redundant response and When the next rising edge of the clock arrives, the next bit of the redundant response is output in sequence until the M+N-2 bits of the redundant response are output; If the number of generated responses cnt is 0, the output terminal OUT of the multi-input characteristic register starts to output the first bit of the original response and When the next rising edge of the clock arrives, the next bit of the original response is output in sequence until the N-1 bit of the original response is output; Step 3.7: Delay the Base Clock When the CM+M+N-1th clock rising edge arrives, if the number of generated responses cnt is 0, the output terminal OUT of the multi-input feature register outputs the Nth bit of the original response, that is, the last bit; If the number of generated responses cnt is greater than 0, the output terminal OUT of the multi-input feature register outputs the M+N-1th bit, i.e., the last bit, of the redundant response; If the number of generated responses cnt is equal to M, the control module clears the number of generated responses cnt to zero and sets the completion signal finish to 1, and delays the reference clock When the CM+M+Nth clock rising edge arrives, the control module clears the completion signal finish and executes step 4; If the number of generated responses cnt is less than M, the controller adds 1 to the number of generated responses cnt and sets the reset signal rst_prpg of the pseudo-random pattern generator to 1 to reset the trigger in the pseudo-random pattern generator, and sets the row index c_index of the feedback coefficient array Array_c[M][N] to , and initialize the delayed reference clock of the clock delay line After the rising count reaches 0, the sequence returns to step 3.

2.

4. An electronic device, comprising a memory and a processor, characterized in that: The memory is used to store a program that supports the processor to execute the signature generation method described in any one of claims 1 to 3, and the processor is configured to execute the program stored in the memory.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the signature generation method according to any one of claims 1 to 3 are executed.

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