Implementation method for configurable LVDS double-packet transmission high-reliability communication protocol based on FPGA

Abstract

The technical scheme of the invention provides a method for realizing a configurable LVDS (Low Voltage Differential Signaling) double-packet transmission high-reliability communication protocol based on an FPGA (Field Programmable Gate Array). According to the invention, a set of configurable double-packet transmission multi-check communication protocol is formulated for LVDS communication based on the FPGA. According to the method, address allocation and data length can be configured through a register according to the actual data packet size, operation is easy and convenient, flexibility is high, meanwhile, double-packet sending is conducted on the data packets, odd verification operation is conducted in the sending process of each packet, and communication reliability is improved through double redundancy.

Description

Technical Field

[0001] The invention relates to a method for realizing a low voltage differential signal (LVDS) communication protocol based on a field programmable gate array (FPGA), which is widely used in the field of aerospace. Background Art

[0002] Low Voltage Differential Signaling (LVDS) uses a relatively low voltage to achieve data transmission. It is a differential signal technology with the characteristics of low power consumption, low bit error rate, low crosstalk, low jitter, and low radiation. It has good signal integrity, so LVDS communication is widely used in video transmission, long-distance transmission, aerospace and other fields. LVDS communication technology based on field programmable gate array (FPGA) is flexible in design and widely used in various fields.

[0003] LVDS communication has mature and fixed general protocols in the field of video transmission, such as single 6-bit LVDS output interface, dual 6-bit LVDS output interface, single 8-bit LVDS output interface, and dual 8-bit LVDS output interface. However, in the aerospace field, LVDS communication uses a pair of differential signals for data transmission. Although LVDS communication has been widely used, there is no unified and reliable solution for the data format in the communication process.

[0004] When different devices communicate, due to the inconsistency of communication formats, the accuracy of sending data packets needs to rely on the upper-layer software, and the data of both parties needs to be processed independently to meet the LVDS communication requirements of different devices. The reliability is greatly reduced, and the resources required for additional processing during the communication process are greatly increased. The different meanings in the LVDS communication protocol, such as the number of data packet transmissions and the verification method, will also affect the reliability and security of the data during the entire communication process. For example, if only a single packet of data is sent during communication and only one data verification is performed, the probability of data transmission errors will be greatly increased. Although sending more than 3 data packets improves the reliability of the data, it causes a lot of waste of resources and makes the entire communication process too lengthy. Therefore, it is extremely universal and applicable to develop a set of highly stable and reliable LVDS communication protocols that can be flexibly configured according to the equipment. Summary of the invention

[0005] The purpose of the present invention is to solve the problems existing in the LVDS communication process in the aerospace field pointed out in the background technology.

[0006] In order to achieve the above object, the technical solution of the present invention is to provide a method for implementing a high-reliability communication protocol based on FPGA-configurable LVDS double-packet transmission, characterized in that the LVDS communication format bit sequence used in the communication protocol is shown in the following table:

[0007]

[0008]

[0009] 1) Data transmission rules: send the data control word first, then the data segment; send the low bit first, and the last data first.

[0010] 2) The sending time is (56+2n*16)*20ns, where n is the number of data sent;

[0011] 3) LVDS communication content: send the packet data sequence number, data ID information, valid data, and check bit in sequence; a single packet of data is sent twice in succession, and the transmission frequency is 50MHz;

[0012] 4) Odd check: odd check is performed on the packet sequence number, control register information, and data segment;

[0013] 5) Continuous transmission: A single packet can send up to 32 data continuously, and the control register determines the starting address and the length of the continuously transmitted data.

[0014] Preferably, the data ID information includes a base address and data length.

[0015] Preferably, the receiving frequency is 200 MHz, and the second beat is sampled in every four beats during LVDS reception.

[0016] Preferably, receiving voting: voting is performed based on the verification status of the received data. If the verification of the first received data is correct, the first received data is stored in DRAM; if the verification of the first received data is incorrect, a second received data judgment is performed; if the second data verification is correct, the second data is stored in DRAM; if the second data is incorrect, the data received for both times is not stored in DRAM.

[0017] The present invention develops a set of configurable dual-packet transmission and multiple-check communication protocols for LVDS communication based on FPGA. The present invention can not only configure the address allocation and data length through registers according to the actual data packet size, but also has simple operation and high flexibility. At the same time, the data packet is sent in dual packets, and an odd check operation is performed during the transmission of each packet, thereby improving the communication reliability by using dual redundancy.

[0018] Due to the adoption of the above technical solution, the present invention has the following beneficial effects:

[0019] 1) A set of universal, reliable and flexibly configurable communication protocols has been developed for LVDS communication in the current aerospace field. This invention patent can configure the address allocation and data length through registers according to the actual data packet size, which is easy to operate and highly flexible.

[0020] 2) Compared with sending a single packet of data in communication, the reliability of the dual-packet sending dual-redundancy mode is improved by 25%. Compared with more packet data communications, dual-packet sending consumes less resources and has good sending reliability.

[0021] Single packet sending truth table

[0022]

[0023] Double packet sending truth table

[0024]

[0025]

[0026] 3) During two consecutive transmissions, odd parity check is performed on the packet number, control register information, and data segment to double-guarantee correct data transmission and improve communication reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1a to Figure 1c This is the block diagram of the LVDS communication format. DETAILED DESCRIPTION

[0028] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0029] The embodiment of the present invention discloses a method for implementing a high-reliability communication protocol based on FPGA-configurable LVDS double-packet transmission. The LVDS communication format is defined by FPGA to ensure that the controllable transmission data length and start address, double-packet transmission, odd parity check, etc. are met during the communication process. The specific format is shown in Figure 1a to Figure 1c , showing the overall LVDS communication format and the specific communication formats of the two packages respectively.

[0030] Table 1 LVDS communication format bit sequence

[0031]

[0032]

[0033]

[0034] Taking the above control register data length configuration as an example, the present invention needs to clarify the following points:

[0035] 1) Data transmission rules: send the data control word first, then the data segment; send the low bit first, and the last data first.

[0036] 2) Sending time: (56+2n*16)*20ns. Example: Sending 32 data times = (56+2*32*16)*20 = 21600ns = 21.6us.

[0037] 3) LVDS communication content: send the packet data sequence number, data ID information (base address and data length), valid data, and check bit in sequence; a single packet of data is sent twice in succession, and the sending frequency is 50MHz.

[0038] 4) Odd parity: Perform odd parity on the packet number, control register information, and data segment.

[0039] 5) Continuous sending: A single packet can send up to 32 data continuously. The control register determines the starting address and the continuous transmission Send data length .

[0040] 6) Receiving frequency (recommended): The receiving frequency is 200MHz. When receiving LVDS, the second beat is sampled every four beats. The receiving frequency can be adjusted according to the different needs of the device to ensure that the data is received completely.

[0041] 7) Receiving voting (suggestion): Vote based on the verification results of the received data. If the first received data verification is correct, the first received data will be stored in DRAM. If the first received data verification is incorrect, perform a second received data judgment. If the second data verification is correct, the second data will be stored in DRAM. If the second data is incorrect, neither of the two received data will be stored in DRAM.

Claims

1. A method for implementing a high-reliability communication protocol based on FPGA-configurable LVDS dual-packet transmission, characterized in that: The LVDS communication format bit sequence used in the communication protocol is shown in the following table: 1) Data transmission rules: send the data control word first, then the data segment; send the low bit first, and the last data first. 2) The sending time is (56+2n*16)*20ns, where n is the number of data sent; 3) LVDS communication content: send the packet data sequence number, data ID information, valid data, and check bit in sequence; a single packet of data is sent twice in succession, and the transmission frequency is 50MHz; 4) Odd check: odd check is performed on the packet sequence number, control register information, and data segment; 5) Continuous transmission: A single packet can send up to 32 data continuously, and the control register determines the starting address and the length of the continuously transmitted data.

2. A method for implementing a high-reliability communication protocol based on FPGA-configurable LVDS dual-packet transmission as claimed in claim 1, characterized in that: The data ID information includes a base address and a data length.

3. A method for implementing a high-reliability communication protocol based on FPGA-configurable LVDS dual-packet transmission as claimed in claim 1, characterized in that: The receiving frequency is 200MHz, and the second beat of every four beats is sampled during LVDS reception.

4. A method for implementing a high-reliability communication protocol based on FPGA-configurable LVDS dual-packet transmission as claimed in claim 1, characterized in that: Receiving voting: voting based on the verification of received data. If the first received data verification is correct, the first received data will be stored in DRAM; If the first received data verification is wrong, the second received data verification is performed; If the second data verification is correct, the second data is stored in the DRAM. If the second data is incorrect, the data received twice are not stored in the DRAM.

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