Memory device and forming method thereof

Abstract

The invention discloses a memory device and a manufacturing method of the memory device. The method comprises the following steps: forming a step structure on at least one side of a dielectric layer stack on a substrate, wherein the dielectric layer stack comprises a plurality of first dielectric layer pairs and second dielectric layer pairs which are alternately stacked; forming a first sacrificial layer on the exposed part of each step of the step structure; a plurality of through holes penetrating through the dielectric layer stacking body in the vertical direction are formed in the step structure, and each through hole in the plurality of through holes penetrates through the first sacrificial layer of the corresponding step; removing the first sacrificial layer of each step; and replacing the second dielectric layer in the dielectric layer stack with a conductive material and depositing in each via.

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductor technology, and more particularly, to a memory device and a method for manufacturing the memory device. Background Art

[0002] Planar memory cells can be scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing techniques become challenging and costly. As a result, the storage density for planar memory cells approaches an upper limit.

[0003] 3D memory architecture can solve the density limitation in planar memory cells. As the development of 3D memory devices (e.g., 3D NAND flash memory) moves toward high-density and high-capacity memory cells, the number of step layers in the step structure in the 3D memory device continues to increase. In the manufacturing process of the 3D memory device and its step structure, some manufacturing technologies related to the 3D memory device and its step structure still need to be further improved. Summary of the invention

[0004] Embodiments of a memory device and a method of manufacturing the same, and a memory system are described in the present disclosure.

[0005] According to one aspect of the present disclosure, a method for forming a memory device is disclosed. The method includes: forming a stepped structure on at least one side of a dielectric layer stack on a substrate, wherein the dielectric layer stack includes a plurality of first dielectric layers and second dielectric layer pairs stacked alternately; forming a first sacrificial layer on a portion exposed at each step of the stepped structure; forming a plurality of through holes penetrating the dielectric layer stack in a vertical direction in the stepped structure, wherein each of the plurality of through holes passes through the first sacrificial layer of the corresponding step; removing the first sacrificial layer of each step; and replacing the second dielectric layer in the dielectric layer stack with a conductive material and depositing it in each of the through holes.

[0006] In some embodiments, the method further includes forming a gate line slit that passes through the dielectric layer stack in the vertical direction and extends in a horizontal direction.

[0007] In some embodiments, each step includes a pair of the first dielectric layer and the second dielectric layer; and forming a first sacrificial layer on the exposed portion of each step of the stepped structure includes: forming a first sacrificial layer on the exposed portion of the second dielectric layer of each step of the stepped structure; and leaving a gap in the horizontal direction between the first sacrificial layer and the first dielectric layer of the adjacent upper step.

[0008] In some embodiments, the method further includes filling an insulating dielectric body on the stepped structure before forming the gate line gap and the plurality of through holes, wherein a portion of the insulating dielectric body is filled in the gap.

[0009] In some embodiments, the first sacrificial material of the first sacrificial layer is different from the first dielectric material of the second dielectric layer, and the first sacrificial material of the first sacrificial layer has a relatively higher etch selectivity than the first dielectric material.

[0010] In some embodiments, the first sacrificial material is polysilicon, the insulating dielectric body is silicon oxide, and the first dielectric material is silicon nitride.

[0011] In some embodiments, removing the first sacrificial layer of each step includes: removing the first sacrificial layer of each step through the gate line gap to expose a portion of the second dielectric layer; and removing the exposed portion of the second dielectric layer to form a first cavity structure corresponding to each step.

[0012] In some embodiments, removing the first sacrificial layer of each step through the gate line gap includes: filling a second sacrificial material in the gate line gap and the multiple through holes; depositing a cap layer on the dielectric layer stack to cover the second sacrificial material in the gate line gap and the multiple through holes; selectively removing the second sacrificial material in the gate line gap in the stepped structure; and removing the first sacrificial layer of each step using an etching process.

[0013] In some embodiments, when the materials of the first sacrificial material, the second sacrificial material, and the substrate are all polysilicon, the method further includes: before filling the second sacrificial material, performing polysilicon oxidation on the portion of the substrate exposed from the bottom of the gate line gap and the portion of the first sacrificial layer exposed from the sidewall of the gate line gap; and after selectively removing the second sacrificial material of the gate line gap in the stepped structure, recessing the second dielectric layer on the sidewall of the gate line gap through an etching process to expose a portion of the first sacrificial layer of each step.

[0014] In some embodiments, replacing the second dielectric layer in the dielectric layer stack with the conductive material and depositing it in each of the through holes includes: removing the second sacrificial material remaining in the gate line gap and the second sacrificial material in the multiple through holes; and replacing the second dielectric layer in the dielectric layer stack with the conductive material, and depositing the conductive material in the first cavity structure and on the side walls of the multiple through holes to form word lines and word line through hole contacts.

[0015] In some embodiments, replacing the second dielectric layer in the dielectric layer stack with the conductive material and depositing the conductive material in the first cavity structure and on the sidewalls of the multiple through holes includes: forming a third sacrificial material on the sidewalls of the gate line gaps in the stepped structure, on the sidewalls of the multiple through holes, and in the first cavity structure; removing the second dielectric layer in the dielectric layer stack to form a second cavity structure; removing the third sacrificial material formed on the sidewalls of the gate line gaps in the stepped structure, on the sidewalls of the multiple through holes, and in the first cavity structure; and depositing the conductive material in the first cavity structure and the second cavity structure, and depositing the conductive material on the sidewalls of each of the through holes and connecting with the conductive material deposited in the corresponding first cavity structure.

[0016] In some embodiments, the third sacrificial material is polysilicon material, and the conductive material is metal material.

[0017] In some embodiments, the method further includes forming a plurality of channel structures in a core region adjacent to the stepped structure, the plurality of channel structures penetrating the dielectric layer stack into the substrate in the vertical direction.

[0018] In some embodiments, the method further includes: after depositing the conductive material, filling the gate line gap with an insulating dielectric body to form a gate line isolation structure.

[0019] According to another aspect of the present disclosure, a memory device is also disclosed. The memory device includes: a memory stack layer, the memory stack layer includes a plurality of conductor layers and a first dielectric layer pair stacked alternately, wherein at least one side of the memory stack layer is a step structure; and a plurality of word line through-hole contacts, the plurality of word line through-hole contacts are arranged in the step structure, wherein each word line through-hole contact penetrates the memory stack layer in a vertical direction, wherein each of the plurality of word line through-hole contacts passes through a conductor layer in a corresponding step of the step structure and is connected to the conductor layer.

[0020] In some embodiments, the memory device further includes a gate line isolation structure, which passes through the storage stack layer in the vertical direction and extends in the horizontal direction, wherein the gate line isolation structure and the multiple word line through-hole contacts pass through the storage stack layer in the vertical direction.

[0021] In some embodiments, a portion of the conductor layer surrounding each word line via contact has a thickness in a vertical direction greater than a thickness of other portions of the conductor layer in the vertical direction.

[0022] In some embodiments, the portion of the conductor layer surrounding each word line via contact is divided into an upper portion and a lower portion, and wherein a length of the upper portion in a horizontal direction is smaller than a length of the lower portion in the horizontal direction.

[0023] In some embodiments, the storage stack layer includes a plurality of conductor layers and first dielectric layer pairs in a core area adjacent to the stepped structure, and includes a plurality of first dielectric layer and second dielectric layer pairs in the stepped structure, and wherein each of the second dielectric layers is surrounded by a conductor layer in a corresponding one of the steps.

[0024] In some embodiments, the memory device further includes a plurality of channel structures, wherein the plurality of channel structures are located in a core region of the memory stack layer adjacent to the stepped structure and penetrate the memory stack layer in the vertical direction.

[0025] In some embodiments, each of the plurality of channel structures includes a semiconductor channel, a tunneling layer, a storage layer, and a barrier layer.

[0026] According to another aspect of the present disclosure, a memory system is also disclosed. The memory system includes: a controller; and a memory device coupled to the controller, wherein the controller is configured to control the memory device, and wherein the memory device includes: a storage stack layer, the storage stack layer including a plurality of conductor layers and a first dielectric layer pair stacked alternately, wherein at least one side of the storage stack layer is a stepped structure; and a plurality of word line through-hole contacts, the plurality of word line through-hole contacts being arranged in the stepped structure, wherein each word line through-hole contact penetrates the storage stack layer in a vertical direction, wherein each of the plurality of word line through-hole contacts passes through a conductor layer in a corresponding step of the stepped structure and is connected to the conductor layer.

[0027] In some embodiments, the memory device further includes a gate line isolation structure, which passes through the storage stack layer in the vertical direction and extends in the horizontal direction, wherein the gate line isolation structure and the multiple word line through-hole contacts pass through the storage stack layer in the vertical direction.

[0028] Other aspects of the present disclosure may be understood by those skilled in the art based on the specification, claims and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate examples of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable those skilled in the relevant art to make and use the present disclosure.

[0030] Figure 1 A perspective view of a portion of a memory structure is shown.

[0031] Figure 2 A top view schematically illustrates a portion of a memory device according to some embodiments of the present disclosure.

[0032] Figure 3A A flow chart of a method for manufacturing a 3D memory device according to some embodiments of the present disclosure is shown.

[0033] Figure 3B A flow chart is shown of a process for forming word lines and word line via contacts using conductive materials according to some embodiments of the present disclosure.

[0034] Figure 4-Figure 22 Schematic cross-sectional views showing various stages of fabrication of a 3D memory device according to some embodiments of the present disclosure.

[0035] Fig.23 A top view schematically illustrates a local area of ​​a stepped structure of a memory device according to some embodiments of the present disclosure.

[0036] Fig.24 A perspective view schematically showing a partial region of a stepped structure of a memory device according to some embodiments of the present disclosure.

[0037] Fig.25 A block diagram of a system having a memory device according to some embodiments of the present disclosure is shown.

[0038] The features and advantages of the present disclosure will become more apparent from the specific embodiments described below in conjunction with the accompanying drawings, in which similar reference numerals always identify corresponding elements. In the accompanying drawings, similar reference numerals generally represent identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit in the corresponding reference numeral. Examples of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0039] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.

[0040] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or features in a plural sense, depending at least in part on the context. Similarly, terms such as "one," "an," or "the" may also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, but may allow for the presence of other factors that are not necessarily explicitly described, which may also depend at least in part on the context.

[0041] It should be readily understood that the meaning of "on", "over", and "over" in the present disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers. Furthermore, "on" or "over" not only means "on something" or "above something", but also includes the meaning of "on something" or "above something" without intervening features or layers (i.e., directly on something).

[0042] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0043] As used herein, the term "substrate" refers to a material to which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, so unless otherwise specified, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the top surface, so the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0044] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer can extend over the entire lower or upper structure, or can have a range that is smaller than the range of the lower or upper structure. In addition, a layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above and / or below it.

[0045] In the present disclosure, for ease of description, "level / step" is used to refer to elements having substantially the same height along the vertical direction. For example, a word line and an underlying gate dielectric layer may be referred to as a "level / step", a word line and an underlying insulating layer may be referred to together as a "level / step", and word lines having substantially the same height may be referred to as "a level / step of word lines" or the like.

[0046] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter of a component or process step set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​can be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" refers to a value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" can refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0047] In the present disclosure, the terms “horizontal / horizontally / lateral / laterally” refer to being nominally parallel to a side surface of a substrate, and the terms “vertical” or “vertically” refer to being nominally perpendicular to a side surface of a substrate.

[0048] As the development of 3D memory devices moves towards high-density and high-capacity storage cells, the number of staircase layers in 3D memory devices continues to increase. Each level / rung of the staircase structure can be used as a word line of the 3D memory device. The levels of the staircase structure may include steps, such as a portion of a level offset from another adjacent level. The steps of the staircase structure may be electrically and physically connected to contacts extending through an insulating layer covering the staircase structure. However, as the number of staircase layers increases, the aspect ratio of the through hole forming the wordline contact also increases, which leads to a continuous increase in process costs due to the high aspect ratio requiring a higher etching selectivity or requiring multiple mask etchings.

[0049] Figure 1 A perspective view of a portion of a 3D memory structure 100 is shown. The memory structure 100 includes a substrate 130, an insulating layer 131 above the substrate 130, a bottom select gate (BSG) 132 above the insulating layer 131, and a multi-level control gate 133, also referred to as a "word line (WL)". The multi-level control gate 133 is stacked on top of the BSG 132 to form a stack layer 135 consisting of alternating stacked pairs of conductive layers and dielectric layers. For clarity, the memory structure 100 includes a substrate 130, an insulating layer 131 above the substrate 130, a bottom select gate (BSG) 132, and a multi-level control gate 133, also referred to as a "word line (WL)". The multi-level control gate 133 is stacked on top of the BSG 132 to form a stack layer 135 consisting of alternating stacked pairs of conductive layers and dielectric layers. Figure 1 The dielectric layer for insulation adjacent to the level of control gates is not shown. The control gates of each level are separated by gate line isolation structures 116-1 and 116-2 through a stacked layer 135. The memory structure 100 also includes a top select gate (TSG) 134 above the stacked layer of control gates 133. The stacked layer of TSG 134, control gate 133 and BSG 132 is also referred to as a "gate electrode". The memory structure 100 also includes a memory string 112 and a source line region 144 in a portion of the substrate 130 between adjacent BSGs 132, and the region where the memory string 112 is formed on the substrate 130 constitutes the core array region 111 of the memory structure 100. Each memory string 112 includes a channel hole 136 extending through an insulating layer 131 and a stacked layer 135 of alternating conductive layers and dielectric layers. The memory string 112 may further include a memory film 137 on the sidewalls of the channel hole 136, a semiconductor channel layer 138 over the memory film 137, and a core filling film 139 surrounded by the semiconductor channel layer 138. The memory film 137 may include a tunneling layer, a storage layer, and a blocking layer.

[0050] like Figure 1As shown, the edge of the stacked layer 135 is configured as a staircase structure to form a staircase structure region 110 of the memory structure 100. The memory structure 100 includes a plurality of word line contacts 114 connected to the word line (gate conductor layer) 133 in the staircase structure region, and each of the plurality of word line contacts 114 is electrically connected to the word line 133 of each level / step of the corresponding staircase structure. The word line contacts 114 are mainly formed by etching an opening through the insulating layer and exposing the steps of the corresponding level of the staircase structure, followed by a deposition process of filling the opening with one or more conductive materials. However, as the number of staircase layers increases, in order to ensure the miniaturization of the 3D memory, the levels of the staircase structure are continuously thinned, so the steps exposed by over-etching may cause "punch-through" of the steps and cause a short circuit between adjacent word lines. On the other hand, as the number of stair layers increases, a dummy channel structure (not shown) needs to be arranged in the stair structure area of ​​the memory structure 100 in the manufacturing process of the memory device, especially the word line contact 114, so that the memory structure 100 provides support, which further increases the process flow and increases the process cost.

[0051] According to some embodiments of the present disclosure, a method for manufacturing a memory device and a memory device thereof are provided. The manufacturing method and the memory device thereof form a sacrificial layer on the steps of each step of the staircase structure so as to only remove the dielectric layer portion in contact with the sacrificial layer in each step and retain the dielectric layer portion of the other steps directly below the sacrificial layer, thereby avoiding the short circuit between adjacent word lines due to the "punch-through" of the steps. Moreover, in the process of removing the dielectric layer to replace the gate conductor layer, since only the dielectric layer portion in contact with the sacrificial layer at the step and the dielectric layer portion adjacent to the gate line isolation structure are removed in each step of the staircase structure, the dielectric layer of the other parts of each step of the staircase structure is still retained, so there is no need to arrange a dummy channel structure to provide support, thereby reducing the process flow and the process cost of manufacturing the memory device, and at the same time, since there is no need to arrange a dummy channel structure, the landing area of ​​the contact through hole is greatly increased, and thus the spacing between the steps of adjacent levels of the staircase structure can be reduced, thereby realizing the miniaturization of the memory device.

[0052] Figure 2 Schematically shows a top view (XY plane) of a portion of a memory device 200 according to some embodiments of the present disclosure. Figure 2As shown, the memory device 200 may include a stepped structure region 210 and a core array region 211. The core array region 211 may include an array of memory strings 212, each memory string including a plurality of stacked memory cells. The stepped structure region 210 may include a stepped structure and an array of word line through-hole contacts 214 formed on the stepped structure. In some examples, a plurality of gate line isolation structures 216 extending across the core array region 211 and the stepped structure region 210 in the word line direction (i.e., the X direction) may divide the 3D memory device 200 into a plurality of finger storage regions 218. A top selection gate cutout 220 may be provided in the middle of each finger storage region 218 to divide the top selection gate (TSG) of the finger storage region 218 into two parts. Figure 2 In the figure, for the purpose of illustration, three rows of word line contacts 214 are arranged between two adjacent gate line isolation structures 216. However, it can be understood by those skilled in the art that, according to actual needs, any rows of word line contacts 214, for example, 1 row, 2 rows, 4 rows, 5 rows, 6 rows, 7 rows, 8 rows, etc., can be arranged between two adjacent gate line isolation structures 216.

[0053] Figure 3A FIG. 1 is a flowchart illustrating an example method 300 of manufacturing a 3D memory device according to some embodiments of the present disclosure. Figure 3B A flow chart is shown of a process 3600 of forming word lines and word line via contacts using conductive material, according to some embodiments of the present disclosure. Figure 4-Figure 22 Schematic cross-sectional views of various manufacturing stages of a 3D memory device according to some embodiments of the present disclosure are shown. Figure 3A-Figure 22 300 for manufacturing a 3D memory device according to some embodiments of the present disclosure. It should be understood that the operations shown in the manufacturing method 300 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown, or the operations may be replaced, changed, or omitted with equivalent solutions. In addition, the operations may be performed simultaneously or in parallel with the operations shown in the manufacturing method 300. Figure 3A-3B Some of the operations are performed in different orders as shown.

[0054] refer to Figure 3A , at operation S310 , a dielectric layer stack may be disposed on a substrate, and a step structure may be formed on at least one side of the dielectric layer stack.

[0055] like Figure 4As shown, in some examples, the semiconductor structure 400 may include a dielectric stack 405 disposed on a substrate 410, and a first dielectric layer 415 and a second dielectric layer 420 may be alternately disposed on the substrate 410 to form the dielectric stack 405. In some examples, the first dielectric layer 415 may be formed using a silicon oxide material, and the second dielectric layer 420 may be formed using a silicon nitride (SiN) material. The first dielectric layer 415 and the second dielectric layer 420 may be deposited using one or more thin layer deposition processes (including but not limited to chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), or any combination thereof). In some examples, the thickness of the first dielectric layer 415 may be the same, or may be different (e.g., Figure 4 Similarly, the thickness of the second dielectric layer 420 can be the same or different.

[0056] For the sake of clarity and brevity, Figure 4 Only the stepped structure region 430 of the semiconductor structure 400 is shown. However, it can be understood that a plurality of channel structures 820 are also formed in the dielectric layer stack 405 in the core array region adjacent to the stepped structure region 430, and each channel structure 820 may include a semiconductor channel, a tunneling layer, a storage layer, and a barrier layer, etc. Figure 8 As shown in .

[0057] return Figure 3A After completing operation S310 , the manufacturing method 300 may proceed to operation S320 , where a first sacrificial layer 510 is formed on a portion (ie, step) exposed at each step of the stair structure.

[0058] like Figure 5As shown, in some examples, each step of the stair structure may include a pair of a first dielectric layer 415 and a second dielectric layer 420 . One or more thin layer deposition processes (including but not limited to chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), or any combination thereof) can be used to deposit the first sacrificial layer 510 on the exposed portion of the second dielectric layer 420 of each step of the step structure, and an etching process such as wet or dry etching is used to form a gap 520 between the first sacrificial layer 510 and the first dielectric layer 415 of the adjacent upper step in the horizontal direction (X direction). The distance d of the gap 520 can be between 5-500nm, and in some examples can be further between 30-200nm (for example, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm).

[0059] In one example, the sacrificial material selected for the first sacrificial layer 510 may have a relatively higher etching selectivity than the dielectric material of the second dielectric layer 420, thereby facilitating the subsequent selective etching process. In the case where the dielectric material of the second dielectric layer 420 is silicon nitride (SiN), the material selected for the first sacrificial layer 510 may include any suitable material, such as polysilicon or single crystal silicon.

[0060] refer to Figure 3A After completing operation S320 , the manufacturing method 300 may proceed to operation S330 , in which an insulating dielectric body 610 is deposited on the stepped structure where the first sacrificial layer 510 is formed.

[0061] In some examples, after forming the first sacrificial layer 510 on the steps of the step structure, one or more thin layer deposition processes may be used to deposit an insulating dielectric body 610 on the step structure, and a portion of the insulating dielectric body 610 may be filled in the gap 520, such as Figure 6 As shown. The insulating dielectric body 610 can be formed using any suitable dielectric material, such as silicon oxide, silicon oxycarbide, silicon oxynitride, or a combination thereof. In some examples, a chemical mechanical polish (CMP) can be performed on the deposited insulating dielectric body 610 to planarize the top surface of the insulating dielectric body 610.

[0062] refer to Figure 3AAfter completing operation S330 , the manufacturing method 300 may proceed to operation S340 , in which a plurality of through holes 710 penetrating the dielectric layer stack in a vertical direction (ie, Z direction) are formed in the step structure.

[0063] In some examples, an etching process (e.g., wet etching or dry etching) can be used to form a plurality of through holes 710 in the stepped structure by anisotropic etching. The etching conditions, such as etching rate and time, can be controlled so that the plurality of through holes 710 vertically penetrate the entire dielectric layer stack 405 to the substrate 410, such as Figure 7 In one example, the plurality of through-holes 710 may penetrate through the dielectric layer stack 405 and into the substrate 410. In one example, each of the plurality of through-holes 710 may pass through the first sacrificial layer 510 on a corresponding step of the stair structure.

[0064] For ease of description, Figure 8-22 The cross-sectional view of the core array region and the step structure region in the Y direction (i.e., the ZY plane) and the cross-sectional view of the step structure region in the X direction (i.e., the ZX plane) at various manufacturing stages of the 3D memory device are respectively shown. Figure 8-22 In the cross-sectional view of the step structure region in the Y direction, only the through hole 710 and the first sacrificial layer 510 on the second dielectric layer are shown on the right side of the gate line gap 810. However, it can be understood that the through hole 710 and the first sacrificial layer 510 on the second dielectric layer may also be included on the left side of the gate line gap. In other words, the through hole 710 and the first sacrificial layer 510 on the second dielectric layer may be symmetrically formed on both sides of the gate line gap 810, as shown in FIG. Figure 2 As shown in the top view.

[0065] In some examples, a gate line gap 810 extending across the stepped structure region 430 and the core array region may be formed in the X direction (ie, the word line direction) during or at the same time as the plurality of through holes 710 are formed. Figure 8 As shown. The gate line gap 810 can be formed through the entire dielectric layer stack 405 to the substrate 410 in the vertical direction by an etching process that is the same or similar to the etching process for forming the plurality of through holes 710. In one example, different etching processes can be used to form the plurality of through holes 710 and the gate line gap 810 in the same period. In another example, the plurality of through holes 710 and the gate line gap 810 can be formed at the same time and by the same etching process, and thus the depths of the plurality of through holes 710 and the gate line gap 810 etched in the vertical direction can be the same, as shown in FIG. Figure 8In this example of the present disclosure, since the process of forming the plurality of through holes 710 and the process of forming the gate line gap 810 can be combined together, the process flow is reduced and the manufacturing cost is effectively reduced.

[0066] refer to Figure 3A After completing operation S340, the method 300 may proceed to operation S350, wherein the first sacrificial layer 510 formed on each step of the step structure is removed by an etching process such as wet etching or dry etching to form a first cavity structure.

[0067] In some examples, the operation S350 of removing the first sacrificial layer 510 may first remove the first sacrificial layer 510 on each step through the gate line gap 810 formed in the dielectric layer stack 405 as described above. Figure 8 As shown, in the operation of etching and removing the first sacrificial layer 510, in order to avoid etching other materials, the second sacrificial material 830 can be first filled in the entire gate line gap 810 extending across the step structure region 430 and the core array region and in the plurality of through holes 710 using a deposition process. In one example, the second sacrificial material 830 can be made of any suitable material, such as polycrystalline silicon or single crystal silicon. After the second sacrificial material 830 is filled, a cap layer 840 is deposited on the dielectric layer stack using one or more thin layer deposition processes (including but not limited to CVD, PECVD, PVD, ALD, PEALD, or any combination thereof) to cover the second sacrificial material 830 in the gate line gap and through hole.

[0068] After forming the cap layer 840 on the dielectric layer stack, the second sacrificial material 830 in the step structure of the gate line gap 810 can be selectively removed by using a suitable mask process and etching process, such as Fig. 9 In one example, after selectively removing the second sacrificial material 830, the second dielectric layer of the dielectric layer stack exposed from the sidewalls of the gate line gap in the stepped structure region can be selectively etched by a selective etching process such as dry etching or wet etching, thereby forming a plurality of lateral grooves 1010 on the sidewalls of the gate line gap, as shown in FIG. Fig.10As shown. Each lateral groove 1010 can be used to form a gate conductor layer (word line) extending to the core array region along the word line direction (X direction) of each step in the subsequent process of depositing conductive materials. In order to prevent the lateral groove of the second dielectric layer from being etched to the adjacent through hole 710 in the horizontal direction (i.e., the Y direction) and causing a short circuit between the subsequently deposited gate conductor layers, the depth of the lateral groove in the horizontal direction can be controlled by controlling the etching conditions, such as the etching rate and time, so that the lateral groove and the adjacent through hole are separated by a certain distance by the retained second dielectric layer. The depth of the etched lateral groove can be determined based on the distance between the gate line gap and the adjacent through hole, and can be between 30-600nm, and in some examples can be further between 50-300nm (for example, 50nm, 75nm, 100nm, 125nm, 150nm, 175nm, 200nm, 225nm, 250nm, 275nm or 300nm). Although in the above example, the process of exposing the second dielectric layer by etching the gate line gap after selectively removing the second sacrificial material in the stepped structure of the gate line gap is discussed, it is understandable to those skilled in the art that the present disclosure is not limited to this operation, and the second dielectric layer exposed from the side wall by etching the gate line gap may also be formed in a subsequent process to form a lateral groove.

[0069] In one example, after the second sacrificial material 830 is selectively removed, or after the second sacrificial material 830 is selectively removed and a lateral groove is etched in the second dielectric layer exposed from the sidewall of the gate line gap, the first sacrificial layer 510 on each step of the second dielectric layer can be removed by a selective etching process such as dry etching or wet etching by utilizing the different etching selectivities of the sacrificial material of the first sacrificial layer and the dielectric material of the second dielectric layer. Fig.11 As shown in the local detail diagram on the right side, since the sacrificial material of the first sacrificial layer has a relatively high etching selectivity compared to the dielectric material of the second dielectric layer, the etchant can selectively etch the first sacrificial layer between the first sacrificial layer and the second dielectric layer, and only a small amount or no etching of the second dielectric layer 420 exposed from the sidewall of the gate line gap.

[0070] After the first sacrificial layer 510 of each step is removed through the gate line gap, the portion of the second dielectric layer where the first sacrificial layer was previously deposited is exposed, such as Fig.11 Thereafter, in operation S350, an etching process is used to remove the portion of the second dielectric layer of each step exposed by removing the first sacrificial layer, thereby forming a first cavity structure corresponding to each step.

[0071] like Fig.11As shown, the portion of the second dielectric layer of each step of the step structure on which the first sacrificial layer 510 is deposited is exposed after the first sacrificial layer 510 is removed. Fig.11 In the local detail diagram on the right, through the etching process, the etchant can not only etch the exposed portion of the second dielectric layer of each step in the horizontal direction (Y direction) through the gate line gap, but also can etch the second dielectric layer in the vertical direction (Z direction) from the entire top surface of the second dielectric layer exposed, so that the portion of the second dielectric layer of the corresponding step exposed by removing the first sacrificial layer 510 can be quickly removed. In some examples, since the etching area of ​​the portion of the second dielectric layer of the corresponding step exposed by removing the first sacrificial layer and the entire top surface is much larger than the etching area of ​​the portion of the second dielectric layer of other steps exposed from the side wall of the gate line gap, the portion of the second dielectric layer of the stepped structure exposed from the side wall of the gate line gap can be etched a small amount by controlling the etching conditions, such as etching rate and time, or the second dielectric layer can be etched to a certain depth in the horizontal direction (Y direction) according to the actual need of depositing the gate conductive layer without performing the above-mentioned process of etching the lateral groove 1010 to form a lateral groove.

[0072] After removing the exposed portion of the second dielectric layer by removing the first sacrificial layer through an etching process, a cavity structure 1210 of each step is formed. Fig.12 As discussed above, only the portion of the second dielectric layer 420 of each step in the stepped structure that is exposed by removing the first sacrificial layer and the portion exposed from the sidewall of the gate line gap are removed through the above etching process, while the other portions of the second dielectric layer 420 of each step that are not exposed are retained. Therefore, compared with the technical solution in which the second dielectric layer 420 of each step in the stepped structure is completely removed and a dummy channel structure needs to be arranged to provide mechanical support, in the above embodiment of the present disclosure, since the other portions of the second dielectric layer 420 of each step in the stepped structure that are not exposed are all retained, there is no need to arrange a dummy channel structure, thereby reducing the process flow and effectively reducing the manufacturing cost.

[0073] refer to Figure 3A After completing operation S350 , the manufacturing method 300 may proceed to operation S360 , where the second dielectric layer in the dielectric layer stack is replaced with a conductive material and the conductive material is deposited in each of the plurality of through holes.

[0074] Operation S360 first removes the remaining second sacrificial material in the gate line gaps and the second sacrificial material in the plurality of through holes. As previously discussed, the second sacrificial material in the gate line gaps in the stepped structure region has been removed, so in some examples, the remaining second sacrificial material in the gate line gaps 810 in the core array region and the second sacrificial material in the plurality of through holes 710 can be removed by masking, etching, and other processes, such as Fig.13 shown.

[0075] Thereafter, the second dielectric layer in the dielectric layer stack in the core array region is replaced with a conductive material, and the conductive material is deposited in the first cavity structure 1210 and on the sidewalls of the plurality of through holes 710 to form word lines and word line through hole contacts. In some examples, the process 3600 of forming word lines and word line through hole contacts using a conductive material may include the following operations, such as Figure 3B shown.

[0076] In some examples, at operation S3602, one or more thin layer deposition processes (including but not limited to CVD, PECVD, PVD, ALD, PEALD, or any combination thereof) may be used to deposit a third sacrificial material 1410 on the sidewalls of the gate line gap 810 extending across the core array region and the stepped structure region, on the sidewalls of each through hole 710, and in the first cavity structure 1210, such as Fig.14 As shown. In one example, the third sacrificial material 1410 may be made of any suitable material, such as polycrystalline silicon or single crystal silicon. Thereafter, at operation S3604, only the third sacrificial material 1410 on the sidewall of the gate line gap 810 in the core array region may be removed by etching, masking, or the like, and the entire second dielectric layer in the dielectric layer stack in the core array region may be etched away through the gate line gap 810 in the core array region by an isotropic etching process (e.g., wet etching), thereby forming a second cavity structure 1510, as shown in FIG. Fig.15 shown.

[0077] It can be understood that since the third sacrificial material 1410 on the side walls of the gate line gaps 810 and the multiple through holes 710 in the stepped structure and the third sacrificial material 1410 in the first cavity structure are retained thereon, the above-mentioned etching process to remove the second dielectric layer in the core array area does not remove the second dielectric layer in the dielectric layer stack in the stepped structure, thereby being able to provide effective mechanical support for the memory device in the gate conductor replacement process of the memory device.

[0078] After forming the second cavity structure 1510, at operation S3606, the third sacrificial material 1410 formed on the sidewalls of the gate line gap 810 and the plurality of through holes 710 in the stepped structure and the third sacrificial material 1410 in the first cavity structure 1210 can be removed by etching, masking or the like, thereby exposing the first cavity structure 1210 and the lateral groove 1010 of the second dielectric layer in the stepped structure region, as shown in FIG. Fig.16 In some examples, after removing the third sacrificial material 1410, at operation S3608, a conductive material may be deposited in the second cavity structure 1510, the first cavity structure 1210 of each step, and the lateral groove 1010 of the second dielectric layer in the step structure region through the gate line gap, and the conductive material may be deposited on the sidewall of each through hole and electrically connected to the conductive material deposited in the first cavity structure of each step, thereby forming a gate conductor layer (word line) 1710 and a word line through hole contact 1720 of a 3D memory device, as shown in FIG. Fig.17 In some examples, the gate conductor may be made of a metal or metal alloy, such as tungsten, cobalt, nickel, copper, or aluminum, and / or combinations thereof. In some examples, the gate conductor may also include a conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), and the like.

[0079] In some examples, after depositing the conductive material, an insulating dielectric body may be deposited in the gate line gap 810 extending across the stepped structure region 430 and the core array region to form a gate line isolation structure 1750. In addition, an insulating dielectric body may be deposited in a through hole having a conductive material deposited on its sidewalls, such as Fig.17 In some examples, the insulating dielectric body can be formed using any suitable dielectric material, such as silicon oxide, silicon oxycarbide, silicon oxynitride, or a combination thereof.

[0080] Reference Fig.17 , the portion of the gate conductor layer 1710 surrounding each word line through hole contact may include an upper conductor layer 1730 and a lower conductor layer 1740. Since in the process of forming the first sacrificial layer 510 previously, a gap 520 may be provided between the first sacrificial layer 510 and the first dielectric layer 415 of the adjacent upper step in the horizontal direction, and the insulating dielectric body 610 is filled in the gap 520, the upper conductor layer 1730 in the gate conductor layer 1710 surrounding the word line through hole contact is separated from the gate conductor layer of the adjacent upper step by a certain distance, such as the distance d mentioned above, thereby effectively avoiding the risk of short circuit between the gate conductor layers of adjacent steps in the stepped structure due to process errors and the like.

[0081] On the other hand, Fig.17As shown, since the second dielectric layer at the step of each step in the stepped structure (i.e., the portion of the second dielectric layer of each step on which the first sacrificial layer 510 is formed) is replaced with a gate conductive layer, and the second dielectric layers of other steps directly below the step are not replaced with gate conductive layers, the word line via contact is only electrically connected to the gate conductor layer of the corresponding step (i.e., the step through which the via passes). Therefore, in the above-mentioned embodiment of the present disclosure, even if the via with the conductor layer deposited on its sidewall passes through the entire dielectric layer stack, the word line via contact formed by the via will not be electrically connected to other gate conductor layers to cause a short circuit between the gate conductor layers, thereby effectively avoiding the step "punch-through" and causing a short circuit between adjacent gate conductor layers (word lines).

[0082] In other examples, when the sacrificial material of the first sacrificial layer 510, the second sacrificial material 830 and the material of the substrate 410 are all polysilicon materials, in order to avoid the influence of subsequent etching, Figure 8 As shown, before the second sacrificial material 830 is filled in the entire gate line gap 810 and the plurality of through holes 710 by a deposition process, polysilicon oxidation is performed on the portion of the substrate 410 exposed from the bottom of the gate line gap and the portion of the first sacrificial layer 510 exposed from the sidewall of the gate line gap, thereby forming polysilicon oxide 1810 on the exposed portion of the substrate, and forming polysilicon oxide 1820 on the exposed end of the first sacrificial layer, as shown in FIG. Fig.18 After the polysilicon oxidation is completed, the second sacrificial material 830 can be filled in the gate line gap 810 and the plurality of through holes by a deposition process, and a cap layer can be deposited on the dielectric layer stack, as in the process discussed previously. Fig.19 shown.

[0083] After selectively removing the second sacrificial material 830 in the step structure of the gate line gap 810 by the same process as previously discussed, since polysilicon oxide 1820 is formed at the exposed end of the first sacrificial layer in the above oxidation process, the first sacrificial layer 510 inside cannot be effectively etched by an etching process using an etchant, as shown in FIG. Fig. 20 In this case, a selective etching process can be used to etch the second dielectric layer exposed from the sidewalls of the gate line gaps through the gate line gaps, thereby forming a plurality of transverse grooves 2110 on the sidewalls of the gate line gaps and exposing the first sacrificial layer, as shown in FIG. Fig.21 As shown in the above Fig.10As discussed, each lateral groove 2110 can be used to form a gate conductor layer (word line) extending to the core array region along the word line direction (X direction) at each step in the subsequent process of depositing a conductive material. As discussed above, in order to prevent the lateral groove of the second dielectric layer from being etched to the adjacent through hole 710 in the horizontal direction (i.e., the Y direction) and causing a short circuit between the subsequently deposited gate conductor layers, the depth of the lateral groove in the horizontal direction can be controlled by controlling the etching conditions, such as the etching rate and time, so that the lateral groove and the adjacent through hole are separated by a certain distance by the retained second dielectric layer.

[0084] Reference Fig. 22 It can be understood that after the first sacrificial layer is exposed, the first sacrificial layer and the exposed portion of the second dielectric layer on each step can be removed by the same process as the previously described operation S350 and operation S360 to form a first cavity structure, and the second dielectric layer in the dielectric layer stack is replaced with a conductive material and the conductive material is deposited in each through hole. Since these processes are exactly the same as the previously described operations S350 and operation S360, in order to make the present disclosure concise and clear, they are not repeated here.

[0085] Fig.23 A top view schematically shows a local area of ​​a stepped structure of a memory device according to some embodiments of the present disclosure, and Fig.24 Schematically illustrates a perspective view of a partial area of ​​a stepped structure of a memory device according to some embodiments of the present disclosure. Fig.24 The first dielectric layer for insulation adjacent to the gate conductor layer in each step is not shown. Figure 2 , 17 , 23-24 to describe a memory device according to some embodiments of the present disclosure.

[0086] In some examples, such as Fig.17 As shown, the memory device 1700 may include a memory stack layer 1705, the memory stack layer may include a plurality of alternately stacked conductor layers 1710 and a first dielectric layer 415, and a staircase structure may be formed on at least one side of the memory stack layer 1705. The memory device may be divided into a staircase structure region 210 and a core array region 211 in the word line direction (i.e., the X direction), as shown in FIG. Figure 2As shown. The memory device 1700 may further include a plurality of word line via contacts 1720 uniformly arranged in a stair structure. Each word line via contact may vertically penetrate the entire memory stack layer until the bottom of the memory stack layer 1705, and each word line via contact may vertically penetrate the gate conductor layer 1710 in a corresponding step of the stair structure (i.e., the step through which the via contact passes) and be electrically connected to the gate conductor layer, as shown. Fig.17 shown.

[0087] In some examples, the memory device 1700 may further include a gate line isolation structure 1750 that passes through the memory stack layer in a vertical direction (Z direction) and extends across the stepped structure region 210 and the core array region 211 in a word line direction (X direction), such as Figure 2 , Fig.17 In one example, the word line via contact 1720 and the gate line isolation structure 1750 can be manufactured by the same etching process, and thus the depths in the vertical direction can be the same.

[0088] Reference Fig.17 , 24 , the gate conductor layer 1710 of each step in the memory stack layer 1705 may be divided into a first portion and a second portion, the first portion of the gate conductor layer may include a gate conductor layer extending along the word line direction (X direction) in the core array region and the step structure region, and the second portion of the gate conductor layer may include a gate conductor layer surrounding the word line through-hole contact 1720. In one example, as Fig.24 As shown, the second portion of the gate conductor layer is a section of the conductor layer formed in the Y direction. As described in the previous manufacturing process, since the space occupied by the first sacrificial layer is also deposited with conductive material after the first sacrificial layer is removed, the thickness of the second portion of the gate conductor layer (i.e., the gate conductor layer surrounding the word line through-hole contact) in the vertical direction can be greater than the thickness of the first portion of the gate conductor layer (i.e., the gate conductor layer extending along the word line direction in the core array region and the stepped structure region) in the vertical direction, as shown in FIG. Fig.17 shown.

[0089] Next refer to Fig.17In some examples, as previously discussed, the portion of the gate conductor layer 1710 of each step surrounding each word line via contact (i.e., the second portion of the gate conductor layer) may include an upper portion of the conductor layer 1730 and a lower portion of the conductor layer 1740. As discussed above, since the upper portion of the conductor layer 1730 is spaced apart from the gate conductor layer 1710 of the adjacent previous step by a certain distance, the length of the upper portion of the conductor layer 1730 in the horizontal direction may be smaller than the length of the lower portion of the conductor layer 1740 in the horizontal direction, thereby effectively avoiding the risk of short circuits that may occur between the gate conductor layers of adjacent steps in the stepped structure due to process errors and the like.

[0090] Next refer to Fig.17 , 24 In some examples, the memory stack layer 1705 of the memory device 1700 may include a plurality of alternately stacked gate conductor layers 1710 and first dielectric layers 415 in the core array region. As discussed in the previous gate conductor layer replacement process, since only the exposed portion of the second dielectric layer of each step of the memory stack layer in the stepped structure region (including the portion of the second dielectric layer exposed by removing the first sacrificial layer and the portion exposed from the sidewall of the gate line gap) is etched away, while the unexposed portion of the second dielectric layer of each step is retained, the memory stack layer 1705 of the memory device 1700 may include a plurality of alternately stacked first dielectric layers and second dielectric layers in the stepped structure region, and the second dielectric layer of each step is surrounded by the gate conductor layer in the step, as shown in FIG. Fig.24 The gate conductor layer surrounding the second dielectric layer in each step extends in the word line direction, one end of the gate conductor layer is connected to the word line through-hole contact 1720, and the other end is electrically connected to the gate conductor layer of the same step in the core array region, thereby forming the word line of the step.

[0091] As discussed above, the memory device according to the above-mentioned embodiment of the present disclosure does not need to worry about short circuits between adjacent word lines due to the "punch-through" of the steps, and since there is no need to lay out a dummy channel structure, on the one hand, the cost of the memory device is reduced, and the miniaturization of the memory device can be achieved.

[0092] Fig.25A block diagram of an example of a system 2500 having a memory device 2504 according to some examples of the present disclosure is shown. The system 2500 may be, for example, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or any other suitable electronic device having a memory therein. Fig.25 As shown, the system 2500 may include a host 2508 and a memory system 2502 having one or more memory devices 2504 and a memory controller 2506. The host 2508 may be, for example, a processor of an electronic device (e.g., a central processing unit (CPU)) or a system on chip (SoC), such as an application processor (AP). The host 2508 may be configured to send data to the memory device 2504 or receive data from the memory device 2504.

[0093] The memory device 2504 may be any memory device disclosed in the present disclosure, such as the memory device 1700. In the present disclosure, the memory device 2504 may include a channel structure penetrating into a semiconductor layer, wherein the channel structure may be processed so that the upper end of each channel structure may be horizontally aligned and the top surface of the semiconductor layer formed above the channel structure may be planarized. Therefore, in some embodiments, it not only makes the dielectric layer formed above the semiconductor layer thinner, but also reduces the aspect ratio of the lead-out contact subsequently formed through the semiconductor layer, which may expand the range of materials for the lead-out contact, thereby eliminating the additional step of forming a connection for the lead-out contact. Due to the different depths of the gate slit lines, such features may also remove the restrictions on the formation position of the lead-out contact and reduce the difficulty of the subsequent chemical mechanical polishing (CMP) process. As a result, the complexity and cost of the manufacturing process may be reduced, and in some cases the product yield may be increased. In addition, the memory device 2504 may include a sealing structure disposed at the upper end of each channel structure. A sealing structure may be formed in the channel structure to seal a top portion of the channel structure to prevent other materials used in subsequent processes from entering the channel structure, which may adversely affect the electrical characteristics of the channel structure. As a result, device performance may be improved in some cases.

[0094] According to some examples, the memory controller 2506 is coupled to the memory device 2504 and the host 2508 and is configured to control the memory device 2504. The memory controller 2506 can manage data stored in the memory device 2504 and communicate with the host 2508. In some examples, the memory controller 2506 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some examples, the memory controller 2506 is designed to operate in a high duty cycle environment SSD or an Embedded Multimedia Card (eMMC) used as a data storage body for mobile devices (such as smart phones, tablet computers, laptop computers, etc.) and enterprise storage arrays. The memory controller 2506 may be configured to control operations of the memory device 2504 , such as read, erase, and program operations.

[0095] The memory controller 2506 may also be configured to manage various functions regarding data stored or to be stored in the memory device 2504, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 2506 is also configured to process error correction codes (ECC) for data read from or written to the memory device 2504. Any other suitable functions may also be performed by the memory controller 2506, such as formatting the memory device 2504. The memory controller 2506 may communicate with an external device (e.g., a host 2508) according to a specific communication protocol. For example, the memory controller 2506 can communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a high-speed PCI (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Drive Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a FireWire protocol, etc.

[0096] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for forming a memory device, comprising: forming a stepped structure on at least one side of a dielectric layer stack on a substrate, wherein the dielectric layer stack includes a plurality of first dielectric layer and second dielectric layer pairs that are alternately stacked; forming a first sacrificial layer on the exposed portion of each step of the step structure; forming a plurality of through holes penetrating the dielectric layer stack in a vertical direction in the stepped structure, wherein each of the plurality of through holes passes through the first sacrificial layer of the corresponding step; removing the first sacrificial layer of each step; and A second dielectric layer in the dielectric layer stack is replaced with a conductive material and deposited in each of the vias. 2 . The method according to claim 1 , further comprising forming a gate line slit that penetrates the dielectric layer stack in the vertical direction and extends in a horizontal direction.

3. The method according to claim 2, wherein: Each step includes a pair of the first dielectric layer and the second dielectric layer; And forming a first sacrificial layer on the exposed portion of each step of the step structure comprises: forming a first sacrificial layer on the exposed portion of the second dielectric layer of each step of the step structure; as well as A gap is formed between the first sacrificial layer and the first dielectric layer of an adjacent upper step in a horizontal direction.

4. The method according to claim 3, further comprising filling an insulating dielectric body on the stepped structure before forming the gate line gap and the plurality of through holes, wherein: A portion of the insulating dielectric body is filled in the gap.

5. The method according to claim 3, wherein: The first sacrificial material of the first sacrificial layer is different from the first dielectric material of the second dielectric layer, and the first sacrificial material of the first sacrificial layer has a relatively higher etch selectivity than the first dielectric material.

6. The method according to claim 5, wherein: The first sacrificial material is polysilicon, the insulating dielectric body is silicon oxide, and the first dielectric material is silicon nitride.

7. The method according to claim 3, wherein: Removing the first sacrificial layer of each step includes: removing the first sacrificial layer of each step through the gate line gap to expose a portion of the second dielectric layer; and The exposed portion of the second dielectric layer is removed to form a first cavity structure corresponding to each step.

8. The method according to claim 7, wherein: Removing the first sacrificial layer of each step through the gate line gap includes: Filling a second sacrificial material in the gate line gaps and the plurality of through holes; depositing a cap layer on the dielectric layer stack to cover the gate line gaps and the second sacrificial material in the plurality of through holes; Selectively removing the second sacrificial material in the gate line gap in the stepped structure; and The first sacrificial layer of each step is removed by an etching process.

9. The method according to claim 8, wherein: When the materials of the first sacrificial material, the second sacrificial material, and the substrate are all polysilicon, the method further includes: Before filling the second sacrificial material, performing polysilicon oxidation on a portion of the substrate exposed from a bottom of the gate line gap and a portion of the first sacrificial layer exposed from a sidewall of the gate line gap; and After selectively removing the second sacrificial material of the gate line gap in the stepped structure, the second dielectric layer on the sidewall of the gate line gap is recessed by an etching process to expose a portion of the first sacrificial layer of each step.

10. The method according to claim 8, wherein: Replacing the second dielectric layer in the dielectric layer stack with the conductive material and depositing it in each of the through holes comprises: removing the second sacrificial material remaining in the gate line gaps and the second sacrificial material in the plurality of through holes; and The second dielectric layer in the dielectric layer stack is replaced with the conductive material, and the conductive material is deposited in the first cavity structure and on sidewalls of the plurality of vias to form word lines and word line via contacts.

11. The method according to claim 10, wherein: Replacing the second dielectric layer in the dielectric layer stack with the conductive material and depositing the conductive material in the first cavity structure and on the sidewalls of the plurality of through holes comprises: forming a third sacrificial material on the sidewalls of the gate line gaps in the stepped structure, on the sidewalls of the plurality of through holes, and in the first cavity structure; removing the second dielectric layer in the dielectric layer stack to form a second cavity structure; removing the third sacrificial material formed on the sidewalls of the gate line gaps in the stepped structure, on the sidewalls of the plurality of through holes, and in the first cavity structure; and The conductive material is deposited in the first cavity structure and the second cavity structure, and the conductive material is deposited on the sidewall of each through hole and connected with the conductive material deposited in the corresponding first cavity structure.

12. The method according to claim 11, wherein: The third sacrificial material is polysilicon material, and the conductive material is metal material.

13. The method according to claim 10, further comprising: A plurality of channel structures are formed in a core region adjacent to the stepped structure, the plurality of channel structures penetrating the dielectric layer stack into the substrate in the vertical direction.

14. The method according to claim 10, further comprising: After depositing the conductive material, an insulating dielectric body is filled in the gate line gap to form a gate line isolation structure.

15. A memory device comprising: A storage stack layer, the storage stack layer comprising a plurality of conductor layers and first dielectric layer pairs stacked alternately, wherein at least one side of the storage stack layer is a stepped structure; and a plurality of word line through-hole contacts, the plurality of word line through-hole contacts being arranged in the stepped structure, wherein each word line through-hole contact penetrates the memory stack layer in a vertical direction, Each of the plurality of word line through-hole contacts passes through a conductor layer in a corresponding step of the step structure and is connected to the conductor layer.

16. The memory device according to claim 15 , further comprising a gate line isolation structure, the gate line isolation structure passing through the memory stack layer in the vertical direction and extending in the horizontal direction, in, The gate line isolation structure and the plurality of word line through-hole contacts penetrate the memory stack layer in the vertical direction.

17. The memory device of claim 15, wherein: A portion of the conductor layer surrounding each word line via contact has a thickness in a vertical direction greater than a thickness of other portions of the conductor layer in the vertical direction.

18. The memory device of claim 17, wherein: The portion of the conductor layer surrounding each word line via contact is divided into an upper portion and a lower portion, and wherein a length of the upper portion in a horizontal direction is smaller than a length of the lower portion in the horizontal direction.

19. The memory device according to claim 15 or 16, wherein: The storage stack layer includes a plurality of conductor layers and first dielectric layer pairs in a core region adjacent to the stepped structure, and includes a plurality of first dielectric layer and second dielectric layer pairs in the stepped structure, and wherein each of the second dielectric layers is surrounded by a conductor layer in a corresponding step. 20 . The memory device according to claim 15 , further comprising a plurality of channel structures, the plurality of channel structures being located in a core region of the memory stack layer adjacent to the stepped structure and penetrating the memory stack layer in the vertical direction.

21. The memory device of claim 20, wherein: Each of the plurality of channel structures includes a semiconductor channel, a tunneling layer, a storage layer, and a barrier layer.

22. A memory system comprising: Controller; as well as a memory device coupled to the controller, wherein the controller is configured to control the memory device, and wherein the memory device comprises: A storage stack layer, the storage stack layer comprising a plurality of conductor layers and first dielectric layer pairs stacked alternately, wherein at least one side of the storage stack layer is a stepped structure; and a plurality of word line through-hole contacts, the plurality of word line through-hole contacts being arranged in the stepped structure, wherein each word line through-hole contact penetrates the memory stack layer in a vertical direction, Each of the plurality of word line through-hole contacts passes through a conductor layer in a corresponding step of the step structure and is connected to the conductor layer.

23. The memory system of claim 22, wherein: The memory device further includes a gate line isolation structure, the gate line isolation structure passing through the memory stack layer in the vertical direction and extending in the horizontal direction, Wherein, the gate line isolation structure and the plurality of word line through-hole contacts penetrate the storage stack layer in the vertical direction.

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