Three-dimensional memory device and manufacturing method thereof

Abstract

The present disclosure relates to a three-dimensional memory device and a method of manufacturing the same, the three-dimensional memory device including: a first stack structure including a first gate isolation structure extending in a first direction and a plurality of first channel structures arranged in an array, in a second direction perpendicular to the first direction, a first distance is formed between a row of first channel structures arranged in the first direction in the plurality of first channel structures and the first gate isolation structure; the second stacking structure is stacked above the first stacking structure and comprises a second gate isolation structure extending in the first direction and a plurality of second channel structures arranged in an array, and in the second direction, the first gate isolation structure extends in the first direction, and the second channel structures extend in the second direction. A second distance is formed between a row of second channel structures corresponding to the row of first channel structures in the plurality of second channel structures and the second gate isolation structure, and the second distance is different from the first distance.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor technology, and more particularly, to a three-dimensional (3D) memory device and a method of manufacturing the same. Background Art

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address density and performance limitations in planar memory cells.

[0003] To further increase the storage capacity in 3D memories, the number of vertically stacked memory cells has been greatly increased while reducing the lateral dimensions of the memory cells. As a result, the aspect ratio of 3D memory cells has increased significantly, introducing complexity in manufacturing. Therefore, there is a need to improve the manufacturing process for 3D memories to achieve high density and good reliability. Summary of the invention

[0004] Embodiments of three-dimensional (3D) memory devices and methods of fabricating the same are described in this disclosure.

[0005] A first aspect of the present disclosure provides a three-dimensional memory device, comprising: a first stacked structure, comprising a first gate isolation structure extending in a first direction and a plurality of first channel structures arranged in an array, wherein, in a second direction perpendicular to the first direction, a row of first channel structures arranged in the first direction among the plurality of first channel structures has a first distance from the first gate isolation structure; a second stacked structure, stacked above the first stacked structure, and comprising a second gate isolation structure extending in the first direction and a plurality of second channel structures arranged in an array, wherein, in the second direction, a row of second channel structures corresponding to the row of first channel structures among the plurality of second channel structures has a second distance from the second gate isolation structure, and wherein the second distance is different from the first distance.

[0006] In some embodiments, at an interface between the second stacked structure and the first stacked structure, a channel structure of the plurality of first channel structures is aligned with a corresponding channel structure of the plurality of second channel structures, and the first gate isolation structure is aligned with the second gate isolation structure.

[0007] In some embodiments, the first distance is measured on a plane where the interface between the second stacked structure and the first stacked structure is located, from a center line of the row of first channel structures along the first direction to a center line of the first gate isolation structure along the first direction, and the second distance is measured on a plane where a surface of the second stacked structure opposite to the interface is located, from a center line of the row of second channel structures along the first direction to a center line of the second gate isolation structure along the first direction.

[0008] In some embodiments, on the interface between the second stacking structure and the first stacking structure, the spacing between two adjacent rows of the first channel structures gradually decreases in a direction away from the first gate isolation structure, and wherein, on the surface of the second stacking structure opposite to the interface, the spacing between two adjacent rows of the second channel structures gradually decreases in a direction away from the second gate isolation structure.

[0009] In some embodiments, in a direction away from the corresponding gate isolation structure, the difference between the first distance and the second distance gradually decreases.

[0010] In some embodiments, the extending direction of the channel structures in the row of first channel structures forms a first angle with a third direction perpendicular to the first direction and the second direction, and the channel structures in the row of second channel structures form a second angle with the third direction.

[0011] In some embodiments, the first angle is equal to the second angle.

[0012] In some embodiments, the second distance is determined according to at least one of the following: the first distance, the first angle, the second angle, a thickness of the second stacked structure, and an etching process used to form the channel hole.

[0013] In some embodiments, the first gate isolation structure and the second gate isolation structure are formed integrally.

[0014] In some embodiments, the plurality of first channel structures are symmetrically arranged in two arrays with respect to the first gate isolation structure, and the plurality of second channel structures are symmetrically arranged in two arrays with respect to the second gate isolation structure.

[0015] In some embodiments, the plurality of first channel structures and the first gate isolation structure are implemented using a first mask, and the plurality of second channel structures and the second gate isolation structure are implemented using a second mask.

[0016] In some embodiments, channel structures in adjacent rows of the plurality of first channel structures are staggered, and channel structures in adjacent rows of the plurality of second channel structures are staggered.

[0017] A second aspect of the present disclosure provides a method for forming a three-dimensional memory device, comprising: forming a first dielectric stack; forming a first gate gap structure extending in a first direction and a plurality of first channel holes arranged in an array in the first dielectric stack, wherein, in a second direction perpendicular to the first direction, a row of first channel holes arranged in the first direction among the plurality of first channel holes has a first distance from the first gate gap structure; forming a second dielectric stack above the first dielectric stack; and forming a second gate gap structure extending in the first direction and a plurality of second channel holes arranged in an array in the second dielectric stack, wherein, in the second direction, a row of second channel holes corresponding to the row of first channel holes among the plurality of second channel holes has a second distance from the second gate gap structure, and wherein the second distance is different from the first distance.

[0018] In some embodiments, the first gate gap structure and the plurality of first channel holes are formed in the first dielectric stack using a first mask, and the second gate gap structure and the plurality of second channel holes are formed in the second dielectric stack using a second mask.

[0019] In some embodiments, forming the second dielectric stack includes forming a material stack at a first surface of the first dielectric stack, and wherein the second gate gap structure and the plurality of second channel holes are formed in the second dielectric stack using the second mask, such that at the first surface, the channel holes among the plurality of first channel holes are aligned with corresponding channel holes among the plurality of second channel holes, and the first gate gap structure is aligned with the second gate gap structure.

[0020] In some embodiments, in the first mask, the spacing between two rows of patterns corresponding to two adjacent rows of the first channel holes gradually decreases in a direction away from the pattern corresponding to the first gate gap structure; and wherein, in the second mask, the spacing between two rows of patterns corresponding to two adjacent rows of the second channel holes gradually decreases in a direction away from the pattern corresponding to the second gate gap structure.

[0021] In some embodiments, in the first mask, patterns of channel holes corresponding to adjacent rows of the plurality of first channel holes are staggered; and wherein, in the second mask, patterns of channel holes corresponding to adjacent rows of the plurality of second channel holes are staggered.

[0022] A third aspect of the present disclosure provides a storage system, comprising: at least one three-dimensional storage device as described in the first aspect; and a memory controller coupled to the three-dimensional storage device and configured to control the three-dimensional storage device.

[0023] In some embodiments, the memory system further includes a host coupled to the memory controller and configured to send or receive the data.

[0024] Other aspects of the present disclosure may be understood by those skilled in the art based on the specification, claims and drawings of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0026] Figure 1 A schematic top view of an exemplary three-dimensional (3D) memory device according to some embodiments of the present disclosure is shown.

[0027] Figure 2 A schematic top view of a region of a 3D memory device according to some embodiments of the present disclosure is shown.

[0028] Figure 3 A perspective view showing a portion of an exemplary 3D memory device according to some embodiments of the present disclosure is shown.

[0029] Figure 4 , 5 6A shows a cross-sectional view of an exemplary 3D memory device at a manufacturing stage according to some embodiments of the present disclosure.

[0030] Figure 6B A cross-sectional view of an exemplary 3D memory device including a dual stacked structure resulting from some embodiments of the present disclosure is shown.

[0031] Fig. 7A , 7B 7C shows a schematic top view of a mask used in the manufacturing process of a 3D memory device according to some embodiments of the present disclosure.

[0032] Figure 8 A flow chart of a method for forming a 3D memory device according to some embodiments of the present disclosure is shown.

[0033] Fig. 9A block diagram of an exemplary system having a 3D memory device according to some embodiments of the present disclosure is shown.

[0034] The features and advantages of the present disclosure will become more apparent from the specific embodiments described below in conjunction with the accompanying drawings. In the accompanying drawings, similar reference numerals always identify corresponding elements. In the accompanying drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements, wherein the drawing in which the element first appears is indicated by the leftmost digit in the corresponding reference numeral.

[0035] Embodiments of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0036] This specification discloses one or more aspects of the features incorporated into the present disclosure. The disclosed aspects are merely illustrative of the present disclosure. The scope of the present disclosure is not limited to the disclosed aspects, but is defined by the appended claims.

[0037] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature relative to another (or multiple) element or feature as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0038] As used herein, the term "about" or "substantially" or "approximately" indicates a value of a given quantity that may vary based on a particular technology. Based on a particular technology, the term "about" or "substantially" or "approximately" may indicate a value of a given quantity that varies within, for example, 1-15% of a value (e.g., ±1%, ±2%, ±5%, ±10%, or ±15% of a value).

[0039] Figure 1 A top view of an exemplary three-dimensional (3D) memory device 100 according to some embodiments of the present disclosure is shown. The 3D memory device 100 may be a memory chip (package), a memory die, or any portion of a memory die, and may include one or more memory planes 101, each of which may include multiple memory blocks 103. The same and concurrent operations may be performed on each memory plane 101. The memory block 103, which may be, for example, a megabyte (MB) in size, is the minimum size for performing an erase operation. Figure 1As shown, the exemplary 3D memory device 100 includes four memory planes 101, and each memory plane 101 includes six memory blocks 103. Each memory block 103 may include a plurality of memory cells, wherein each memory cell may be addressed by interconnects such as bit lines and word lines. The bit lines and word lines may be arranged vertically (e.g., arranged in rows and columns, respectively), thereby forming a metal line array. Figure 1 In the embodiment of the present invention, the directions of the bit lines and word lines are marked as “BL” and “WL”. In the present disclosure, the memory block 103 is also referred to as a “memory array” or “array”. The memory array is a core area in a memory device that performs a storage function.

[0040] The 3D memory device 100 also includes a peripheral region 105, i.e., an area surrounding the memory plane 101. The peripheral region 105 contains many digital, analog, and / or mixed signal circuits for supporting the functions of the memory array, such as page buffers, row and column decoders, and sense amplifiers. The peripheral circuits use active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., which are obvious to those skilled in the art.

[0041] It should be noted that in Figure 1 The arrangement of the memory planes 101 in the 3D memory device 100 and the arrangement of the memory blocks 103 in each memory plane 101 shown in FIG. 1 are merely used as examples, which do not limit the scope of the present disclosure.

[0042] refer to Figure 2 , showing some embodiments according to the present disclosure, Figure 1 1. The region 108 of the 3D memory device 100 may include a step region 210 and a channel structure region 211. The channel structure region 211 may include an array of channel structures 212, each corresponding to a memory string including a plurality of stacked memory cells. The step region 210 may include a step structure and an array of contact structures 214 formed on the step structure. In some embodiments, a plurality of gate isolation structures (Gate Line Slit, GLS) 216 extending across the channel structure region 211 and the step region 210 in the WL direction may divide the memory block into a plurality of memory fingers 218. In some embodiments, at least some of the gate isolation structures 216 may be used as a common source contact for the array of channel structures 212 in the channel structure region 211. In some embodiments, the region 108 also includes a dummy channel structure 222, which is used for process variation control during manufacturing and / or for additional mechanical support.

[0043] Figure 3A perspective view of a portion of an exemplary three-dimensional (3D) memory device 300 according to some embodiments of the present disclosure is shown. The memory device 300 includes a substrate 330, an insulating film 331 on the substrate 330, a first-level lower select gate (LSG) 332 on the insulating film 331, and a multi-level control gate 333 (also referred to as a "word line (WL)") stacked on top of the LSG 332 to form a film stack 335 of alternating conductive layers and dielectric layers. For clarity, the memory device 300 includes a substrate 330, an insulating film 331 on the substrate 330, a first-level lower select gate (LSG) 332 on the insulating film 331, and a multi-level control gate 333 (also referred to as a "word line (WL)") stacked on top of the LSG 332 to form a film stack 335 of alternating conductive layers and dielectric layers. Figure 3 The dielectric layers adjacent to the control gates of each stage are not shown.

[0044] The control gates of each stage are separated by gate isolation structures 216-1 and 216-2 passing through the film stack 335. The memory device 300 also includes a top select gate (TSG) 334 on the stack of control gates 333. The stack of TSG 334, control gate 333 and LSG 332 is also referred to as a "gate electrode". The memory device 300 also includes a channel structure 212, and a doped source line region 344 in each portion of the substrate 330 between adjacent LSGs 332. Each channel structure 212 includes a channel hole 336 extending through an insulating film 331 and a film stack 335 of alternating conductive layers and dielectric layers. The channel structure 212 also includes a storage film 337 on the sidewalls of the channel hole 336, a channel layer 338 on the storage film 337, and a core filling film 339 surrounded by the channel layer 338. The memory cell 340 may be formed at the intersection of the control gate 333 and the channel structure 212. The memory device 300 further includes a plurality of bit lines (BL) 341 connected to the channel structure 212 over the TSG 334. The memory device 300 further includes a plurality of metal interconnect lines 343 connected to the gate electrode through the plurality of contact structures 214. The edge of the film stack 335 is configured in a stepped shape to allow electrical connection to each level of the gate electrode.

[0045] exist Figure 3 , for illustration purposes, three levels of control gates 333-1, 333-2, and 333-3, a level TSG 334, and a level LSG 332 are shown. In this example, each channel structure 212 may include three memory cells 340-1, 340-2, and 340-3, which correspond to the control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may exceed three to increase storage capacity. The memory device 300 may also include other structures, such as TSG cuts, common source contacts, and dummy channel structures. For simplicity, in Figure 3These structures are not shown in FIG.

[0046] In pursuit of higher storage capacity in 3D memory, the number of vertically stacked memory cells has been greatly increased. Therefore, the number of control gates or word lines 333 has been greatly increased. Accordingly, the total thickness of the film stack 335 of alternating conductive layers and dielectric layers has been increased. At the same time, the lateral dimensions of the channel structure 212 have been reduced to further increase the density of the memory cell 340 and the storage capacity of the 3D memory. Therefore, the aspect ratio of the channel structure 212 has been significantly increased, which has brought many challenges in various processes, such as the etching process for forming the channel hole 336 that penetrates the entire film stack 335, and removing the storage film from the bottom of the channel hole 336 to connect the channel layer 338 to the epitaxial layer or substrate 330.

[0047] In view of the complexity of manufacturing 3D memory, a double stack structure and a multi-stack structure have been developed. Taking the double stack structure as an example, in the double stack 3D memory, the vertically stacked memory cell is divided into two parts, namely an upper stack and a lower stack, wherein the lower stack and the upper stack can be formed sequentially. For example, the lower stack of the film stack 335 can be formed first, wherein the channel hole 336 can be etched only for the lower stack. Then, the upper stack of the film stack 335 can be formed on top of the lower stack, wherein the channel hole can be etched again for the upper stack using a separate photolithography process. The double stack structure and the two-step process can reduce the complexity of high aspect ratio etching or film deposition.

[0048] Figure 4 1 shows a cross-sectional view of a 3D memory device having a double stack structure during manufacturing according to some embodiments of the present disclosure. Figure 4As shown in the schematic diagram (a) in FIG. 4 , a first dielectric stack 450-1 consisting of an interlaced insulating layer 452 and a sacrificial layer 454 is formed on a substrate 430, and a lower channel hole 412-1 and a lower gate gap 416-1 vertically extend through the first dielectric stack 450-1 and extend into the substrate 430. In an embodiment, the sacrificial layer 454 may be a nitride material, such as silicon nitride. In an embodiment, the insulating layer 452 may be an oxide material, such as silicon oxide. In an embodiment, the manufacturing process for forming the channel hole and the gate gap includes wet etching and / or dry etching, such as deep reactive ion etching (DRIE). In this structure, optionally, the lower channel hole 412-1 and the lower gate gap 16-1 can be formed by the same mask, the same photolithography and etching process, or they can be formed separately by different photolithography processes, wherein the former process can greatly simplify the process and save production costs because the masks used for the channel hole and the gate gap are combined into the same mask. This process can also be called a mask merging process.

[0049] In the formation Figure 4 After the structure shown in the schematic diagram (a) in FIG. 1 is formed, a sacrificial material 440 may be further filled in the lower channel hole 412-1 and the lower gate gap 416-1, as shown in FIG. Figure 4 As shown in the schematic diagram (b) in FIG. Figure 4 As shown in the schematic diagram (b) in the figure, a second dielectric stack 450-2 composed of staggered sacrificial layers and insulating layers is further formed on the first dielectric stack 450-1, and the upper channel hole 412-2 and the upper gate gap 416-2 extend vertically through the second dielectric stack 450-2 and land on the corresponding lower channel hole 412-1 and lower gate gap 416-1 below, respectively, to form an overall channel hole and gate gap.

[0050] In the formation of Figure 4 After the structure shown in the schematic diagram (b) in FIG. 1 , a channel structure including a storage film and a gate isolation structure obtained by filling the gate gap can be further formed through processes known in the art, and the present disclosure does not specifically limit this.

[0051] In the above-mentioned 3D memory device composed of, for example, a double stack structure, an additional photolithography step needs to be added to realize the segmented formation of the channel structure. However, the additional photolithography step may cause an overlay error between the upper stack and the lower stack, resulting in the lower channel hole 412-1 and the upper channel hole 412-2 being unable to align with each other at the interface I0 between the first dielectric stack 450-1 and the second dielectric stack 450-2, which may cause damage to the channel structure, fail to form a workable channel structure, and / or may cause leakage of the word line.

[0052] According to an embodiment of the present disclosure, Figure 4 As shown in , the alignment tolerance can be increased by forming the channel hole to have a tapered cross section. Figure 4 In the cross section shown in the schematic diagram (b) in FIG. 1 , the top widths of the lower channel hole 412-1 and the upper channel hole 412-2 are both greater than their respective bottom widths, and accordingly, at the interface I0, the width of the lower channel hole 412-1 is greater than the width of the upper channel hole 412-2, thereby achieving relatively good alignment. The lower gate slit 416-1 and the upper gate slit 416-2 can also achieve alignment optimization in this way.

[0053] However, the present disclosure further notes that as the number of material layers in the stacked structure continues to increase, the channel holes formed by etching generally do not extend strictly in the vertical direction (Z direction), but may be systematically tilted, that is, the channel holes are at a certain angle to the Z direction. Moreover, the closer the channel holes are to the gate gap, the more serious their tilt may be. This phenomenon is particularly prominent when the mask merging process mentioned above is adopted. This can be attributed to, for example, uneven local load of the channel holes, material selection, differences in process conditions, etc.

[0054] Figure 5 A cross-sectional view of a 3D memory device having a double stacked structure during manufacturing in which a channel hole tilt occurs according to some embodiments of the present disclosure is illustrated. Figure 5 As shown in the schematic diagram (a) in FIG. 1 , the upper end of the lower channel hole 412-1 formed in the first dielectric stack 450-1 is tilted toward the lower gate slit 416-1. Accordingly, an angle θ (hereinafter referred to as the tilt angle θ) is formed between the center line of the channel hole 412-1 and the vertical direction (Z direction). The present disclosure notes that the closer the channel hole 412-1 is to the gate slit, the more serious its tilt will be, that is, the larger the angle θ will be.

[0055] In this case, if the same mask is still used to form the upper channel hole 412-2 in the second dielectric stack 450-2, even if the channel hole is formed to have a conical cross-section, a mismatch that is difficult to align is likely to occur between the lower channel hole 412-1 and the upper channel hole 412-2 at the interface I0 between the first dielectric stack 450-1 and the second dielectric stack 450-2, especially for several rows of channel holes close to the gate gap structure.

[0056] like Figure 5 As shown in the cross-sectional view (b) in FIG. 1 , at the interface I0, a serious deviation occurs between the lower channel hole 412-1 and the upper channel hole 412-2, which may cause damage to the channel structure, failure to form a workable channel structure and / or may cause leakage of the word line.

[0057] In view of the above findings, the present disclosure further proposes to overcome or improve the above channel hole mismatch by performing pre-compensation at the mask layout design stage.

[0058] Fig. 6A A cross-sectional view of a 3D memory device with a double stack structure during manufacturing according to some embodiments of the present disclosure is shown, wherein the misalignment at the interface I0 caused by the tilt of the channel hole is compensated by modifying the layout design of the mask, thereby achieving alignment between the lower channel hole and the upper channel hole and alignment of the channel structure in the corresponding final device. Fig. 6A As shown in FIG. 1 , at the interface I0 , the corresponding lower channel hole 412 - 1 is substantially aligned with the upper channel hole 412 - 2 , and the lower gate slit 416 - 1 is substantially aligned with the upper gate slit 416 - 2 . Figure 6B A cross-sectional view of an exemplary 3D memory device including a double stacked structure obtained according to some embodiments of the present disclosure is shown. Figure 6B As shown in FIG. 1 , at the interface I0 ′, the corresponding lower first channel structure 412 ′- 1 is substantially aligned with the upper second channel structure 412 ′- 2 , and the lower first gate isolation structure 416 ′- 1 is substantially aligned with the upper second gate isolation structure 416 ′- 2 .

[0059] Fig. 7A , 7B 7C shows a schematic top view of a mask used in a manufacturing process of a region of a 3D memory device according to some embodiments of the present disclosure.

[0060] Fig. 7AA top view of a mask 700 - 1 including a pattern to form a lower gate slit 416 - 1 and a lower channel hole 412 - 1 in a first dielectric stack 450 - 1 is shown according to some embodiments of the present disclosure. Figure 7B A top view of a mask 700 - 2 including a pattern to form an upper gate slit 416 - 2 and an upper channel hole 412 - 2 in the second dielectric stack 450 - 2 is shown, according to some embodiments of the present disclosure.

[0061] like Fig. 7A As shown in FIG. 1 , in the case of the first dielectric stack 450-1 (see FIG. Fig. 6A ) includes a lower gate slit pattern 716-1 extending in a first direction (X direction) and corresponding to the lower gate slit 416-1, and a plurality of channel hole patterns 712-1 arranged in an array on both sides of the lower gate slit pattern 716-1. In an embodiment, the plurality of channel hole patterns 712-1 are symmetrically arranged in two arrays relative to the lower gate slit pattern 716-1. Taking the channel hole pattern array arranged above the lower gate slit pattern 716-1 in the second direction (Y direction) perpendicular to the first direction as an example, the spacing between the center line of the first row of channel hole patterns R1-1 along the X direction and the center line of the lower gate slit pattern 716-1 along the X direction is L1. It should be noted that, in the embodiment, the first row of channel hole patterns R1-1 can be a row of channel hole patterns closest to the lower gate gap pattern 716-1, or any row of channel hole patterns in the channel hole pattern array, as long as the rows of channel hole patterns satisfy the relative position relationship shown in the figure.

[0062] like Figure 7B As shown in FIG. 1 , in the case of the second dielectric stack 450-2 (see FIG. Fig. 6A ) in the pattern of the mask 700-2, similarly includes an upper gate slit pattern 716-2 extending in the first direction (X direction) and corresponding to the upper gate slit 416-2, and a plurality of channel hole patterns 712-2 arranged in an array on both sides of the upper gate slit pattern 716-2. In an embodiment, the plurality of channel hole patterns 712-2 are symmetrically arranged in two arrays relative to the upper gate slit pattern 716-2. Also, taking the channel hole pattern array arranged above the upper gate slit pattern 716-2 in the second direction (Y direction) as an example, the spacing between the center line of the first row of channel hole patterns R1-2 along the X direction and the center line of the upper gate slit pattern 716-2 along the X direction is L2. It should also be noted that, in the embodiment, the first row of channel hole patterns R1-2 can be either a row of channel hole patterns closest to the upper gate gap pattern 716-2, or any row of channel hole patterns in the channel hole pattern array, as long as the rows of channel hole patterns satisfy the relative position relationship shown in the figure and are consistent with the upper gate gap pattern 716-2. Fig. 7A It only needs to correspond to the first row of channel hole pattern R1-1 in .

[0063] According to the present disclosure, by appropriately adjusting and compensating the mask 700-2 relative to the mask 700-1, when the etched channel hole is tilted due to uneven local load, etc., it is ensured that the channel holes formed in the lower first dielectric stack 450-1 and the upper second dielectric stack 450-2 are substantially aligned at the interface I0, as shown in FIG. Fig. 6A as shown in .

[0064] Accordingly, in the above example, the spacings L1 and L2 are different from each other, wherein L2 can be determined according to one or more of factors such as the size of the spacing L2, the inclination angle θ of each of the lower channel hole 412-1 and the upper channel hole 412-2, the thickness of the second dielectric stack 450-2, the etching process used to form the channel hole, etc. In an embodiment using a mask merging process, the channel hole may be more likely to be inclined toward the gate gap structure at the top, in which case L2 may be set to be smaller than L1.

[0065] Similarly, other rows of channel hole patterns in the mask 700-2 may also be adjusted and compensated accordingly with respect to the mask 700-1. In other words, the spacing between any row of channel hole patterns in the mask 700-1 and the lower gate slit pattern 716-1 and the spacing between a corresponding row of channel hole patterns in the mask 700-2 and the upper gate slit pattern 716-2 may all be subject to the above rules. It should be noted that, in an embodiment, adjustments may also be made only for a specific row or rows of channel hole patterns, which is not limited in the present disclosure.

[0066] The present disclosure also notes that the closer the channel hole is to the gate gap 416, the higher its inclination tends to be. In view of this phenomenon, on the one hand, according to some embodiments, in the direction away from the corresponding gate gap structure, the difference between the first distance and the second distance can be set to gradually decrease. On the other hand, in an embodiment, the spacing between the rows of channel hole patterns in the masks 700-1 and 700-2 can be set to be gradual. In an embodiment, as Fig. 7AAs shown in , the spacing between the center line of the second row of channel hole patterns R2-1 and the center line of the first row of channel hole patterns R1-1 in the mask 700-1 is d1, and the spacing between the center line of the third row of channel hole patterns R3-1 and the center line of the second row of channel hole patterns R2-1 is d2, where d1>d2. In an embodiment, L1>d1>d2. The situation of the channel hole patterns in other rows can be deduced by analogy, that is, the distance between two adjacent rows of channel hole patterns gradually decreases in the direction away from the gate gap pattern. In an embodiment, this gradual spacing setting can be applied only to 2 or more rows of channel hole patterns close to the gate gap.

[0067] Similarly, if Figure 7B As shown in , the channel hole pattern in the mask 700-2 can also be set to a corresponding gradient. In an embodiment, the corresponding spacing in the mask 700-2 can be the same as that in the mask 700-1. For example, the spacing between the center line of the second row of channel hole pattern R2-2 and the center line of the first row of channel hole pattern R1-2 can also be d1, and the spacing between the center line of the third row of channel hole pattern R3-2 and the center line of the second row of channel hole pattern R2-2 can also be d2. Through this mask setting, the alignment accuracy between the lower channel hole 412-1 and the upper channel hole 412-2 can be further improved, and the performance and yield rate of the resulting device can be improved.

[0068] In addition, Fig. 7A and Figure 7B In the mask pattern shown, adjacent rows of channel hole patterns are arranged to be aligned with each other in the Y direction; in an embodiment, adjacent rows of channel hole patterns may also be arranged in a staggered arrangement. Figure 7C As shown in FIG. 7 , the channel hole pattern 712 in the first row of channel hole patterns R1 and the channel hole pattern 712 in the second row of channel hole patterns R2 located on one side of the gate gap pattern 716 are not aligned in the Y direction, but are staggered with each other. In this way, the spacing between the channel hole patterns in adjacent rows can be further reduced, thereby increasing the arrangement density of the channel holes in the resulting three-dimensional memory device.

[0069] It should be noted that although in the above public content, Fig. 7A and Figure 7B The icons 700-1 and 700-2 shown in FIG. 1 are respectively described as masks corresponding to the first and second dielectric stacks 450-1 and 450-2, which can also be used to indicate the Fig. 6A A top view of the interface I0 in and the upper surface S of the second dielectric stack 450-2. In this context, Fig. 6A Shown by Figure 7B The cross section is taken along the line C-C' in FIG. 1 , where for the convenience of illustration, Fig. 6AOnly three channel holes 412 located on both sides of the gate gap 416 are shown. Alternatively, Fig. 7A and Figure 7B The icons 700-1 and 700-2 shown in FIG. 1 can also be used to indicate Fig. 6A FIG. 4 is a top view of a cross section parallel to the substrate (XY plane) at a specific height of the first and second dielectric stacks 450 - 1 and 450 - 2 in FIG.

[0070] Similarly, Fig. 7A and Figure 7B The icons 700-1 and 700-2 shown in FIG. 1 can also be used to indicate: Figure 6B , a top view of an interface I0′ between a lower first stacking structure 450′-1 and an upper second stacking structure 450′-2 in a three-dimensional memory device including a dual stacking structure obtained according to some embodiments of the present disclosure, and an upper surface S′ of the second stacking structure 450′-2. In this context, Figure 6B Shown by Figure 7B The cross section is taken along the line C-C' in FIG. 1 , where for the convenience of illustration, Figure 6B Only three channel structures 412' located on both sides of the gate isolation structure 416' are shown. According to an embodiment, Figure 6B The three-dimensional memory device structure shown in Fig. 6A The corresponding manufacturing process is then further formed by a process known in the art. For example, the three-dimensional memory device structure may include a conductive layer 454' formed by replacing the sacrificial layer 454 with a conductive material, a channel structure 412' including a storage film, etc. formed by filling the channel hole 412, and a gate isolation structure 416' formed by filling the gate gap 416, which is not particularly limited in the present disclosure.

[0071] According to an embodiment, a three-dimensional memory device obtained by using the present disclosure may have the following features, including a first stacked structure 450'-1 and a second stacked structure 450'-2, wherein the first stacked structure 450'-1 includes a first gate isolation structure 416'-1 extending in a first direction (X direction) (corresponding to Fig. 7A Icon 716-1 in FIG. 716-1) and a plurality of first channel structures 412'-1 arranged in an array (corresponding to Fig. 7A712-1 in the figure), wherein, in a second direction (Y direction) perpendicular to the first direction (X direction), a row of first channel structures (taking R1-1 as an example) arranged in the first direction (X direction) among the plurality of first channel structures has a first distance L1 from the first gate isolation structure; a second stacked structure 450'-2 is stacked above the first stacked structure 450'-1, and includes a second gate isolation structure 416'-2 extending in the first direction (X direction) (corresponding to Figure 7B Icon 716-2 in FIG. 716-2) and a plurality of second channel structures 412'-2 arranged in an array (corresponding to Figure 7B 712-2 in the figure), wherein, in the second direction (Y direction), a row of second channel structures (e.g., R1-2) among the plurality of second channel structures corresponding to the row of first channel structures has a second distance L2 with the second gate isolation structure, and wherein the second distance L2 is different from the first distance L1. The above structural features characterize the adoption of the compensation scheme of the present disclosure in the product, and accordingly can benefit from improved channel structure alignment accuracy and improved device performance and yield.

[0072] In an embodiment, Fig. 7A and Figure 7B The icons 700-1 and 700-2 shown in FIG. 1 can also be used to indicate Figure 6B FIG. 4 is a top view of a cross section parallel to the substrate (XY plane) at a specific height of the first and second stack structures 450 ′- 1 and 450 ′- 2 in FIG.

[0073] According to the embodiment, reference Figure 5 , Figure 6B and Fig. 7A As shown, in the three-dimensional memory device including the double stack structure obtained according to the present disclosure, the extension direction of the channel structure 412'-1 in the row of first channel structures (taking R1-1 as an example) forms a first angle with the Z direction, and the channel structure 412'-2 in the row of second channel structures (taking R1-2 as an example) forms a second angle with the Z direction. In an embodiment, the first angle is equal to the second angle.

[0074] In an embodiment, in a three-dimensional memory device including a dual stacked structure obtained according to the present disclosure, the first gate isolation structure 416'-1 in the first stacked structure 450'-1 and the second gate isolation structure 416'-2 in the second stacked structure 450'-2 may be integrally formed to further simplify the process.

[0075] According to this disclosure, Figure 7C The pattern shown in can also be used to indicate: Fig. 6Aor a top view of the interface I0 in the second dielectric stack 450-2 or a top view of the upper surface S of the second dielectric stack 450-2, or Fig. 6A A top view of a cross section parallel to the substrate (XY plane) at a specific height of the first dielectric stack 450-1 or the second dielectric stack 450-2 in FIG. Figure 7C The pattern shown in can also be used to indicate: Figure 6B A top view of the interface I0′ or the upper surface S′ of the second stacked structure 450′-2, or Figure 6B FIG. 4 is a top view of a cross section parallel to the substrate (XY plane) at a specific height of the first and second stack structures 450 ′- 1 and 450 ′- 2 in FIG.

[0076] It should be noted that all the relevant features described above in the context of "mask" are also applicable in other contexts. Fig. 7A and 7B The icons 700-1 and 700-2 shown in the figure are used to indicate the interface I0' between the lower and upper stacked structures 450'-1 and 450'-2 in the three-dimensional memory device and the top view of the upper surface S' of the upper stacked structure 450'-2, and the spacing between the channel structures in each row also satisfies the characteristics such as gradual change described in the context of "mask". Since the corresponding relationship between the elements is clear and explicit to those skilled in the art, a repeated description is not given.

[0077] In addition, although the double stack structure is described as an example in the present disclosure, the present disclosure is not limited thereto. As can be understood by those skilled in the art, the present disclosure can also be applied to a multi-stack structure in which the channel hole is divided into three or more parts.

[0078] Figure 8 FIG. 8 is a flow chart showing a method 800 for forming a three-dimensional memory device according to an embodiment of the present disclosure. Figure 5 , Fig. 6A , Fig. 7A , Figure 7B It should be understood that the operations shown in method 800 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in parallel. Figure 8 The different orders are shown.

[0079] like Figure 8 As shown, at step S810, a first dielectric stack consisting of alternating sacrificial layers and insulating layers is formed.

[0080] At step S820, a first gate gap structure extending in a first direction and a plurality of first channel holes arranged in an array are formed in the first dielectric stack. In an embodiment, the first gate gap structure and the plurality of first channel holes are formed using, for example, the mask 700-1 shown in FIG. 7A. Figure 5 Schematic diagram (a), a gate gap structure 416-1 and a plurality of first channel holes 412-1 are formed in the first dielectric stack 450-1, wherein Fig. 7A As shown in , the first gate gap structure (corresponding to 716-1) extends in the X direction, and the first channel holes (corresponding to 712-1) are arranged in an array; and wherein, in the Y direction, a row of first channel holes (e.g., R1-1) arranged in the X direction among the plurality of first channel holes has a first distance L1 between it and the first gate gap structure.

[0081] At step S830, in the first dielectric stack (see Fig. 6A A second dielectric stack is formed above the first dielectric stack 450-1 in FIG. Fig. 6A The second dielectric stack 450-2 in FIG.

[0082] At step S840, a second gate gap structure extending in the first direction and a plurality of second channel holes arranged in an array are formed in the second dielectric stack. In an embodiment, the second gate gap structure and the plurality of second channel holes are formed using, for example, the mask 700-2 shown in FIG. 7B. Fig. 6A , a gate gap structure 416-2 and a plurality of second channel holes 412-2 are formed in the second dielectric stack 450-2, wherein Figure 7B As shown in , the second gate gap structure (corresponding to 716-2) extends in the X direction, and the second channel holes (corresponding to 712-2) are arranged in an array; and wherein, in the Y direction, the plurality of second channel holes are aligned with the row of first channel holes (corresponding to Fig. 7A A second distance L2 exists between a row of second channel holes (eg, R1-2) corresponding to 712-1) and the second gate gap structure, and the second distance L2 is different from the first distance L1.

[0083] In the method for forming a three-dimensional memory device according to the present disclosure, the following method may be used: Fig. 7A , 7B , the mask shown in 7C, so accordingly, the mask may have all or part of the features described above with respect to these figures, which will not be repeated here.

[0084] According to the present disclosure, when the etched channel hole is tilted due to uneven local load, etc., it is possible to ensure that the channel hole formed in the lower first dielectric stack 450-1 and the upper second dielectric stack 450-2 remain aligned at the interface I0; accordingly, it is ensured that the channel structures in the lower first stacking structure 450'-1 and the upper second stacking structure 450'-2 in the obtained 3D memory device remain aligned at the interface I0'. The improved alignment accuracy can improve the performance and yield of the manufactured three-dimensional memory device. On the other hand, compared with the solution that challenges overcoming the problem of channel hole tilt by solving the problem of uneven local load, the present disclosure has significant time and cost advantages.

[0085] Fig. 9 1 shows a block diagram of an exemplary system 900 having a 3D storage device according to an embodiment of the present disclosure. The system 900 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Fig. 9 As shown in , system 900 may include a host 908 and a storage system 902, the storage system 902 having one or more 3D storage devices 904 and a memory controller 906. The host 908 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 908 may be configured to send or receive data to or from the storage device 904. In order to send or receive data to or from the storage device 904, the host 908 may also send instructions to the storage system 902 in addition to the data.

[0086] The 3D memory device 904 may be any 3D memory device / semiconductor structure disclosed herein. In some embodiments, each 3D memory device 904 may include a NAND flash memory. Consistent with the scope of the present disclosure, the 3D memory device 904 may be made by forming a stacked structure laterally on a substrate. The stacked structure may have a storage array region and a connection region. Next, a plurality of channel holes extending vertically in the storage array region may be formed and the channel holes may be filled to form a plurality of channel structures. Then, a plurality of contact plugs may be formed in the connection region. Since part of the initial stacked structure is removed in advance, after the channel holes are filled to form the channel structure, the final storage array region is substantially flush with the connection region. Therefore, the performance of the 3D memory device 904 may be improved, which in turn may improve the performance of the storage system 902 and the system 900.

[0087] According to some embodiments, the memory controller 906 is coupled to the 3D memory device 904 and the host 908, and is configured to control the 3D memory device 904. The memory controller 906 may manage data stored in the 3D memory device 904 and communicate with the host 908. In some embodiments, the memory controller 906 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 906 is designed to operate in a high duty cycle environment, such as an SSD or an embedded Multimedia Card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc. and an enterprise storage array. The memory controller 906 may be configured to control operations of the 3D memory device 904, such as read, erase, and program operations. The memory controller 906 may also be configured to manage various functions related to data stored or to be stored in the 3D storage device 904, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 906 is also configured to process error correction codes (ECC) related to data read from or written to the 3D storage device 904. Any other suitable functions may also be performed by the memory controller 906, such as formatting the 3D storage device 904. The memory controller 906 may communicate with an external device (e.g., a host 908) according to a specific communication protocol.For example, the memory controller 906 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, high-speed PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Drive Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0088] The above description of specific embodiments reveals the general nature of the present disclosure, so that those skilled in the art can easily modify and / or adapt these specific embodiments for various applications by applying the knowledge within the art, without excessive experimentation, and without departing from the general concept of the present disclosure. For example, when different material combinations are used to form a material stack structure, due to different situations of uneven local loads, the channel hole may also tilt away from the gate gap structure at the top. In this case, the first distance L1 and the second distance L2 also need to be adjusted accordingly, which is conceivable by those skilled in the art based on the teachings of the present disclosure. Therefore, based on the disclosure and guidance given herein, such adaptations and modifications are intended to be within the meaning and scope of the equivalents of the disclosed embodiments. It is to be understood that the wording or terminology herein is for descriptive purposes rather than for limiting purposes, so that the terms or wording of this specification will be interpreted by the technician based on the disclosure and guidance.

[0089] The Summary and Abstract sections may set forth one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0090] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional storage device, comprising: A first stacked structure, comprising a first gate isolation structure extending in a first direction and a plurality of first channel structures arranged in an array, wherein in a second direction perpendicular to the first direction, a first distance exists between a row of first channel structures arranged in the first direction and the first gate isolation structure among the plurality of first channel structures; A second stacked structure is stacked above the first stacked structure and includes a second gate isolation structure extending in the first direction and a plurality of second channel structures arranged in an array, wherein in the second direction, a row of second channel structures among the plurality of second channel structures corresponding to the row of first channel structures has a second distance from the second gate isolation structure, and wherein the second distance is different from the first distance.

2. The memory device according to claim 1, wherein: At an interface between the second stacked structure and the first stacked structure, a channel structure of the plurality of first channel structures is aligned with a corresponding channel structure of the plurality of second channel structures, and the first gate isolation structure is aligned with the second gate isolation structure.

3. The memory device according to claim 1, wherein: The first distance is measured on a plane where the interface between the second stacking structure and the first stacking structure is located, from a center line of the row of first channel structures along the first direction to a center line of the first gate isolation structure along the first direction, and the second distance is measured on a plane where a surface of the second stacking structure opposite to the interface is located, from a center line of the row of second channel structures along the first direction to a center line of the second gate isolation structure along the first direction.

4. The memory device according to claim 1, wherein: On the interface between the second stacking structure and the first stacking structure, the spacing between two adjacent rows of the first channel structures gradually decreases in a direction away from the first gate isolation structure, and wherein, on the surface of the second stacking structure opposite to the interface, the spacing between two adjacent rows of the second channel structures gradually decreases in a direction away from the second gate isolation structure.

5. The memory device according to claim 1, wherein: In a direction away from the corresponding gate isolation structure, the difference between the first distance and the second distance gradually decreases.

6. The memory device according to claim 1, wherein: An extension direction of the channel structures in the row of first channel structures forms a first angle with a third direction perpendicular to the first direction and the second direction, and an extension direction of the channel structures in the row of second channel structures forms a second angle with the third direction.

7. The memory device according to claim 6, wherein: The first angle is equal to the second angle.

8. The memory device according to claim 6, wherein: The second distance is determined according to at least one of the following items: the first distance, the first angle, the second angle, the thickness of the second stacked structure, and an etching process used to form the channel hole.

9. The memory device according to claim 1, wherein: The first gate isolation structure and the second gate isolation structure are formed integrally.

10. The memory device according to claim 1, wherein: The plurality of first channel structures are symmetrically arranged in two arrays with respect to the first gate isolation structure, and the plurality of second channel structures are symmetrically arranged in two arrays with respect to the second gate isolation structure.

11. The memory device according to claim 1, wherein: The plurality of first channel structures and the first gate isolation structure are realized by using a first mask, and the plurality of second channel structures and the second gate isolation structure are realized by using a second mask.

12. The memory device according to claim 1, wherein: The channel structures in adjacent rows among the plurality of first channel structures are arranged in a staggered manner, and the channel structures in adjacent rows among the plurality of second channel structures are arranged in a staggered manner.

13. A method for forming a three-dimensional memory device, comprising: forming a first dielectric stack; A first gate gap structure extending in a first direction and a plurality of first channel holes arranged in an array are formed in the first dielectric stack, wherein in a second direction perpendicular to the first direction, a row of first channel holes arranged in the first direction among the plurality of first channel holes has a first distance from the first gate gap structure; forming a second dielectric stack over the first dielectric stack; and A second gate gap structure extending in the first direction and a plurality of second channel holes arranged in an array are formed in the second dielectric stack, wherein in the second direction, a row of second channel holes among the plurality of second channel holes corresponding to the row of first channel holes has a second distance from the second gate gap structure, and wherein the second distance is different from the first distance.

14. The method according to claim 13, wherein: The first gate gap structure and the plurality of first channel holes are formed in the first dielectric stack using a first mask, and the second gate gap structure and the plurality of second channel holes are formed in the second dielectric stack using a second mask.

15. The method according to claim 14, wherein: Forming the second dielectric stack includes forming a material stack at the first surface of the first dielectric stack, and wherein the second gate gap structure and the plurality of second channel holes are formed in the second dielectric stack using the second mask, so that at the first surface, the channel holes among the plurality of first channel holes are aligned with corresponding channel holes among the plurality of second channel holes, and the first gate gap structure is aligned with the second gate gap structure.

16. The method according to claim 14, wherein: In the first mask, the spacing between two rows of patterns corresponding to two adjacent rows of the first channel holes gradually decreases in a direction away from the pattern corresponding to the first gate gap structure; and wherein, in the second mask, the spacing between two rows of patterns corresponding to two adjacent rows of the second channel holes gradually decreases in a direction away from the pattern corresponding to the second gate gap structure.

17. The method according to claim 14, wherein: In the first mask, patterns of channel holes corresponding to adjacent rows of the plurality of first channel holes are staggered; and wherein in the second mask, patterns of channel holes corresponding to adjacent rows of the plurality of second channel holes are staggered.

18. A storage system comprising: At least one three-dimensional memory device according to any one of claims 1 to 12; as well as A memory controller is coupled to the three-dimensional memory device and is configured to control the three-dimensional memory device.

19. The memory system of claim 18, further comprising a host coupled to the memory controller and configured to send or receive the data.

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