Thin film device with high pixel density, photosensitive device and display device

Abstract

The invention discloses a thin film device with high pixel density, a photosensitive device and a display device. The thin film device is characterized in that a bottom metal electrode array is formed on a back plate; passivating a compact and pinhole-free metal compound film layer on the free surface of the bottom metal electrode to completely cover the bottom metal electrode; the metal compound film layer located on the upper surface of the bottom metal electrode is a P-type or N-type semiconductor and forms ohmic contact with the upper surface of the bottom metal electrode; and sequentially forming a continuous / non-patterned active layer, a continuous / non-patterned upper charge transport layer, a continuous / non-patterned top metal electrode and a continuous / non-patterned transparent packaging layer on the metal compound thin film layer from bottom to top. According to the invention, the metal compound film layer wrapping the bottom metal electrodes is passivated, so that the problem of current leakage between adjacent pixels caused by too small distance between two patterned adjacent bottom metal electrodes is avoided, and the definition is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic devices, and more specifically, to a thin film device, a photosensitive device and a display device with high pixel density. Background Art

[0002] Infrared photodetectors and imaging arrays have great application potential in artificial intelligence, machine vision, stereo integrated circuit chip preparation and online detection, health monitoring and biometric detection. However, existing infrared photodetectors made of inorganic semiconductor crystal materials (such as Ge, InGaAs) have the defects of high dark current and low detection rate at room temperature. Photodetectors and imaging arrays based on such materials require active cooling to reduce thermal noise, especially for applications with low light intensity. However, the size and power consumption of currently used thermoelectric coolers make them unusable in battery-powered portable applications.

[0003] The optoelectronic imaging array used in infrared cameras requires high-purity, large-size, low-defect-density semiconductor crystals to be processed into a PIN structure; then the imaging element is photolithographically formed to form a sensor array. Pixel formation includes deep trench etching of the PIN structure at the pixel scale, post-surface treatment, encapsulation passivation, and bonding with a complementary metal oxide semiconductor (CMOS)-based readout circuit integrated array on a silicon wafer. These processes limit the pixel size, total number of pixels, and manufacturing yield, thereby limiting system cost. In addition, imperfect etching processes and post-passivation can also lead to charge traps in the semiconductor energy gap, which also limits device performance and manufacturing yield.

[0004] In contrast, thin-film photodetectors based on organic semiconductors offer new opportunities for wearable electronics and image sensing due to their excellent mechanical flexibility, bandgap tunability, and direct on-wafer integration into CMOS integrated circuits. In addition, organic semiconductors have high light absorption coefficients (typically >10 5 cm 2 ), moderate carrier mobility and low charge trap density within the energy gap, these properties make low-cost, large-area, high-pixel-count thin-film optical display or thin-film optical detection image array possible without the need for patterning the active layer (G. Yu et al., "Large-area full-color image sensor made of semiconductor polymers", Adv. Materials 10, 1431 (1998)).

[0005] Whether this simple array structure with a non-patterned active layer can be used for image arrays with small pixel pitch and photosensitive (or luminescent) arrays in PIN structures remains to be solved. This is because the non-patterned lower charge transfer layer between the active layer and the patterned bottom metal electrode will cause current leakage between adjacent pixels. This leakage will cause image blur and reduce image contrast when the image pixel pitch is too small.

[0006] Therefore, it is necessary to pattern the lower charge transport layer on the patterned bottom metal electrode. However, when the pixel pitch is reduced to the micron or submicron level, the alignment of the patterned lower charge transport layer pattern with the bottom metal electrode pattern becomes a challenge, especially in image arrays with a total pixel number exceeding one million (commonly referred to as million-pixel focal plane arrays). Summary of the invention

[0007] In order to solve the problem of current leakage between adjacent pixels due to the non-patterned lower charge transfer layer between the active layer and the patterned bottom metal electrode in the above prior art, the present invention provides a thin film device, a photosensitive device and a display device with high pixel density.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0009] A thin film device with high pixel density, comprising:

[0010] forming a bottom metal electrode array on the backplane;

[0011] Passivating a dense, pinhole-free metal compound thin film layer on the free surface of the bottom metal electrode in the bottom metal electrode array to completely cover the bottom metal electrode;

[0012] Wherein, the metal compound thin film layer located on the upper surface of the bottom metal electrode is a P-type or N-type semiconductor and forms an ohmic contact with the upper surface of the bottom metal electrode;

[0013] A continuous / non-patterned active layer, a continuous / non-patterned upper charge transport layer, a continuous / non-patterned top metal electrode, and a continuous / non-patterned transparent encapsulation layer are sequentially formed on the metal compound thin film layer from bottom to top.

[0014] Preferably, a dense, pinhole-free metal compound film layer is passivated on the free surface of the bottom metal electrode in the bottom metal electrode array, including: using a self-aligned process to perform surface chemical reaction on the free surface of the bottom metal electrode to form a dense, pinhole-free metal compound film layer.

[0015] Furthermore, the surface chemical reaction includes one or more combinations of anodic oxidation, oxygen plasma oxidation, high temperature thermal oxidation, chemical oxidation, and sulfurization.

[0016] Furthermore, the specific process steps of the anodizing are as follows:

[0017] After the bottom metal electrode arrays of multiple thin film devices are prepared on the wafer,

[0018] Cleaning the free surface of the bottom metal electrode;

[0019] immersing the bottom metal electrode array on the wafer in a non-strong acid anodizing solution;

[0020] First, a metal compound thin film layer is formed under a constant current until the thickness of the metal compound thin film layer reaches a voltage corresponding to a target thickness;

[0021] Then, the voltage corresponding to the target thickness is maintained at a constant voltage until the oxidation current decreases to a certain threshold of the constant current, thereby ending the anodization.

[0022] Preferably, when the bottom metal electrode is a metal layer, the metal compound film layer passivated on the upper surface and sidewall of the metal layer is a P-type or N-type semiconductor;

[0023] When the bottom metal electrode is two or more metal layers, the metal compound film layer passivated on the upper surface of the topmost metal layer is a P-type or N-type semiconductor; the metal compound film layer passivated on the side walls of the remaining metal layers is an insulating layer, or a P-type semiconductor, or an N-type semiconductor.

[0024] Preferably, the thickness of the metal compound thin film layer is 5nm-100nm.

[0025] Furthermore, the thickness of the metal compound thin film layer is 10nm-50nm.

[0026] Preferably, the average surface roughness of the metal compound thin film layer is less than 5 nm.

[0027] Furthermore, the average surface roughness of the metal compound thin film layer is less than 3 nm.

[0028] Preferably, the carrier concentration of the metal compound thin film layer is in the range of 10 15 cm -3 -10 20 cm -3 .

[0029] Furthermore, the carrier concentration of the metal compound thin film layer is in the range of 10 16 cm -3 -10 19 cm -3 .

[0030] Preferably, the energy gap of the metal compound thin film layer is greater than the energy gap of the active layer.

[0031] Preferably, when the metal compound thin film layer is of P type, the material of the metal compound thin film layer includes oxides or sulfides of Cu, Cr, Ni, V, Ga, W, Zr or Mo, or oxides or sulfides of their metal alloys.

[0032] Preferably, when the metal compound thin film layer is of N type, the material of the metal compound thin film layer includes oxides of Ti, Ta, Zn, In, Sn, Mg, Hf, Nd, or Nb, or oxides of metal alloys thereof.

[0033] Preferably, the method further comprises: adding a surface promoting material between the metal compound film layer and the active layer for improving adhesion and reducing surface defects at the interface.

[0034] Preferably, the active layer comprises an organic semiconductor in the form of a single-phase film or a D / A bulk heterojunction blended film, an inorganic semiconductor or a compound semiconductor in the form of a single-phase or quantum dot nanoparticle, or a combination in a mixed form or a thin film stack; wherein D represents an organic molecule of an electron donor; A represents an organic molecule of an electron acceptor;

[0035] Wherein, the inorganic semiconductor includes Si, Ge, SiGe, CuInS in crystalline or polycrystalline form. x Se 2-x (0≤x≤2), CuInGa(S,Se), PbS, PbI2, PBI3, InGaAs nano-quantum dots or nano-quantum films, or single-phase films;

[0036] The organic semiconductor includes an organic blend of one or more organic molecules used as electron donors (D) and one or more organic molecules used as electron acceptors (A) to form D / A.

[0037] A photosensitive device, comprising a back plate with a plurality of pixel readout circuits integrated therein, and the thin film device with high pixel density arranged on the back plate;

[0038] The active layer serves as a photosensitive layer for detecting light incident on the photosensitive device;

[0039] Each of the pixel readout circuits is connected to a corresponding bottom metal electrode through a metal conductive column.

[0040] A display device, comprising a backplane with a plurality of pixel driving circuits integrated therein, and the thin film device with high pixel density arranged on the backplane;

[0041] The active layer is used as a light-emitting layer to generate light for light-emitting display;

[0042] Each of the pixel driving circuits is connected to a corresponding bottom metal electrode through a metal guide column.

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] The present invention passivates a dense, pinhole-free metal compound film layer on the free surface of each bottom metal electrode in the bottom metal electrode array to completely cover the bottom metal electrode; and the metal compound film layer forms an ohmic contact with the bottom metal electrode. Since the bottom metal electrode is wrapped by the passivated metal compound film layer, the problem of current leakage between adjacent pixels caused by too small a spacing between two adjacent bottom metal electrodes in the pattern is avoided, thereby improving the clarity and achieving low pixel signal crosstalk. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a schematic diagram of the passivation of the metal compound thin film layer on the bottom metal electrode of the present invention.

[0046] Figure 2 It is a structural schematic diagram of the device provided by the present invention.

[0047] Figure 3 It is a schematic structural diagram of a bottom metal electrode using two metal layers in the present invention.

[0048] Figure 4 Yes Figure 3 Schematic diagram of the structure of the bottom metal electrode passivated to form a metal compound film layer.

[0049] Figure 5 It is a typical pixel readout circuit for passive detection pixel (PPS).

[0050] Figure 6 It is a typical pixel readout circuit for active detection pixel (APS).

[0051] Figure 7 It is a schematic diagram of a reset line driving integrated circuit provided by the present invention.

[0052] Figure 8 It is a schematic diagram of a reset line driving integrated circuit provided by the present invention.

[0053] Fig. 9 It is a schematic diagram of the silicon wafer provided by the present invention.

[0054] Fig.10 It is a typical pixel driving circuit of the display device of the present invention.

[0055] Fig.11 It is a schematic diagram of the circuit density changing with time under a constant voltage according to the present invention.

[0056] Fig.12 It is a structural schematic diagram of a carrier provided by the present invention.

[0057] Fig.13 It is a structural schematic diagram of another carrier provided by the present invention.

[0058] Fig.14 This is an image without pixel signal crosstalk provided by the present invention.

[0059] Fig.15 This is an image with pixel signal crosstalk provided by the present invention.

[0060] In the figure, 100-backplane, 1001-substrate, 1002-pixel readout circuit, 1003-flat layer, 1004-metal guide column, 200-bottom metal electrode, 2001-first electrode layer, 2002-second electrode layer, 300-metal compound thin film layer, 400-active layer, 500-upper charge transfer layer, 600-top metal electrode, 700-packaging layer, 800-silicon wafer, 801-contact pad, 900-thin film device, 110-carrier, 120-stainless steel, 130-slot. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. The present invention is described in detail below in combination with the drawings and specific implementation methods.

[0062] It should be understood that when used in this specification, the terms "include" and "comprising" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0063] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention, unless the context clearly indicates otherwise, the singular forms of "a", "an" and "the" are intended to include plural forms.

[0064] It should be further understood that the term “and / or” used in the specification of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0065] The term "bulk heterojunction structure" in the present invention refers to an interpenetrating network structure with nanoscale phase separation formed by blending donor and acceptor materials.

[0066] The term "donor material" in the present invention refers to a P-type semiconductor material.

[0067] The term "acceptor material" in the present invention refers to an N-type semiconductor material.

[0068] The term "I-semiconductor material" in the present invention refers to a non-doped intrinsic semiconductor material. The term "bandgap" in the present invention refers to the optical bandgap of the semiconductor material, and its value (in electron volts) can be obtained by dividing 1240 by the cutoff wavelength (in nanometers) of the absorption edge of the semiconductor material.

[0069] The term "active layer" in the present invention refers to a thin film layer having photoelectric or electro-optical activity in a device structure.

[0070] The term "photosensitive layer" in the present invention refers to a thin film layer in the device structure that is responsible for absorbing photons and generating free electrons and holes.

[0071] The term "light-emitting layer" in the present invention refers to a thin film layer that converts injected free electrons and holes into photons in a device structure.

[0072] The term "AFM" in the present invention refers to an atomic force microscope.

[0073] Generally, in metal-semiconductor-metal (MSM) thin film devices, only the bottom metal electrode is patterned, and a continuous active layer and top metal electrode layer are used. The pixel size and pixel pitch of such thin film devices can be defined by the bottom metal electrode. However, whether such a thin film device structure with a non-patterned active layer can be used for image devices with small pixel pitch and light sensing (or light emitting) devices with a PIN structure remains to be solved. The non-patterned doped metal compound thin film layer between the active layer and the patterned bottom metal electrode will cause current leakage between adjacent pixels. This leakage will cause image blur and reduce image contrast when the image pixel pitch is too small.

[0074] Therefore, on the basis of the patterned bottom metal electrode, the metal compound thin film layer is patterned; especially for image array devices with small pixel pitch and narrow space between adjacent pixels. When the pixel pitch is reduced to micrometer or submicrometer level, how to align the metal compound thin film layer pattern with the bottom metal electrode pattern becomes a challenge, especially in large-scale image array devices with a total number of pixels exceeding one million (commonly known as million-pixel focal plane array devices). In addition, it is also necessary to use the metal compound thin film layer to encapsulate the free surface (upper surface and sidewall) of the entire bottom metal electrode to eliminate the current leakage between adjacent pixels caused by adjacent bottom metal electrodes.

[0075] For this reason, Figure 1 , Figure 2 As shown, the present invention provides a thin film device with high pixel density, the thin film device comprising:

[0076] forming a bottom metal electrode array on the back plate 100;

[0077] Passivating a dense, pinhole-free metal compound thin film layer 300 on the free surface of the bottom metal electrode 200 in the bottom metal electrode array to completely cover the bottom metal electrode 200;

[0078] The metal compound film layer 300 located on the upper surface of the bottom metal electrode 200 is a P-type or N-type semiconductor and forms an ohmic contact with the upper surface of the bottom metal electrode 200;

[0079] A continuous / non-patterned active layer 400 , a continuous / non-patterned upper charge transport layer 500 , a continuous / non-patterned top metal electrode 600 , and a continuous / non-patterned transparent encapsulation layer 700 are sequentially formed on the metal compound thin film layer 300 from bottom to top.

[0080] The present invention provides a thin film device with a PIN pixel structure having high pixel density and small pixel pitch, wherein the metal compound thin film layer (P type or N type) at the bottom is encapsulated on the free surface of the bottom metal electrode 200 by a self-patterning preparation process; the free surface of the bottom metal electrode 200 includes the upper surface and side walls exposed to the air. This patterned metal compound thin film layer 300 is formed by a surface chemical reaction (e.g., surface oxidation) on the exposed free surface of the bottom metal electrode 200. The upper surface and the surrounding side walls of the bottom metal electrode 200 are wrapped by the metal compound thin film layer 300, and the metal compound thin film layer 300 serves as a pixel isolation structure to separate two adjacent pixels, thereby effectively suppressing signal crosstalk between adjacent pixels, thereby effectively improving the pixel density. Therefore, the leakage caused by defect points in the pixels of traditional thin film devices and the current leakage between adjacent pixels are greatly suppressed. The present invention only needs to perform one photolithography step on the bottom metal electrode to realize a large-size thin film device with high pixel density, millions of pixels, and PIN sensor elements, eliminating the alignment problem introduced by preparing a large-area array by multi-layer photolithography, so it has a very high manufacturing yield. In addition to being used as a photosensitive layer, when the active layer uses a luminescent material, the thin film device at this time is a display device.

[0081] Example 1

[0082] This embodiment takes a photosensitive device as an example to explain in detail. Figure 1 , Figure 2 As shown, a photosensitive device with high pixel density, the photosensitive device comprises:

[0083] A backplane 100 having a plurality of pixel readout circuits integrated therein;

[0084] A thin film device with high pixel density disposed on the backplane 100, the thin film device specifically comprising: a bottom metal electrode array composed of a plurality of bottom metal electrodes 200 formed on the backplane;

[0085] Passivating a dense, pinhole-free metal compound thin film layer 300 on the free surface of the bottom metal electrode 200 in the bottom metal electrode array to completely cover the bottom metal electrode 200;

[0086] The metal compound film layer 300 located on the upper surface of the bottom metal electrode 200 is a P-type or N-type semiconductor and forms an ohmic contact with the upper surface of the bottom metal electrode 200;

[0087] A continuous / non-patterned photosensitive layer, a continuous / non-patterned upper charge transport layer 500 , a continuous / non-patterned top metal electrode 600 , and a continuous / non-patterned transparent encapsulation layer 700 are sequentially formed on the metal compound thin film layer 300 from bottom to top.

[0088] Each of the pixel readout circuits 1002 is connected to a corresponding bottom metal electrode 200 via a metal conductive column 1004 .

[0089] In this embodiment, the photosensitive layer is used to detect light incident on the photosensitive device. The metal compound film layer located on the upper surface of the bottom metal electrode 200 serves as a lower charge transport layer, and forms a PIN junction or a NIP junction with the photosensitive layer and the upper charge transport layer respectively.

[0090] like Figure 2 As shown, it is a cross-sectional view of the entire photosensitive device. The backplane 100 can be made of various insulating materials or high-resistance semiconductor materials, and it can have a flat surface or a curved surface of a specific shape; in addition to inorganic semiconductor wafer materials, the backplane 100 can also be glass, ceramic or plastic. For a photosensitive device for image sensing, a plurality of pixel readout circuits 1002 are integrated on the backplane 100. For a photosensitive device with a high pixel density, the pixel readout circuit 1002 is usually made on the upper surface of a single crystal silicon wafer using a CMOS process. For a photosensitive device with a medium or low light-sensitive pixel density, the backplane 100 can integrate a pixel readout circuit 1002 of a CMOS field effect tube or a thin film transistor (TFT). For an image array with an ultra-large scale and a high light-sensitive pixel density, the pixel readout circuit 1002 on the backplane 100 can be made of a CMOS field effect tube (MOSFET, or FET). For the pixel readout circuit 1002 made on a single crystal silicon wafer using a CMOS integrated circuit process, it can be connected to a corresponding bottom metal electrode 200 through a metal guide pillar 1004. The preparation of the metal guide pillar 1004 and the flat layer 1003 can be achieved using materials and processes for the back-end preparation of a conventional silicon wafer. In addition to using the preparation process of the back-end of a silicon crystal production line, the preparation of the metal guide pillar 1004 and the flat layer 1003 can also be achieved using the corresponding process in the thin film transistor (TFT) backplane process. Specifically, above the pixel readout circuit 1002 of a CMOS field effect tube or a thin film transistor (TFT), the flat layer 1003 can be formed into a film using an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride by vapor deposition. The flat layer 1003 can also be made of an organic insulating material that can be prepared by photolithography patterning (such as a polyimide film that can be photolithography patterned, a polyacrylate film that can be photolithography patterned). The flat layer 1003 can also be implemented using a stack of the above-mentioned inorganic insulating material and organic insulating material. When this preparation method is adopted, the metal guide pillar 1004 does not need to be prepared separately, and can be simultaneously prepared when the bottom metal electrode is prepared.

[0091] In this embodiment, Figure 2The device structure shown can vertically stack the photosensitive pixels (200-600 stacked structure) and the pixel readout circuit 1002 below, which is commonly known as a three-dimensional circuit. This design can effectively reduce the pixel size and thus increase the pixel density.

[0092] In this embodiment, a metal film array is formed on the upper surface of the back plate 100, which is usually called a bottom metal electrode array, and includes a plurality of bottom metal electrodes 200. The thickness thereof can be selected in the range of 50nm to 500nm according to the requirements for the reflectivity of the photosensitive layer. Commonly used metal materials for the bottom metal electrodes include but are not limited to Ta, Ti, Ni, Cr, Cu, Al, Mg, V, Ga, Zr, Zn, Sn, Hf, Nb, W or Mo, or their metal alloys.

[0093] Under each bottom metal electrode 200, a metal plug 1004 is connected to the pixel readout circuit 1002. This structure allows the photosensitive pixel (also called photosensitive pixel) to be vertically stacked with the pixel readout circuit 1002 below, which is commonly known as a three-dimensional circuit. This design can effectively reduce the pixel size, thereby increasing the pixel density.

[0094] In this embodiment, the bottom metal electrode 200 has a smooth surface. In the AFM test, the surface roughness of the bottom metal electrode 200 is generally less than 5nm. To achieve such a smooth top surface, appropriate deposition methods and process conditions are required. Common deposition methods include direct current, radio frequency or pulsed sputtering deposition, electron beam deposition, ion beam assisted deposition or thermal deposition. However, compared with the process conditions for high conductivity applications (high deposition rate at high temperature), the high smoothness surface of the bottom metal electrode 200 described in this embodiment can be achieved on the backplane 100 at low temperature and at medium or low deposition power. If necessary, the deposition rate can also change from high to low during the deposition process to obtain the surface smoothness of the optimized bottom metal electrode 200. Since the total thickness of the bottom metal electrode 200 is in the nanometer (nm) range, the preparation method of the bottom metal electrode 200 provided by the present invention can meet the production capacity requirements and manufacturability required for mass production. In the working spectrum band range, the thickness of the above-mentioned bottom metal electrode 200 provides sufficient optical reflectivity.

[0095] Generally, for a photosensitive device with a large size or a large pixel pitch, such as a bottom metal electrode array in which the pitch between two bottom metal electrodes 200 is greater than 20 um, a shadow mask can be placed in front of the back plate 100 during the deposition process. Then, the metal layer is patterned according to a photolithography process well known in the field of thin film device preparation to form a bottom metal electrode array consisting of a plurality of bottom metal electrodes 200.

[0096] Common photolithography processes such as wet etching or dry etching are usually used to form the desired electrode pattern. For example, dry etching is usually used to pattern Ta, Ti or Ni films. Wet etching is usually used to pattern Cr, Cu, Al, V, W or Mo films. For metal layers that can be patterned by either wet or dry etching, dry etching is usually used to achieve better size control, especially at the submicron level; for large-scale imagers or micro display arrays with micron or submicron gaps between adjacent pixels, dry etching can achieve pixel pitches of less than 1 micron.

[0097] In a specific embodiment, a dense, pinhole-free metal compound film layer 300 is passivated on the free surface of the bottom metal electrode 200 in the bottom metal electrode array, including: using a self-aligned process to perform surface chemical reaction on the free surface of the bottom metal electrode 200 to form a dense, pinhole-free metal compound film layer 300.

[0098] In this embodiment, a dense, pinhole-free metal compound thin film layer is formed on the free surface of the bottom metal electrode 200 of the high-density, small-size pixel, such as Figure 1 The metal compound thin film layer 300 is grown on the free surface of each bottom metal electrode 200. The free surface of the bottom metal electrode array 200 refers to all surfaces (including the upper surface and sidewalls) of each bottom metal electrode 200 exposed to the air after the metal layer is patterned.

[0099] In this embodiment, the surface chemical reaction includes one or more combinations of anodic oxidation, oxygen plasma oxidation, high temperature thermal oxidation, chemical oxidation, and sulfurization.

[0100] Compared with various defects that are easily formed during the photolithography patterning process, the metal compound film layer 300 formed by the surface chemical process is dense and has no pinhole defects. In addition, the metal compound film layer pattern generated by the surface chemical reaction is automatically aligned with the bottom metal electrode pattern below, without the need for the mask alignment process in traditional photolithography, that is, the metal compound film layer 300 pattern is self-aligned with the bottom metal electrode array 200 pattern. This method of forming the metal compound film layer 300 on the bottom metal electrode 200 through the surface chemical reaction can well prepare a photosensitive device with a small pixel pitch and a high pixel density.

[0101] In this embodiment, the thickness of the metal compound film layer 300 can be controlled by the process parameters used in the surface chemical reaction. For an array device including a PIN sensor element, the thickness of the metal compound film layer 300 is generally set to 5nm-100nm. Preferably, the thickness of the metal compound film layer 300 is 10-50nm. If the average surface roughness of the metal compound film layer 300 is relatively large, the photosensitive layer 400 formed on the metal compound film layer 300 will form pinholes, shorten the device and form bright pixel defects, which is not conducive to forming a high-quality photosensitive layer 400. Therefore, the average surface roughness of the metal compound film layer 300 is less than 5nm, preferably, the average surface roughness of the metal compound film layer 300 is less than 3nm. The present invention makes it possible to have a photosensitive device with millions of pixels through the characteristics of compactness, no pinholes and high uniformity over a large device area. The present invention has the advantages of high process yield and no pixel short circuit.

[0102] In this embodiment, the surface chemical reaction specifically includes anodic oxidation, oxygen plasma surface treatment at room temperature or high temperature, chemical oxidation in air and oxygen-rich environment, humid air at room temperature or high temperature, and chemical oxidation using an oxidant (such as H2O2, 85C-100C hot water), or a combination of the above processes. In addition to oxidation on the free surface of each bottom metal electrode 200, sulfidation (such as treatment with H2S) can also be performed on the free surface of each bottom metal electrode 200. Therefore, a metal sulfide or metal sulfate film layer can also be formed by surface reaction of the bottom metal electrode with the corresponding reactant.

[0103] In a specific embodiment, when the bottom metal electrode 200 is a metal layer, the metal compound film layer passivated on the upper surface and sidewall of the metal layer is a P-type or N-type semiconductor;

[0104] In this embodiment, when the bottom metal electrode is a metal layer, the metal compound film layer passivated at the bottom metal electrode is an oxide or sulfide of the corresponding metal; at this time, the metal compound film layer can be a P-type or N-type semiconductor, which serves as a lower charge transfer layer and forms a PIN or NIP structure with the photosensitive layer and the upper charge transfer layer. It should be noted that Al cannot be used as the bottom metal electrode at this time, because the aluminum oxide formed after Al oxidation is an insulator, not a semiconductor. Since the wrapped metal compound film layer is a semiconductor, its conductivity is much smaller than that of the bottom metal electrode, so it can effectively suppress the current leakage between adjacent pixels and avoid pixel signal crosstalk.

[0105] When the bottom metal electrode is two or more metal layers, the metal compound film layer passivated on the upper surface of the topmost metal layer is a P-type or N-type semiconductor; the metal compound film layer passivated on the side walls of the remaining metal layers is an insulating layer, or a P-type semiconductor, or an N-type semiconductor.

[0106] It should be noted that, except for the topmost metal layer which cannot use Al, the other metal layers can all use Al; the advantage of using Al for the other metal layers is that aluminum oxide or aluminum sulfide formed by oxidation or sulfidation of Al is insulating, which can completely suppress current leakage between adjacent pixels and avoid signal crosstalk between adjacent pixels.

[0107] In this embodiment, the metal compound film layer 300 can be made into P type or N type. When the metal compound film layer 300 is a P type semiconductor layer, the material of the metal compound film layer 300 includes oxides or sulfides of Cu, Cr, Ni, V, Ga, W, Zr or Mo, or oxides or sulfides of metal alloys thereof. When the metal compound film layer is an N type semiconductor layer, the material of the metal compound film layer includes oxides of Ti, Ta, Zn, In, Sn, Mg, Hf, Nd, or Nb, or oxides of metal alloys thereof.

[0108] In a specific embodiment, a patterned bottom metal electrode, a metal compound film layer (such as Figure 1 200 and 300). Generally, this can be achieved by controlling the thickness of a suitable metal material or metal compound thin film layer. For example, metal titanium Ti has a strong reflection in a wide spectrum range of visible light and infrared light. A TiO2-x layer is formed on a bottom metal electrode prepared using metal titanium Ti through a surface chemical reaction. Since a strong optical resonant cavity effect is formed on the upper and lower surfaces of the TiO2-x layer, the Ti / TiO2-x double-layer film can show the maximum reflection in certain spectral ranges, and thus can be used to optimize the photosensitivity of the photosensitive device at a specific wavelength of use. In addition to metal titanium Ti, metals with high optical reflectivity in the ultraviolet, visible and infrared spectral ranges also include aluminum, magnesium and copper.

[0109] In this embodiment, Ta2O 5-x 、TiO 2-xThe N-type metal compound semiconductor film has a Fermi level of about -4 eV. Its Fermi level can be regulated by doping with magnesium, aluminum, zinc, tin or copper to form an alloy compound film layer. The metal oxide film layer is provided with additional electrons by interstitial metals and oxygen vacancies, and serves as the main charge carriers. The carrier concentration can be regulated by surface chemical reaction conditions, or by annealing the generated (bottom metal electrode 200 / metal compound film layer 300) array under different partial pressures of N2 or O2 or H2O in air, wherein the concentration of the doped metal compound component determines the carrier concentration. The carrier concentration of the metal compound film layer 300 can range from 10 15 cm -3 -10 20 cm -3 Preferably, when the metal compound thin film layer is an N-type semiconductor layer, its carrier concentration is preferably 10 16 cm -3 -10 19 cm -3 In addition to Ti and Ta, the metal compound thin film layer of the N-type semiconductor can also be made of metals including Zn, Mg, Hf, or Nb, or metal alloys thereof through surface reaction. The carrier concentration of the metal compound thin film layer of the P-type semiconductor is usually between 10 16 cm -3 -10 19 cm -3 within the range.

[0110] In this embodiment, the optical and electrical properties of the bottom metal electrode and the metal compound thin film layer can be further optimized by designing a laminated metal structure with two or more bottom metal electrodes. Figure 3 As shown, the bottom metal electrode 200 includes a first electrode layer 2001 and a second electrode layer 2002, which are made of Al and Ti thin films respectively. Patterning the bottom metal electrode 200 including the first electrode layer 2001 and the second electrode layer 2002 can be achieved by one-step photolithography. The double-layer bottom metal electrode is subjected to a surface oxidation process to form a patterned metal compound thin film layer 300, whose cross section is as shown in FIG. Figure 4 shown.

[0111] In this embodiment, the metal compound film layer 300 formed by the surface oxidation process includes two parts: (1) a TiO2-x film layer 3002 located on the top and sidewall of the Ti electrode layer; (2) an Al2O3 film layer 3001 surrounding and wrapping the sidewall of the Al electrode layer, in which case the Al2O3 is insulating. This double-layer bottom metal electrode design can not only optimize the optical reflection of the upper photosensitive layer, thereby optimizing the sensing spectrum range of the PIN sensor element. It can also provide a highly insulating Al2O3 encapsulation (sometimes also called a passivation layer) for the sidewall of the bottom metal electrode, thereby eliminating leakage between adjacent pixels (commonly referred to as crosstalk). It should be noted that the innovative structural design and molding process disclosed in the present invention are suitable for electronic array active functional elements with a vertical PIN structure, whose pixel size can be as small as microns and the gap between adjacent pixels can be as small as sub-micron size; that is, close to the optical wavelength of light detection or emission.

[0112] In this embodiment, one of the characteristics of the inorganic metal oxide formed by the surface reaction is that the Fermi level of the inorganic metal oxide is close to the Fermi level of its corresponding pure metal. The present invention obtains the metal compound thin film layer 300 by anodizing a bottom metal electrode structure composed of two or more electrode layers with different work functions, thereby optimizing the Fermi level according to the device requirements.

[0113] For example, the Fermi level of TiO2-x is about -4.1eV, while the Fermi level of Al is about -3.7eV; for the Ti electrode layer and Al electrode layer structure, the target Fermi level between -3.7eV and -4.1eV can be achieved by appropriate stacking design. For example, the oxide Ti-Al-O alloy can be achieved by anodizing the bottom metal electrode structure of Ti(x nm) / Al(y nm) / Ti(100nm). When the anodization enters or passes through the Al electrode layer and enters the next Ti electrode layer, the target alloy oxide can be achieved by adjusting the thickness of Ti(xnm) / Al(y nm) and the anodization depth in the next Ti layer. Similarly, it can also be used to achieve an alloy metal oxide with a Fermi level of -3.5eV (using Ti-Mg or Ta-Al structures) or a Fermi level in the range of -4.1 to -4.4eV (using Ti-Sn, Ti-Ni or Ti-Cu structures).

[0114] In a specific embodiment, the energy gap of the metal compound thin film layer is greater than the energy gap of the active layer.

[0115] Taking TiO2-x as an example, TiO2-x is an N-type semiconductor with an energy gap of about 3.1eV (light absorption starts at 400nm). The Fermi level of TiO2-x is ~4.1eV, close to the bottom of the conduction band on the surface of pure titanium metal. This wide-gap N-type oxide semiconductor can effectively pull photogenerated electrons out of the active layer, but will block photogenerated holes at the TiO2-x / I layer interface.

[0116] As for the dark current, under low-field reverse bias or zero bias, the blocked holes in the I layer at the NI interface and the blocked electrons at the IP interface reduce the dark current again.

[0117] The metal compound film layer obtained by the surface oxidation process provided by the present invention is very thin (usually in the range of 5-100nm), dense and free of pinhole defects. It should be particularly pointed out that the anodizing process provided by the present invention is different from the anodizing process used in the metal anti-corrosion industry. In the metal anti-corrosion industry, electric pulse operation, high power density, strong electrolyte, high temperature reaction conditions under heating or self-heating are usually adopted; however, the metal oxide layer formed by this method has a porous structure and high surface roughness. The oxidation thickness is usually 10-100 microns, and the surface roughness exceeds microns.

[0118] Specifically, the specific steps of an anodizing process provided by the present invention are as follows:

[0119] After the bottom metal electrode arrays of multiple thin film devices are prepared on the wafer,

[0120] First, clean the free surface of the bottom metal electrode;

[0121] The bottom metal electrode array on the silicon wafer is immersed in a non-strong acid anodizing solution (usually a mild electrolyte such as an organic acid or salt) and anodized at low temperature, specifically:

[0122] First, a metal compound thin film layer is formed under a constant current until the thickness of the metal compound thin film layer reaches a voltage corresponding to a target thickness; this process is a film forming process;

[0123] Then, the voltage corresponding to the target thickness is maintained at a constant voltage until the oxidation current decreases to below a certain threshold value (such as 1%) of the constant current; this process is a sealing process; and anodization is terminated.

[0124] In this embodiment, the anodic oxidation process can be kept in a low temperature environment (0-25° C.) by circulating the anodic oxidation solution and controlling the temperature. The anodic oxidation solution is also an electrolyte solution.

[0125] The rate of anodization can be controlled by adjusting the electrolyte solution concentration and the current density of the constant current.

[0126] In addition to sealing at a constant voltage (the current density of anodization will drop by 2-3 orders of magnitude from the initial constant current used in the film formation process), other oxidation processes such as surface O2 plasma treatment, thermal annealing, and surface oxidation with an oxidant can also be combined to further improve the sealing and quality of the oxide film.

[0127] The present invention realizes self-alignment to form a metal compound thin film layer on the bottom metal electrode through the above-mentioned oxidation process. Figure 1 , Figure 2 As shown, the bottom metal electrode array 200 is constructed on the pixel readout circuit 1002. Figure 5 A typical pixel readout circuit for a passive sensing pixel (PPS) is shown. Figure 6 A typical pixel readout circuit for an active detection pixel (APS) is shown. The positions marked with "*" are the bottom metal electrodes of each pixel in the photosensitive device. They are blocked by the channel of the CMOS field effect transistor T1 in the pixel readout circuit and cannot be directly connected from the edge of the device.

[0128] The present invention uses the existing pixel readout circuit, and by appropriately connecting the corresponding CMOS field effect tube to bias and apply an anode voltage to the bottom metal electrode (*) of each pixel, realizes the anodic oxidation of the bottom metal electrode of each pixel, thereby forming a self-patterned metal compound film layer.

[0129] This embodiment takes a CMOS pixel readout circuit on a silicon wafer as an example (it is also applicable to a pixel readout circuit composed of a thin film field effect transistor (TFT) on a glass or plastic substrate) to describe in detail the wiring method for connecting each photosensitive device at the edge of the silicon wafer.

[0130] Specific as Figure 5 , Figure 6 As shown, the power supply lines "Vdd" and "Vss" can reach the edge inspection / test point of each photosensitive device. In addition, the signal lines "Select", "Vdata" and "Reset" of each pixel can also be accessed near the boundary of each photosensitive device. In the case where these lines are fully integrated with the external drive circuit or signal acquisition circuit of the photosensitive device, a simple "MUX" circuit can be integrated at the outer edge of the device for anodization process purposes. Figure 7 , 8 shown. Figure 7 The connection circuit for passive detection pixel (PPS) array is given. Figure 8 The connection circuit for the active pixel element (APS) array is given. Figure 7When the contact points "A", "B", "A" and "B" in the MUX circuit are connected to the positive electrode of the anodic oxidation power supply, all the field effect tubes in the MUX circuit and the field effect tubes in each PPS pixel readout circuit are turned on. The bottom metal electrode "*" of each pixel is connected to the high potential of the anodic oxidation power supply (i.e., the anode potential). In the anodic oxidation tank, these bottom metal electrodes "*", the anodic oxidation solution and the counter electrode plate connected to the low potential (cathode potential) of the anodic oxidation power supply form an anodic oxidation circuit loop, thereby anodizing all the bottom metal electrodes.

[0131] Similarly, if Figure 8 As shown in FIG. 1 , for a photosensitive device with an active detection pixel (APS), each row of select lines (“select”) can be turned on by a “MUX” circuit incorporated at the edge of the device. The specific operation is as follows: Figure 8 The "A", "B" and "Vdd" contact points outside the array are connected to the positive electrode of the anodizing power supply. All field effect tubes in the MUX circuit and the field effect tube (T1) used as a selection switch in each APS pixel readout circuit are turned on. The bottom metal electrode "*" of each pixel is connected to the high potential (i.e., anode potential) of the anodizing power supply. In the anodizing tank, these bottom metal electrodes "*", the anodizing solution and the counter electrode plate connected to the low potential (cathode potential) of the anodizing power supply form an anodizing circuit loop, thereby anodizing all bottom metal electrode arrays.

[0132] It should be noted that Figure 7 The "MUX" circuit in the silicon wafer 800 does not need to be removed. After a metal compound film layer is formed on the surface of the bottom metal electrode array by anodization, the high potential of the anodization can be disconnected. During the manufacturing process, multiple photosensitive devices can be arranged in the vertical and horizontal directions on the silicon wafer 800, such as Fig. 9 As shown. The wires used for the self-aligned, patterned metal compound thin film layer 300 can be connected horizontally or vertically at the edge of the photosensitive device 900 and connected to the contact point 801 on the edge of the wafer for the anodizing process. After the thin film device is manufactured, when the silicon wafer is cut into each individual photosensitive device, these connecting wires can be automatically disconnected when the photosensitive device is cut, without the need for additional cutting or etching processes.

[0133] In this embodiment, Figure 5 , Figure 6The basic structure of the PPS and APS pixel readout circuits is given. Any pixel readout circuit including corresponding transistors for similar functions has similar unit circuits, and as long as they are connected in accordance with the same principle disclosed in the present invention and an anodic oxidation process is used to form a self-aligned metal compound film layer 300 for completely encapsulating the bottom metal electrode, they all fall within the scope of protection of the present invention and will not be described in detail one by one.

[0134] Figure 5 , Figure 6 The transistor shown can be a pixel readout circuit made of an N-type transistor or a P-type transistor and connected using a similar principle to implement the anodization process.

[0135] The photosensitive layer of this embodiment includes an organic semiconductor in the form of a single-phase film or a D / A bulk heterojunction blended film, an inorganic semiconductor or a compound semiconductor in the form of a single-phase or quantum dot nanoparticle, or a combination thereof in a mixed form or a thin film stack. Wherein, D represents an organic molecule of an electron donor; A represents an organic molecule of an electron acceptor.

[0136] Wherein, the inorganic semiconductor includes Si, Ge, SiGe, CuInS in crystalline or polycrystalline form. x Se 2-x (0≤x≤2), CuInGa(S,Se), PbS, PbI2, PBI3, InGaAs nano-quantum dots, nano-quantum thin films or single-phase films.

[0137] The organic semiconductor includes an organic blend of one or more organic molecules used as electron donors (D) and one or more organic molecules used as electron acceptors (A) to form D / A.

[0138] In this embodiment, the photosensitive layer may have at least one molecular component with an energy gap smaller than 1.7 eV (wavelength larger than 700 nm), that is, the photosensitive device in this embodiment is an infrared photodetector.

[0139] In this embodiment, the photosensitive layer can be a monomolecular type organic semiconductor film, or a mixed film (commonly referred to as a D / A body heterojunction film) comprising at least one donor molecule (D) and one acceptor molecule (A). Donor (acceptor) molecules are often referred to as P-type (N-type) in the traditional inorganic semiconductor device industry. The photosensitive layer 400 can also be made together with other thin film semiconductor layers. For example, it includes perovskite semiconductor films (such as PbI2 and / or PbI3), PbS, CuInSe2, CuInSSe, CuInGaSe, CuInGaSSe.

[0140] The absorption coefficients of the organic and inorganic semiconductor compounds listed above are in the range of 10 4 -105 cm -1 In the range of 100nm-1um, the photosensitive layer can achieve a light absorption rate of 90%-99% in the working range. This is in sharp contrast to the active layer in the silicon CMOS image array, where the active layer usually needs a thickness of 10-500um to achieve more than 90% light absorption in the near-infrared region (700nm-1000nm).

[0141] The photosensitive layer can also be made of a thin film composed of multiple semiconductor materials listed above to achieve the desired spectral response or performance improvement. In addition, the photosensitive layer can also be made of a composite film containing the above-mentioned semiconductor materials. As mentioned above, the photosensitive layer can be made of organic molecules in the form of a D / A body heterojunction. The photosensitive layer can also be made of a phase including an organic semiconductor and another phase including inorganic semiconductor nanoparticles (or quantum dots). By utilizing the unique mechanical and electronic properties of organic semiconductors, this hybridized photosensitive layer can be made in a low trap state in the semiconductor energy gap, thereby improving device performance.

[0142] It is worth mentioning that due to the thin film nature of the photosensitive layer, a photosensitive layer with a pixel size as small as micrometer can be produced without patterning the photosensitive layer, e.g. Figure 2 As shown in Figure 2, image dispersion caused by optical and / or electrical crosstalk becomes a negligible factor. Figure 2 In the photosensitive array shown, the continuous / unpatterned top metal electrode 600 is shared by all pixels of the photosensitive device. Due to the design of the "common" top metal electrode, the upper charge transport layer 500 between the photosensitive layer and the top metal electrode layer 600 can also be made into a continuous film form.

[0143] In this embodiment, the upper charge transport layer 500 is generally composed of a metal compound thin film layer 300 having a charge opposite to that of the semiconductor. At this time, the metal compound thin film layer 300, the photosensitive layer, and the upper charge transport layer 500 located on the upper surface of the bottom metal electrode can be stacked to form a PIN (or NIP) structure. In addition to the PIN junction or NIP junction, various structures such as PIP, NIN, NIPIN, and PINIP can also be stacked to form.

[0144] This embodiment also includes: adding a surface promoting material (commonly referred to as a self-assembled monolayer, SAM) between the metal compound film layer 300 of the semiconductor and the photosensitive layer to improve adhesion and reduce surface defects at the interface. When the metal compound film layer 300 is an N-type semiconductor, the SAM material used in the formed NI contact interface includes SAM-C60, C60-COOH-SAM and SAM-PBD. When the metal compound film layer 300 is a P-type semiconductor, the SAM materials suitable for the formed PI contact interface include 2PACz, x-4PACz (where x = H, Cl, F, Ph) and PPAOMe. Their molecular structures are shown below.

[0145]

[0146] In this embodiment, depending on the organic molecular material used in the photosensitive layer, the wavelength band of light that can be detected is ultraviolet (200-400nm), visible light (400-700nm), near infrared light (700-1000nm), short-wave infrared light (1000-2500nm), mid-infrared (2.5-25um) or a combination of multiple bands above.

[0147] When necessary, a packaging layer 700 is added above the top metal electrode 600 to ensure that the photosensitive array works stably under various usage environments and during the target lifespan. The packaging layer should be transparent in the working band and the optical transmittance should be above 50%.

[0148] The encapsulation layer 700 can be formed by various vacuum coating methods, such as thermal evaporation, molecular beam coating or plasma sputtering, atomic layer deposition. It can also be prepared by liquid film forming methods, such as drop coating, dip coating, spin coating and various printing methods. In addition to selecting a single material, the encapsulation layer can also be formed by alternating multiple layers of film. In addition to improving the performance of the encapsulation layer, this multi-layer film structure can also be used to optimize the optical resonant cavity structure of the thin film photodiode in the working band, thereby optimizing its photosensitivity and specific detection rate.

[0149] The encapsulation layer 700 , commonly used inorganic materials include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, magnesium oxide, zirconium oxide and magnesium fluoride; commonly used organic materials include polymethyl methacrylate, polyethylene oxide, polystyrene, polyvinyl pyrrolidone, polycarbonate, polyacrylic acid, epoxy resin, polyparaxylene, polysiloxane.

[0150] In this embodiment, examples of the constituent material of the continuous / non-patterned top metal electrode 600 include thin layers of titanium (Ti), tungsten (W), titanium nitride (TiN), platinum (Pt), gold (Au), silver (Ag), germanium (Ge), nickel (Ni), any single substance of tin (Sn) and aluminum (Al) or an alloy containing at least one of them. Among them, indium titanium oxide (InTiO) has high light transmittance with respect to the infrared region and is expected to be used as a constituent material of the continuous / non-patterned top metal electrode. In addition to the materials mentioned above, examples of materials for the top metal electrode include indium tin oxide (ITO), tin oxide (SnO2), indium tungsten oxide (InWO), indium zinc composite oxide (InZnO), aluminum-doped zinc oxide (AlZnO), gallium-doped zinc oxide (GaZnO), magnesium- and aluminum-doped zinc oxide (AlMgZnO), indium gallium composite oxide (InGaO), InGaZnO4 (IGZO), fluorine-doped indium oxide (FIO), antimony-doped tin oxide (ATO), fluorine-doped tin oxide (FTO), zinc oxide (ZnO), boron-doped ZnO (BZnO), and indium tin zinc oxide (InSnZnO).

[0151] The material of the upper charge transport layer 500 as an electron transport layer is selected from organic compound 1, inorganic compound 1, or a combination thereof;

[0152] Wherein, the organic compound 1 is selected from fullerene and its derivatives, 4,7-diphenyl-1,10-phenanthroline, polyethyleneimine, polyethoxyethyleneimine, 2,9-dimethyl-4,7-biphenyl-1,10-phenanthroline,

[0153] [9,9-dioctylfluorene-9,9-bis(N,N-dimethylaminopropyl)fluorene], bromo-[9,9-dioctylfluorene-9,9-bis(N,N-dimethylaminopropyl)fluorene], 8-hydroxyquinoline lithium, 1,3,5-tri(1-phenyl-1H-benzimidazol-2-yl)benzene, bis(2-methyl-8-quinolinol)-4-(phenylphenol)aluminum, 1,3,5-tri[(3-pyridyl)-phenyl-3-yl]benzene, or a mixture or a composite of the above materials;

[0154] The inorganic compound 1 is selected from zinc oxide, tin oxide, aluminum-doped zinc oxide, magnesium-doped zinc oxide, gallium-doped zinc oxide, tin-doped zinc oxide, titanium oxide, tantalum oxide, zinc sulfide, chromium sulfide, or a mixture or composite of the above materials.

[0155] The material of the upper charge transport layer 500 as a hole transport layer is selected from organic compound 2, inorganic compound 2, or a combination thereof;

[0156] Wherein, the organic compound 2 is selected from one or more of 4,4'-cyclohexylbis[N,N'-bis(4-methylphenyl)aniline], N,N'-bis(naphthalene-1-yl)-N,N'-bis(phenyl)-benzidine, N,N'-bis(naphthalene-1-yl)-N,N'-bis(phenyl)-2,7-diamino-9,9-spirobifluorene, 2,2',7,7'-tetrakis[N,N-bis(4-methoxyphenyl)amino]-9,9'-spirobifluorene, 4,4',4"-tri(carbazole-9-yl)triphenylamine, poly(4-butyltriphenylamine), polyvinylcarbazole, polystyrene-N,N'-diphenyl-N,N'-bis-(3-methylphenyl)-(1,1)-biphenyl-4,4'-diamineperfluorocyclobutane, poly(3,4-ethylenedioxythiophene) mixed polystyrene sulfonate;

[0157] The inorganic compound 2 is selected from tungsten oxide, molybdenum oxide, vanadium oxide, chromium oxide, nickel oxide, copper oxide, cuprous oxide, cuprous thiocyanate, copper sulfide, copper iodide, or a mixture or a composite of the above materials.

[0158] This embodiment also provides a method for preparing a thin film device with high pixel density, comprising the following steps:

[0159] patterning a bottom metal electrode on the backplane to form a bottom metal electrode array;

[0160] A surface chemical reaction is carried out on the free surface of the bottom metal electrode by using a self-aligned process to form a dense, pinhole-free metal compound film layer;

[0161] preparing a continuous / non-patterned photosensitive layer;

[0162] preparing a continuous / non-patterned upper charge transport layer;

[0163] preparing a continuous / non-patterned top metal electrode layer;

[0164] Prepare a continuous / non-patterned encapsulation layer.

[0165] Wherein, the preparation of the photosensitive layer is selected from solution film formation or vacuum thermal evaporation deposition method.

[0166] The preparation of the upper charge transport layer is independently selected from one or more of solution film formation, sol-gel film formation, vacuum thermal evaporation, atomic layer deposition, chemical vapor deposition, electrodeposition, and anodization.

[0167] The preparation of the top metal electrode layer and the bottom metal electrode layer are independently selected from one or more of vacuum thermal evaporation, electron beam evaporation, molecular beam evaporation or plasma sputtering, atomic layer deposition or liquid film formation followed by reduction conversion, electroplating or electrodeposition.

[0168] Example 2

[0169] This embodiment provides a display device such as Figure 1 , Figure 2 shown.

[0170] The display device comprises a backplane with a plurality of pixel driving circuits integrated therein, and a thin film device with a high pixel density arranged on the backplane;

[0171] Each of the pixel driving circuits is connected to a corresponding bottom metal electrode through a metal guide column.

[0172] Wherein, the thin film device comprises:

[0173] forming a bottom metal electrode array on the back plate 100;

[0174] Passivating a dense, pinhole-free metal compound thin film layer 300 on the free surface of the bottom metal electrode 200 in the bottom metal electrode array to completely cover the bottom metal electrode 200;

[0175] The metal compound film layer 300 located on the upper surface of the bottom metal electrode 200 is a P-type or N-type semiconductor and forms an ohmic contact with the upper surface of the bottom metal electrode 200;

[0176] A continuous / non-patterned active layer 400 , a continuous / non-patterned upper charge transport layer 500 , a continuous / non-patterned top metal electrode 600 , and a continuous / non-patterned transparent encapsulation layer 700 are sequentially formed on the metal compound thin film layer 300 from bottom to top.

[0177] The structure and manufacturing process of the display device are basically the same as those of the photosensitive device in Example 1, and the specific differences are as follows:

[0178] The photosensitive layer is replaced by a light-emitting layer for generating light for light-emitting display.

[0179] In this embodiment, the undoped active layer 400 can be used as a light-emitting layer, which includes one or more light-emitting materials and can adopt a multi-layer or single-layer structure. The light-emitting efficiency can be optimized by adjusting the mixing ratio and film thickness in the form of a donor / host (host / guest) mixture.

[0180] Depending on the material used in the light-emitting layer, the emission wavelength can be UV (200-400nm), visible light (400-700nm), near infrared (700-1000nm), short wavelength infrared (1000-2500nm), medium wavelength infrared (2.5-25um) or a combination of multiple bands above.

[0181] The material of the light-emitting layer includes a p-type organic semiconductor material and an n-type organic semiconductor material, wherein the p-type organic semiconductor may be a compound that functions as an electron donor for supplying electrons.

[0182] For example, the p-type organic semiconductor may be boron subphthalocyanine chloride (SubPc), copper (II) phthalocyanine (CuPc), tetraphenyldibenzoperiflanthene (DBP), or any combination thereof, but is not limited thereto. The n-type organic semiconductor may be a compound that acts as an electron acceptor for receiving electrons. For example, the n-type organic semiconductor may be N2200, C60 fullerene, C70 fullerene, or any combination thereof, but is not limited thereto.

[0183] Among them, the molecular structure of N2200 is as follows:

[0184]

[0185] When the upper charge transport layer is used as an electron transport layer, it can include 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP: 2,9-Dimethyl-4,7-diphenyl-1,10-phenanthroline), 4,7-diphenyl-1,10-phenanthroline (Bphen: 4,7-Diphenyl-1,10-phenanthroline), Alq3, BAlq, TAZ, NTAZ or any combination thereof.

[0186] The electron transport layer may further include a metal-containing substance in addition to the above materials.

[0187] The metal-containing substance may include an alkali metal complex, an alkaline earth metal complex or any combination thereof. The metal ion of the alkali metal complex may be a Li ion, a Na ion, a K ion, a Rb ion or a Cs ion, and the metal ion of the alkaline earth metal complex may be a Be ion, a Mg ion, a Ca ion, a Sr ion or a Ba ion. The ligand coordinated with the metal ions of the alkali metal complex and the alkaline earth metal complex may independently include hydroxyquinoline, hydroxyisoquinoline, hydroxybenzoquinoline, hydroxyacridine, hydroxyphenanthridine, hydroxyphenyloxazole, hydroxyphenylthiazole, hydroxyphenyloxadiazole, hydroxyphenylthiadiazole, hydroxyphenylpyridine, hydroxyphenylbenzimidazole, hydroxyphenylbenzothiazole, bipyridine, phenanthroline, cyclopentadiene or any combination thereof.

[0188] When the upper charge transport layer is used as a hole transport layer, it can include the following m-MTDATA, TDATA, 2-TNATA, NPB (NPD), β-NPB, TPD, Spiro-TPD (Spiro-TPD), Spiro-NPB (Spiro-NPB), methylated-NPB, TAPC, HMTPD, 4,4',4"-tris(N-carbazolyl)triphenylamine (TCTA: 4,4',4"-tris(N-carbazolyl)triphenylamine), polyaniline / dodecylbenzenesulfonic acid (PANI / DBSA: Polyaniline / Dodecylbenzenesulfonic acid), poly(3,4-ethylenedioxythiophene) / poly(4-styrenesulfonate) (PEDOT / PSS: Poly(3,4-ethylenedioxythiophene) / Poly(4-styrenesulfonate)), polyaniline / camphorsulfonic acid (PANI / CSA: Polyaniline / Camphor sulfonic acid acid), polyaniline / poly(4-styrenesulfonate) (PANI / PSS: Polyaniline / Poly(4-styrenesulfonate)), or any combination thereof.

[0189] The pixel driving circuit in a typical display device of this embodiment is as follows: Fig.10 As shown in FIG. 1 , a typical pixel driving circuit of an active matrix display array of a display device (organic or inorganic element) is shown. When the "Vdata" and "Vdd" lines are respectively connected through Figure 6 The "A" and "B" lines in the circuit are connected to the high potential of the anodized power supply, and each "VSeset" line is connected to the line driver integrated in the silicon wafer. Fig.10 When the T1 and T2 transistors in the display are turned on, the bottom metal electrode is connected to the high potential of the anodizing power supply, so that after the metal compound thin film layer is formed by the anodizing process, the high potential of the anodizing can be disconnected. After the anodizing is completed, when the silicon wafer is cut into each display device, all the connection lines connected to the silicon wafer in the pixel readout circuit of the display device are automatically cut along the cutting line between adjacent display devices, without the need for additional cutting or etching processes.

[0190] Example 3

[0191] Generally, the thin film device (photosensitive device or display device) is prepared on a silicon wafer. In this embodiment, a backplane is first prepared on the silicon wafer, and a layer of tantalum Ta metal film layer is sputtered on the backplane using a DC sputtering device. The thickness of the Ta metal film layer ranges from about 170 to about 500 nm. The Ta metal film layer is patterned using a photolithography process to form a bottom metal electrode array.

[0192] In this embodiment, a dense, pinhole-free Ta2O5 thin film layer is formed on the free surface of the corresponding bottom metal electrode, and the specific steps are as follows:

[0193] S1. First, clean the free surface of the bottom metal electrode by rinsing with IPA and DIW; air-blade drying; UV-Ozone treatment (365-385nm, 533mW / cm 2 ), 10-15 minutes.

[0194] S2. Connect the power clip of the anode to the contact pad near the edge of the silicon wafer.

[0195] S3. Immerse the silicon wafer in a container filled with anodizing solution until the liquid surface reaches the specified line; immerse a stainless steel plate as the counter electrode of the anode (that is, the cathode) in the container filled with anodizing solution, with a distance of 4 cm between the stainless steel plate and the silicon wafer; connect the stainless steel plate to the negative power clamp.

[0196] The anodizing solution includes an organic acid, a weak acid or weak base weak acid salt aqueous solution, and a solution doped with an organic polar solvent.

[0197] The organic polar solvent includes formamide, acetonitrile, methanol, ethanol, propanol, acetone, dioxane, tetrahydrofuran, methyl ethyl ketone, n-butanol, ethyl acetate, ethyl ether, isopropyl ether, dichloromethane, chloroform, ethyl bromide, benzene, chloropropane, toluene, carbon tetrachloride, carbon disulfide, cyclohexane, hexane, and heptane.

[0198] The organic acid includes tartaric acid, oxalic acid, malic acid, citric acid, benzoic acid, salicylic acid, caffeic acid and citric acid.

[0199] The weakly acidic salt aqueous solution includes carbonic acid H2CO3, acetic acid CH3COOH, silicic acid H2SiO3, nitrous acid HNO2, hydrosulfuric acid H2S, hydrofluoric acid HF, hypochlorous acid HCIO, hydrocyanic acid HCN, sulfurous acid H2SO3, and phosphoric acid H3PO4.

[0200] The weak base and weak acid salt aqueous solution includes ammonium carbonate, ammonium acetate and copper sulfide.

[0201] S4. In 0.01M citric acid solution at 0.2mA / cm 2 (Generally the current density can be between 0.1-1 mA / cm 2 The metal surface is anodized by applying a constant current (adjusted within a range) until the voltage corresponding to the target thickness of Ta2O5 is reached (growth rate of Ta2O5 = 0.46 V / nm). It should be noted that 0.01 M citric acid solution is used as the anodizing solution here.

[0202] S5. After reaching a voltage of 17.5 V (corresponding to the formation of a 30 nm film), the constant current is stopped and the power supply is switched to a constant voltage mode. In the constant voltage mode, the current of the anodization will begin to decrease over time, such as Fig.11 shown.

[0203] S6. When the current density drops below 1% of the constant current used in step S4, turn off the power supply.

[0204] S7. Take the silicon wafer out of the container containing the anodizing solution.

[0205] S8. Air dry; if there are water marks on the oxide surface, perform ultrasonic deionized water cleaning.

[0206] In this embodiment, the rate of the anodizing can be adjusted according to the current density used in the constant current stage. It can also be adjusted by the temperature of the anodizing solution. Generally, the temperature of the anodizing solution is between 2°C and 25°C.

[0207] The anodizing process disclosed in the present invention is very different from the anodizing process used in the metal corrosion protection industry. The former uses a DC power supply with a low current density, and there is no obvious temperature rise in the anodizing solution. A dense oxide film is formed in the constant current stage, which has no large crystalline particles and cracks, and the oxide film is further sealed in the constant voltage stage; when the anodizing is completed, the current drops to a negligible level, and the resulting dense, smooth, pinhole-free metal oxide film layer has a thickness that can be selected in the range of a few nanometers to hundreds of nanometers. However, the metal surface passivation process used in the metal corrosion protection industry uses a pulse voltage, and the current is relatively large, and the electrolyte is relatively strong. The thickness of the resulting oxide coating is 10-100 microns, and the porous surface includes many submicron diameter pores.

[0208] Example 4

[0209] For the bottom metal electrode, this embodiment can also use O2 plasma to form a dense, pinhole-free metal compound film layer on the free surface of the bottom metal electrode.

[0210] Same as O2 plasma process conditions and equipment. Pump down to 300mtorr, then turn on the plasma source, set the power to 300W, and last for 15 minutes. The backplane temperature can be set in the range of 25℃ to 100℃. If necessary, the above process can be repeated, thereby producing a dense, pinhole-free metal compound film layer on the surface of the bottom metal electrode, which can be confirmed by impedance test and photodiode test.

[0211] Example 5

[0212] For the oxidation of the bottom metal electrode, annealing in high temperature air at 100-300° C. may also be used to form a dense metal compound film layer on the bottom metal electrode.

[0213] Specifically, after patterning the bottom metal electrode (the bottom metal electrode material is tantalum) on the silicon wafer, the silicon wafer is cleaned in an ultrasonic bath in acetone for 5 minutes, and then in an ultrasonic bath in isopropanol for 5 minutes. The silicon wafer is then heated at about 120°C for 20 minutes and annealed so that the free surface of the bottom metal electrode on the silicon wafer forms a semiconductor metal oxide film layer. At this time, the tantalum oxide obtained by oxidation is used as a broadband semiconductor layer with a Fermi energy of about -4.1eV. It should be noted that if the metal compound film layer is formed only by high-temperature oxidation, it is not necessary to be on the silicon wafer.

[0214] Example 6

[0215] For the bottom metal electrode, this embodiment can use chemical oxidation treatment (H2O2 or 85°C hot water) to form a dense metal compound film layer on the bottom metal electrode.

[0216] Example 7

[0217] A dense semiconductor metal compound thin film layer is formed on the bottom metal electrode by using a combination of any several oxidation methods in Examples 3 to 6.

[0218] It is also possible to use the oxidation process of Examples 4 to 6 to continuously perform the pinhole sealing process after Example 3, thereby forming a higher quality pinhole-free and dense metal compound thin film layer on the bottom metal electrode.

[0219] Example 8

[0220] This embodiment also provides a carrier 110 for anodizing the surface of a large-sized silicon wafer (up to 16-inch silicon wafer).

[0221] The carrier 110 may be made of a plastic plate or an anodized aluminum plate; an anodized aluminum plate generally has better wear resistance and corrosion resistance. The number of silicon wafers 800 that the carrier 110 can accommodate may be 2 (eg Fig.12 As shown), 8 or 16 pieces (as Fig.13 The slots 130 for the 24 silicon wafers 800 can be designed according to actual needs. The corresponding slots 130 are arranged on the inner wall of the carrier 110, such as Fig.12 As shown, a piece of stainless steel 120 is disposed between two silicon wafers 800 .

[0222] Insert the silicon wafer 800 and the stainless steel 120 into the slot 130 of the carrier 110 respectively, connect the contact pad 801 of each silicon wafer 800 to the positive electrode fixture of the anodizing power supply, and connect the stainless steel to the negative electrode of the anodizing power supply. Then transfer the carrier 110 as a whole to the oxidation tank. Control the liquid level of the anodizing solution to be higher than the carrier. Turn on the anodizing power supply. Oxidation can be carried out according to Example 3. After the reaction is completed, lift the carrier, remove the wiring of the anodizing power supply, and move it into the cleaning tank for cleaning.

[0223] For example, the anodization process time of Ta in Example 3 is about 60-120 minutes. Taking 120 minutes as an example, when a container is filled with 24 silicon wafers, the equivalent time for each silicon wafer is 5 minutes. The corresponding production capacity is 8,600 silicon wafers per month (annual production capacity is greater than 100,000). This example shows that the self-aligned, patterned semiconductor forming process disclosed in the present invention can meet the requirements of high-capacity, large-scale production.

[0224] Example 9

[0225] This embodiment provides a photosensitive device, which is prepared by the following method:

[0226] In 5×10 -7 Under vacuum conditions of 0.1 torr, a 100nm thick Ta metal film is deposited on the backplane. The rate of thermal evaporation deposition on the backplane.

[0227] The Ta-based metal electrode array on the back plate is anodized by the method of the above-mentioned embodiment 3 to form a 30 nm Ta2O5 metal compound thin film layer.

[0228] The lead sulfide quantum dot solution wrapped with oleic acid ligands is spin-coated onto the above-mentioned Ta2O5 metal compound film layer, and then a methanol solution of tetrabutylammonium iodide is used as a short-chain ligand for solid-state ligand exchange. Finally, the film is washed twice with methanol solvent to obtain a passivated lead sulfide quantum dot film. The above steps are repeated four times to obtain a lead sulfide quantum dot layer of a specified thickness.

[0229] The polymer donor JD40 and the non-fullerene acceptor Y6 were blended in a mass ratio of 1:1 and added to a chloroform solvent. The dissolved solution was then spin-coated onto the lead sulfide quantum dot layer to prepare an organic semiconductor layer of a specified thickness. The organic semiconductor layer was then annealed on a heating platform at 80°C for 5 minutes.

[0230] The above structure was transferred to a thermal evaporation device and -7 Under vacuum conditions of torr, a molybdenum oxide film layer of specified thickness is formed. The photosensitive layer is thermally evaporated and deposited on the photosensitive layer at a rate of.

[0231] In 5×10 -7 Under vacuum conditions of 0.1 torr, a 30nm thick silver film is thermally evaporated and deposited on the molybdenum oxide film layer as an anode, thereby obtaining a photosensitive device with a specific high pixel density.

[0232] The Ta2O5 thin film layer as the electron transport layer, the photosensitive layer, and the molybdenum oxide as the hole transport layer form a NIP junction.

[0233] In this embodiment, the photosensitive layer can form a BHJ using binary organic materials. The photosensitive layer can also be prepared using ternary or higher materials, as described in detail in the patent publication number: CN113823744A, publication date: 2021.12.21, and the patent name: A highly sensitive organic photodiode and an array thereof, as well as a method for preparing the organic photodiode. The photosensitive layer can also be made of a hybrid of organic semiconductor materials and inorganic semiconductor materials, as described in detail in the patent publication number: CN 114284436 A, publication date: 2022.04.05, and the patent name: An organic-inorganic hybrid short-wave infrared photodetector and an array thereof, as well as related preparation methods.

[0234] The photosensitive device prepared in this embodiment is used to shoot and display the captured image. Fig.14 As shown. Fig.15 As shown in the figure, the image is taken by a photosensitive device where the distance between adjacent bottom metal electrodes is too close, resulting in current leakage. Fig.15 It can be seen that due to the current leakage between adjacent bottom metal electrodes, there is pixel signal crosstalk, resulting in blurred images. However, the photosensitive device of the present invention can improve the resolution of the image, and the clarity of the captured image is relatively high.

[0235] Example 10

[0236] The display device provided in this embodiment has a similar structure to the photosensitive device, except that the semiconductor material used in the light-emitting layer is different from the semiconductor material used in the photosensitive layer of the photosensitive device, and the working principles of the two are opposite. As a light-emitting display array, a light-emitting display array with ITIC as the main molecule and Y6-4F or IEICO-4F as the guest molecule at a concentration of 0.5-10% is used. A metal oxide thin film layer can be formed on the bottom metal electrode by the anodizing method of Example 3.

[0237] Within the scope of protection of the present invention, the technical solutions and / or implementation methods may be modified and varied in various ways. For example, a bottom metal electrode that is transparent in the short-wave infrared region (such as ITO, AlZnO, CuOx) may be used to replace the opaque metal electrode. Figure 2The photosensitive device shown can detect incident images from both the top and bottom. For images incident from the top, it can detect image information in a wide band from ultraviolet, visible, near infrared to short-wave infrared; for images incident from the bottom, this device is only sensitive to image information in the short-wave infrared region (wavelength greater than 1 micron). This image photosensitive device can replace multiple cameras in portable devices such as mobile phones and helmets.

[0238] Obviously, the above embodiments of the present invention are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A thin film device with high pixel density, characterized in that: The thin film device comprises: forming a bottom metal electrode array on the backplane; Passivating a dense, pinhole-free metal compound thin film layer on the free surface of the bottom metal electrode in the bottom metal electrode array to completely cover the bottom metal electrode; Wherein, the metal compound thin film layer located on the upper surface of the bottom metal electrode is a P-type or N-type semiconductor and forms an ohmic contact with the upper surface of the bottom metal electrode; A continuous / non-patterned active layer, a continuous / non-patterned upper charge transport layer, a continuous / non-patterned top metal electrode, and a continuous / non-patterned transparent encapsulation layer are sequentially formed on the metal compound thin film layer from bottom to top.

2. The thin film device with high pixel density according to claim 1, characterized in that: A dense, pinhole-free metal compound film layer is passivated on the free surface of the bottom metal electrode in the bottom metal electrode array, including: using a self-alignment process to perform surface chemical reaction on the free surface of the bottom metal electrode to form a dense, pinhole-free metal compound film layer.

3. The thin film device with high pixel density according to claim 2, characterized in that: The surface chemical reaction includes one or more combinations of anodic oxidation, oxygen plasma oxidation, high temperature thermal oxidation, chemical oxidation, and sulfurization.

4. The thin film device with high pixel density according to claim 3, characterized in that: The specific process steps of the anodizing are as follows: After a bottom metal electrode array of a plurality of thin film devices is prepared on a wafer; Cleaning the free surface of the bottom metal electrode; immersing the bottom metal electrode array on the wafer in a non-strong acid anodizing solution; First, a metal compound thin film layer is formed under a constant current until the thickness of the metal compound thin film layer reaches a voltage corresponding to a target thickness; Then, the voltage corresponding to the target thickness is maintained at a constant voltage until the oxidation current decreases below a certain threshold of the constant current, thereby terminating the anodization.

5. The thin film device with high pixel density according to claim 1, characterized in that: When the bottom metal electrode is a metal layer, the metal compound film layer passivated on the upper surface and sidewall of the metal layer is a P-type or N-type semiconductor; When the bottom metal electrode is two or more metal layers, the metal compound film layer passivated on the upper surface of the topmost metal layer is a P-type or N-type semiconductor; the metal compound film layer passivated on the side walls of the remaining metal layers is an insulating layer, or a P-type semiconductor, or an N-type semiconductor.

6. The thin film device with high pixel density according to claim 1, characterized in that: The thickness of the metal compound thin film layer is 5nm-100nm.

7. The thin film device with high pixel density according to claim 1, characterized in that: The average surface roughness of the metal compound thin film layer is less than 5 nm.

8. The thin film device with high pixel density according to claim 1, characterized in that: The carrier concentration of the metal compound thin film layer is in the range of 10 15 cm -3 -10 20 cm -3 .

9. The thin film device with high pixel density according to claim 1, characterized in that: The energy gap of the metal compound thin film layer is greater than the energy gap of the active layer.

10. The thin film device with high pixel density according to claim 1, characterized in that: When the metal compound thin film layer is of P type, the material of the metal compound thin film layer includes oxides or sulfides of Cu, Cr, Ni, V, Ga, W, Zr or Mo, or oxides or sulfides of their metal alloys.

11. The thin film device with high pixel density according to claim 1, characterized in that: When the metal compound thin film layer is of N type, the material of the metal compound thin film layer includes an oxide of Ti, Ta, Zn, In, Sn, Mg, Hf, Nd, or Nb, or an oxide of a metal alloy thereof.

12. The thin film device with high pixel density according to claim 1, characterized in that: Also includes: A surface promoting material is added between the metal compound thin film layer and the active layer to improve adhesion and reduce surface defects at the interface.

13. The thin film device with high pixel density according to claim 1, characterized in that: The active layer comprises an organic semiconductor in the form of a single-phase film or a D / A bulk heterojunction blended film, an inorganic semiconductor or a compound semiconductor in the form of a single-phase or quantum dot nanoparticle, or a combination in a mixed form or a thin film stack; wherein D represents an organic molecule of an electron donor; and A represents an organic molecule of an electron acceptor; Wherein, the inorganic semiconductor includes Si, Ge, SiGe, CuInS in crystalline or polycrystalline form. x Se 2-x (0≤x≤2), CuInGa(S,Se), PbS, PbI2, PBI3, InGaAs nano-quantum dots, nano-quantum thin films or single-phase films; The organic semiconductor includes an organic blend of one or more organic molecules used as electron donors (D) and one or more organic molecules used as electron acceptors (A) to form D / A.

14. A photosensitive device, characterized in that: A backplane having a plurality of pixel readout circuits integrated therein, and a thin film device with a high pixel density as claimed in any one of claims 1 to 13 arranged on the backplane; The active layer serves as a photosensitive layer for detecting light incident on the photosensitive device; Each of the pixel readout circuits is connected to a corresponding bottom metal electrode through a metal conductive column.

15. A display device, characterized in that: A backplane having a plurality of pixel driving circuits integrated therein, and a thin film device with a high pixel density as claimed in any one of claims 1 to 13 arranged on the backplane; The active layer is used as a light-emitting layer to generate light for light-emitting display; Each of the pixel driving circuits is connected to a corresponding bottom metal electrode through a metal guide column.

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