Display panel and display device

Abstract

The invention discloses a display panel and a display device, and relates to the technical field of display, the display panel comprises a substrate and a plurality of pixel circuit groups located on one side of the substrate, the plurality of pixel circuit groups are arranged in an array along a first direction and a second direction which are intersected, the pixel circuit group at least comprises a first pixel circuit, a second pixel circuit and a third pixel circuit; wherein the first pixel circuit and the second pixel circuit are in mirror symmetry along the second direction, so that the first pixel circuit and the second pixel circuit which are in mirror symmetry along the second direction can share part of via holes, the occupied space of the pixel circuits is saved, the pixel density of the display panel can be improved, and the resolution of the display panel is improved; the third pixel circuit is in non-mirror symmetry with the adjacent pixel circuit along the first direction, so that the pixel circuits of the sub-pixels with the same color have the same structure, the offset directions of key nodes of the pixel circuits of the sub-pixels with the same color due to process fluctuation are the same, and the display effect of the display panel can be improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] A display panel includes a plurality of sub-pixels. Each sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit drives the corresponding light-emitting element to emit light and display according to a target light-emitting brightness, so that the display panel displays a target image.

[0003] With the continuous progress of display technologies, display panels are rapidly developing towards higher resolutions and better display effects. Therefore, how to arrange and design the sub-pixels in a display panel to improve the pixel density (Pixels Per Inch, PPI) of the display panel, thereby improving the resolution of the display panel, while also improving the display effect of the display panel, is a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0004] To solve the above technical problems, embodiments of this application provide a display panel and a display device. By arranging and designing the sub-pixels in the display panel, the pixel density of the display panel can be increased, thereby improving the resolution of the display panel, while also improving the display effect of the display panel.

[0005] To achieve the above object, embodiments of this application provide the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a display panel, which includes:

[0007] A substrate;

[0008] A plurality of pixel circuit groups, located on one side of the substrate, and the plurality of pixel circuit groups are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect;

[0009] Each pixel circuit group includes at least three pixel circuits. The at least three pixel circuits include a first pixel circuit, a second pixel circuit, and a third pixel circuit. The first pixel circuit and the second pixel circuit are mirror-symmetrical along the second direction, and the third pixel circuit is not mirror-symmetrical with the pixel circuit adjacent along the first direction.

[0010] In a second aspect, embodiments of this application provide another display panel, which includes:

[0011] A substrate;

[0012] A plurality of pixel circuit groups, located on one side of the substrate, and the plurality of pixel circuit groups are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect;

[0013] The pixel circuit group includes three pixel circuits arranged in a first direction, namely a first pixel circuit, a second pixel circuit, and a third pixel circuit. The first pixel circuit and the second pixel circuit are mirror-symmetrical along a second direction, and the third pixel circuit is not mirror-symmetrical with the adjacent pixel circuit along the first direction;

[0014] The display panel includes multiple light-emitting element groups. The light-emitting element groups are located on the side of the pixel circuit group away from the substrate. The light-emitting element group includes three light-emitting elements with different emission colors, namely a first light-emitting element, a second light-emitting element, and a third light-emitting element. The first pixel circuit is electrically connected to the first light-emitting element, the second pixel circuit is electrically connected to the second light-emitting element, and the third pixel circuit is electrically connected to the third light-emitting element.

[0015] In a third aspect, an embodiment of the present application provides a display device, and the display device includes any one of the above display panels.

[0016] The display panel provided by the embodiment of the present application includes a substrate and multiple pixel circuit groups located on one side of the substrate. The multiple pixel circuit groups are arranged in an array along the intersecting first direction and second direction. The pixel circuit group includes at least three pixel circuits, and the at least three pixel circuits include a first pixel circuit, a second pixel circuit, and a third pixel circuit; wherein, the first pixel circuit and the second pixel circuit are mirror-symmetrical along the second direction. In this way, the first pixel circuit and the second pixel circuit that are mirror-symmetrical along the second direction can share some vias, saving the occupied space of the pixel circuit, improving the pixel density of the display panel, and thus improving the resolution of the display panel; and, the third pixel circuit is not mirror-symmetrical with the adjacent pixel circuit (such as the first pixel circuit and / or the second pixel circuit) along the first direction. In this way, the structures of the pixel circuits of the same-color sub-pixels are the same. Then, the directions in which the key nodes of the pixel circuits of the same-color sub-pixels shift due to process fluctuations are the same, thereby improving the display effect of the display panel. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application;

[0019] Figure 2 It is a schematic structural diagram of a pixel circuit in the display panel provided by an embodiment of the present application;

[0020] Figure 3 Schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present application;

[0021] Figure 4 For providing to Figure 3 A timing diagram of each signal of the pixel circuit shown;

[0022] Figure 5 Top view schematic diagram of an arrangement structure of a pixel circuit in a display panel provided by an embodiment of the present application;

[0023] Figure 6 Top view schematic diagram of another arrangement structure of a pixel circuit in a display panel provided by an embodiment of the present application;

[0024] Figure 7 Top view schematic diagram of yet another arrangement structure of a pixel circuit in a display panel provided by an embodiment of the present application;

[0025] Figure 8 Top view schematic diagram of still another arrangement structure of a pixel circuit in a display panel provided by an embodiment of the present application;

[0026] Figure 9 Top view schematic diagram of yet another arrangement structure of a pixel circuit in a display panel provided by an embodiment of the present application;

[0027] Figure 10 Top view schematic diagram of still another arrangement structure of a pixel circuit in a display panel provided by an embodiment of the present application;

[0028] Figure 11 Partial stacked layout structure schematic diagram of a group of pixel circuit groups in a display panel provided by an embodiment of the present application;

[0029] Figure 12 Top view schematic diagram of yet another arrangement structure of a pixel circuit in a display panel provided by an embodiment of the present application;

[0030] Figure 13 Top view schematic diagram of still another arrangement structure of a pixel circuit in a display panel provided by an embodiment of the present application;

[0031] Figure 14 Top view schematic diagram of yet another arrangement structure of a pixel circuit in a display panel provided by an embodiment of the present application;

[0032] Figure 15 Top view schematic diagram of still another arrangement structure of a pixel circuit in a display panel provided by an embodiment of the present application;

[0033] Figure 16 Top view schematic diagram of yet another arrangement structure of a pixel circuit in a display panel provided by an embodiment of the present application;

[0034] Figure 17 It is a top - view schematic diagram of another pixel circuit layout structure in the display panel provided by the embodiment of the present application;

[0035] Figure 18 It is a partial layout structure schematic diagram of the active layer poly in a display panel provided by the embodiment of the present application;

[0036] Figure 19 It is a partial layout structure schematic diagram of the metal layer M1 in a display panel provided by the embodiment of the present application;

[0037] Figure 20 It is a partial layout structure schematic diagram of a stack composed of the active layer poly and the metal layer M1 in a display panel provided by the embodiment of the present application;

[0038] Figure 21 It is a partial layout structure schematic diagram of the metal layer MC in a display panel provided by the embodiment of the present application;

[0039] Figure 22 It is a partial layout structure schematic diagram of the oxide layer IGZO in a display panel provided by the embodiment of the present application;

[0040] Figure 23 It is a partial layout structure schematic diagram of the metal layer MG in a display panel provided by the embodiment of the present application;

[0041] Figure 24 It is a partial layout structure schematic diagram of a stack composed of the metal layer MC, the oxide layer IGZO, and the metal layer MG in a display panel provided by the embodiment of the present application;

[0042] Figure 25 It is a partial layout structure schematic diagram of the metal layer M2 in a display panel provided by the embodiment of the present application;

[0043] Figure 26 It is a partial layout structure schematic diagram of a stack composed of the metal layer M3 and the metal layer M4 in a display panel provided by the embodiment of the present application;

[0044] Figure 27 It is a partial layout structure schematic diagram of the first reference voltage line and the bias voltage line in a display panel provided by the embodiment of the present application;

[0045] Figure 28 It is a partial layout structure schematic diagram of the first reference voltage line, the bias voltage line, and the second reference voltage line in a display panel provided by the embodiment of the present application;

[0046] Figure 29A top view schematic diagram of a display panel provided by an embodiment of the present application;

[0047] Figure 30 A partially enlarged top view schematic diagram of a display panel provided by an embodiment of the present application;

[0048] Figure 31 For Figure 26 A layout structure schematic diagram of the second - first power supply voltage line in

[0049] Figure 32 A structure schematic diagram of another pixel circuit in the display panel provided by an embodiment of the present application;

[0050] Figure 33 A partially layout structure schematic diagram of metal layer M4 and metal layer RE in a display panel provided by an embodiment of the present application;

[0051] Figure 34 A partially layout structure schematic diagram of a single pixel circuit group and a single light - emitting element group in a display panel provided by an embodiment of the present application;

[0052] Figure 35 A layout structure schematic diagram of a light - emitting element group in the display panel provided by an embodiment of the present application;

[0053] Figure 36 A layout structure schematic diagram of another light - emitting element group in the display panel provided by an embodiment of the present application;

[0054] Figure 37 A layout structure schematic diagram of another light - emitting element group in the display panel provided by an embodiment of the present application;

[0055] Figure 38 A top view schematic diagram of a display device provided by an embodiment of the present application. Detailed implementation manners

[0056] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0057] In the description and claims of this application and the above-mentioned drawings, terms such as "first" and "second" are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing embodiments of this application. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0058] As described in the background art section, how to arrange and design sub-pixels in a display panel to improve the pixel density (Pixels Per Inch, PPI) of the display panel, thereby improving the resolution of the display panel while also improving the display effect of the display panel is a technical problem that those skilled in the art urgently need to solve.

[0059] In view of this, an embodiment of this application provides a display panel. Figure 1 The cross-sectional structure schematic diagram of a display panel provided by an embodiment of this application is shown, as Figure 1 shown, the display panel includes a substrate sub, a driving circuit layer 100 on one side of the substrate sub, and a light-emitting element layer 200 on the side of the driving circuit layer 100 facing away from the substrate sub. The driving circuit layer 100 includes a pixel circuit 10 and a signal line 20, and the light-emitting element layer 200 includes a light-emitting element 30.

[0060] It can be understood that the signal line 20 is configured to provide a voltage signal and / or a current signal to the pixel circuit 10; the pixel circuit 10 is configured to drive the light-emitting element 30 to emit light and display, and control the light-emitting brightness of the light-emitting element 30; a pixel circuit 10 and a corresponding driven light-emitting element 30 form a sub-pixel, and multiple sub-pixels in the display panel are arranged in an array.

[0061] Figure 2 and Figure 3 The structure schematic diagrams of two pixel circuits 10 in the display panel provided by an embodiment of this application are shown, as Figure 2 and Figure 3As shown, the pixel circuit 10 includes eight thin film transistors, namely a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a compensating transistor T4, a gate reset transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, and a bias transistor T8, as well as a storage capacitor Cst; the signal lines 20 include a scan line, a reference voltage line, a power supply voltage line, and a data line DL. Among them, the scan line includes a first scan line SN1, a second scan line SP, a third scan line SN2, a bias control line SPX, and a light-emitting control line EM, the reference voltage line includes at least one of a first reference voltage line Ref1 and a second reference voltage line Ref2, and the power supply voltage line includes a first power supply voltage line PVDD and a second power supply voltage line PVEE; the pixel circuit 10 is electrically connected to the anode of the light-emitting element 30, and the cathode of the light-emitting element 30 is electrically connected to the second power supply voltage line PVEE.

[0062] In the pixel circuit 10, as Figure 2 and Figure 3 shown, the first pole of the first light-emitting control transistor T1 is electrically connected to the first power supply voltage line PVDD, the second pole of the first light-emitting control transistor T1 is electrically connected to the second node N2, and the gate of the first light-emitting control transistor T2 is electrically connected to the light-emitting control line EM;

[0063] The first pole of the data writing transistor T2 is electrically connected to the data line DL, the second pole of the data writing transistor T2 is electrically connected to the second node N2, and the gate of the data writing transistor T2 is electrically connected to the second scan line SP;

[0064] The first pole of the driving transistor T3 is electrically connected to the second node N2, the second pole of the driving transistor T3 is electrically connected to the third node N3, and the gate of the driving transistor T3 is electrically connected to the first node N1;

[0065] The first pole of the gate reset transistor T5 is electrically connected to the second reference signal line Ref2, the second pole of the gate reset transistor T5 is electrically connected to the first node N1, and the gate of the gate reset transistor T5 is electrically connected to the first scan line SN1;

[0066] The first pole of the compensating transistor T4 is electrically connected to the third node N3, the second pole of the compensating transistor T4 is electrically connected to the first node N1, and the gate of the compensating transistor T4 is electrically connected to the third scan line SN2;

[0067] The first pole of the second light-emitting control transistor T6 is electrically connected to the third node N3, the second pole of the second light-emitting control transistor T6 is electrically connected to the fourth node N4, and the gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line EMIT;

[0068] The first pole of the anode reset transistor T7 is electrically connected to the first reference voltage line Ref1, the second pole of the anode reset transistor T7 is electrically connected to the fourth node N4, and the gate of the anode reset transistor T7 is electrically connected to the bias control line SPX;

[0069] The first pole of the bias transistor T8 is electrically connected to the bias voltage line DVH, the second pole of the bias transistor T8 is electrically connected to the second node N2, and the gate of the bias transistor T8 is electrically connected to the bias control line SPX;

[0070] The first plate of the storage capacitor Cst is electrically connected to the first power supply voltage line PVDD, and the second plate of the storage capacitor Cst is electrically connected to the first node N1;

[0071] Thus, the pixel circuit 10 of the 8T1C structure is realized.

[0072] It can be understood that the first node N1, the second node N2, the third node N3, and the fourth node N4 can be virtual connection nodes or actual connection nodes.

[0073] It should be noted that Figure 2 and Figure 3 The pixel circuit 10 shown is only an example. In actual applications, a pixel circuit 10 with other circuit structures can be selected based on requirements, and it is not limited to Figure 1 and Figure 2 the 8T1C pixel circuit shown.

[0074] It should also be noted that the first reference voltage line Ref1 and the second reference voltage line Ref2 can transmit the same reference signal, that is, one reference signal can be used to reset the first node N1 and the fourth node N4. Alternatively, the reference signals transmitted by the first reference voltage line Ref1 and the second reference voltage line Ref2 can also be different, that is, the reset voltage of the first node N1 can be different from the reset voltage of the fourth node N4. This application does not make any limitations in this regard and depends on the specific situation.

[0075] Combined with Figures 1 - 3 shown, each thin film transistor in the pixel circuit 10 can be a low-temperature polycrystalline silicon (LTPS) thin film transistor Qx. Specifically, the LTPS thin film transistor Qx includes an active layer b1, a gate g, a source electrode s1, and a drain electrode d1. It can also be an indium gallium zinc oxide (IGZO) thin film transistor Qy. Specifically, the IGZO thin film transistor Qy includes an oxide layer b2, a bottom gate dg, a top gate tg, a source electrode s2, and a drain electrode d2.

[0076] Optionally, combined withFigure 1 and Figure 2 As shown in Figure 1 and Figure 2 , each thin film transistor in the pixel circuit 10 can be an LTPS thin film transistor. At this time, each thin film transistor in the pixel circuit 10 can be a PMOS thin film transistor, but the present application does not limit this, and it depends on the specific situation.

[0077] Optionally, as shown in Figure 1 and Figure 3 , in the pixel circuit 10, the compensation transistor T4 and the gate initialization transistor T5 can be IGZO thin film transistors with a double gate structure having a bottom gate dg and a top gate tg, and other thin film transistors can be LTPS thin film transistors. Since the IGZO thin film transistor has less leakage, the pixel circuit 10 can achieve low-frequency driving, that is, it can be a low-frequency pixel circuit; at this time, the compensation transistor T4 and the gate initialization transistor T5 can be NMOS thin film transistors, and other thin film transistors can be PMOS thin film transistors, but the present application does not limit this, and it depends on the specific situation.

[0078] Figure 4 shows a timing diagram of each signal provided to the pixel circuit 10 shown in Figure 3 . As shown in Figure 3 and Figure 4 , taking the compensation transistor T4 and the gate initialization transistor T5 as NMOS thin film transistors and other transistors as PMOS thin film transistors as an example. A signal at an enabling level can turn on the transistor, and a signal at a non-enabling level can turn off (or cut off) the transistor. The enabling level of the scan signal VSN1 provided by the first scan line SN1 and the scan signal VSN2 provided by the third scan line SN2 is a high level, and the non-enabling level is a low level; the enabling level of the scan signal VSP provided by the second scan line SP, the bias control signal VSPX provided by the bias control line SPX, and the light emission control signal VEM provided by the light emission control line EM is a low level, and the non-enabling level is a high level.

[0079] As shown in Figure 3 and Figure 4 , a driving cycle of the pixel circuit 10 in the low-frequency state is divided into a data writing stage P1, a light emission stage P2, and a light emission holding stage P2. Among them, the data writing stage P1 is further divided into four time periods t1 - t4, where:

[0080] ​​​​​​​​​​​​​​During the t1 period, the scanning signal VSN2 is at the enable level, the compensation transistor T4 is turned on, and the bias control signal VSPX is at the enable level, the anode reset transistor T7 and the bias transistor T8 are turned on, and the bias voltage signal VDVH provided by the bias signal line DVH can be written to the first pole and / or the second pole of the driving transistor T3, refreshing the potential of the first pole and / or the second pole of the driving transistor T3, setting the device characteristics of the driving transistor T3 to a determined initial state, eliminating the influence of the data signal written in the previous frame on the device characteristics of the driving transistor T3, and resetting the anode of the light-emitting element 30;

[0081] During the t2 period, the scanning signal VSN1 is at the enable level, the gate reset transistor T5 is turned on, and the reference voltage signal provided by the second reference voltage line Ref2 can be transmitted to the gate of the driving transistor T3 to reset the gate of the driving transistor T3. Subsequently, the scanning signal VSN2 is at the enable level, the compensation transistor T4 is turned on, and the driving transistor T3 is diode-connected through the turned-on compensation transistor T4;

[0082] During the t3 period, the scanning signal VSN2 is at the enable level, the compensation transistor T4 is turned on, and the scanning signal VSP is at the enable level, the data writing transistor T2 is turned on, so that the data signal transmitted by the data signal line DL is written to the gate of the driving transistor T2 (also known as the threshold capture of the driving transistor T3);

[0083] During the t4 stage, the bias control signal VSPX is at the enable level, the anode reset transistor T7 and the bias transistor T8 are turned on, and the bias voltage can be written to the first pole and / or the second pole of the driving transistor T3 by using the bias transistor T8, so that the bias state of the driving transistor T3 can be maintained consistent with the bias state when the data voltage is just written, to improve the stability of the working state of the driving transistor T3, improve low-frequency flicker, and reset the anode of the light-emitting element 40.

[0084] During the light-emitting stage P2, the light-emitting control signal VEM is at the enable level, the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on, and the driving transistor T3 drives the light-emitting element 40 to emit light.

[0085] It can be seen that the data writing stage P1 includes a non - enabling level stage of the light - emitting control signal VEM, the light - emitting stage P2 includes an enabling level stage of the light - emitting control signal VEM, and the light - emitting holding stage P3 includes at least one non - enabling level stage and at least one enabling level stage of the light - emitting control signal VEM. In fact, when the display panel needs to have different refresh frequencies, the duration of the light - emitting holding stage P3 can be appropriately adjusted. When the display panel needs a high - frequency driving mode, compared with the low - frequency driving mode, the duration of the light - emitting holding stage P3 can be reduced as much as possible, or even there is no light - emitting holding stage P3. At this time, after the light - emitting stage P2, it re - enters the next data writing stage P1.

[0086] Multiple sub - pixels in the display panel are divided into different - colored sub - pixels according to the different light - emitting colors of the light - emitting elements. For example, the sub - pixel corresponding to the red light - emitting element is the red sub - pixel, the sub - pixel corresponding to the green light - emitting element is the green sub - pixel, and the sub - pixel corresponding to the blue light - emitting element is the blue sub - pixel. Usually, different - colored sub - pixels adjacent to each other (such as red, green, and blue sub - pixels) are regarded as a pixel as a whole. By controlling the brightness of different - colored sub - pixels (such as red, green, and blue sub - pixels) in a pixel, a pixel can display various colors. Therefore, how the sub - pixels are arranged and designed in the display panel is crucial for the resolution and display effect of the display panel.

[0087] Since the sub - pixels in the display panel include pixel circuits and light - emitting elements, the arrangement design of the pixel circuits and the arrangement design of the light - emitting elements in the display panel will be described separately below.

[0088] First, the arrangement design of the pixel circuits in the display panel will be described. Since the pixel circuit 10 and the signal line 20 are both located in the driving circuit layer 100, when introducing the arrangement design of the pixel circuit 10, the arrangement design of the signal line 20 will also be introduced.

[0089] Figures 5 - 10 The top - view schematic diagram of six pixel - circuit arrangement structures in the display panel provided by the embodiment of the present application is shown. As Figures 5 - 10 shown, the display panel includes multiple pixel - circuit groups 110, and the multiple pixel - circuit groups 110 are arranged in an array along the first direction X and the second direction Y, and the first direction X and the second direction Y intersect. Optionally, the first direction X and the second direction Y are perpendicular. For example, the first direction X is the row direction and the second direction Y is the column direction.

[0090] As Figures 5 - 10 shown, the pixel - circuit group 110 includes at least three pixel circuits 10, and the at least three pixel circuits 10 include a first pixel circuit 11, a second pixel circuit 12, and a third pixel circuit 13. Combining Figure 1 、Figures 5 - 10 As shown, the pixel circuit group 110 is located on the driving circuit layer 100, that is, the pixel circuit group 110 is located on one side of the substrate 10.

[0091] As Figures 5 - 10 shown, in the pixel circuit group 110, the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, and the third pixel circuit 13 is not mirror-symmetrical with the adjacent pixel circuit along the first direction X.

[0092] Figure 11 The figure shows a partial stacked layout structure diagram of a group of pixel circuit groups 110 in a display panel provided by an embodiment of the present application. Combining Figure 5 、 Figure 6 and Figure 11 shown, in the pixel circuit group 110, the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y. For example, the orthographic projection of the first pixel circuit 11 on the plane of the substrate is the first pattern structure, and the orthographic projection of the second pixel circuit 12 on the plane of the substrate is the second pattern structure. Along the second direction Y, the first pattern structure and the second pattern structure are mirror-symmetrical. It should be noted that for the first pattern structure and the second pattern structure to be mirror-symmetrical along the second direction Y, a certain error is allowed. For example, if 80% or more of the first pattern structure and the second pattern structure are mirror-symmetrical along the second direction Y, then it can be considered that the first pattern structure and the second pattern structure are mirror-symmetrical along the second direction Y.

[0093] Combining Figure 5 、 Figure 6 and Figure 11 shown, the third pixel circuit 13 in the pixel circuit group 110 is not mirror-symmetrical with the adjacent pixel circuit along the first direction X. For example, the orthographic projection of the third pixel circuit 13 on the plane of the substrate is the third pattern structure. Along the second direction Y, the third pattern structure is not mirror-symmetrical with the pattern structures of the pixel circuits adjacent to the third pixel circuit 13 along the first direction X, such as the first pixel circuit 11 and / or the second pixel circuit 12. Specifically, for example, the orthographic projection of the third pixel circuit 13 on the plane of the substrate is the third pattern structure. Along the second direction Y, the third pattern structure is not mirror-symmetrical with the pattern structures of the first pixel circuit 11 or the second pixel circuit 12 in the pixel circuit 110 adjacent to the third pixel circuit 13 along the first direction X. It should be noted that the two pattern structures being non-mirror-symmetrical along the second direction Y means that the non-mirror-symmetrical part of the two pattern structures along the second direction Y exceeds a certain proportion.

[0094] Combining Figure 2 、 Figure 3 and Figure 11As shown, regardless of whether the pixel circuit 10 is the first pixel circuit 11, the second pixel circuit 12, or the third pixel circuit 13, the pixel circuit 10 includes a plurality of thin film transistors (T1-T8), a storage capacitor Cst, and key nodes (such as the first node N1, the second node N2, the third node N3, and the fourth node N4). In the present application, the fact that the first pixel circuit 11 and the second pixel circuit 12 in the pixel circuit group 110 are mirror-symmetrical along the second direction Y mainly means that the thin film transistors (such as T1-T8), the storage capacitor Cst, and the key nodes (such as the first node N1, the second node N2, the third node N3, and the fourth node N4) in the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y.

[0095] It can be understood that the first pixel circuit 11 and the second pixel circuit 12 in the pixel circuit group 110 are mirror-symmetrical along the second direction Y. Thus, the first pixel circuit 11 and the second pixel circuit 12 that are mirror-symmetrical along the second direction Y can share some vias, saving the occupied space of the pixel circuit, improving the pixel density of the display panel, and thus improving the resolution of the display panel.

[0096] Optionally, in some embodiments, such as Figures 5 - 10 As shown, in the pixel circuit group 110, the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 are arranged along the first direction X.

[0097] Further optionally, in some embodiments, such as Figures 5 - 8 As shown, in the pixel circuit group 110, the first pixel circuit 11 and the second pixel circuit 12 are adjacent to each other along the first direction X, the third pixel circuit 13 is adjacent to the first pixel circuit 11 or the second pixel circuit 12 along the first direction X, and the third pixel circuit 13 is not mirror-symmetrical with the first pixel circuit 11 or the second pixel circuit 12 that is adjacent along the first direction X.

[0098] Taking the pixel circuit group 110 including the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 as an example, optionally, such as Figure 5 and Figure 6 As shown, the first pixel circuit 11 and the second pixel circuit 12 are two adjacent pixel circuits on the left side of the pixel circuit group 110 along the first direction X, and the third pixel circuit 13 is a pixel circuit on the right side of the pixel circuit group 110 along the first direction X. Since the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, therefore, Figure 5 and Figure 6 substantially represent the same pixel circuit arrangement.

[0099] Taking the pixel circuit group 110 including the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 as an example, another optionally, such asFigure 7 and Figure 8 As shown in Figure 8 , the first pixel circuit 1 and the second pixel circuit 12 are two adjacent pixel circuits on the right side of the pixel circuit group 110 along the first direction X, and the third pixel circuit 13 is a pixel circuit on the left side of the pixel circuit group 110 along the first direction X. Since the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, therefore, Figure 7 and Figure 8 substantially represent the same pixel circuit arrangement.

[0100] Considering that a pixel in the display panel usually includes three sub-pixels of red (R), green (G), and blue (B), then, in a pixel, there are three implementation modes for which two-color sub-pixel pixel circuits are the adjacent first pixel circuit 11 and second pixel circuit 12 that are mirror-symmetrical along the second direction Y, and which one-color sub-pixel pixel circuit is the third pixel circuit 13:

[0101] The first implementation mode is as shown in Figure 12 . In a pixel, the pixel circuits of the red (R) and green (G) sub-pixels are the adjacent first pixel circuit 11 and second pixel circuit 12 that are mirror-symmetrical along the second direction Y. The pixel circuit of the red (R) sub-pixel is one of the first pixel circuit 11 and the second pixel circuit 12, the pixel circuit of the green (G) sub-pixel is the other of the first pixel circuit 11 and the second pixel circuit 12, and the pixel circuit of the blue (B) sub-pixel is the third pixel circuit 13.

[0102] The second implementation mode is as shown in Figure 13 . In a pixel, the pixel circuits of the green (G) and blue (B) sub-pixels are the adjacent first pixel circuit 11 and second pixel circuit 12 that are mirror-symmetrical along the second direction Y. The pixel circuit of the green (G) sub-pixel is one of the first pixel circuit 11 and the second pixel circuit 12, the pixel circuit of the blue (B) sub-pixel is the other of the first pixel circuit 11 and the second pixel circuit 12, and the pixel circuit of the red (R) sub-pixel is the third pixel circuit 13.

[0103] The third implementation mode is as shown in Figure 14 . In a pixel, the pixel circuits of the blue (B) and red (R) sub-pixels are the adjacent first pixel circuit 11 and second pixel circuit 12 that are mirror-symmetrical along the second direction Y. The pixel circuit of the blue (B) sub-pixel is one of the first pixel circuit 11 and the second pixel circuit 12, the pixel circuit of the red (R) sub-pixel is the other of the first pixel circuit 11 and the second pixel circuit 12, and the pixel circuit of the green (G) sub-pixel is the third pixel circuit 13.

[0104] ​​​​​​Based on the arrangement of the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 in the pixel circuit group 110 along the first direction X, optionally, in some other embodiments, such as Figure 9 and Figure 10 shown, in the pixel circuit group 110, the third pixel circuit 13 is located between the first pixel circuit 11 and the second pixel circuit 12, but does not affect the mirror symmetry of the first pixel circuit 11 and the second pixel circuit 12 along the second direction Y, and the third pixel circuit 13 is not mirror-symmetrical with the adjacent first pixel circuit 11 and second pixel circuit 12 along the first direction X. Since the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, therefore, Figure 9 and Figure 10 substantially represent the same pixel circuit arrangement.

[0105] Considering that a pixel in the display panel usually includes red (R), green (G), and blue (B) sub-pixels, then, in a pixel, there are three embodiments regarding which two-color sub-pixel pixel circuits are the first pixel circuit 11 and the second pixel circuit 12 that are spaced apart and mirror-symmetrical along the second direction Y, and which one-color sub-pixel pixel circuit is the third pixel circuit 13:

[0106] The first embodiment is as Figure 15 shown. In a pixel, the pixel circuits of the red (R) and green (G) sub-pixels are the first pixel circuit 11 and the second pixel circuit 12 that are spaced apart and mirror-symmetrical along the second direction Y. The pixel circuit of the red (R) sub-pixel is one of the first pixel circuit 11 and the second pixel circuit 12, and the pixel circuit of the green (G) sub-pixel is the other of the first pixel circuit 11 and the second pixel circuit 12. The pixel circuit of the blue (B) sub-pixel is the third pixel circuit 13.

[0107] The second embodiment is as Figure 16 shown. In a pixel, the pixel circuits of the green (G) and blue (B) sub-pixels are the first pixel circuit 11 and the second pixel circuit 12 that are spaced apart and mirror-symmetrical along the second direction Y. The pixel circuit of the green (G) sub-pixel is one of the first pixel circuit 11 and the second pixel circuit 12, and the pixel circuit of the blue (B) sub-pixel is the other of the first pixel circuit 11 and the second pixel circuit 12. The pixel circuit of the red (R) sub-pixel is the third pixel circuit 13.

[0108] The third embodiment is as Figure 17As shown, in a pixel, the pixel circuits of the blue (B) and red (R) sub-pixels are the first pixel circuit 11 and the second pixel circuit 12 that are spaced apart and mirror-symmetrical along the second direction Y. The pixel circuit of the blue (B) sub-pixel is one of the first pixel circuit 11 and the second pixel circuit 12, and the pixel circuit of the red (R) sub-pixel is the other of the first pixel circuit 11 and the second pixel circuit 12. The pixel circuit of the green (G) sub-pixel is the third pixel circuit 13.

[0109] Reference Figures 12 - 17 As shown, in the pixel circuit group 110, the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, so that the first pixel circuit 11 and the second pixel circuit 12 that are mirror-symmetrical along the second direction Y can share some vias, saving the occupied space of the pixel circuit, improving the pixel density of the display panel, and thus improving the resolution of the display panel. At the same time, the third pixel circuit 13 is set to be non-mirror-symmetrical with the pixel circuits adjacent along the first direction X (such as the first pixel circuit 11 and / or the second pixel circuit 12). In this way, the structures of the pixel circuits of the same-color sub-pixels are the same. For example, the structures of the pixel circuits of the red (R) sub-pixels are the same, the structures of the pixel circuits of the green (G) sub-pixels are the same, and the structures of the pixel circuits of the blue (B) sub-pixels are the same. Then, the directions in which the key nodes of the pixel circuits of the same-color sub-pixels shift due to process fluctuations are the same, thereby improving the display effect of the display panel.

[0110] It should be noted that Figure 1 is a schematic diagram of the film stack structure of a display panel shown by taking the pixel circuit 10 including LTPS thin-film transistors and IGZO thin-film transistors as an example. It can be seen that the display panel includes a substrate sub, an active layer poly on one side of the substrate sub, a multi-layer metal layer on the side of the active layer poly facing away from the substrate sub, and an oxide layer IGZO. Among them, the multi-layer metal layer includes a metal layer M1, a metal layer MC, a metal layer MG, a metal layer M2, a metal layer M3, a metal layer M4, and a metal layer RE arranged in the direction away from the substrate sub. The oxide layer IGZO is located between the metal layer MC and the metal layer MG. Different metal layers, between the metal layer and the active layer, and between the metal layer and the oxide layer are all isolated by insulating layers. And, in the display panel, the light-emitting element 30 is located on the side of the pixel circuit 10 facing away from the substrate sub. The light-emitting element 30 includes an anode E1, a light-emitting layer E2, and a cathode E3 arranged in the direction away from the substrate sub.

[0111] On this basis, in a display panel provided by an embodiment of the present application, the local layout structure of the active layer poly is as Figure 18 shown, and the local layout structure of the metal layer M1 is as Figure 19As shown, the partial layout structure of the stack composed of the active layer poly and the metal layer M1 is as Figure 20 shown; the partial layout structure of the metal layer MC is as Figure 21 shown; the partial layout structure of the oxide layer IGZO is as Figure 22 shown; the partial layout structure of the metal layer MG is as Figure 23 shown; the partial layout structure of the stack composed of the metal layer MC, the oxide layer IGZO, and the metal layer MG is as Figure 24 shown; the partial layout structure of the metal layer M2 is as Figure 25 shown; the partial layout structure of the metal layer M3 and the metal layer M4 is as Figure 26 shown.

[0112] It should be noted that, to clearly distinguish different pixel circuit regions, in Figures 18 - 26 , horizontal dotted lines and vertical dotted lines are used to represent the boundaries of adjacent pixel circuit regions along the first direction X and the second direction Y. It can be understood that this boundary is only for the convenience of explanation and does not limit the pixel circuit 10. Similar situations in other drawings of this application will not be elaborated. Additionally, Figure 11 shown, the layout structure of a pixel circuit group 110 includes the layout structure of the stack of the active layer poly, the metal layer M1, the metal layer MC, the oxide layer IGZO, and the metal layer MG.

[0113] Referring to Figure 2 and Figure 3 shown, the display panel includes a first reference voltage line Ref1, and the pixel circuit 10 includes an anode reset transistor T7. The anode reset transistor T7 is electrically connected between the first reference voltage line Ref1 and the anode of the light-emitting element 30. When the anode reset transistor T7 is turned on, the anode reset transistor T7 can transmit the reference voltage signal transmitted on the first reference voltage line Ref1 to the anode of the light-emitting element 30 to reset the anode of the light-emitting element 30.

[0114] Corresponding to the layout structure of the display panel, in combination with Figure 21 and Figure 25 shown, the first reference voltage line Ref1 may include first sub-reference voltage lines Ref11 extending along the first direction X and arranged along the second direction Y, and second sub-reference voltage lines Ref12 extending along the second direction Y and arranged along the first direction X. Figure 27 Further shows a schematic diagram of the partial layout structure of the first reference voltage line Ref1 in a display panel provided by an embodiment of the present application. In combination with Figure 21 , Figure 25 and Figure 27 shown, in the first reference voltage line Ref1, the first sub-reference voltage lines Ref11 and the second sub-reference voltage lines Ref12 are electrically connected.

[0115] Optionally, both the first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 can be multiple. There can be multiple crossing positions of the multiple first sub-reference voltage lines Ref11 and the multiple second sub-reference voltage lines Ref12. The electrical connection between the first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 includes: the first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 are electrically connected at all their crossing positions, as Figure 27 shown, or, the first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 are electrically connected at some of their crossing positions. Specifically, each first sub-reference voltage line Ref11 can be electrically connected to at least one second sub-reference voltage line Ref12, and each second sub-reference voltage line Ref12 can be electrically connected to at least one first sub-reference voltage line Ref11. Combining Figure 21 、 Figure 25 and Figure 27 shown, the first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 can be electrically connected through the connection part L1 located at their crossing position and in the metal layer M2.

[0116] Optionally, combining Figure 21 、 Figure 25 and Figure 27 shown, the first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 are arranged in different layers. In this way, the signal lines extending in different directions are located in different metal layers, so as to reduce the difficulty of arranging the signal lines in the same metal layer. For example, the first sub-reference voltage line Ref11 is located in the metal layer MC, and the second sub-reference voltage line Ref12 is located in the metal layer M2. The first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 are electrically connected through vias between the metal layer MC and the metal layer M2.

[0117] It can be understood that by setting the first reference voltage line Ref1 to include the first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 that extend in different directions and are cross-connected electrically, a grid-structured first reference voltage line Ref1 is formed, so as to reduce the overall resistance of the first reference voltage line Ref1, further reduce the power consumption of the first reference voltage line Ref1, and improve the signal transmission stability of the first reference voltage line Ref1, which is beneficial to improving display effects such as the display uniformity of the display panel.

[0118] It can also be understood that the first sub-reference voltage line Ref11 can be located in a metal layer (such as metal layer M1); or, the first sub-reference voltage line Ref11 can include sub-reference voltage lines located in different conductive layers, extending along the first direction X, and arranged along the second direction Y. Similarly, the second sub-reference voltage line Ref12 can be located in a metal layer (such as metal layer M2); or, the second sub-reference voltage line Ref12 can include sub-reference voltage lines located in different conductive layers, extending along the second direction Y, and arranged along the first direction X.

[0119] As shown in combination with Figures 18 - 20 the anode reset transistor T7 includes a channel region p7 located in the active layer poly, and a first pole p71 and a second pole p72 connected to the channel region p7; and, the display panel includes a bias control line SPX, the bias control line SPX extends along the second direction Y, optionally, the bias control line SPX is located in the metal layer M1; in a direction perpendicular to the plane of the substrate, the bias control line SPX at least partially overlaps with the channel region p7 of the anode reset transistor T7, optionally, in a direction perpendicular to the plane of the substrate, the overlapping part of the second scan line SP and the channel region p7 of the anode reset transistor T7 is the gate g7 of the anode reset transistor T7, so that the bias control line SPX is electrically connected to the gate of the anode reset transistor T7.

[0120] As shown in combination with Figures 18 - 21 、 Figure 25 and Figure 26 the first pole p71 of the anode reset transistor T7 is electrically connected to the first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 through a connection part L1 located in the metal layer M2, and the second pole p721 of the anode reset transistor T7 is electrically connected to the anode of the light-emitting element through a connection part L2 located in the metal layer M2, a connection part L3 located in the metal layer M3, and a connection part L4 located in the metal layer M4.

[0121] As shown in combination with Figure 25 and Figure 27As shown, a plurality of pixel circuit groups 110 in the display panel are arranged in an array along a first direction X and along a second direction Y. Taking the second direction Y as the column direction, the number of columns of the array formed by the plurality of pixel circuit groups 110 is N10, and the number of second sub-reference voltage lines Ref12 is N11. Optionally, N11 ≤ N10, and both N10 and N11 are positive integers. That is, taking the number of columns N10 of the pixel circuit group 110 as a reference, the number of second sub-reference voltage lines Ref12, N11, can be equal to or less than the number of columns N10 of the pixel circuit group 110. Or rather, at least one column of pixel circuit groups 110 (one column of pixel circuit groups 110 includes at least three columns of pixel circuits 10) is correspondingly provided with one second sub-reference voltage line Ref12 in terms of quantity. Thus, to a great extent, the arrangement density of the second sub-reference voltage lines Ref12 extending along the second direction Y is reduced, which is beneficial to reducing the layout space of the pixel circuits 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0122] Combined with Figures 18 - 27 As shown, in the pixel circuit group 110, the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 are arranged along the first direction X; the first pixel circuit 11 is arranged in a first pixel circuit column 11B along the second direction Y, the second pixel circuit 12 is arranged in a second pixel circuit column 12B along the second direction Y, and the third pixel circuit 13 is arranged in a third pixel circuit column 13B along the second direction Y. It can be understood that since the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, and the first pixel circuit 11 is arranged in the first pixel circuit column 11B along the second direction Y, and the second pixel circuit 12 is arranged in the second pixel circuit column 12B along the second direction Y, therefore, the first pixel circuit column 11B and the second pixel circuit column 12B are mirror-symmetrical along the second direction Y. Similarly, the third pixel circuit column 13B is not mirror-symmetrical with the pixel circuit column adjacent along the first direction X (such as the first pixel circuit column 11B and / or the second pixel circuit column 12B).

[0123] Optionally, as Figure 25 and Figure 27As shown in the figure, in the direction perpendicular to the plane where the substrate is located, the second sub-reference voltage line Ref12 is correspondingly arranged with the first pixel circuit column 11B or the second pixel circuit column 12B in a column of pixel circuit groups 110. That is to say, the second sub-reference voltage line Ref12 is correspondingly arranged with one of the two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y in a column of pixel circuit groups 110. In terms of position, the second sub-reference voltage line Ref12 overlaps with one of the two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y in a column of pixel circuit groups 110 in the direction perpendicular to the plane where the substrate is located, so as to facilitate the periodic arrangement design of the second sub-reference voltage line Ref12 along the first direction X, and is also conducive to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0124] As Figure 26 shown in the figure, the display panel includes data lines DL. The data lines DL include first data lines DL1, second data lines DL2, and third data lines DL3 that extend along the second direction Y and are arranged along the first direction X. The first pixel circuit column 11B is electrically connected to the first data line DL1, the second pixel circuit column 12B is electrically connected to the second data line DL2, and the third pixel circuit column 13B is electrically connected to the third data line DL3.

[0125] Combined with Figures 25 - 27 shown in the figure, in the direction perpendicular to the plane where the substrate is located, the second sub-reference voltage line Ref12 is correspondingly arranged with the first pixel circuit column 11B in a column of pixel circuit groups 110, and the second sub-reference voltage line Ref12 at least partially overlaps with the first data line DL1 electrically connected to the first pixel circuit column 11B in a column of pixel circuit groups 110; or, in the direction perpendicular to the plane where the substrate is located, the second sub-reference voltage line Ref12 is correspondingly arranged with the second pixel circuit column 12B in a column of pixel circuit groups 110, and the second sub-reference voltage line Ref12 at least partially overlaps with the second data line DL2 electrically connected to the second pixel circuit column 12B in a column of pixel circuit groups 110. That is to say, the second sub-reference voltage line Ref12 is correspondingly arranged with one of the two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y in a column of pixel circuit groups 110, and the data line DL electrically connected to the column of pixel circuits 10 of the second sub-reference voltage line Ref12 at least partially overlaps in the direction perpendicular to the plane where the substrate is located. In this way, the arrangement density of the signal lines extending along the second direction Y can be reduced, which is conducive to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0126] It should be noted that when the number N11 of the second sub-reference voltage lines Ref12 is equal to or less than the number N10 of columns of the pixel circuit group 110, optionally, as Figure 21 and Figure 27 shown, one first sub-reference voltage line Ref11 is correspondingly set for one row of pixel circuit groups 110. For example, in terms of quantity, one first sub-reference voltage line Ref11 is correspondingly set for one row of pixel circuits 110, and in terms of position, one row of pixel circuit groups 110 overlaps with one first sub-reference voltage line Ref11 in the direction perpendicular to the plane of the substrate, so that each pixel circuit 10 can be electrically connected to the first reference voltage line Ref1.

[0127] Refer to Figure 2 and Figure 3 shown, the display panel includes a bias voltage line DVH, and the pixel circuit 10 includes a driving transistor T3 and a bias transistor T8. The bias transistor T8 is electrically connected between at least one of the first pole and the second pole of the driving transistor T3 and the bias voltage line DVH, that is, the bias transistor T8 can be electrically connected between the first pole of the driving transistor T3 and the bias voltage line DVH, or the bias transistor T8 can be electrically connected between the second pole of the driving transistor T3 and the bias voltage line DVH, or, the bias transistor T8 is simultaneously electrically connected to the first pole and the second pole of the driving transistor T3, and the bias transistor T8 is electrically connected to the bias voltage line DVH. Figure 2 and Figure 3 Only the case where the bias transistor T8 is electrically connected between the first pole of the driving transistor T3 and the bias voltage line DVH is exemplified.

[0128] It can be understood that when the bias transistor T8 is turned on, the bias transistor T8 can transmit the bias voltage signal transmitted on the bias voltage line DVH to the first pole and / or the second pole of the driving transistor T3, so as to bias the first pole and / or the second pole of the driving transistor T3, improve the brightness of the first frame during picture display, avoid too low brightness of the first frame, and ensure good consistency of the picture display effect. In addition, before resetting the gate of the driving transistor T3, by controlling the bias transistor T8 to be turned on, the bias voltage signal provided by the bias voltage line DVH can be written into the first pole and / or the second pole of the driving transistor T3, and the potential of the first pole and / or the second pole of the driving transistor T3 is refreshed, so that the device characteristics of the driving transistor T3 are set to a determined initial state, and the influence of the data signal written in the previous frame on the device characteristics of the driving transistor T3 is eliminated. After writing the data voltage to the driving transistor T3, the voltage of the first pole and / or the second pole of the driving transistor T3 will leak, especially under low-frequency driving, the leakage is more obvious, resulting in a large shift in the potential of the first pole and / or the second pole of the driving transistor T3. At this time, by controlling the bias transistor T8 to be turned on and using the bias transistor T8 to write a bias voltage signal to the first pole and / or the second pole of the driving transistor T3, the bias state of the driving transistor T3 can be maintained consistent with the bias state when the data voltage was just written, so as to improve the stability of the working state of the driving transistor T3, improve low-frequency flicker, and thus improve the picture display effect of the display panel.

[0129] Corresponding to the layout structure of the display panel, as Figure 23 , Figure 25 and Figure 27 shown, the bias voltage line DVH includes a first sub-bias voltage line DVH1 extending along the first direction X and arranged along the second direction Y, and a second sub-bias voltage line DVH2 extending along the second direction Y and arranged along the first direction X. The first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 are electrically connected. Among them, Figure 27 also shows the layout structure of the bias voltage line DVH.

[0130] Optionally, both the first sub-bias signal line DVH1 and the second sub-bias signal line DVH2 can be multiple. The intersection positions of the multiple first sub-bias signal lines DVH1 and the multiple second sub-bias signal lines DVH2 can be multiple. The electrical connection between the first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 includes: the first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 are electrically connected at all their intersection positions, as Figure 27As shown, alternatively, the first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 are electrically connected at a partial intersection position therebetween. Specifically, each first sub-bias signal line DVH1 can be electrically connected to at least one second sub-bias signal line DVH2, and each second sub-bias signal line DVH2 can be electrically connected to at least one first sub-bias signal line DVH1. In combination with Figure 23 , Figure 25 and Figure 27 As shown, the first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 can be electrically connected through a connection portion L5 located at the intersection position therebetween and in the metal layer M2.

[0131] Optionally, in combination with Figure 23 , Figure 25 and Figure 27 As shown, the first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 are arranged in different layers. In this way, signal lines extending in different directions are located in different metal layers to reduce the difficulty of arranging signal lines in the same metal layer. For example, the first sub-bias voltage line DVH1 is located in the metal layer MG, the second sub-bias voltage line DVH2 is located in the metal layer M2, and the first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 are electrically connected through vias between the metal layer MG and the metal layer M2.

[0132] For example, by setting the bias voltage line DVH to include a first sub-bias voltage line DVH1 and a second sub-bias voltage line DVH2 that extend in different directions and are cross-connected electrically, a grid-structured bias voltage line DVH is formed, so as to reduce the overall resistance of the bias voltage line DVH, thereby reducing the power consumption of the bias voltage line DVH, and improving the signal transmission stability of the bias voltage line DVH, which is beneficial to improving display effects such as display uniformity of the display panel.

[0133] In addition, the first sub-bias voltage line DVH1 can be located in one metal layer; or, the first sub-bias voltage line DVH1 can include sub-bias voltage lines located in different conductive layers, extending along the first direction X and arranged along the second direction Y. Similarly, the second sub-bias voltage line DVH2 can be located in one metal layer; or, the second sub-bias voltage line DVH2 can include sub-bias voltage lines located in different conductive layers, extending along the second direction Y and arranged along the first direction X.

[0134] In combination with Figures 18 - 20As shown, the bias transistor T8 includes a channel region p8 located in the active layer poly, and a first pole p81 and a second pole p82 connected to the channel region p8; and, the display panel includes a bias control line SPX, the bias control line SPX extends along the second direction Y, optionally, the bias control line SPX is located in the metal layer M1; in a direction perpendicular to the plane of the substrate, the channel region p8 of the bias transistor T8 and the bias control line SPX at least partially overlap. Optionally, in a direction perpendicular to the plane of the substrate, the overlapping portion of the bias control line SPX and the channel region p8 of the bias transistor T8 is the gate g8 of the bias transistor T8, such that the bias control line SPX is electrically connected to the gate g8 of the bias transistor T8.

[0135] Combined with Figures 18 - 20 As shown, the driving transistor T3 includes a channel region p3 located in the active layer poly, and a first pole p31 and a second pole p32 connected to the channel region p3, and, the driving transistor T3 further includes a gate g3 located in the metal layer M1, in a direction perpendicular to the plane of the substrate, the gate g3 of the driving transistor T3 and the channel region p3 of the driving transistor T3 at least partially overlap.

[0136] Combined with Figures 18 - 20 、 Figure 23 and Figure 25 As shown, the first pole p81 of the bias transistor T8 is electrically connected to the first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 through a connection portion L5 located in the metal layer M2, and the second pole p82 of the bias transistor T8 is electrically connected to the first pole p31 of the driving transistor T3 through a connection portion L6 located in the metal layer M2. Referring to Figure 2 and Figure 3 As shown, the connection portion L6 is the second node N2.

[0137] And, combined with Figures 18 - 20 、 Figure 23 and Figure 25 As shown, the bias transistors T8 of the first pixel circuit 11 and the second pixel circuit 12 that are mirror-symmetrical along the second direction Y in a group of pixel circuit groups 110 share a via (corresponding to the position of the connection portion L5) electrically connected to the bias voltage line DVH, which is beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0138] Optionally, combined with Figure 19 and Figure 23As shown, the bias control line SPX and the first sub-bias voltage line DVH1 both extend along the first direction X, and the bias control line SPX and the first sub-bias voltage line DVH1 are arranged in different layers. For example, the bias control line SPX is located in the metal layer M1, and the first sub-bias voltage line is located in the metal layer MG; in the direction perpendicular to the plane of the substrate, the first sub-bias voltage line DVH1 and the bias control line SPX at least partially overlap; thus, the layout density of the signal lines extending along the first direction X can be reduced, which is beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0139] Optionally, in combination with Figures 18 - 20 As shown, the bias control line SPX can also be electrically connected to the gate g7 of the anode reset transistor T7.

[0140] In combination with Figure 25 and Figure 27 As shown, multiple pixel circuit groups 110 in the display panel are arranged in an array along the first direction X and the second direction Y. Taking the second direction Y as the column direction, the number of columns of the array formed by the multiple pixel circuit groups 110 is N10, and the number of the second sub-bias voltage lines DVH2 is N12. Optionally, N12 ≤ N10, and both N10 and N12 are positive integers. That is, with reference to the number of columns N10 of the pixel circuit groups 110, the number of the second sub-bias voltage lines DVH2 can be equal to or less than the number of columns N10 of the pixel circuit groups 110. Or rather, at least one column of pixel circuit groups 110 (one column of pixel circuit groups 110 includes at least three columns of pixel circuits 10) corresponds to one second sub-bias voltage line DVH2 in terms of quantity; thus, to a great extent, the layout density of the second sub-bias voltage lines DVH2 extending along the second direction Y is reduced, which is beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0141] In combination with Figures 18 - 27As shown, in the pixel circuit group 110, the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 are arranged along the first direction X; the first pixel circuits 11 are arranged along the second direction Y to form a first pixel circuit column 11B, the second pixel circuits 12 are arranged along the second direction Y to form a second pixel circuit column 12B, and the third pixel circuits 13 are arranged along the second direction Y to form a third pixel circuit column 13B. It can be understood that since the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, and the first pixel circuits 11 are arranged along the second direction Y to form a first pixel circuit column 11B, and the second pixel circuits 12 are arranged along the second direction Y to form a second pixel circuit column 12B, therefore, the first pixel circuit column 11B and the second pixel circuit column 12B are mirror-symmetrical along the second direction Y. Similarly, the third pixel circuit column 13B is not mirror-symmetrical with the adjacent pixel circuit columns along the first direction X (such as the first pixel circuit column 11B and / or the second pixel circuit column 12B).

[0142] Optionally, as Figure 25 and Figure 27 shown, in the direction perpendicular to the plane of the substrate, the second sub-bias voltage line DVH2 is correspondingly arranged with the first pixel circuit column 11B or the second pixel circuit column 12B in a column of pixel circuit groups 110. That is to say, the second sub-bias voltage line DVH2 is correspondingly arranged with one of the two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y in a column of pixel circuit groups 110. In terms of position, the second sub-bias voltage line DVH2 overlaps with one of the two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y in a column of pixel circuit groups 110 in the direction perpendicular to the plane of the substrate, so as to facilitate the periodic arrangement design of the second sub-bias voltage line DVH2 along the first direction X, and is also beneficial to reducing the layout space of the pixel circuits 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0143] As Figure 26 shown, the display panel includes data lines DL. The data lines DL include first data lines DL1, second data lines DL2, and third data lines DL3 that extend along the second direction Y and are arranged along the first direction X. The first pixel circuit column 11B is electrically connected to the first data lines DL1, the second pixel circuit column 12B is electrically connected to the second data lines DL2, and the third pixel circuit column 13B is electrically connected to the third data lines DL3.

[0144] Combined with Figure 25 and Figure 26As shown, in the direction perpendicular to the plane of the substrate, the second sub-bias voltage line DVH2 is correspondingly arranged with the first pixel circuit column 11B in a column of pixel circuit groups 110, and the first data line DL1 electrically connected to the second sub-bias voltage line DVH2 and the first pixel circuit column 11B in a column of pixel circuit groups 110 at least partially overlaps; or, in the direction perpendicular to the plane of the substrate, the second sub-bias voltage line DVH2 is correspondingly arranged with the second pixel circuit column 12B in a column of pixel circuit groups 110, and the second data line DL2 electrically connected to the second sub-bias voltage line DVH2 and the second pixel circuit column 12B in a column of pixel circuit groups 110 at least partially overlaps. That is to say, the second sub-bias voltage line DVH2 is correspondingly arranged with one of the two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y in a column of pixel circuit groups 110, and the data line DL electrically connected to the second sub-bias voltage line DVH2 and this column of pixel circuits 10 at least partially overlaps in the direction perpendicular to the plane of the substrate. In this way, the layout density of the signal lines extending along the second direction Y can be reduced, which is beneficial to reducing the layout space of the pixel circuits 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0145] Similarly, when the number N12 of the second sub-bias voltage lines DVH2 is equal to or less than the number N10 of columns of the pixel circuit groups 110, optionally, as Figure 23 and Figure 27 shown, one first sub-bias voltage line DVH1 is correspondingly arranged for one row of pixel circuit groups 110. For example, in terms of quantity, one first sub-bias voltage line DVH1 is correspondingly arranged for one row of pixel circuit groups 110, and in terms of position, one row of pixel circuit groups 110 and one first sub-bias voltage line DVH1 overlap in the direction perpendicular to the plane of the substrate, so that each pixel circuit 10 can be electrically connected to the bias voltage line DVH.

[0146] The cases where the first reference voltage line Ref1 and the bias voltage line DVH in the display panel are separately arranged are introduced above to reduce the layout space of the pixel circuits, increase the pixel density of the display panel, and improve the resolution of the display panel. Of course, the display panel can also include the first reference voltage line Ref1 and the bias voltage line DVH at the same time. Referring to Figure 2 and Figure 3 shown, the pixel circuit 10 includes an anode reset transistor T7, a driving transistor T3, and a bias transistor T8. The anode reset transistor T7 is electrically connected between the first reference voltage line Ref1 and the anode of the light-emitting element 30, and the bias transistor T8 is electrically connected between at least one of the first pole and the second pole of the driving transistor T3 and the bias voltage line DVH.

[0147] Corresponding to the layout structure of the display panel, in combination with Figure 21 、Figure 25 and Figure 27 As shown in Figure 27 , the first reference voltage line Ref1 may include first sub-reference voltage lines Ref11 extending along the first direction X and arranged along the second direction Y, and second sub-reference voltage lines Ref12 extending along the second direction Y and arranged along the first direction X. The first sub-reference voltage lines Ref11 and the second sub-reference voltage lines Ref12 are arranged in different layers and are electrically connected to each other.

[0148] Combined with Figure 23 、 Figure 25 and Figure 27 As shown in Figure 27 , the bias voltage line DVH includes first sub-bias voltage lines DVH1 extending along the first direction X and arranged along the second direction Y, and second sub-bias voltage lines DVH2 extending along the second direction Y and arranged along the first direction X. The first sub-bias voltage lines DVH1 and the second sub-bias voltage lines DVH2 are arranged in different layers and are electrically connected to each other.

[0149] For example, by setting the first reference voltage line Ref1 to include the first sub-reference signal lines Ref11 and the second sub-reference signal lines Ref12 that extend in different directions and are cross-connected electrically, a first reference voltage line Ref1 with a grid structure is formed, so as to reduce the overall resistance of the first reference voltage line Ref1, thereby reducing the power consumption of the first reference voltage line Ref1, and improving the signal transmission stability of the first reference voltage line Ref1, which is beneficial to improving display effects such as the display uniformity of the display panel; and, by setting the bias voltage line DVH to include the first sub-bias voltage lines DVH1 and the second sub-bias voltage lines DVH2 that extend in different directions and are cross-connected electrically, a bias voltage line DVH with a grid structure is formed, so as to reduce the overall resistance of the bias voltage line DVH, thereby reducing the power consumption of the bias voltage line DVH, and improving the signal transmission stability of the bias voltage line DVH, which is beneficial to improving display effects such as the display uniformity of the display panel.

[0150] Optionally, as Figure 25 and Figure 27 shown, the second sub-reference voltage lines Ref12 and the second sub-bias voltage lines DVH2 are arranged in the same layer. For example, both the second sub-reference voltage lines Ref12 and the second sub-bias voltage lines DVH2 are located in the metal layer M2.

[0151] Combined with Figure 25 and Figure 27As shown, multiple pixel circuit groups 110 in the display panel are arranged in an array along the first direction X and the second direction Y. Taking the second direction Y as the column direction, the number of columns of the array formed by the multiple pixel circuit groups 110 is N10, the number of the second sub-reference voltage lines Ref12 is N11, and the number of the second sub-bias voltage lines DVH2 is N12. Optionally, N11 ≤ N10, N12 ≤ N10, and N10, N11, and N12 are all positive integers. That is, taking the number of columns N10 of the pixel circuit group 110 as a reference, the number of the second sub-reference voltage lines Ref12, N11, can be equal to or less than the number of columns N10 of the pixel circuit group 110, and the number of the second sub-bias voltage lines DVH2, N12, can be equal to or less than the number of columns N10 of the pixel circuit group 110. In other words, at least one column of pixel circuit groups 110 (one column of pixel circuit groups 110 includes at least three columns of pixel circuits 10) is correspondingly provided with one second sub-reference voltage line Ref12 in terms of quantity, and at least one column of pixel circuit groups 110 (one column of pixel circuit groups 110 includes at least three columns of pixel circuits 10) is correspondingly provided with one second sub-bias voltage line DVH2 in terms of quantity. Thus, the layout density of the signal lines extending along the second direction Y (such as the second sub-reference voltage line Ref12 and the second sub-bias voltage line DVH2) is greatly reduced, which is beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0152] Optionally, as Figure 25 and Figure 27 shown, one column of pixel circuit groups 110 is correspondingly provided with one second sub-reference voltage line Ref12 and one second sub-bias voltage line DVH2, that is, N11 = N12 = N10. And along the first direction X, the second sub-reference voltage line Ref12 and the second sub-bias voltage line DVH2 are arranged alternately, so as to improve the distribution uniformity of the second sub-reference signal line Vref12 and the distribution uniformity of the second sub-bias voltage line DVH2, and further improve the wiring uniformity in the film layer, which is beneficial to improving the overall signal consistency of the display panel.

[0153] Combined with Figures 18 - 27As shown, in the pixel circuit group 110, the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 are arranged along the first direction X; the first pixel circuit 11 is arranged along the second direction Y to form the first pixel circuit column 11B, the second pixel circuit 12 is arranged along the second direction Y to form the second pixel circuit column 12B, and the third pixel circuit 13 is arranged along the second direction Y to form the third pixel circuit column 13B. It can be understood that since the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, and the first pixel circuit 11 is arranged along the second direction Y to form the first pixel circuit column 11B, and the second pixel circuit 12 is arranged along the second direction Y to form the second pixel circuit column 12B, therefore, the first pixel circuit column 11B and the second pixel circuit column 12B are mirror-symmetrical along the second direction Y. Similarly, the third pixel circuit column 13B is not mirror-symmetrical with the pixel circuit columns adjacent along the first direction X (such as the first pixel circuit column 11B and / or the second pixel circuit column 12B).

[0154] Optionally, as Figure 25 and Figure 27 shown, in the direction perpendicular to the plane of the substrate, the second sub-reference voltage line Ref12 is correspondingly arranged with one of the first pixel circuit column 11B and the second pixel circuit column 12B in a column of pixel circuit groups 110, that is, the second sub-reference voltage line Ref12 overlaps with one of the first pixel circuit column 11B and the second pixel circuit column 12B in a column of pixel circuit groups 110, and the second sub-bias voltage line DVH2 is correspondingly arranged with the other of the first pixel circuit column 11B and the second pixel circuit column 12B in a column of pixel circuit groups 110, that is, the second sub-bias voltage line DVH2 overlaps with the other of the first pixel circuit column 11B and the second pixel circuit column 12B in a column of pixel circuit groups 110. That is to say, the second sub-reference voltage line Ref12 and the second sub-bias voltage line DVH2 are respectively arranged corresponding to the two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y in a column of pixel circuit groups 110, so as to facilitate the periodic layout design of the second sub-reference voltage line Ref12 and the second sub-bias voltage line DVH2 along the first direction X, and is also beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0155] As Figure 26 shown, the display panel includes data lines DL, and the data lines DL include first data lines DL1, second data lines DL2, and third data lines DL3 that extend along the second direction Y and are arranged along the first direction X. The first pixel circuit column 11B is electrically connected to the first data line DL1, the second pixel circuit column 12B is electrically connected to the second data line DL2, and the third pixel circuit column 13B is electrically connected to the third data line DL3.

[0156] CombinedFigure 25 and Figure 26 As shown in Figure 26 , in a direction perpendicular to the plane of the substrate, the second sub-reference voltage line Ref12 is correspondingly arranged with the first pixel circuit column 11B in a column of pixel circuit groups 110, and the first data line DL1 through which the second sub-reference voltage line Ref12 is electrically connected to the first pixel circuit column 11B in a column of pixel circuit groups 110 overlaps at least partially. Moreover, the second sub-bias voltage line DVH2 is correspondingly arranged with the second pixel circuit column 12B in a column of pixel circuit groups 110, and the second data line DL2 through which the second sub-bias voltage line DVH2 is electrically connected to the second pixel circuit column 12B in a column of pixel circuit groups 110 overlaps at least partially; or, in a direction perpendicular to the plane of the substrate, the second sub-reference voltage line Ref12 is correspondingly arranged with the second pixel circuit column 12B in a column of pixel circuit groups 110, and the second data line DL2 through which the second sub-reference voltage line Ref12 is electrically connected to the second pixel circuit column 12B in a column of pixel circuit groups 110 overlaps at least partially. Moreover, the second sub-bias voltage line DVH2 is correspondingly arranged with the first pixel circuit column 11B in a column of pixel circuit groups 110, and the first data line DL1 through which the second sub-bias voltage line DVH2 is electrically connected to the first pixel circuit column 11B in a column of pixel circuit groups 110 overlaps at least partially.

[0157] That is to say, the second sub-reference voltage line Ref12 and the second sub-bias voltage line DVH2 are respectively correspondingly arranged with two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y in a column of pixel circuit groups 110, and the data line DL through which the second sub-reference voltage line Ref12 is electrically connected to the correspondingly arranged pixel circuits 10 overlaps at least partially in a direction perpendicular to the plane of the substrate, and the data line DL through which the second sub-bias voltage line DVH2 is electrically connected to the correspondingly arranged pixel circuits 10 overlaps at least partially in a direction perpendicular to the plane of the substrate. Thus, the layout density of the signal lines extending along the second direction Y can be reduced, which is beneficial to reducing the layout space of the pixel circuits 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0158] Optionally, as Figure 21 、 Figure 23 and Figure 27 shown, the first sub-reference signal line Ref11 and the first sub-bias voltage line DVH1 are arranged in different layers. For example, the first sub-reference signal line Ref11 is located in the metal layer MC, and the first sub-bias voltage line DVH1 is located in the metal layer MG.

[0159] Optionally, as Figure 21 、 Figure 23 and Figure 27 shown, along the second direction Y, the first sub-reference signal line Ref11 and the first sub-bias voltage line DVH1 are arranged alternately.

[0160] It should be noted that when the number N11 of the second sub-reference voltage lines Ref12 is equal to or less than the number N10 of columns of the pixel circuit group 110, optionally, as Figure 21 and Figure 27 shown, one first sub-reference voltage line Ref11 is correspondingly arranged for one row of pixel circuit groups 110. For example, in terms of quantity, one first sub-reference voltage line Ref11 is correspondingly arranged for one row of pixel circuits 110, and in terms of position, one row of pixel circuit groups 110 overlaps with one first sub-reference voltage line Ref11 in a direction perpendicular to the plane of the substrate, so that each pixel circuit 10 can be electrically connected to the first reference voltage line Ref1.

[0161] Similarly, when the number N12 of the second sub-bias voltage lines DVH2 is equal to or less than the number N10 of columns of the pixel circuit group 110, optionally, as Figure 23 and Figure 27 shown, one first sub-bias voltage line DVH1 is correspondingly arranged for one row of pixel circuit groups 110. For example, in terms of quantity, one first sub-bias voltage line DVH1 is correspondingly arranged for one row of pixel circuit groups 110, and in terms of position, one row of pixel circuit groups 110 overlaps with one first sub-bias voltage line DVH1 in a direction perpendicular to the plane of the substrate, so that each pixel circuit 10 can be electrically connected to the bias voltage line DVH.

[0162] Referring to Figure 2 and Figure 3 shown, the display panel further includes a second reference voltage line Ref2, and the pixel circuit 10 further includes a gate reset transistor T5. The gate reset transistor T5 is electrically connected between the second reference voltage line Ref2 and the gate of the driving transistor T3. When the gate reset transistor T5 is turned on, the gate reset transistor T5 transmits the reference voltage signal transmitted on the second reference voltage line Ref2 to the gate of the driving transistor T3 to reset the gate of the light-emitting element 30.

[0163] In some optional embodiments, referring to Figure 19 and Figure 22 shown, the second reference voltage line Ref2 includes third sub-reference voltage lines Ref21 extending along the first direction X and arranged along the second direction Y. Optionally, the third sub-reference voltage lines Ref21 include third-first sub-reference voltage lines Ref21-1 and third-second sub-reference voltage lines Ref21-2 extending along the first direction X. The third-first sub-reference voltage lines Ref21-1 and the third-second sub-reference voltage lines Ref21-2 are arranged in different layers. For example, the third-first sub-reference voltage lines Ref21-1 may be located in the metal layer M1, and the third-first sub-reference voltage lines Ref21-1 may be in the oxide layer IGZO; and, referring to Figure 19 、Figure 22 and Figure 25 As shown in Figure 25 , the third-first reference voltage line Ref21-1 and the third-second reference voltage line Ref21-2 are electrically connected. Specifically, the third-second reference voltage line Ref21-2 can be electrically connected to the third-first reference voltage line Ref21-1 through the connection portion L7 located in the metal layer M2. In this way, the overall resistance of the second reference voltage line Ref2 can be reduced, thereby reducing the power consumption of the second reference voltage line Ref2 and improving the signal transmission stability of the second reference voltage line Ref2, which is beneficial to improving display effects such as the display uniformity of the display panel.

[0164] Optionally, in combination with Figure 19 and Figure 22 As shown in Figure 22 , in the direction perpendicular to the plane of the substrate, the third-first reference voltage line Ref21-1 and the third-second reference voltage line Ref21-2 at least partially overlap. In this way, the layout density of the signal lines extending along the first direction X can be reduced, which is beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0165] In other optional embodiments, the third reference voltage line Ref21 may also only include the third-first reference voltage line Ref21-1 extending along the first direction X (for example, located in the metal layer M1), or only include the third-second reference voltage line Ref21-2 extending along the first direction X (for example, located in the oxide layer IGZO).

[0166] In some other optional embodiments, as Figure 28 shown Figure 28 Figure 28 shows a partial layout structure schematic diagram of the first reference voltage line Ref1, the bias voltage line DVH, and the second reference voltage line Ref2 in a display panel provided by an embodiment of the present application. It can be seen that in addition to the first reference voltage line Ref1 and the bias voltage line DVH being in a grid structure, the second reference voltage line Ref2 is also in a grid structure. Specifically, as Figure 28 shown

[0167] Optionally, both the third sub-reference voltage line Ref21 and the fourth sub-reference voltage line Ref22 can be multiple. There can be multiple crossing positions of the multiple third sub-reference voltage lines Ref21 and the multiple fourth sub-reference voltage lines Ref22. The electrical connection between the third sub-reference voltage line Ref21 and the fourth sub-reference voltage line Ref22 includes: the third sub-reference voltage line Ref21 and the fourth sub-reference voltage line Ref22 are electrically connected at all their crossing positions, as Figure 28 shown, or the third sub-reference voltage line Ref21 and the fourth sub-reference voltage line Ref22 are electrically connected at some of their crossing positions. Specifically, each third sub-reference voltage line Ref21 can be electrically connected to at least one fourth sub-reference voltage line Ref22, and each fourth sub-reference voltage line Ref22 can be electrically connected to at least one third sub-reference voltage line Ref21. Combining Figure 19 , Figure 23 and Figure 28 shown, the third sub-reference voltage line Ref21 and the fourth sub-reference voltage line Ref22 can be electrically connected through the connection part L7 located at their crossing position and in the metal layer M2.

[0168] Optionally, combining Figure 19 , Figure 23 and Figure 28 shown, the third sub-reference voltage line Ref21 and the fourth sub-reference voltage line Ref22 are arranged in different layers. In this way, the signal lines extending in different directions are located in different metal layers, so as to reduce the difficulty of arranging signal lines in the same metal layer. For example, the third sub-reference voltage line Ref21 is located in the metal layer M1 and / or the oxide layer IGZO, and the fourth sub-reference voltage line Ref22 is located in the metal layer M2. The third sub-reference voltage line Ref21 and the fourth sub-reference voltage line Ref22 are electrically connected through a via between the metal layer where the third sub-reference voltage line Ref21 is located and the metal layer M2.

[0169] It can be understood that by setting the second reference voltage line Ref2 to include the third sub-reference voltage line Ref21 and the fourth sub-reference voltage line Ref22 that extend in different directions and are cross-connected electrically, a second reference voltage line Ref2 in a grid structure is formed, so as to reduce the overall resistance of the second reference voltage line Ref2, thereby reducing the power consumption of the second reference voltage line Ref2, and improving the signal transmission stability of the second reference voltage line Ref2, which is beneficial to improving display effects such as display uniformity of the display panel.

[0170] Optionally, the second sub-reference voltage line Ref12, the second sub-bias voltage line DVH2, and the fourth sub-reference voltage line Ref22 are arranged in the same layer. For example, the second sub-reference voltage line Ref12, the second sub-bias voltage line DVH2, and the fourth sub-reference voltage line Ref22 are all located in the metal layer M2.

[0171] As Figure 28 shown, multiple pixel circuit groups 110 in the display panel are arranged in an array along a first direction X and a second direction Y. Taking the second direction Y as the column direction, the number of columns of the array formed by the multiple pixel circuit groups 110 is N10, and the number of the fourth sub-reference voltage lines Ref22 is N13. Optionally, N12 + N13 ≤ N10, and N13 is a positive integer. That is, taking the number of columns N10 of the pixel circuit groups 110 as a reference, the total number N12 + N13 of the second sub-bias voltage lines DVH2 and the fourth sub-reference voltage lines Ref22 can be equal to or less than the number of columns N10 of the pixel circuit groups 110. Or rather, for at least two columns of pixel circuit groups 110 (one column of pixel circuit groups 110 includes at least three columns of pixels 10), one second sub-bias voltage line DVH2 and one fourth sub-reference voltage line Ref22 are correspondingly arranged in terms of quantity. Thus, to a great extent, the arrangement density of the second sub-bias voltage lines DVH2 and the fourth sub-reference voltage lines Ref22 extending along the second direction Y is reduced, which is beneficial to reducing the layout space of the pixel circuits 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0172] As Figure 28 shown, one second sub-reference voltage line Ref12 is correspondingly arranged for one column of pixel circuit groups 110; among two adjacent columns of pixel circuit groups 110, one second sub-bias voltage line DVH2 is correspondingly arranged for one column of pixel circuit groups 110, and one fourth sub-reference voltage line Ref22 is correspondingly arranged for the other column of pixel circuit groups 110; that is, N11 = N10, N12 + N13 = N10; and along the first direction X, the second sub-bias voltage lines DVH2 and the fourth sub-reference voltage lines Ref22 are arranged alternately, and the second sub-reference voltage line Ref12 is located between the second sub-bias voltage lines DVH2 and the fourth sub-reference voltage lines Ref22; thereby, the distribution uniformity of the second sub-reference voltage line Ref12, the second sub-bias voltage line DVH2, and the fourth sub-reference voltage line Ref22 can be improved, and further, the wiring uniformity in the film layer can be improved, which is beneficial to improving the overall signal consistency of the display panel.

[0173] Combined with Figures 18 - 26 and Figure 28As shown, in the pixel circuit group 110, the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 are arranged along the first direction X; the first pixel circuit 11 is arranged along the second direction Y to form the first pixel circuit column 11B, the second pixel circuit 12 is arranged along the second direction Y to form the second pixel circuit column 12B, and the third pixel circuit 13 is arranged along the second direction Y to form the third pixel circuit column 13B. It can be understood that since the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, and the first pixel circuit 11 is arranged along the second direction Y to form the first pixel circuit column 11B, and the second pixel circuit 12 is arranged along the second direction Y to form the second pixel circuit column 12B, therefore, the first pixel circuit column 11B and the second pixel circuit column 12B are mirror-symmetrical along the second direction Y. Similarly, the third pixel circuit column 13B is not mirror-symmetrical with the adjacent pixel circuit column (such as the first pixel circuit column 11B and / or the second pixel circuit column 12B) along the first direction X.

[0174] Optionally, as Figure 28 shown, in two adjacent columns of pixel circuit groups 110, for one column of pixel circuit groups 110, the first pixel circuit column 11B is correspondingly provided with the second sub-reference voltage line Ref12, and the second pixel circuit column 12B is correspondingly provided with the second sub-bias voltage line DVH2; for the other column of pixel circuit groups 110, the first pixel circuit column 11B is correspondingly provided with the second sub-reference voltage line Ref12, and the second pixel circuit column 12B is correspondingly provided with the fourth sub-reference voltage line Ref22; or, in two adjacent columns of pixel circuit groups 110, for one column of pixel circuit groups 110, the first pixel circuit column 11B is correspondingly provided with the second sub-bias voltage line DVH2, and the second pixel circuit column 12B is correspondingly provided with the second sub-reference voltage line Ref12; for the other column of pixel circuit groups 110, the first pixel circuit column 11B is correspondingly provided with the fourth sub-reference voltage line Ref22, and the second pixel circuit column 12B is correspondingly provided with the second sub-reference voltage line Ref12. Here, the corresponding setting of the pixel circuit column and the signal line means that they are correspondingly set in position, that is, they overlap in the direction perpendicular to the plane of the substrate.

[0175] That is to say, in two adjacent columns of pixel circuit groups 110, for a column of pixel circuit groups 110, a second sub-reference voltage line Ref12 and a second sub-bias voltage line DVH2 are respectively provided for two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y. For the other column of pixel circuit groups 110, a second sub-reference voltage line Ref12 and a second sub-reference voltage line Ref12 are respectively provided for two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y. This facilitates the periodic layout design of the second sub-reference voltage line Ref12, the second sub-bias voltage line DVH2, and the second sub-reference voltage line Ref12 along the first direction X, is also conducive to reducing the layout space of the pixel circuits 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0176] As Figure 26 shown, the display panel includes data lines DL. The data lines DL include first data lines DL1, second data lines DL2, and third data lines DL3 that extend along the second direction Y and are arranged along the first direction X. The first pixel circuit column 11B is electrically connected to the first data line DL1, the second pixel circuit column 12B is electrically connected to the second data line DL2, and the third pixel circuit column 13B is electrically connected to the third data line DL3.

[0177] Combined with Figure 26 and Figure 28 shown, in the direction perpendicular to the plane of the substrate, the second sub-reference voltage line Ref12 and the data line DL to which the corresponding pixel circuit column is electrically connected overlap at least partially, the second sub-bias voltage line DVH2 and the data line DL to which the corresponding pixel circuit column is electrically connected overlap at least partially, and the fourth sub-reference voltage line Ref22 and the data line DL to which the corresponding pixel circuit column is electrically connected overlap at least partially. In this way, the layout density of the signal lines extending along the second direction Y can be reduced, which is conducive to reducing the layout space of the pixel circuits 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0178] Optionally, combined with Figure 19 and Figures 22 - 23 shown, the first sub-reference voltage line Ref1, the first sub-bias voltage line DVH2, and the third sub-reference voltage line Ref2 are arranged in different layers. For example, the first sub-reference voltage line Ref1 is located in the metal layer MC, the first sub-bias voltage line DVH2 is located in the metal layer MG, and the third sub-reference voltage line Ref2 is located in the metal layer M1 and / or the oxide layer IGZO.

[0179] Optionally, combined with Figure 19 and Figures 22 - 23 shown, along the second direction Y, the third sub-reference voltage line Ref21, the first sub-reference voltage line Ref11, and the first sub-bias voltage line DVH1 are arranged in sequence.

[0180] It is understandable that the third sub-reference voltage line Ref21 may be located in a metal layer (such as metal layer M1); alternatively, the third sub-reference voltage line Ref21 may be located in an oxide layer (such as oxide layer IGZO); or, the first sub-reference voltage line Ref21 may include sub-reference voltage lines located in different conductive layers, extending along the first direction X and arranged along the second direction Y.

[0181] Optionally, in combination with Figure 19 , Figure 22 and Figure 28 shown, the third sub-reference voltage line Ref21 includes a third-first sub-reference voltage line Ref21-1 and a third-second sub-reference voltage line Ref21-2 extending along the first direction X. For example, the third-first sub-reference voltage line Ref21-1 is located in metal layer M1, and the third-second sub-reference voltage line Ref21-2 is located in oxide layer IGZO. The fourth sub-reference voltage line Ref22 is located in metal layer M2. At this time, the third-first sub-reference voltage line Ref21-1, the third-second sub-reference voltage line Ref21-2, and the fourth sub-reference voltage line Ref22 are arranged in different layers from each other, and the third-first sub-reference voltage line Ref21-1, the third-second sub-reference voltage line Ref21-2, and the fourth sub-reference voltage line Ref22 are electrically connected to each other. In this way, the overall resistance of the second reference voltage line Ref2 can be further reduced, thereby reducing the power consumption of the second reference voltage line Ref2, and improving the signal transmission stability of the second reference voltage line Ref2, which is beneficial to improving display effects such as display uniformity of the display panel.

[0182] Further optionally, in combination with Figure 19 and Figure 23 shown, in the direction perpendicular to the plane of the substrate, the third-first sub-reference voltage line Ref21-1 and the third-second sub-reference voltage line Ref22-2 at least partially overlap. In this way, the arrangement density of the signal lines extending along the first direction X can be reduced, which is beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0183] Similarly, the second sub-reference voltage line Ref2 may be located in a metal layer (such as metal layer M2); or, the second sub-reference voltage line Ref2 may include sub-reference voltage lines located in different conductive layers, extending along the first direction X and arranged along the second direction Y.

[0184] It should be noted that when the number N13 of the fourth sub-reference voltage lines Ref22 is equal to or less than the number N10 of columns of the pixel circuit group 110, optionally, as Figure 19 and Figure 22As shown, a third sub-reference voltage line Ref21 is correspondingly provided for each row of pixel circuit groups 110. For example, in terms of quantity, a third sub-reference voltage line Ref21 is correspondingly provided for each row of pixel circuit groups 110, and in terms of position, each row of pixel circuit groups 110 overlaps with a third sub-reference voltage line Ref21 in a direction perpendicular to the plane of the substrate, so that each pixel circuit 10 can be electrically connected to the second reference voltage line Ref2. Wherein, when the third sub-reference voltage line Ref21 includes sub-reference voltage lines of different conductive layers, for example, the third sub-reference voltage line Ref21 includes a third-first sub-reference voltage line Ref21-1 and a third-second sub-reference voltage line Ref21-2, then correspondingly providing a third sub-reference voltage line Ref21 for each row of pixel circuit groups 110 may mean correspondingly providing a set of a third-first sub-reference voltage line Ref21-1 and a third-second sub-reference voltage line Ref21-2 for each row of pixel circuit groups 110. In the present application, when signal lines of the same type of transmission signal and the same extension direction include signal lines located in different conductive layers, a set of signal lines located in different conductive layers can be regarded as a whole, and other similar situations will not be elaborated.

[0185] Combined with Figures 21 - 24 As shown, the gate reset transistor T5 can be an IGZO thin film transistor. The gate reset transistor T5 includes a first oxide region p5 located in the oxide layer IGZO, and a first pole p51 and a second pole p52 connected to the first oxide region p5; and, the display panel includes a first scan line SN1 extending along the first direction X. The first scan line SN1 includes a first sub-scan line SN11 and a second sub-scan line SN12 that transmit the same scan signal. The metal layer where the first sub-scan line SN11 is located (such as the metal layer MC) is on the side of the oxide layer IGZO close to the substrate, and the metal layer where the second sub-scan line SN12 is located (such as the metal layer MG) is on the side of the oxide layer IGZO away from the substrate; in a direction perpendicular to the plane of the substrate, both the first sub-scan line SN11 and the second sub-scan line SN12 at least partially overlap with the first oxide region p5. Optionally, in a direction perpendicular to the plane of the substrate, the overlapping part of the first sub-scan line SN11 and the first oxide region p5 of the gate reset transistor T5 is the first bottom gate bg5 of the gate reset transistor T5, so that the first bottom gate bg5 of the gate reset transistor T5 is electrically connected to the first sub-scan line SN11; in a direction perpendicular to the plane of the substrate, the overlapping part of the second sub-scan line SN12 and the first oxide region p5 of the gate reset transistor T5 is the first top gate tg5 of the gate reset transistor T5, so that the first top gate tg5 of the gate reset transistor T5 is electrically connected to the second sub-scan line SN12; thus, both the first top gate tg5 and the first bottom gate bg5 of the reset transistor T5 are electrically connected to the first scan line SN1 to receive the same scan signal.

[0186] Combined Figure 19 、 Figures 21 - 25 As shown, the second reference voltage line Ref2 includes third sub-reference voltage lines Ref21 extending along the first direction X and arranged along the second direction Y. The third sub-reference voltage lines Ref21 include third-one sub-reference voltage lines Ref21-1 and third-two sub-reference voltage lines Ref21-2 extending along the first direction X. The third-one sub-reference voltage lines Ref21-1 can be located in the metal layer M1, and the third-one sub-reference voltage lines Ref21-1 can be located in the oxide layer IGZO. The first pole p51 of the gate reset transistor T5 can be electrically connected to the third-two sub-reference voltage lines Ref21-2 in the third sub-reference voltage lines Ref21 on the same layer. Moreover, the third-two sub-reference voltage lines Ref21-2 can be electrically connected to the third-one sub-reference voltage lines Ref21-1 and the first pole p51 of the gate reset transistor T5 through a connection portion L7 located in the metal layer M2.

[0187] Combined Figures 18 - 20 、 Figures 21 - 24 And Figure 25 As shown, the second pole p52 of the gate reset transistor T5 can be electrically connected to the gate g3 of the driving transistor T3 through a connection portion L8 located in the metal layer M2. Refer to Figure 2 And Figure 3 As shown, the connection portion L8 is the first node N1.

[0188] Figure 29 The figure shows a top view schematic diagram of a display panel provided by an embodiment of the present application. As Figure 29 shown, the display panel includes a display area AA and at least a non-display area NA surrounding the display area AA. The display area AA includes a first display area AA1 and a second display area AA2 located on at least one side of the first display area AA1 along the first direction X. Combined Figures 18 - 28 As shown, the pixel circuit 10 is located in the display area AA, and the pixel circuits 10 are arranged in an array along the first direction X and the second direction Y. One column of pixel circuits 10 is correspondingly electrically connected to one data line DL.

[0189] As Figure 29 shown, the non-display area NA includes a fan-out area FA located on one side of the display area AA along the second direction Y and a pin area PA located on the side of the fan-out area FA away from the display area AA. The fan-out area FA includes multiple fan-out wires S1. The pin area PA is provided with multiple pins (pads), including data pins, power pins, etc. After the display panel is manufactured, the driver integrated circuit (Integrated Circuit, abbreviated as IC) is bonded to the data pins, power pins, and other pins in the pin area PA. In practical applications, the pin area PA will be bent to the back of the display panel.

[0190] It can be understood that the data line DL in the display area AA is electrically connected to the fan-out trace S1 in the fan-out area FA, so that the data signal output by the driver integrated circuit IC is transmitted to the data line DL in the display area AA after passing through the data pin in the pin area PA and the fan-out trace S1 in the fan-out area FA, so as to drive the pixel circuit 10 in the display area AA to work, and further drive the light-emitting element 30 in the display area AA for display.

[0191] As Figure 29 shown, the first display area AA1 is located in the central area of the display area AA along the first direction X, and the data line DL in the first display area AA1 can directly extend to the position of the fan-out area FA and be electrically connected to the fan-out trace S1 in the fan-out area FA.

[0192] The second display area AA2 is located in the left area or the right area of the display area AA along the second direction Y. In some existing display panels, the fan-out trace S1 in the fan-out area FA needs to be routed in the non-display area of the lower border of the display panel, so as to be electrically connected to the data line DL in the second display area AA2. However, in this way, the fan-out trace S1 electrically connected to the data line DL in the second display area AA2 will be arranged at the position of the lower left border or the lower right border of the display panel, making the fan-out trace S1 occupy a large space along the first direction X, which is not conducive to narrowing the lower border of the display panel.

[0193] For this reason, optionally, in some embodiments of the present application, as Figure 29 shown, a first connection line segment DH1 and a second connection line segment DV1 are provided in the display area AA. The first connection line segment DH1 extends along the first direction X, and the second connection line segment DV1 extends along the second direction Y. Thus, the data signal line ND in the second display area AA2 is electrically connected to the fan-out trace S1 through the first connection line segment DH1 and the second connection line segment DV1. For example, the data line DL in the second display area AA2 can first pass through the first connection line segment DH1 extending along the first direction X, and then pass through the second connection line segment DV1 extending along the second direction Y, and be electrically connected to the fan-out trace S1 in the fan-out area FA. In this way, there is no need to arrange the fan-out trace S1 at the position close to the lower left border and / or the lower right border of the display panel, but to route the data signal to the data line DL in the second display area AA2 in the display area AA, and arrange part of the fan-out trace in the display area (Fanout in AA, FIAA), so as to provide a compression space for the lower border of the display panel, which is conducive to realizing the narrow border of the display panel.

[0194] Figure 30 shows a partially enlarged top view schematic diagram of a display panel provided by an embodiment of the present application, as Figure 30As shown, considering the etching uniformity of the display panel and the uniformity of the reflection effect, the display area AA further includes a first non-connection line segment DH2. The first non-connection line segment DH2 is insulated from the first connection line segment DH1 on the same layer. The first non-connection line segment DH2 extends along the first direction X. Thus, the first connection line segment DV1 and the first non-connection line segment DV2 form a first auxiliary trace D1. That is to say, the display area AA includes multiple first auxiliary traces D1 extending along the first direction X. At least part of the first auxiliary traces D1 includes the first connection line segment DH1. The multiple first auxiliary traces D1 further include a first non-connection line segment DV2 that is insulated from the first connection line segment DV1 on the same layer.

[0195] Similarly, the display area AA further includes a second non-connection line segment DV2. The second non-connection line segment DV2 is insulated from the second connection line segment DV1 on the same layer. The second non-connection line segment DV2 extends along the second direction Y. Thus, the second connection line segment DV1 and the second non-connection line segment DV2 form a second auxiliary trace D2. That is to say, the display area AA includes multiple second auxiliary traces D2 extending along the second direction Y. At least part of the second auxiliary traces D2 includes the second connection line segment DV1. The multiple second auxiliary traces D2 further include a second non-connection line segment DV2 that is insulated from the second connection line segment DV1 on the same layer.

[0196] It should be noted that, as Figure 30 shown, in the first auxiliary trace D1, the first non-connection line segment DH2 can include the entire segment that does not transmit data signals to the data line DL along the first direction X, or can include a partial segment in the entire segment that does not transmit data signals to the data line DL along the first direction X.

[0197] Similarly, as Figure 30 shown, in the second auxiliary trace D2, the second non-connection line segment DV2 can include the entire segment that does not transmit data signals to the data line DL along the second direction Y, or can include a partial segment in the entire segment that does not transmit data signals to the data line DL along the second direction Y.

[0198] It should also be noted that part or all of the first non-connection line segments DH2 can be connected to a fixed potential to reduce the resistance of the fixed-potential trace and reduce the voltage drop on the fixed-potential trace. For example, as Figure 30 shown, at least part of the first non-connection line segment DH1 is electrically connected to the power supply voltage line PVEE to be in parallel with the power supply voltage line PVEE, thereby reducing the resistance of the power supply voltage line PVEE and reducing the voltage drop on the power supply voltage line PVEE.

[0199] Similarly, part or all of the second non-connection line segments DV2 can be connected to a fixed potential to reduce the resistance of the fixed-potential trace and reduce the voltage drop on the fixed-potential trace. For example, asFigure 30 As shown, at least a part of the second non-connected line segment DV2 is electrically connected to the power supply voltage line PVEE in parallel with the power supply voltage line PVEE, thereby reducing the resistance of the power supply voltage line PVEE and decreasing the voltage drop across the power supply voltage line PVEE.

[0200] Moreover, the first non-connected line segment DH2 and the second non-connected line segment DV2 can be electrically connected to form a grid structure to further reduce the resistance of the fixed potential trace and decrease the voltage drop across the fixed potential trace.

[0201] Optionally, as Figure 26 shown, the second auxiliary trace D2 is disposed on the same layer as the data line DL, and the first auxiliary trace D1 is disposed on a different layer from the second auxiliary trace D2; for example, the second auxiliary trace D2 and the data line DL are located in the metal layer M4, and the first auxiliary trace D1 is located in the metal layer M3.

[0202] As known from the foregoing, in combination with Figures 1 - 3 shown, the display panel includes a light-emitting element 30 on the side of the pixel circuit 10 away from the substrate. The light-emitting element 30 includes an anode E1, a light-emitting layer E2, and a cathode E3 arranged in the direction away from the substrate; moreover, the display panel includes a first reference voltage line Ref1, and the pixel circuit 10 includes an anode reset transistor T7. The anode reset transistor T7 is electrically connected between the first reference voltage line Ref1 and the anode of the light-emitting element 30.

[0203] Optionally, in combination with Figure 21 and Figure 26 shown, the first reference voltage line Ref1 includes first sub-reference voltage lines Ref11 extending along the first direction X and arranged along the second direction Y. The first sub-reference voltage lines Ref11 are disposed on a different layer from the first auxiliary trace D1; for example, the first sub-reference voltage lines Ref11 are located in the metal layer MC, and the first auxiliary trace D1 is located in the metal layer M3; moreover, in the direction perpendicular to the plane of the substrate, the first auxiliary trace D1 and the first sub-reference voltage lines Ref11 overlap at least partially; arranged in this way, the layout density of the signal lines extending along the first direction X can be reduced, which is beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0204] As known from the foregoing, referring to Figure 2 and Figure 3 shown, the display panel includes a second reference voltage line Ref2, and the pixel circuit 10 includes a driving transistor T3 and a gate reset transistor T5. The gate reset transistor T5 is electrically connected between the second reference voltage line Ref2 and the gate of the driving transistor T3.

[0205] Optionally, in combination with Figure 19 and Figure 22As shown, the second reference voltage line Ref2 includes third sub-reference voltage lines Ref21 that extend along the first direction X and are arranged along the second direction Y; combined with Figures 21 - 24 As shown, the display panel includes first scan lines SN1 that extend along the first direction X and are arranged along the second direction Y. The first scan lines SN1 are electrically connected to the gates of the gate reset transistors T5 (including the first bottom gate bg5 and the second top gate tg5); combined with Figure 19 , Figures 21 - 24 and ​ As shown, along the second direction Y, the first scan lines SN1, the third sub-reference voltage lines Ref21, and the first sub-reference voltage lines Ref11 are arranged adjacent to each other in sequence.

[0206] Optionally, combined with ​ As shown, the gate reset transistor T5 is an IGZO thin film transistor. The gate reset transistor T5 includes a first oxide region p5 located in the oxide layer IGZO; the first scan lines SN1 include first sub-scan lines SN11 and second sub-scan lines SN12 that transmit the same scan signal. The metal layer where the first sub-scan lines SN11 are located (such as the metal layer MC) is on the side of the oxide layer IGZO close to the substrate, and the metal layer where the second sub-scan lines SN12 are located (such as the metal layer MG) is on the side of the oxide layer IGZO away from the substrate; in the direction perpendicular to the plane of the substrate, both the first sub-scan lines SN11 and the second sub-scan lines SN12 at least partially overlap with the first oxide region p5.

[0207] It should be noted that, combined with ​ , ​ and ​ As shown, the first scan lines SN1, the third sub-reference voltage lines Ref21, and the first sub-reference voltage lines Ref11 are arranged adjacent to each other in sequence along the second direction Y. And, in the direction perpendicular to the plane of the substrate, the first auxiliary trace D1 at least partially overlaps with the first sub-reference voltage lines Ref11. That is to say, the first scan lines SN1, the third sub-reference voltage lines Ref21, and the first auxiliary trace D1 are also arranged adjacent to each other in sequence along the second direction Y. In this way, there is a lateral capacitance between the first auxiliary trace D1 (located in the metal layer M3) and the first scan lines SN1 (located in the metal layer MC and the metal layer MG), which may affect the data signal transmitted by the first connection segment DH1 in the first auxiliary trace D1, and / or may affect the scan signal transmitted by the first scan lines SN1 to the gates of the gate reset transistors T5.

[0208] Therefore, further optionally, combined with ​ and ​As shown, the third sub-reference voltage line Ref21 includes a third-first sub-reference voltage line Ref21-1 extending along the first direction X and a third-second sub-reference voltage line Ref21-2. The third-first sub-reference voltage line Ref21-1 and the third-second sub-reference voltage line Ref21-2 are arranged on different layers. For example, the third-first sub-reference voltage line Ref21-1 is located in the metal layer M1, and the third-second sub-reference voltage line Ref21-2 is located in the oxide layer IGZO, and the third-first sub-reference voltage line Ref21-1 and the third-second sub-reference voltage line Ref21-2 are electrically connected; combined with ​ , ​ and ​ As shown, in the direction perpendicular to the plane of the substrate, the third-first sub-reference voltage line Ref21-1 and the third-second sub-reference voltage line Ref21-2 at least partially overlap; the third-second sub-reference voltage line Ref21-2 is located on the side of the third-first sub-reference voltage line Ref21-1 away from the substrate, and the third-second sub-reference voltage line Ref21-2 is located on the side of the first auxiliary trace D1 close to the substrate.

[0209] With such an arrangement, along the second direction Y, the third-second sub-reference voltage line Ref21-2 is located between the first auxiliary trace D1 and the first scan line SN1, and the third-second sub-reference voltage line Ref21-2 is located on the side of the first auxiliary trace D1 close to the substrate. Thus, the third-second sub-reference voltage line Ref21-2 can play a shielding role between the first auxiliary trace D1 and the first scan line SN1, avoiding the lateral capacitance between the first auxiliary trace D1 and the first scan line SN1 from affecting the signals transmitted on the first auxiliary trace D1 and / or the first scan line SN1.

[0210] Further optionally, the third-second sub-reference voltage line Ref21-2 is located in the oxide layer IGZO. At this time, in the direction perpendicular to the plane of the substrate, the third-second sub-reference voltage line Ref21-2 is relatively close to the first scan line SN1, and the third-second sub-reference voltage line Ref21-2 is also relatively close to the first auxiliary trace D1. Thus, the third-second sub-reference voltage line Ref21-2 can effectively play a shielding role between the first auxiliary trace D1 and the first scan line SN1.

[0211] Combined with ​As shown, in the pixel circuit group 110, the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 are arranged along the first direction X; the first pixel circuit 11 is arranged along the second direction Y into the first pixel circuit column 11B, the second pixel circuit 12 is arranged along the second direction Y into the second pixel circuit column 12B, and the third pixel circuit 13 is arranged along the second direction Y into the third pixel circuit column 13B. It can be understood that since the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, and the first pixel circuit 11 is arranged along the second direction Y into the first pixel circuit column 11B, and the second pixel circuit 12 is arranged along the second direction Y into the second pixel circuit column 12B, therefore, the first pixel circuit column 11B and the second pixel circuit column 12B are mirror-symmetrical along the second direction Y. Specifically, the first pixel circuit column 11B and the second pixel circuit column 12B are mirror-symmetrical along the first virtual line Q1, and the first virtual line Q1 extends along the second direction Y. The third pixel circuit column 13B is not mirror-symmetrical with the pixel circuit columns adjacent along the first direction X (such as the first pixel circuit column 11B and / or the second pixel circuit column 12B).

[0212] As ​ shown, the data line DL includes a first data line DL1, a second data line DL2, and a third data line DL3 that extend along the second direction Y and are arranged along the first direction X. The first pixel circuit column 11B is electrically connected to the first data line DL1, the second pixel circuit column 12B is electrically connected to the second data line DL2, and the third pixel circuit column 13B is electrically connected to the third data line DL3.

[0213] As ​ shown, since the first pixel circuit column 11B and the second pixel circuit column 12B are mirror-symmetrical along the first virtual line Q1, and the first pixel circuit column 11B is electrically connected to the first data line DL1, and the second pixel circuit column 12B is electrically connected to the second data line DL2, therefore, optionally, the first data line DL1 and the second data line DL2 are also mirror-symmetrical along the first virtual line Q1. And, in the direction perpendicular to the plane of the substrate, the third data line DL3 overlaps with the third pixel circuit column 13B, which is convenient for the periodic arrangement design of the data line DL along the first direction X, is also beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0214] And, since the first pixel circuit column 11B is electrically connected to the first data line DL1, and the second pixel circuit column 12B is electrically connected to the second data line DL2, therefore, usually, in the direction perpendicular to the plane of the substrate, the first data line DL1 overlaps with the first pixel circuit column 11B, and the second data line DL2 overlaps with the second pixel circuit column 12B.

[0215] Optionally, as ​As shown, a column of pixel circuit groups 110 (including at least three columns of pixel circuits 10) corresponds to two second auxiliary traces D2. That is, with the second direction Y as the column direction, the number of columns of the array formed by multiple pixel circuit groups 110 is N10, and the number of second auxiliary traces D2 is N15, where N15 = 2N10. This can not only achieve the design of partially routing the fan-out traces in the display area (i.e., FIAA), but also avoid affecting the layout of other structures due to excessive space occupied by adding the second auxiliary traces D2.

[0216] Further optionally, as ​ shown, in the direction perpendicular to the plane of the substrate, among the two second auxiliary traces D2 corresponding to a column of pixel circuit groups 110, one second auxiliary trace D2 overlaps with one of the first pixel circuit column 11B and the second pixel circuit column 12B, and the other second auxiliary trace D2 overlaps with the other of the first pixel circuit column 11B and the second pixel circuit column 12B. That is, in the direction perpendicular to the plane of the substrate, among the two second auxiliary traces D2 corresponding to a column of pixel circuit groups 110, one second auxiliary trace D2 overlaps with the first pixel circuit column 11B, and the other second auxiliary trace D2 overlaps with the second pixel circuit column 12B; or, in the direction perpendicular to the plane of the substrate, among the two second auxiliary traces D2 corresponding to a column of pixel circuit groups 110, one second auxiliary trace D2 overlaps with the second pixel circuit column 12B, and the other second auxiliary trace D2 overlaps with the first pixel circuit column 11B. That is to say, the two second auxiliary traces D2 corresponding to a column of pixel circuit groups 110 are respectively set corresponding to two columns of pixel circuits 10 that are mirror-symmetrical about the second direction Y in this column of pixel circuit groups 110, which is convenient for the periodic layout design of the second auxiliary traces D2 along the first direction X, is also beneficial to reducing the layout space of the pixel circuits 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0217] Considering that the data line DL and the second auxiliary trace D2 are set on the same layer, therefore, optionally, as ​ shown, the first data line DL1 and the second data line DL2 corresponding to a column of pixel circuit groups 110 are located between the two second auxiliary traces D2 corresponding to this column of pixel circuit groups 110, and the two second auxiliary traces D2 corresponding to a column of pixel circuit groups 110 are mirror-symmetrical about the first virtual line Q1.

[0218] Another option is that the two second auxiliary traces D2 corresponding to a column of pixel circuit groups 110 can also be located between the first data line DL1 and the second data line DL2 corresponding to this column of pixel circuit groups 110, and the two second auxiliary traces D2 corresponding to a column of pixel circuit groups 110 are mirror-symmetrical about the first virtual line Q1.

[0219] As ​ shown, the display panel includes a first power supply voltage line PVDD. The first power supply voltage line PVDD includes first sub-power supply voltage lines PVDD1 that extend along the second direction Y and are arranged along the first direction X. The first sub-power supply voltage lines PVDD1 are disposed on the same layer as the data lines DL. For example, both the first sub-power supply voltage lines and the data lines DL are located in the metal layer M4. Optionally, taking the second direction Y as the column direction, the number of columns of the array formed by a plurality of pixel circuit groups 110 in the display panel is N10, and the number of the first sub-power supply voltage lines PVDD1 is N14, where N14 ≤ N10, and both N10 and N14 are positive integers. That is, with reference to the number of columns N10 of the pixel circuit groups 110, the number of the first sub-power supply voltage lines PVDD1, N14, can be equal to or less than the number of columns N10 of the pixel circuit groups 110. In this way, to a great extent, the arrangement density of the first sub-power supply voltage lines PVDD1 extending along the second direction Y is reduced, which is beneficial to reducing the layout space of the pixel circuits 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0220] Optionally, as ​ shown, one first sub-power supply voltage line PVDD1 is correspondingly provided for one column of pixel circuit groups 110, that is, N14 = N10, and, in the direction perpendicular to the plane of the substrate, the first sub-power supply voltage line PVDD1 at least partially overlaps with the third pixel circuit column 13B.

[0221] It can be understood that since the data lines DL, the second auxiliary traces D2, and the first sub-power supply voltage lines PVDD1 are disposed on the same layer. For example, the data lines DL, the second auxiliary traces D2, and the first sub-power supply voltage lines PVDD1 are all located in the metal layer M4. Then, on the basis that three data lines DL (i.e., the first data line DL1, the second data line DL2, and the third data line DL3) and two second auxiliary traces D2 are correspondingly provided for one column of pixel circuit groups 110 (including at least three columns of pixel circuits 10), there is not much space left for the first sub-power supply voltage lines PVDD1. Therefore, one first sub-power supply voltage line PVDD1 is correspondingly provided for one column of pixel circuit groups 110.

[0222] It can also be understood that in the direction perpendicular to the plane of the substrate, the first pixel circuit column 11B, the second pixel circuit column 12B, and the third pixel circuit column 13B in a column of pixel circuit groups 110 respectively overlap with the data lines DL (i.e., the first data line DL1, the second data line DL2, and the third data line DL3) electrically connected thereto. Moreover, two second auxiliary traces D2 correspondingly arranged for a column of pixel circuit groups 110 are respectively correspondingly arranged with the first pixel circuit column 11B and the second pixel circuit column 12B that are mirror-symmetrical along the second direction Y in this column of pixel circuit groups 110. Therefore, in the direction perpendicular to the plane of the substrate, the first sub-power supply voltage line PVDD1 and the third pixel circuit column 13B at least partially overlap.

[0223] Further optionally, as ​ shown, the first sub-power supply voltage line PVDD1 correspondingly arranged for a column of pixel circuit groups 110 is located between the first data line DL1, the second data line DL2, and the two second auxiliary traces D2 as a whole correspondingly arranged for this column of pixel circuit groups 110 and the third data line DL3.

[0224] However, since one first sub-power supply voltage line PVDD1 is correspondingly arranged for a column of pixel circuit groups 110, and the width of the first sub-power supply voltage line PVDD1 along the first direction X is limited by the data lines DL and the second auxiliary traces D2, the resistance of the first sub-power supply voltage line PVDD1 may increase. Furthermore, the power consumption of the first sub-power supply voltage line PVDD1 may increase, making the overall signal consistency of the first sub-power supply voltage line PVDD1 in the display panel not very good.

[0225] For this reason, optionally, in combination with ​ 、 ​ and ​ shown, the first power supply voltage line PVDD further includes a second sub-power supply voltage line PVDD2 that extends along the first direction X and is arranged along the second direction Y. The second sub-power supply voltage line PVDD2 is arranged on a different layer from the first sub-power supply voltage line PVDD1, and the second sub-power supply voltage line PVDD2 is electrically connected to the first sub-power supply voltage line PVDD1. In this way, the first sub-power supply voltage line PVDD1 and the second sub-power supply voltage line PVDD2 form a grid structure, which can reduce the overall resistance of the first power supply voltage line PVDD, reduce the power consumption of the first power supply voltage line PVDD, and improve the signal transmission stability of the first power supply voltage line PVDD, which is beneficial to improving display effects such as the display uniformity of the display panel; and it is also beneficial to the electrical connection between the first power supply voltage line PVDD and each pixel circuit 10.

[0226] Optionally, as ​As shown, the second sub-power supply voltage line PVDD2 includes a second first sub-power supply voltage line PVDD2-1. The second first sub-power supply voltage line PVDD2-1 is arranged on the same layer as the first auxiliary trace D1. For example, the second first sub-power supply voltage line PVDD2-1 and the first auxiliary trace D1 are located on the metal layer M3.

[0227] As ​ shown, the second first sub-power supply voltage line PVDD2-1 is electrically connected to the first sub-power supply voltage line PVDD1. It can be understood that both the second first sub-power supply voltage line PVDD2-1 and the first sub-power supply voltage line PVDD1 can be multiple. The intersection positions of multiple second first sub-power supply voltage lines PVDD2-1 and multiple first sub-power supply voltage lines PVDD1 can be multiple. The electrical connection between the second first sub-power supply voltage line PVDD2-1 and the first sub-power supply voltage line PVDD1 includes: the second first sub-power supply voltage line PVDD2-1 is electrically connected to the first sub-power supply voltage line PVDD1 at all their intersection positions, as ​ shown, or the second first sub-power supply voltage line PVDD2-1 is electrically connected to the first sub-power supply voltage line PVDD1 at some of their intersection positions. Specifically, each second first sub-power supply voltage line PVDD2-1 can be electrically connected to at least one first sub-power supply voltage line PVDD1, and each first sub-power supply voltage line PVDD1 can be electrically connected to at least one second first sub-power supply voltage line PVDD2-1. As ​ shown, the second first sub-power supply voltage line PVDD2-1 and the first sub-power supply voltage line PVDD1 can be electrically connected through a connection part L9 located at their intersection position and on the metal layer M4.

[0228] To understand the present application more clearly, ​ shows ​ the layout structure schematic diagram of the second first sub-power supply voltage line PVDD2-1 in ​ and ​ shown, the second first sub-power supply voltage line PVDD2-1 includes a first main part Z1 and a first extension part Z2 extending from the first main part Z1 along the second direction Y. The first extension part Z2 overlaps with the first virtual line Q1.

[0229] Referring to ​ and ​ shown, the pixel circuit 10 includes a driving transistor T3 and a first light-emitting control transistor T1. The first light-emitting control transistor T1 is electrically connected between the first power supply voltage line PVDD and the gate of the driving transistor T3.

[0230] Corresponding to the layout structure, in combination with ​As shown, the first light-emitting control transistor T1 includes a channel region p1 located in the active layer poly, and a first pole p11 and a second pole p12 connected to the channel region p1; and, the display panel includes a light-emitting control line EM. In a direction perpendicular to the plane of the substrate, the channel region p1 of the first light-emitting control transistor T1 at least partially overlaps with the light-emitting control line EM. Optionally, in a direction perpendicular to the plane of the substrate, the overlapping portion of the light-emitting control line EM and the channel region p1 of the first light-emitting control transistor T1 is the gate g1 of the first light-emitting control transistor T1, such that the light-emitting control line EM is electrically connected to the gate g1 of the first light-emitting control transistor T1.

[0231] Combined with Figures 18 - 20 、 Figures 25 - 26 and Figure 31 As shown, the first extension Z2 is electrically connected to the first pole p11 of the first light-emitting control transistor T1 through a connection portion L10 located in the metal layer M2. The second pole p12 of the first light-emitting control transistor T1 is electrically connected to the first pole p31 of the driving transistor T3 in the same layer within the active layer poly; and, since the first extension Z2 overlaps with the first virtual line Q1, the first extension Z2 can be electrically connected to the first pole p11 of the first light-emitting control transistor T1 in both the first pixel circuit 11 and the second pixel circuit 12 in a group of pixel circuit groups 110 at the same time. That is, the first pixel circuit 11 and the second pixel circuit 12 that are mirror-symmetrical along the second direction Y in a group of pixel circuit groups 110 share a via electrically connected to the first power supply voltage line PVDD, which is beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0232] Combined with Figure 26 and Figure 31 As shown, the main body Z1 of the second sub-power supply voltage line PVDD2-1 includes a plurality of first sub-parts Z11 and a plurality of second sub-parts Z12. Along the second direction Y, the width of the second sub-parts Z12 is greater than the width of the first sub-parts Z11; one first sub-part Z11 and one second sub-part Z12 are correspondingly arranged for one pixel circuit 10, that is, one first sub-part Z11 and one second sub-part Z12 are correspondingly arranged for the first pixel circuit 11, one first sub-part Z11 and one second sub-part Z12 are correspondingly arranged for the second pixel circuit 12, and one first sub-part Z11 and one second sub-part Z12 are correspondingly arranged for the third pixel circuit 13.

[0233] It can be understood that by setting the width of the second sub - section Z12 along the second direction Y to be greater than the width of the first example sub - section Z11 along the second direction Y, the resistance of the second - one power - supply voltage line PVDD2 - 1 can be reduced, thereby further reducing the overall resistance of the first power - supply voltage line PVDD, lowering the power consumption of the first power - supply voltage line PVDD, and improving the signal - transmission stability of the first power - supply voltage line PVDD, which is beneficial to enhancing display effects such as the display uniformity of the display panel.

[0234] Reference Figure 2 and Figure 3 As shown, the display panel includes a second reference voltage line Ref2. The pixel circuit 10 includes a driving transistor T3, a gate - reset transistor T5, and a threshold - compensation transistor T4. The gate - reset transistor T5 is electrically connected between the second reference voltage line Ref2 and the gate of the driving transistor T3. The threshold - compensation transistor T4 is electrically connected between the gate of the driving transistor T3 and the second pole.

[0235] Corresponding to the layout structure, combined with 21 - Figure 24As shown, both the gate reset transistor T5 and the threshold compensation transistor T4 can be IGZO thin film transistors. The gate reset transistor T5 includes a first oxide region p5 located in the oxide layer IGZO, and a first pole p51 and a second pole p52 connected to the first oxide region p5 (which can be referred to the foregoing). The threshold compensation transistor T4 includes a second oxide region p4 located in the oxide layer IGZO, and a first pole p41 and a second pole p42 connected to the second oxide region p4. Moreover, the display panel includes a third scan line SN2 extending along the first direction X. The third scan line SN2 includes a third sub-scan line SN21 and a fourth sub-scan line SN22 that transmit the same scan signal. The metal layer where the third sub-scan line SN21 is located (such as the metal layer MC) is on the side of the oxide layer IGZO close to the substrate, and the metal layer where the fourth sub-scan line SN22 is located (such as the metal layer MG) is on the side of the oxide layer IGZO away from the substrate. In the direction perpendicular to the plane of the substrate, both the third sub-scan line SN21 and the fourth sub-scan line SN22 at least partially overlap with the second oxide region p4. Optionally, in the direction perpendicular to the plane of the substrate, the overlapping part of the third sub-scan line SN21 and the second oxide region p4 of the threshold compensation transistor T4 is the second bottom gate bg4 of the threshold compensation transistor T4, so that the third sub-scan line SN21 is electrically connected to the second bottom gate bg4 of the threshold compensation transistor T4. In the direction perpendicular to the plane of the substrate, the overlapping part of the fourth sub-scan line SN22 and the second oxide region p4 of the threshold compensation transistor T4 is the second top gate tg4 of the threshold compensation transistor T4, so that the fourth sub-scan line SN22 is electrically connected to the second top gate tg4 of the threshold compensation transistor T4. Thus, both the second top gate tg4 and the second bottom gate bg4 of the threshold compensation transistor T4 are electrically connected to the third scan line SN2 and receive the same scan signal.

[0236] Combined with Figure 19 、 Figures 21 - 25 As shown, the first pole p51 of the gate reset transistor T5 is electrically connected to the second reference voltage line Ref2, and the specific connection situation can be referred to the foregoing; combined with Figures 18 - 25 As shown, the second pole p52 of the gate reset transistor T5 can be electrically connected to the gate g3 of the driving transistor T3 through a connection portion L8 located in the metal layer M2.

[0237] Combined with Figures 21 - 25 As shown, the first pole p41 of the threshold compensation transistor T4 is electrically connected to the second pole p32 of the driving transistor T3 through a connection portion L11 located in the metal layer M2; combined with Figures 18 - 25As shown, the second pole p42 of the threshold compensation transistor T4 is electrically connected to the second pole p52 of the gate reset transistor T5 on the same layer of the IGZO oxide layer. That is, the second pole p42 of the threshold compensation transistor T4 is also electrically connected to the gate g3 of the driving transistor T3 through the connection portion L8 located in the metal layer M2.

[0238] Optionally, as Figures 21 - 24 , Figure 26 and Figure 31 shown, in the direction perpendicular to the plane of the substrate, the second sub-portion Z12 of the first main portion Z1 in the second sub-power supply voltage line PVDD2-1 along the second direction Y covers at least one of the gate reset transistor T5 and the threshold compensation transistor T4. That is, the second sub-portion Z12 covers the gate reset transistor T5, or the second sub-portion Z12 covers the threshold compensation transistor T4, or the second sub-portion Z12 covers both the gate reset transistor T5 and the threshold compensation transistor T4 at the same time. With such a setting, the second sub-portion Z12 can block external light, preventing external light from irradiating the gate reset transistor T5 and / or the threshold compensation transistor T4 and affecting the performance of the gate reset transistor T5 and / or the threshold compensation transistor T4, thereby improving the performance stability of the gate reset transistor T5 and / or the threshold compensation transistor T4.

[0239] It should be noted that in the direction perpendicular to the plane of the substrate, the second sub-portion Z12 covering at least one of the gate reset transistor T5 and the threshold compensation transistor T4 mainly means that the second sub-portion Z12 covers the oxide region of at least one of the gate reset transistor T5 and the threshold compensation transistor T4.

[0240] Combined with Figure 26 and Figure 31As shown, in the pixel circuit group 110, the first sub - part Z11 and the second sub - part Z12 corresponding to the first pixel circuit 11 and the first sub - part Z11 and the second sub - part Z12 corresponding to the second pixel circuit 12 are arranged in a mirror image along the first virtual line Q1. That is, the first sub - part Z11 and the second sub - part Z12 corresponding to the first pixel circuit 11 and the first sub - part Z11 and the second sub - part Z12 corresponding to the second pixel circuit 12 are arranged in the order of Z12 / Z11 / Z11 / Z12 along the first direction X; and, in the pixel circuit group 110, the first sub - part Z11 and the second sub - part Z12 corresponding to the third pixel circuit 13 and the first sub - part Z11 and the second sub - part Z12 corresponding to the adjacent first pixel circuit 11 or second pixel circuit 12 are arranged in a mirror image along the second direction Y. That is, in the pixel circuit group 110, the first sub - part Z11 and the second sub - part Z12 corresponding to the third pixel circuit 13 and the first sub - part Z11 and the second sub - part Z12 corresponding to the adjacent first pixel circuit 11 or second pixel circuit 12 are arranged in the order of Z11 / Z12 / Z12 / Z11 along the first direction X; with such a setting, it is convenient to use the second sub - part Z12 with a larger width along the second direction Y to cover the gate reset transistor T5 and / or the threshold compensation transistor T4.

[0241] It should be noted that the second - one power supply voltage line PVDD2 - 1 is actually an integrally formed structure. Here, for the convenience of description, the second - one power supply voltage line PVDD2 - 1 is divided into a plurality of first sub - parts Z11, a plurality of second sub - parts Z12, and a first extension part Z2.

[0242] Further optionally, as shown in Figure 21 、 Figure 26 and Figure 31 The second power supply voltage line PVDD2 further includes a second - two power supply voltage line PVDD2 - 2. The second - two power supply voltage line PVDD2 - 2, the second - one power supply voltage line PVDD2 - 1, and the first power supply voltage PVDD1 line are arranged in different layers from each other. For example, the second - two power supply voltage line PVDD2 - 2 is located in the metal layer MC, the second - one power supply voltage line PVDD2 - 1 is located in the metal layer M3, and the first power supply voltage PVDD1 is located in the metal layer M4; and, the second - two power supply voltage line PVDD2 - 2 is electrically connected to the second - one power supply voltage line PVDD2 - 1; with such a setting, the overall resistance of the first power supply voltage line PVDD can be further reduced, the power consumption of the first power supply voltage line PVDD can be reduced, and the signal transmission stability of the first power supply voltage line PVDD can be improved, which is beneficial to improving display effects such as the display uniformity of the display panel.

[0243] Considering that both the second - two power supply voltage line PVDD2 - 2 and the second - one power supply voltage line PVDD2 - 1 extend along the first direction X, therefore, optionally, as shown inFigure 21 , Figure 26 and Figure 31 As shown in Figure 31 , the electrical connection between the second-secondary power supply voltage line PVDD2-2 and the second-primary power supply voltage line PVDD2-1 includes: in a direction perpendicular to the plane of the substrate, the second-secondary power supply voltage line PVDD2-2 and the second-primary power supply voltage line PVDD2-1 at least partially overlap; and the second-secondary power supply voltage line PVDD2-2 and the second-primary power supply voltage line PVDD2-1 are electrically connected through the first via K1, and the first via K1 overlaps with the first virtual line Q1.

[0244] Optionally, as shown in Figures 18 - 20 , the pixel circuit 10 includes a driving transistor T3 and a storage capacitor Cst. The second-secondary power supply voltage line PVDD2-2 includes a plurality of third sub-parts Z3 arranged along the first direction X and connected in sequence. The third sub-part Z3 is the first electrode plate Cst1 of the storage capacitor Cst, and the second electrode plate Cst2 of the storage capacitor Cst is electrically connected to the gate g3 of the driving transistor T3. It can be understood that the third sub-part Z3 in the second-secondary power supply voltage line PVDD2-2 is the first electrode plate Cst1 of the storage capacitor Cst, so that the first electrode plate Cst1 of the storage capacitor Cst is electrically connected to the second-secondary power supply voltage line PVDD2-2, that is, electrically connected to the first power supply voltage line PVDD; the second electrode plate Cst2 of the storage capacitor Cst is the gate g3 of the driving transistor T3, so that the second electrode plate Cst2 of the storage capacitor Cst is electrically connected to the gate g3 of the driving transistor T3.

[0245] It can be understood that, as shown in Figure 21 , Figures 25 - 26 and Figure 31 , the second-secondary power supply voltage line PVDD2-2 is located in the metal layer MC, the second-primary power supply voltage line PVDD2-1 is located in the metal layer M3, and there is also a metal layer M2 between the metal layer MC and the metal layer M3. The first via K1 includes a via between the metal layer MC and the metal layer M2 and a via between the metal layer M2 and the metal layer M3, and the metal layer M2 also includes a connecting portion L13. The second-secondary power supply voltage line PVDD2-2 is electrically connected to the second-primary power supply voltage line PVDD2-1 through the first via K1 and the connecting portion L13 located in the metal layer M2.

[0246] Further optionally, as shown in Figure 21 , Figure 23 , Figure 26 and Figure 31 ​​​​​​​​​​​​​​​As shown, the second sub-power supply voltage line PVDD2 further includes a second-third sub-power supply voltage line PVDD2-3. The second-third sub-power supply voltage line PVDD2-3, the second-second sub-power supply voltage line PVDD2-2, the second-first sub-power supply voltage line PVDD2-1, and the first sub-power supply voltage line PVDD1 are arranged on different layers from each other. For example, the second-third sub-power supply voltage line PVDD2-3 is located on the metal layer MG, the second-second sub-power supply voltage line PVDD2-2 is located on the metal layer MC, the second-first sub-power supply voltage line PVDD2-1 is located on the metal layer M3, and the first sub-power supply voltage line PVDD1 is located on the metal layer M4. And the second-third sub-power supply voltage line PVDD2-3 is electrically connected to the second-first sub-power supply voltage line PVDD2-1 through the first extension part Z2. With such an arrangement, the overall resistance of the first power supply voltage line PVDD can be further reduced, the power consumption of the first power supply voltage line PVDD can be lowered, and the signal transmission stability of the first power supply voltage line PVDD can be improved, which is beneficial to enhancing display effects such as the display uniformity of the display panel.

[0247] As known from the foregoing, in combination with Figure 18 , Figure 23 , Figures 25 - 26 and Figure 31 shown, the first extension part Z2 is electrically connected to the first pole p11 of the first light-emitting control transistor T1 through the connection part L10 located on the metal layer M2. And the second-third sub-power supply voltage line PVDD2-3 is electrically connected to the second-first sub-power supply voltage line PVDD2-1 through the first extension part Z2. Specifically, the first extension part Z2 is also electrically connected to the second-third sub-power supply voltage line PVDD2-3 through the connection part L10 located on the metal layer M2, that is, the first extension part Z2 is electrically connected to the first pole p11 of the first light-emitting control transistor T1 and the second-third sub-power supply voltage line PVDD2-3 through the connection part L10 located on the metal layer M2 at the same time. With such an arrangement, it is beneficial to reduce the layout space of the pixel circuit 10, increase the pixel density of the display panel, and facilitate the realization of high-resolution and high-definition displays.

[0248] Specifically, in combination with Figure 21 , Figure 23 , Figure 26 and Figure 31 shown, the second-second sub-power supply voltage line PVDD2-2 is located on the first metal layer (i.e., the metal layer MC), the second-third sub-power supply voltage line PVDD2-3 is located on the second metal layer (i.e., the metal layer MG), the second-first sub-power supply voltage line PVDD2-1 is located on the third metal layer (i.e., the metal layer M3), and the first sub-power supply voltage line PVDD1 is located on the fourth metal layer (i.e., the metal layer M4). Then, in combination with Figure 1As shown, a first metal layer (i.e., metal layer MC), a second metal layer (i.e., metal layer MG), a third metal layer (i.e., metal layer M3), and a fourth metal layer (i.e., metal layer M4) are disposed in a direction away from the substrate.

[0249] Combined with Figure 18 , Figure 23 , Figures 25 - 26 and Figure 31 As shown, in the pixel circuit group 110, a first pole p11 of a first light-emitting control transistor T1 of a first pixel circuit 11 and a second pixel circuit 12 is electrically connected to a first extension Z2 and a second-third sub-power supply voltage line PVDD2-3, realizing the electrical connection between the first pole p11 of the first light-emitting control transistor T1 of the first pixel circuit 11 and the second pixel circuit 12 and a first power supply voltage line PVDD.

[0250] It can be understood that the first pole p11 of the first light-emitting control transistor T1 of the first pixel circuit 11 and the second pixel circuit 12 in the pixel circuit group 110 is electrically connected to the first extension Z2 through a connection portion L10 located in the metal layer M2, that is, electrically connected to a second-first sub-power supply voltage line PVDD2-1. At the same time, the first pole p11 of the first light-emitting control transistor T1 of the first pixel circuit 11 and the second pixel circuit 12 in the pixel circuit group 110 is electrically connected to the second-third sub-power supply voltage line PVDD2-3 through the connection portion L10 located in the metal layer M2. And the second-third sub-power supply voltage line PVDD2-3 is electrically connected to the first extension Z2 through the connection portion L10 located in the metal layer M2, that is, also electrically connected to the second-first sub-power supply voltage line PVDD2-1.

[0251] Combined with Figure 18 , Figure 23 , Figures 25 - 26 and Figure 31 As shown, in the pixel circuit group 110, a first pole p11 of a first light-emitting control transistor T1 of a third pixel circuit 13 is electrically connected to the second-third sub-power supply voltage line PVDD2-3. Specifically, the first pole p11 of the first light-emitting control transistor T1 of the third pixel circuit 13 is electrically connected to the second-third sub-power supply voltage line PVDD2-3 through a connection portion L12 located in the metal layer M2, realizing the electrical connection between the first pole p11 of the first light-emitting control transistor T1 of the third pixel circuit 13 and a first power supply voltage line PVDD.

[0252] As known from the foregoing, referring to Figure 2 and Figure 3 shown, the display panel includes a bias voltage line DVH. The pixel circuit 10 includes a driving transistor T3 and a bias transistor T8. The bias transistor T8 is electrically connected between at least one of a first pole and a second pole of the driving transistor T3 and the bias voltage line DVH. Specifically, as Figure 1As shown, a fifth metal layer (i.e., metal layer M2) is also provided between the second metal layer (i.e., metal layer MG) and the third metal layer (i.e., metal layer M3). Combining with Figures 18 - 20 、 Figure 23 and Figure 25 shown, the fifth metal layer (i.e., metal layer M2) includes a first connection portion (i.e., connection portion L6). The bias transistor T8 (specifically, the second pole p82 of the bias transistor T8) is electrically connected to the driving transistor T3 through the first connection portion (i.e., connection portion L6). It can be understood that referring to Figure 2 and Figure 3 shown, the first connection portion (i.e., connection portion L6) corresponds to the second node N2.

[0253] As known from the foregoing, referring to Figure 1 shown, the display panel includes a light-emitting element 30 located on the side of the pixel circuit 10 away from the substrate sub. The light-emitting element 30 includes an anode E1, a light-emitting layer E2, and a cathode E3 arranged in a direction away from the substrate sub. The pixel circuit 10 includes a second light-emitting control transistor T6, and the second light-emitting control transistor T6 is electrically connected between the second pole of the driving transistor T3 and the anode of the light-emitting element 30.

[0254] Corresponding to the layout structure, combining with Figures 18 - 20 shown, the second light-emitting control transistor T6 includes a channel region p6 located in the active layer poly, and a first pole p61 and a second pole p62 connected to the channel region p6. The first pole p61 of the second light-emitting control transistor T6 is electrically connected to the second pole p32 of the driving transistor T3 in the same layer within the active layer poly. Combining with Figure 25 and Figure 26 shown, the second pole p62 of the second light-emitting control transistor T6 and the second pole p72 of the anode reset transistor T7 are electrically connected to the anode of the light-emitting element through a connection portion L2 located in the metal layer M2, a connection portion L3 located in the metal layer M3, and a connection portion L4 located in the metal layer M4.

[0255] Referring to Figure 2 and Figure 3 shown, the pixel circuit 10 further includes a first light-emitting control transistor T1. Combining with Figures 18 - 20As shown, the display panel includes an emission control line EM. The emission control line EM is electrically connected not only to the gate g1 of the first emission control transistor T1, but also to the gate g6 of the second emission control transistor T6. The case of the first emission control transistor T1 is as described above. For the second emission control transistor T6, in a direction perpendicular to the plane of the substrate, at least a part of the channel region p6 of the second emission control transistor T6 overlaps with the emission control line EM; optionally, in a direction perpendicular to the plane of the substrate, the overlapping part of the emission control line EM and the channel region p6 of the sixth emission control transistor T6 is the gate g6 of the second emission control transistor T6, so that the emission control line EM is electrically connected to the gate g6 of the second emission control transistor T3.

[0256] As Figure 19 shown, the emission control line EM is located in the sixth metal layer (i.e., metal layer M1). Combining Figure 1 shown, the sixth metal layer (i.e., metal layer M1) is located on a side closer to the substrate sub than the first metal layer (i.e., metal layer MC).

[0257] Combining Figure 19 , Figure 23 and Figure 25 shown, the emission control line EM is located in the sixth metal layer (i.e., metal layer M1), the second-third sub-power voltage line PVDD2-3 is located in the second metal layer (i.e., metal layer MG), and the first connection part (i.e., connection part L6, which is also the second node N2) is located in the fifth metal layer (i.e., metal layer M2). In a direction perpendicular to the plane of the substrate, the emission control line EM, the second-third sub-power voltage line PVDD2-3, and the first connection part (i.e., connection part L6, which is also the second node N2) overlap with each other, and the second-third power voltage line PVDD2-3 is between the emission control line EM and the first connection part (i.e., connection part L6, which is also the second node N2); thus, since the second-third power voltage line PVDD2-3 receives a fixed power voltage signal and is between the emission control line EM and the first connection part (i.e., connection part L6, which is also the second node N2), it can play a shielding role between the emission control line EM and the first connection part (i.e., connection part L6, which is also the second node N2) to prevent the emission control signal transmitted on the emission control line EM from affecting the second node N2.

[0258] The layout design of the above-mentioned first power supply voltage line PVDD is described based on the design of the display panel with part of the fan-out routing layout in the display area (i.e., FIAA). However, it can be understood that the layout design of the first power supply voltage line PVDD is not limited to the display panel must adopt the FIAA design. That is to say, whether the display panel adopts the FIAA design or not, the first power supply voltage line PVDD in the display panel can adopt the above-mentioned layout design. Next, the layout design of the first power supply voltage line PVDD will be described separately.

[0259] Refer to Figure 2 and Figure 3 As shown, the display panel includes a first power supply voltage line PVDD. The pixel circuit 10 includes a first light-emitting control transistor T1, a driving transistor T3, and a storage capacitor Cst. The first light-emitting control transistor T1 is electrically connected between the first power supply voltage line PVDD and the first pole of the driving transistor T3, and the storage capacitor Cst is electrically connected between the first power supply voltage line PVDD and the gate of the driving transistor T3.

[0260] Corresponding to the layout structure, as Figure 26 shown, the first power supply voltage line PVDD includes a first sub-power supply voltage line PVDD1 that extends along the second direction Y and is arranged along the first direction X. For example, the first sub-power supply voltage line is located in the metal layer M4. Optionally, taking the second direction Y as the column direction, the number of columns of the array formed by multiple pixel circuit groups 110 in the display panel is N10, and the number of the first sub-power supply voltage lines PVDD1 is N14, N14 ≤ N10, and both N10 and N14 are positive integers. That is, with reference to the number of columns N10 of the pixel circuit group 110, the number of the first sub-power supply voltage lines PVDD1, N14, can be equal to or less than the number of columns N10 of the pixel circuit group 110. In this way, to a great extent, the arrangement density of the first sub-power supply voltage line PVDD1 extending along the second direction Y is reduced, which is beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0261] Optionally, as Figure 26 shown, one first sub-power supply voltage line PVDD1 is correspondingly arranged for one column of pixel circuit groups 110, that is, N14 = N10. And, in the direction perpendicular to the plane of the substrate, the first sub-power supply voltage line PVDD1 at least partially overlaps with the third pixel circuit column 13B, that is, the first sub-power supply voltage line PVDD1 is correspondingly arranged with the third pixel circuit column 13B that is not mirror-symmetrical with the adjacent pixel circuit column along the second direction Y in one column of pixel circuit groups 110, leaving more space for the arrangement of other signal lines.

[0262] Optionally, in combination with Figure 21 、 Figures 23 - 24 andFigure 26 As shown, the first power supply voltage line PVDD further includes second sub-power supply voltage lines PVDD2 that extend along the first direction X and are arranged along the second direction Y. The second sub-power supply voltage lines PVDD2 are disposed on a different layer from the first sub-power supply voltage lines PVDD1, and the second sub-power supply voltage lines PVDD2 are electrically connected to the first sub-power supply voltage lines PVDD1. In this way, the first sub-power supply voltage lines PVDD1 and the second sub-power supply voltage lines PVDD2 form a grid structure, which can reduce the overall resistance of the first power supply voltage line PVDD, lower the power consumption of the first power supply voltage line PVDD, and improve the signal transmission stability of the first power supply voltage line PVDD, which is beneficial to improving display effects such as the display uniformity of the display panel. Moreover, it is also beneficial to the electrical connection between the first power supply voltage line PVDD and each pixel circuit 10.

[0263] Optionally, as Figure 26 shown, the second sub-power supply voltage line PVDD2 includes a second-first sub-power supply voltage line PVDD2-1. The second-first sub-power supply voltage line PVDD2-1 is disposed on a different layer from the first sub-power supply voltage line PVDD1. For example, the second-first sub-power supply voltage line PVDD2-1 is located in the metal layer M3, and the first sub-power supply voltage line PVDD1 is located in the metal layer M4, and the second-first sub-power supply voltage line PVDD2-1 is electrically connected to the first sub-power supply voltage line PVDD1.

[0264] It can be understood that both the second-first sub-power supply voltage lines PVDD2-1 and the first sub-power supply voltage lines PVDD1 can be multiple. The intersection positions of the multiple second-first sub-power supply voltage lines PVDD2-1 and the multiple first sub-power supply voltage lines PVDD1 can be multiple. The electrical connection between the second-first sub-power supply voltage line PVDD2-1 and the first sub-power supply voltage line PVDD1 includes: the second-first sub-power supply voltage line PVDD2-1 is electrically connected to the first sub-power supply voltage line PVDD1 at all intersection positions of the two, as Figure 26 shown, or the second-first sub-power supply voltage line PVDD2-1 is electrically connected to the first sub-power supply voltage line PVDD1 at some intersection positions of the two. Specifically, each second-first sub-power supply voltage line PVDD2-1 can be electrically connected to at least one first sub-power supply voltage line PVDD1, and each first sub-power supply voltage line PVDD1 can be electrically connected to at least one second-first sub-power supply voltage line PVDD2-1. As Figure 26 shown, the second-first sub-power supply voltage line PVDD2-1 and the first sub-power supply voltage line PVDD1 can be electrically connected through a connection portion L9 located at the intersection position of the two and in the metal layer M4.

[0265] To understand the present application more clearly, Figure 31 is shown Figure 26Schematic layout diagram of the second primary power supply voltage line PVDD2-1, combined with Figure 26 and Figure 31 shown, the second primary power supply voltage line PVDD2-1 includes a first main body portion Z1 and a first extension portion Z2 extending from the first main body portion Z1 along the second direction Y.

[0266] Combined with Figures 18 - 26 shown, in the pixel circuit group 110, the first pixel circuit 10, the second pixel circuit 20, and the third pixel circuit 30 are arranged along the first direction X, and the first pixel circuit 10 and the second pixel circuit 20 are mirror-symmetrical along the first virtual line Q1, and the first virtual line Q1 extends along the second direction Y, specifically as Figure 26 and Figure 31 shown, the first extension portion Z2 overlaps with the first virtual line Q1.

[0267] Combined with Figures 18 - 20 shown, the first light-emitting control transistor T1 includes a channel region p1 located in the active layer poly, and a first pole p11 and a second pole p12 connected to the channel region p1; and, the display panel includes a light-emitting control line EM, and in the direction perpendicular to the plane of the substrate, the channel region p1 of the first light-emitting control transistor T1 and the light-emitting control line EM at least partially overlap. Optionally, in the direction perpendicular to the plane of the substrate, the overlapping portion of the light-emitting control line EM and the channel region p1 of the first light-emitting control transistor T1 is the gate g1 of the first light-emitting control transistor T1, so that the light-emitting control line EM is electrically connected to the gate g1 of the first light-emitting control transistor T1.

[0268] Combined with Figures 18 - 20 , Figures 25 - 26 and Figure 31 shown, the first extension portion Z2 is electrically connected to the first pole p11 of the first light-emitting control transistor T1 through a connection portion L10 located in the metal layer M2, and the second pole p12 of the first light-emitting control transistor T1 is electrically connected to the first pole p31 of the driving transistor T3 on the same layer within the active layer poly; that is, the first extension portion Z2 is electrically connected to the first pole p11 of the first light-emitting control transistor T1, and the second pole p12 of the first light-emitting control transistor T1 is electrically connected to the first pole p31 of the driving transistor T3.

[0269] Moreover, since the first extension Z2 overlaps with the first virtual line Q1, the first extension Z2 can be electrically connected to the first pole p11 of the first light-emitting control transistor T1 in the first pixel circuit 11 and the second pixel circuit 12 in a group of pixel circuit groups 110 simultaneously. That is, the first pixel circuit 11 and the second pixel circuit 12 that are mirror-symmetrical along the second direction Y in a group of pixel circuit groups 110 share a via electrically connected to the first power supply voltage line PVDD, which is beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition displays.

[0270] Combined with Figure 26 and Figure 31 As shown, the main body Z1 of the second primary power supply voltage line PVDD2-1 includes a plurality of first sub-parts Z11 and a plurality of second sub-parts Z12. Along the second direction Y, the width of the second sub-part Z12 is greater than the width of the first sub-part Z11; one pixel circuit 10 is correspondingly provided with one first sub-part Z11 and one second sub-part Z12, that is, the first pixel circuit 11 is correspondingly provided with one first sub-part Z11 and one second sub-part Z12, the second pixel circuit 12 is correspondingly provided with one first sub-part Z11 and one second sub-part Z12, and the third pixel circuit 13 is correspondingly provided with one first sub-part Z11 and one second sub-part Z12.

[0271] It can be understood that setting the width of the second sub-part Z12 along the second direction Y to be greater than the width of the first example sub-part Z11 along the second direction Y can reduce the resistance of the second primary power supply voltage line PVDD2-1, thereby further reducing the overall resistance of the first power supply voltage line PVDD, reducing the power consumption of the first power supply voltage line PVDD, and improving the signal transmission stability of the first power supply voltage line PVDD, which is beneficial to improving display effects such as the display uniformity of the display panel.

[0272] Referring to Figure 2 and Figure 3 As shown, the display panel includes a second reference voltage line Ref2, and the pixel circuit 10 includes a driving transistor T3, a gate reset transistor T5, and a threshold compensation transistor T4. The gate reset transistor T5 is electrically connected between the second reference voltage line Ref2 and the gate of the driving transistor T3, and the threshold compensation transistor T4 is electrically connected between the gate of the driving transistor T3 and the second pole.

[0273] Corresponding to the layout structure, combined with 21- Figure 24As shown, both the gate reset transistor T5 and the threshold compensation transistor T4 can be IGZO thin film transistors. The gate reset transistor T5 includes a first oxide region p5 located in the oxide layer IGZO, and a first pole p51 and a second pole p52 connected to the first oxide region p5. The threshold compensation transistor T4 includes a second oxide region p4 located in the oxide layer IGZO, and a first pole p41 and a second pole p42 connected to the second oxide region p4.

[0274] Moreover, the display panel includes a third scan line SN2 extending along the first direction X. The third scan line SN2 includes a third sub-scan line SN21 and a fourth sub-scan line SN22 that transmit the same scan signal. The metal layer (such as the metal layer MC) where the third sub-scan line SN21 is located is on the side of the oxide layer IGZO close to the substrate, and the metal layer (such as the metal layer MG) where the fourth sub-scan line SN22 is located is on the side of the oxide layer IGZO away from the substrate; in the direction perpendicular to the plane of the substrate, both the third sub-scan line SN21 and the fourth sub-scan line SN22 at least partially overlap with the second oxide region p4. Optionally, in the direction perpendicular to the plane of the substrate, the overlapping part of the third sub-scan line SN21 and the second oxide region p4 of the threshold compensation transistor T4 is the second bottom gate bg4 of the threshold compensation transistor T4, so that the third sub-scan line SN21 is electrically connected to the second bottom gate bg4 of the threshold compensation transistor T4; in the direction perpendicular to the plane of the substrate, the overlapping part of the fourth sub-scan line SN22 and the second oxide region p4 of the threshold compensation transistor T4 is the second top gate tg4 of the threshold compensation transistor T4, so that the fourth sub-scan line SN22 is electrically connected to the second top gate tg4 of the threshold compensation transistor T4; thus, both the second top gate tg4 and the second bottom gate bg4 of the threshold compensation transistor T4 are electrically connected to the third scan line SN2 and receive the same scan signal.

[0275] The display panel includes a first scan line SN1 extending along a first direction X. The first scan line SN1 includes a first sub-scan line SN11 and a second sub-scan line SN12 that transmit the same scan signal. The metal layer where the first sub-scan line SN11 is located (such as metal layer MC) is on the side of the oxide layer IGZO closer to the substrate, and the metal layer where the second sub-scan line SN12 is located (such as metal layer MG) is on the side of the oxide layer IGZO away from the substrate; in the direction perpendicular to the plane of the substrate, both the first sub-scan line SN11 and the second sub-scan line SN12 at least partially overlap with a first oxide region p5. Optionally, in the direction perpendicular to the plane of the substrate, the overlapping part of the first sub-scan line SN11 and the first oxide region p5 of the gate reset transistor T5 is the first bottom gate bg5 of the gate reset transistor T5, such that the first sub-scan line SN11 is electrically connected to the first bottom gate bg5 of the gate reset transistor T5; in the direction perpendicular to the plane of the substrate, the overlapping part of the second sub-scan line SN12 and the first oxide region p5 of the gate reset transistor T5 is the first top gate tg5 of the gate reset transistor T5, such that the second sub-scan line SN12 is electrically connected to the first top gate tg5 of the gate reset transistor T5; thereby enabling both the first top gate tg5 and the first bottom gate bg5 of the reset transistor T5 to be electrically connected to the first scan line SN1 and receive the same scan signal.

[0276] As shown in combination with Figure 19 and Figures 21 - 25 , the first pole p51 of the gate reset transistor T5 is electrically connected to the second reference voltage line Ref2, and the specific connection situation can be referred to the foregoing; as shown in combination with Figures 18 - 25 , the second pole p52 of the gate reset transistor T5 can be electrically connected to the gate g3 of the driving transistor T3 through a connection portion L8 located in the metal layer M2.

[0277] As shown in combination with Figures 21 - 25 , the first pole p41 of the threshold compensation transistor T4 is electrically connected to the second pole p32 of the driving transistor T3 through a connection portion L11 located in the metal layer M2; as shown in combination with Figures 18 - 25 , the second pole p42 of the threshold compensation transistor T4 is electrically connected to the second pole p52 of the gate reset transistor T5 in the same layer of the oxide layer IGZO, that is, the second pole p42 of the threshold compensation transistor T4 is also electrically connected to the gate g3 of the driving transistor T3 through the connection portion L8 located in the metal layer M2.

[0278] Optionally, as shown in Figures 21 - 24 and Figure 26 and Figure 31As shown, in the direction perpendicular to the plane of the substrate, in the second sub-power supply voltage line PVDD2-1, the second sub-portion Z12 of the first main portion Z1 that is wider in the second direction Y covers at least one of the gate reset transistor T5 and the threshold compensation transistor T4. That is, the second sub-portion Z12 covers the gate reset transistor T5, or the second sub-portion Z12 covers the threshold compensation transistor T4, or the second sub-portion Z12 covers both the gate reset transistor T5 and the threshold compensation transistor T4 at the same time. With such a setting, the second sub-portion Z12 can block external light, preventing the external light from irradiating the gate reset transistor T5 and / or the threshold compensation transistor T4 and affecting the performance of the gate reset transistor T5 and / or the threshold compensation transistor T4, thereby improving the performance stability of the gate reset transistor T5 and / or the threshold compensation transistor T4.

[0279] It should be noted that in the direction perpendicular to the plane of the substrate, the second sub-portion Z12 covering at least one of the gate reset transistor T5 and the threshold compensation transistor T4 mainly means that the second sub-portion Z12 covers the oxide region of at least one of the gate reset transistor T5 and the threshold compensation transistor T4.

[0280] Combined Figure 26 and Figure 31 As shown, in the pixel circuit group 110, the first sub-portion Z11 and the second sub-portion Z12 corresponding to the first pixel circuit 11 and the first sub-portion Z11 and the second sub-portion Z12 corresponding to the second pixel circuit 12 are arranged in a mirror image along the first virtual line Q1. That is, the first sub-portion Z11 and the second sub-portion Z12 corresponding to the first pixel circuit 11 and the first sub-portion Z11 and the second sub-portion Z12 corresponding to the second pixel circuit 12 are arranged in the order of Z12 / Z11 / Z11 / Z12 along the first direction X. And in the pixel circuit group 110, the first sub-portion Z11 and the second sub-portion Z12 corresponding to the third pixel circuit 13 and the first sub-portion Z11 and the second sub-portion Z12 corresponding to the adjacent first pixel circuit 11 or second pixel circuit 12 are arranged in a mirror image along the second direction Y. That is, the first sub-portion Z11 and the second sub-portion Z12 corresponding to the third pixel circuit 13 and the first sub-portion Z11 and the second sub-portion Z12 corresponding to the adjacent first pixel circuit 11 or second pixel circuit 12 are arranged in the order of Z11 / Z12 / Z12 / Z11 along the first direction X. With such a setting, it is convenient to use the second sub-portion Z12 with a larger width in the second direction Y to cover the gate reset transistor T5 and / or the threshold compensation transistor T4.

[0281] It should be noted that the second sub-power supply voltage line PVDD2-1 is actually an integrally formed structure. Here, for the convenience of description, the second sub-power supply voltage line PVDD2-1 is divided into a plurality of first sub-portions Z11, a plurality of second sub-portions Z12, and a first extension portion Z2.

[0282] Further optionally, in combination with Figure 21 、 Figure 26 and Figure 31 As shown, the second sub-power supply voltage line PVDD2 further includes a second-second sub-power supply voltage line PVDD2-2. The second-second sub-power supply voltage line PVDD2-2, the second-first sub-power supply voltage line PVDD2-1, and the first sub-power supply voltage PVDD1 line are arranged in different layers from each other. For example, the second-second sub-power supply voltage line PVDD2-2 is located in the metal layer MC, the second-first sub-power supply voltage line PVDD2-1 is located in the metal layer M3, and the first sub-power supply voltage PVDD1 is located in the metal layer M4; and, the second-second sub-power supply voltage line PVDD2-2 is electrically connected to the second-first sub-power supply voltage line PVDD2-1; with such an arrangement, the overall resistance of the first power supply voltage line PVDD can be further reduced, the power consumption of the first power supply voltage line PVDD can be lowered, and the signal transmission stability of the first power supply voltage line PVDD can be improved, which is beneficial to improving display effects such as the display uniformity of the display panel.

[0283] Considering that both the second-second sub-power supply voltage line PVDD2-2 and the second-first sub-power supply voltage line PVDD2-1 extend along the first direction X, therefore, optionally, in combination with Figure 21 、 Figure 26 and Figure 31 As shown, the electrical connection between the second-second sub-power supply voltage line PVDD2-2 and the second-first sub-power supply voltage line PVDD2-1 includes: in the direction perpendicular to the plane where the substrate is located, the second-second sub-power supply voltage line PVDD2-2 and the second-first sub-power supply voltage line PVDD2-1 at least partially overlap; and, the second-second sub-power supply voltage line PVDD2-2 and the second-first sub-power supply voltage line PVDD2-1 are electrically connected through a first via K1, and the first via K1 overlaps with a first virtual line Q1.

[0284] Optionally, in combination with Figures 18 - 20As shown, the pixel circuit 10 includes a driving transistor T3 and a storage capacitor Cst. The second-secondary power supply voltage line PVDD2-2 includes a plurality of third sub-parts Z3 arranged along the first direction X and connected in sequence. The third sub-part Z3 is the first electrode plate Cst1 of the storage capacitor Cst. The second electrode plate Cst2 of the storage capacitor Cst is electrically connected to the gate g3 of the driving transistor T3. It can be understood that the third sub-part Z3 in the second-secondary power supply voltage line PVDD2-2 is the first electrode plate Cst1 of the storage capacitor Cst, so that the first electrode plate Cst1 of the storage capacitor Cst is electrically connected to the second-secondary power supply voltage line PVDD2-2, that is, electrically connected to the first power supply voltage line PVDD; the second electrode plate Cst2 of the storage capacitor Cst is the gate g3 of the driving transistor T3, so that the second electrode plate Cst2 of the storage capacitor Cst is electrically connected to the gate g3 of the driving transistor T3.

[0285] It can be understood that in combination with Figure 21 、 Figure 25 、 Figure 26 and Figure 31 As shown, the second-secondary power supply voltage line PVDD2-2 is located in the metal layer MC, the second-primary power supply voltage line PVDD2-1 is located in the metal layer M3, there is also a metal layer M2 between the metal layer MC and the metal layer M3. The first via K1 includes vias between the metal layer MC and the metal layer M2 and vias between the metal layer M2 and the metal layer M3. And the metal layer M2 also includes a connecting part L13. The second-secondary power supply voltage line PVDD2-2 is electrically connected to the second-primary power supply voltage line PVDD2-1 through the first via K1 and the connecting part L13 located in the metal layer M2.

[0286] Further optionally, in combination with Figure 21 、 Figure 23 、 Figure 26 and Figure 31As shown, the second sub-power supply voltage line PVDD2 further includes a second-third sub-power supply voltage line PVDD2-3. The second-third sub-power supply voltage line PVDD2-3, the second-second sub-power supply voltage line PVDD2-2, the second-first sub-power supply voltage line PVDD2-1, and the first sub-power supply voltage line PVDD1 are arranged on different layers from each other. For example, the second-third sub-power supply voltage line PVDD2-3 is located on the metal layer MG, the second-second sub-power supply voltage line PVDD2-2 is located on the metal layer MC, the second-first sub-power supply voltage line PVDD2-1 is located on the metal layer M3, and the first sub-power supply voltage line PVDD1 is located on the metal layer M4. And the second-third sub-power supply voltage line PVDD2-3 is electrically connected to the second-first sub-power supply voltage line PVDD2-1 through the first extension Z2. With such an arrangement, the overall resistance of the first power supply voltage line PVDD can be further reduced, the power consumption of the first power supply voltage line PVDD can be lowered, and the signal transmission stability of the first power supply voltage line PVDD can be improved, which is beneficial to enhancing display effects such as the display uniformity of the display panel.

[0287] Specifically, in combination with Figure 21 , Figure 23 , Figure 26 and Figure 31 shown, the second-second sub-power supply voltage line PVDD2-2 is located on the first metal layer (i.e., the metal layer MC), the second-third sub-power supply voltage line PVDD2-3 is located on the second metal layer (i.e., the metal layer MG), the second-first sub-power supply voltage line PVDD2-1 is located on the third metal layer (i.e., the metal layer M3), and the first sub-power supply voltage line PVDD1 is located on the fourth metal layer (i.e., the metal layer M4). Then, in combination with Figure 1 shown, the first metal layer (i.e., the metal layer MC), the second metal layer (i.e., the metal layer MG), the third metal layer (i.e., the metal layer M3), and the fourth metal layer (i.e., the metal layer M4) are arranged in a direction away from the substrate.

[0288] In combination with Figure 18 , Figure 23 , Figures 25 - 26 and Figure 31 shown, in the pixel circuit group 110, the first poles p11 of the first light-emitting control transistors T1 of the first pixel circuit 11 and the second pixel circuit 12 are electrically connected to the first extension Z2 and the second-third sub-power supply voltage line PVDD2-3, realizing the electrical connection between the first poles p11 of the first light-emitting control transistors T1 of the first pixel circuit 11 and the second pixel circuit 12 and the first power supply voltage line PVDD.

[0289] It can be understood that the first pole p11 of the first light-emitting control transistor T1 of the first pixel circuit 11 and the second pixel circuit 12 in the pixel circuit group 110 is electrically connected to the first extension Z2 through the connection portion L10 located in the metal layer M2, that is, electrically connected to the second-one sub-power supply voltage line PVDD2-1. At the same time, the first pole p11 of the first light-emitting control transistor T1 of the first pixel circuit 11 and the second pixel circuit 12 in the pixel circuit group 110 is electrically connected to the second-three sub-power supply voltage line PVDD2-3 through the connection portion L10 located in the metal layer M2. And the second-three sub-power supply voltage line PVDD2-3 is electrically connected to the first extension Z2 through the connection portion L10 located in the metal layer M2, that is, also electrically connected to the second-one sub-power supply voltage line PVDD2-1.

[0290] Combined with Figure 18 、 Figure 23 、 Figures 25 - 26 and Figure 31 As shown, in the pixel circuit group 110, the first pole p11 of the first light-emitting control transistor T1 of the third pixel circuit 13 is electrically connected to the second-three sub-power supply voltage line PVDD2-3. Specifically, the first pole p11 of the first light-emitting control transistor T1 of the third pixel circuit 13 is electrically connected to the second-three sub-power supply voltage line PVDD2-3 through the connection portion L12 located in the metal layer M2, realizing the electrical connection between the first pole p11 of the first light-emitting control transistor T1 of the third pixel circuit 13 and the first power supply voltage line PVDD.

[0291] As known from the foregoing, referring to Figure 2 and Figure 3 shown, the display panel includes a bias voltage line DVH. The pixel circuit 10 includes a driving transistor T3 and a bias transistor T8. The bias transistor T8 is electrically connected between at least one of the first pole and the second pole of the driving transistor T3 and the bias voltage line DVH. Specifically, as Figure 1 shown, a fifth metal layer (i.e., metal layer M2) is further provided between the second metal layer (i.e., metal layer MG) and the third metal layer (i.e., metal layer M3). Combining with Figures 18 - 20 、 Figure 23 and Figure 25 shown, the fifth metal layer (i.e., metal layer M2) includes a first connection portion (i.e., connection portion L6). The bias transistor T8 (specifically, the second pole p82 of the bias transistor T8) is electrically connected to the driving transistor T3 through the first connection portion (i.e., connection portion L6). It can be understood that referring to Figure 2 and Figure 3 shown, the first connection portion (i.e., connection portion L6) corresponds to the second node N2.

[0292] As known from the foregoing, referring to Figure 1As shown, the display panel includes a light-emitting element 30 located on the side of the pixel circuit 10 away from the substrate sub. The light-emitting element 30 includes an anode E1, a light-emitting layer E2, and a cathode E3 arranged in a direction away from the substrate sub. The pixel circuit 10 includes a second light-emitting control transistor T6, and the second light-emitting control transistor T6 is electrically connected between the second pole of the driving transistor T3 and the anode of the light-emitting element 30.

[0293] Corresponding to the layout structure, in combination with Figures 18 - 20 As shown, the second light-emitting control transistor T6 includes a channel region p6 located in the active layer poly, and a first pole p61 and a second pole p62 connected to the channel region p6. The first pole p61 of the second light-emitting control transistor T6 is electrically connected to the second pole p32 of the driving transistor T3 in the same layer within the active layer poly. Then, in combination with Figure 25 and Figure 26 As shown, the second pole p62 of the second light-emitting control transistor T6 is electrically connected to the anode of the light-emitting element through a connection portion L2 located in the metal layer M2, a connection portion L3 located in the metal layer M3, and a connection portion L4 located in the metal layer M4.

[0294] Referring to Figure 2 and Figure 3 As shown, the pixel circuit 10 further includes a first light-emitting control transistor T1. In combination with Figures 18 - 20 As shown, the display panel includes a light-emitting control line EM, and the light-emitting control line EM is electrically connected not only to the gate g1 of the first light-emitting control transistor T1 but also to the gate g6 of the second light-emitting control transistor T6.

[0295] For the first light-emitting control transistor T1, in a direction perpendicular to the plane of the substrate, the channel region p1 of the first light-emitting control transistor T1 at least partially overlaps with the light-emitting control line EM; optionally, in a direction perpendicular to the plane of the substrate, the overlapping portion of the light-emitting control line EM and the channel region p1 of the first light-emitting control transistor T1 is the gate g1 of the first light-emitting control transistor T1, so that the light-emitting control line EM is electrically connected to the gate g1 of the first light-emitting control transistor T1.

[0296] For the second light-emitting control transistor T6, in a direction perpendicular to the plane of the substrate, the channel region p6 of the second light-emitting control transistor T6 at least partially overlaps with the light-emitting control line EM; optionally, in a direction perpendicular to the plane of the substrate, the overlapping portion of the light-emitting control line EM and the channel region p6 of the sixth light-emitting control transistor T6 is the gate g6 of the second light-emitting control transistor T6, so that the light-emitting control line EM is electrically connected to the gate g6 of the second light-emitting control transistor T3.

[0297] As Figure 19As shown, the light-emitting control line EM is located in the sixth metal layer (i.e., metal layer M1), and in combination with Figure 1 As shown, the sixth metal layer (i.e., metal layer M1) is located on the side of the first metal layer (i.e., metal layer MC) close to the substrate sub.

[0298] In combination with Figure 19 、 Figure 23 and Figure 25 As shown, the light-emitting control line EM is located in the sixth metal layer (i.e., metal layer M1), the second-third power supply voltage line PVDD2-3 is located in the second metal layer (i.e., metal layer MG), and the first connection part (i.e., connection part L6, also the second node N2) is located in the fifth metal layer (i.e., metal layer M2). In the direction perpendicular to the plane of the substrate, the light-emitting control line EM, the second-third power supply voltage line PVDD2-3, and the first connection part (i.e., connection part L6, also the second node N2) overlap each other, and the second-third power supply voltage line PVDD2-3 is between the light-emitting control line EM and the first connection part (i.e., connection part L6, also the second node N2); thus, the second-third power supply voltage line PVDD2-3 can play a shielding role between the light-emitting control line EM and the first connection part (i.e., connection part L6, also the second node N2) because it receives a fixed power supply voltage signal and is between them, preventing the light-emitting control signal transmitted on the light-emitting control line EM from affecting the second node N2.

[0299] Referring to Figure 2 and Figure 3 As shown, the display panel includes a data line DL, and the pixel circuit 10 includes a data writing transistor T2 and a driving transistor T3. The data writing transistor T2 is electrically connected between the data line DL and the first pole of the driving transistor T3; the display panel includes a first reference voltage line Ref1, and the pixel circuit 10 includes a gate reset transistor T5 and a threshold compensation transistor T4. The gate reset transistor T5 is electrically connected between the first reference voltage line Ref1 and the gate of the driving transistor T3, and the threshold compensation transistor T4 is electrically connected between the gate and the second pole of the driving transistor T3.

[0300] Corresponding to the layout structure, the driving transistor T3, the gate reset transistor T5, and the threshold compensation transistor T4 have been described above. For the data writing transistor T2, in combination with Figures 18 - 20 As shown, the data writing transistor T2 includes a channel region p2 located in the active layer poly, and a first pole p21 and a second pole p22 connected to the channel region p2. Then, in combination with Figure 25 and Figure 26As shown, the first pole p21 of the data writing transistor T2 is electrically connected to the data line DL through the connection part L14 located in the metal layer M2, and the second pole p22 of the data writing transistor T2 is electrically connected to the first pole p31 of the driving transistor T3 within the active layer poly.

[0301] Combined with Figures 18 - 20 As shown, the display panel includes a second scanning line SP extending along the first direction X. In the direction perpendicular to the plane of the substrate, the second scanning line SP at least partially overlaps with the channel region p2 of the data writing transistor T2. Optionally, in the direction perpendicular to the plane of the substrate, the overlapping part of the second scanning line SP and the channel region p2 of the data writing transistor T2 is the gate g2 of the data writing transistor T2, such that the second scanning line SP is electrically connected to the gate g2 of the data writing transistor T2.

[0302] Combined with Figures 18 - 25 As shown, both the gate reset transistor T5 and the threshold compensation transistor T4 can be IGZO thin film transistors. The gate reset transistor T5 includes a first oxide region p5 located in the oxide layer IGZO, and the threshold compensation transistor T4 includes a second oxide region p4 located in the oxide layer IGZO. The first oxide region p5 and the second oxide region p4 are connected on the same layer. The connection region of the first oxide region p5 and the second oxide region p4 is electrically connected to the gate g3 of the driving transistor T3 through a second connection part (i.e., the connection part L8 located in the metal layer M2), and a protruding part W1 is provided in the connection region of the first oxide region p5 and the second oxide region p4; combined with Figure 2 and Figure 3 , the second connection part (i.e., the connection part L8 located in the metal layer M2) is the first node N1.

[0303] Combined with 18 - Figure 25 As shown, in the direction perpendicular to the plane of the substrate, the protruding part W1 at least partially overlaps with the second scanning line SP, and the protruding part W1 at least partially overlaps with the second connection part (i.e., the connection part L8 located in the metal layer M2). It can be understood that the second scanning line SP is located in the metal layer M1, the protruding part W1 is located in the IGZO layer, and the second connection part (i.e., the connection part L8) is located in the metal layer M2, that is, the protruding part W1 is between the second scanning line SP and the second connection part (i.e., the connection part L8), which is equivalent to adding an equivalent capacitor C2 between the second scanning line SP and the first node N1. At this time, the equivalent circuit structure of the pixel circuit is as Figure 32 shown. Thus, when the display panel is in the dark state, the second scanning line SP jumps from a low level to a high level, and the potential of the first node N1 is pulled up through the equivalent capacitor C2, thereby reducing the dark state voltage.

[0304] The above mainly describes the layout design of the pixel circuit 10 and the signal line 20 in the display panel. Next, the layout design of the light-emitting elements in the display panel will be continued to be introduced.

[0305] Figure 33 shows Figure 1 the partial layout structure of the metal layer M4 and the metal layer RE in []. As known from the foregoing, the metal layer M4 includes a data line DL, a first sub-power supply voltage line PVDD, and a second auxiliary trace D2. Combining Figure 1 as shown, the display panel includes a light-emitting element 30 on the side of the pixel circuit 10 facing away from the substrate sub. The light-emitting element 30 includes an anode E1, a light-emitting layer E2, and a cathode E3 arranged in a direction away from the substrate sub. In fact, the display panel includes a pixel definition layer PDL on the side of the anode E1 facing away from the substrate sub. An opening C1 is provided in the pixel definition layer PDL. The light-emitting layer E2 of the light-emitting element 30 covers the opening C1 in the pixel definition layer PDL. It can be understood that the opening C1 in the pixel definition layer PDL defines the light-emitting area of the light-emitting element 30. The deposition area of the light-emitting layer E2 of the light-emitting element 30 is usually larger than the light-emitting area of the light-emitting element 30 defined by the opening C1 of the pixel definition layer PDL. The anode E1 of the light-emitting element 30 is also usually larger than the light-emitting area of the light-emitting element 30 defined by the opening C1 of the pixel definition layer PDL. And the cathode E3 of the light-emitting element 30 is usually disposed over the entire surface of the display panel.

[0306] In Figure 33 [], the anode E1 of the light-emitting element 30 and the opening C1 in the pixel definition layer PDL corresponding to the light-emitting element 30 are used to represent the light-emitting element 30, and horizontal dotted lines and vertical dotted lines are used to represent the boundaries of adjacent pixel circuit regions in the first direction X and the second direction Y. As Figure 33 shown, in the pixel circuit group 110, the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 are arranged in the first direction. Optionally, the first pixel circuit 11 and the second pixel circuit 12 are adjacent to each other in the first direction X, and the third pixel circuit 13 is adjacent to the first pixel circuit 11 or the second pixel circuit 12 in the first direction X; and the display panel includes a plurality of light-emitting element groups 210. The light-emitting element group 210 includes a first light-emitting element 31, a second light-emitting element 32, and a third light-emitting element 33 with different emission colors. The first pixel circuit 11 is electrically connected to the first light-emitting element 31, the second pixel circuit 12 is electrically connected to the second light-emitting element 32, and the third pixel circuit 13 is electrically connected to the third light-emitting element 33.

[0307] Exemplarily, the three light-emitting elements 30 of a light-emitting element group 210 are a red light-emitting element 30-R, a green light-emitting element 30-G, and a blue light-emitting element 30-B respectively. Thus, the display panel adopts a Real RGB pixel design, and each pixel is composed of three independent sub-pixels of red (R), green (G), and blue (B), without sharing sub-pixels, and directly generates the target color by mixing the three primary colors. Since each pixel in the display panel adopting the Real RGB pixel design completely contains the three primary colors, when displaying fine contents such as text and lines, the edges are sharp. Especially for medium-sized products, the display screen effect is more delicate; moreover, there is no sharing of sub-pixels, the color transition is natural, and there is no "mosquito net effect". Of course, the display panel provided by the embodiments of the present application is not limited to adopting the Real RGB pixel design. As long as in the pixel circuit group arranged in an array in the display panel, the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, and the third pixel circuit 30 is not mirror-symmetrical with the pixel circuit adjacent along the first direction X, it is within the protection scope of the present application.

[0308] It should be noted that the present application does not limit the light-emitting color of the first light-emitting element 31 electrically connected to the first pixel circuit 11. Similarly, the present application does not limit the light-emitting color of the second light-emitting element 32 electrically connected to the second pixel circuit 12, and the present application does not limit the light-emitting color of the third light-emitting element 33 electrically connected to the third pixel circuit 13 either. That is to say, in a group of pixel circuit groups 110, the first pixel circuit 11 and the second pixel circuit 12 are mirror-arranged along the second direction Y, and the third pixel circuit 13 is not mirror-symmetrical with the pixel circuit adjacent along the first direction X, which has nothing to do with the light-emitting colors of the three light-emitting elements 30 electrically connected to them. Figure 33 It is only shown by taking the first light-emitting element 31 electrically connected to the first pixel circuit 11 as one of the green light-emitting element 30-G and the blue light-emitting element 30-B, the second light-emitting element 32 electrically connected to the second pixel circuit 12 as the other of the green light-emitting element 30-G and the blue light-emitting element 30-B, and the third light-emitting element 33 electrically connected to the third pixel circuit 13 as the red light-emitting element 30-R as an example.

[0309] It should also be noted that the present application does not limit the shape of the anode E1 of the light-emitting element 30. Optionally, as Figure 33 shown, the anode E1 of the light-emitting element 30 is rectangular; another option is, as Figure 34 shown, Figure 34 shows a partial layout structure diagram of a single pixel circuit group 110 and a single light-emitting element group 210 in a display panel provided by an embodiment of the present application, which also corresponds to the metal layer M4 and the metal layer RE. It can be seen that the anode E1 of the light-emitting element 30 can also be circular.

[0310] AsFigure 33 As shown, the pixel circuits 10 are arranged in an array along a first direction X and a second direction Y, and one column of pixel circuits 10 is electrically connected to one data line DL.

[0311] Optional, such as Figure 33 and Figure 34 As shown, the light emitting element 30 includes a green light emitting element 30-G. In a direction perpendicular to the plane where the substrate is located, the anode E1 of the green light emitting element 30-G at least partially overlaps with the first sub-power supply voltage line PVDD-1, and the anode E1 of the green light emitting element 30-G does not overlap with the data line DL and the second auxiliary wiring D2. This is because the luminous efficiency of the green light emitting element 30-G is relatively high, and it contributes greatly to the brightness of the pixel. Therefore, in a direction perpendicular to the plane where the substrate is located, the anode E1 of the green light emitting element 30-G is set to at least partially overlap with the first sub-power supply voltage line PVDD-1, and the anode E1 of the green light emitting element 30-G does not overlap with the data line DL and the second auxiliary wiring D2 as much as possible, so as to prevent the anode E1 of the green light emitting element 30-G from coupling with the data line DL and the second auxiliary wiring D2 that transmit data signals, thereby causing display abnormality.

[0312] However, in practical applications, the anode E1 of the green light-emitting element 30-G may at least partially overlap with the data line DL and the second auxiliary routing D2 in the direction perpendicular to the plane of the substrate. For example, when the anode E1 of the green light-emitting element 30-G is circular, it may inevitably overlap with the data line DL and the second auxiliary routing D2 in the direction perpendicular to the plane of the substrate, but the overlap of the anode E1 of the green light-emitting element 30-G with the data line DL and the second auxiliary routing D2 in the direction perpendicular to the plane of the substrate should be reduced.

[0313] Furthermore, since the power supply voltage signal transmitted by the first sub-power supply voltage line PVDD1 is a fixed potential, the anode E1 of the green light emitting element 30-G at least partially overlaps with the first sub-power supply voltage line PVDD-1 in the direction perpendicular to the plane where the substrate is located, and the stability of the green light emitting element 30-G can also be improved. In other words, the anode E1 of the green light emitting element 30-G can be arranged to overlap with the first sub-power supply voltage line PVDD-1 as much as possible in the direction perpendicular to the plane where the substrate is located.

[0314] Optionally, in a direction perpendicular to the plane of the substrate, the area where the anode E1 of the green light-emitting element 30-G overlaps with the first sub-power supply voltage line PVDD1 accounts for no less than 70% of the total area of the anode E1 of the green light-emitting element 30-G, and may preferably be no less than 85%. For example, the area where the anode E1 of the green light-emitting element 30-G overlaps with the first sub-power supply voltage line PVDD1 accounts for 90%, 95% or even 100% of the total area of the anode E1 of the green light-emitting element 30-G.

[0315] Optional, such as Figure 33 and Figure 34 As shown, the light emitting element 30 includes a red light emitting element 30-R, and in a direction perpendicular to the plane where the substrate is located, the anode E1 of the red light emitting element 30-R at least partially overlaps with the first sub-power supply voltage line PVDD-1, and the anode E1 of the red light emitting element 30-R does not overlap with the data line DL and the second auxiliary wiring D2. This is because the luminous efficiency of the red light emitting element 30-R is also relatively high, and its contribution to the brightness of the pixel is also relatively large. Therefore, in a direction perpendicular to the plane where the substrate is located, the anode E1 of the red light emitting element 30-R is set to at least partially overlap with the first sub-power supply voltage line PVDD-1, and the anode E1 of the red light emitting element 30-R does not overlap with the data line DL and the second auxiliary wiring D2 as much as possible, so as to prevent the anode E1 of the red light emitting element 30-R from coupling with the data line DL and the second auxiliary wiring D2 that transmit data signals, thereby causing display abnormality.

[0316] However, in practical applications, the anode E1 of the red light-emitting element 30-R may at least partially overlap with the data line DL and the second auxiliary routing D2 in the direction perpendicular to the plane of the substrate. For example, when the anode E1 of the red light-emitting element 30-R is circular, it may inevitably overlap with the data line DL and the second auxiliary routing D2 in the direction perpendicular to the plane of the substrate, but the overlap of the anode E1 of the red light-emitting element 30-R with the data line DL and the second auxiliary routing D2 in the direction perpendicular to the plane of the substrate should be reduced.

[0317] Furthermore, since the power supply voltage signal transmitted by the first sub-power supply voltage line PVDD1 is a fixed potential, the anode E1 of the red light emitting element 30-R at least partially overlaps with the first sub-power supply voltage line PVDD-1 in the direction perpendicular to the plane where the substrate is located, and the stability of the red light emitting element 30-R can be improved. In other words, the anode E1 of the red light emitting element 30-R can be arranged to overlap with the first sub-power supply voltage line PVDD-1 as much as possible in the direction perpendicular to the plane where the substrate is located.

[0318] Optionally, in a direction perpendicular to the plane of the substrate, the area of overlap between the anode E1 of the red light-emitting element 30-R and the first sub-power voltage line PVDD1 is not less than 70% of the total area of the anode E1 of the green light-emitting element 30-G, and may preferably be not less than 85%. For example, the area of overlap between the anode E1 of the red light-emitting element 30-R and the first sub-power voltage line PVDD1 is 90%, 95% or even 100% of the total area of the anode E1 of the red light-emitting element 30-R.

[0319] Optionally, as Figure 33 and Figure 34 shown, the light-emitting element 30 includes a blue light-emitting element 30-B. In a direction perpendicular to the plane of the substrate, the anode E1 of the blue light-emitting element 30-B overlaps at least one of the data line DL and the second auxiliary trace D2. It can be understood that, in order to reduce the coupling of the anode E1 of the light-emitting element 30 to the data line DL for transmitting data signals and the second auxiliary trace D2, resulting in display anomalies, the overlap of the anode E1 of all the light-emitting elements 30 with the data line DL for transmitting data signals and the second auxiliary trace D2 in a direction perpendicular to the plane of the substrate should be minimized as much as possible. However, considering the actual situation, since the luminous efficiency of the blue light-emitting element 30-B is relatively low and the contribution to the brightness of the pixel is small, therefore, it is only inevitable to sacrifice the blue light-emitting element 30-B. In a direction perpendicular to the plane of the substrate, the anode E1 of the blue light-emitting element 30-B is arranged to overlap at least one of the data line DL and the second auxiliary trace D2.

[0320] The layout design of the anode E1 of the above light-emitting element 30 is described based on the design of the display panel in which part of the fan-out trace is arranged in the display area (i.e., FIAA) (the metal layer M4 includes the second auxiliary trace D2). However, it can be understood that the layout design of the anode E1 of the above light-emitting element 30 is not limited to the display panel must adopt the FIAA design. That is to say, whether the display panel adopts the FIAA design or not, the anode E1 of the light-emitting element 30 in the display panel can adopt the above layout design. Next, the layout design of the anode E1 of the light-emitting element 30 will be described separately.

[0321] Optionally, as Figure 33 and Figure 34As shown, the light emitting element 30 includes a green light emitting element 30-G, and in a direction perpendicular to the plane where the substrate is located, the anode E1 of the green light emitting element 30-G at least partially overlaps with the first sub-power supply voltage line PVDD-1, and the anode E1 of the green light emitting element 30-G does not overlap with the data line DL. This is because the luminous efficiency of the green light emitting element 30-G is relatively high, and it contributes greatly to the brightness of the pixel. Therefore, in a direction perpendicular to the plane where the substrate is located, the anode E1 of the green light emitting element 30-G is set to at least partially overlap with the first sub-power supply voltage line PVDD-1, and the anode E1 of the green light emitting element 30-G does not overlap with the data line DL as much as possible, so as to prevent the anode E1 of the green light emitting element 30-G from coupling with the data line DL that transmits the data signal and causing display abnormality.

[0322] However, in practical applications, the anode E1 of the green light emitting element 30-G may at least partially overlap with the data line DL in the direction perpendicular to the plane of the substrate. For example, when the anode E1 of the green light emitting element 30-G is circular, it may inevitably overlap with the data line DL in the direction perpendicular to the plane of the substrate, but the overlap between the anode E1 of the green light emitting element 30-G and the data line DL in the direction perpendicular to the plane of the substrate should be reduced.

[0323] Furthermore, since the power supply voltage signal transmitted by the first sub-power supply voltage line PVDD1 is a fixed potential, the anode E1 of the green light emitting element 30-G at least partially overlaps with the first sub-power supply voltage line PVDD-1 in the direction perpendicular to the plane where the substrate is located, and the stability of the green light emitting element 30-G can also be improved. In other words, the anode E1 of the green light emitting element 30-G can be arranged to overlap with the first sub-power supply voltage line PVDD-1 as much as possible in the direction perpendicular to the plane where the substrate is located.

[0324] Optionally, in a direction perpendicular to the plane of the substrate, the area where the anode E1 of the green light-emitting element 30-G overlaps with the first sub-power supply voltage line PVDD1 accounts for no less than 70% of the total area of the anode E1 of the green light-emitting element 30-G, and may preferably be no less than 85%. For example, the area where the anode E1 of the green light-emitting element 30-G overlaps with the first sub-power supply voltage line PVDD1 accounts for 90%, 95% or even 100% of the total area of the anode E1 of the green light-emitting element 30-G.

[0325] Optional, such as Figure 33 and Figure 34As shown, the light-emitting element 30 includes a red light-emitting element 30-R. In a direction perpendicular to the plane of the substrate, the anode E1 of the red light-emitting element 30-R at least partially overlaps with the first sub-power supply voltage line PVDD-1, and the anode E1 of the red light-emitting element 30-R does not overlap with the data line DL. This is because the luminous efficiency of the red light-emitting element 30-R is relatively high and it contributes relatively greatly to the brightness of the pixel. Therefore, in a direction perpendicular to the plane of the substrate, the anode E1 of the red light-emitting element 30-R is set to at least partially overlap with the first sub-power supply voltage line PVDD-1, and the anode E1 of the red light-emitting element 30-R is made to not overlap with the data line DL as much as possible, so as to prevent the anode E1 of the red light-emitting element 30-R from coupling to the data line DL that transmits data signals and causing display anomalies.

[0326] However, in actual applications, it is also possible that in a direction perpendicular to the plane of the substrate, the anode E1 of the red light-emitting element 30-R at least partially overlaps with the data line DL. For example, when the anode E1 of the red light-emitting element 30-R is circular, it may inevitably overlap with the data line DL in a direction perpendicular to the plane of the substrate, but the overlap between the anode E1 of the red light-emitting element 30-R and the data line DL in a direction perpendicular to the plane of the substrate should be reduced.

[0327] Moreover, since the power supply voltage signal transmitted by the first sub-power supply voltage line PVDD1 is a fixed potential, in a direction perpendicular to the plane of the substrate, the anode E1 of the red light-emitting element 30-R at least partially overlapping with the first sub-power supply voltage line PVDD-1 can also improve the stability of the red light-emitting element 30-R. That is to say, in a direction perpendicular to the plane of the substrate, the anode E1 of the red light-emitting element 30-R can be set to overlap with the first sub-power supply voltage line PVDD-1 as much as possible.

[0328] Optionally, in a direction perpendicular to the plane of the substrate, the proportion of the overlapping area between the anode E1 of the red light-emitting element 30-R and the first sub-power supply voltage line PVDD1 in the total area of the anode E1 of the green light-emitting element 30-G is not less than 70%, and can preferably be not less than 85%. For example, the proportion of the overlapping area between the anode E1 of the red light-emitting element 30-R and the first sub-power supply voltage line PVDD1 in the total area of the anode E1 of the red light-emitting element 30-R is 90%, 95% or even 100%.

[0329] Optionally, as Figure 33 and Figure 34As shown, the light-emitting element 30 includes a blue light-emitting element 30-B. In a direction perpendicular to the plane of the substrate, the anode E1 of the blue light-emitting element 30-B overlaps at least one of the data line DL and the second auxiliary trace D2. It can be understood that in order to reduce the coupling of the anode E1 of the light-emitting element 30 to the data line DL transmitting the data signal, which may cause display abnormalities, the overlap of the anodes E1 of all the light-emitting elements 30 with the data line DL transmitting the data signal in the direction perpendicular to the plane of the substrate should be minimized as much as possible. However, considering the actual situation, since the luminous efficiency of the blue light-emitting element 30-B is relatively low and its contribution to the brightness of the pixel is small, therefore, it is inevitable to sacrifice the blue light-emitting element 30-B, and in the direction perpendicular to the plane of the substrate, the anode E1 of the blue light-emitting element 30-B is arranged to overlap at least one of the data line DL and the second auxiliary trace D2.

[0330] Figure 35 The schematic diagram of the arrangement structure of a light-emitting element group 210 in the display panel provided by the embodiment of the present application is shown. Figure 36 The schematic diagram of the arrangement structure of another light-emitting element group 210 in the display panel provided by the embodiment of the present application is shown. Figure 37 The schematic diagram of the arrangement structure of yet another light-emitting element group 210 in the display panel provided by the embodiment of the present application is shown. As Figures 35 - 37 shown, the light-emitting element groups 210 are arranged in an array along the first direction X and the second direction Y; among the three light-emitting elements 30 of one light-emitting element group 210, two are the first-color light-emitting elements 301 and the second-color light-emitting elements 302, and the other is the third-color light-emitting element 303; wherein, the first-color light-emitting elements 301 and the second-color light-emitting elements 302 are alternately arranged along the second direction Y, and the third-color light-emitting element 303 is arranged along the first direction X relative to the first-color light-emitting elements 301 and the second-color light-emitting elements 302.

[0331] That is to say, the first-color light-emitting elements 301 and the second-color light-emitting elements 302 are alternately arranged in a column along the second direction Y, the third-color light-emitting elements 303 are arranged in a column along the second direction Y, and the light-emitting element column formed by the first-color light-emitting elements 301 and the second-color light-emitting elements 302 and the light-emitting element column formed by the third-color light-emitting elements 303 are alternately arranged along the first direction X.

[0332] As known from the foregoing, refer to Figure 1As shown, the first color light-emitting element 301, the second color light-emitting element 302, and the third color light-emitting element 303 all include: an anode E1; a pixel definition layer PDL located on the side of the anode E1 facing away from the substrate sub; a light-emitting layer E2 covering the opening C1 of the pixel definition layer PDL, the opening C1 being provided in the pixel definition layer PDL and defining the light-emitting area of the color light-emitting element; and a cathode E3 located on the side of the light-emitting layer E2 facing away from the substrate sub; it can be understood that the deposition area of the light-emitting layer E2 is usually larger than the light-emitting area of the light-emitting element defined by the opening C1 of the pixel definition layer PDL. In Figures 35 - 37 , the opening C1 of the pixel definition layer PDL is used to represent the light-emitting area of the light-emitting element, and the light-emitting layer E2 is used to represent the deposition area of the light-emitting layer E2.

[0333] It should be noted that, as shown in Figure 1 , a fine metal mask (FMM) is usually used to selectively deposit the light-emitting layer E2 at the opening C1 of the pixel definition layer PDL to form the light-emitting element 30 of the corresponding color. It can be understood that an opening C2 is also provided on the FMM, and the opening C2 on the FMM corresponds to the deposition area of the light-emitting layer E2. The opening C2 on the FMM is usually larger than the opening C1 of the pixel definition layer PDL, but the true light-emitting area of the light-emitting element 30 is still defined by the opening C1 in the pixel definition layer PDL.

[0334] Comparing Figure 35 , Figure 36 and Figure 37 it can be seen that, in the arrangement structure of the light-emitting element group 210 shown in Figure 35 , the openings C1 of the pixel definition layer PDL corresponding to the first color light-emitting element 301 and the second color light-emitting element 302 are in a groove shape, and the opening C1 of the pixel definition layer PDL corresponding to the third color light-emitting element 303 is in a slit shape. At this time, when using the FMM to selectively deposit the light-emitting layer E2 of the third color light-emitting element 303 at the opening C1 of the pixel definition layer PDL corresponding to the third color light-emitting element 303, the opening C2 on the FMM can correspond to the openings C1 of the entire column of the third color light-emitting elements 303 in the pixel definition layer PDL. Thus, the light-emitting layer E2 of the entire column of the third color light-emitting elements 303 is deposited, that is, the light-emitting layer E2 of the third color light-emitting element 303 can be deposited across the light-emitting element group 210, thereby increasing the light-emitting area of the third color light-emitting element 303 in the light-emitting element group 210. However, in this case, the FMM becomes a structure in which multiple slender metal thin films separated by one column of the third color light-emitting elements 303 are arranged separately. Thus, it is difficult to fabricate and handle the FMM.

[0335] Therefore, optionally, as shown in Figure 36 andFigure 37 As shown, the opening C1 of the pixel definition layer PDL corresponding to the third color light-emitting element 303 is also set to a groove shape, and one opening C2 on the FMM corresponds to the third color light-emitting elements 303 that are adjacent to each other in pairs along the second direction Y. In this way, not only can the strength of the FMM be ensured, but also the light-emitting layer E2 of the third color light-emitting element 303 can be deposited across two adjacent openings C1 of the pixel definition layer PDL along the second direction Y. That is, one opening C2 on the FMM exposes two adjacent openings C1 of the pixel definition layer PDL along the second direction Y, thereby increasing the light-emitting area of the third color light-emitting element 303 and further extending the life of the third color light-emitting element 303.

[0336] For this reason, optionally, in combination with Figures 36 - 37 As shown, the light-emitting element groups 210 that are adjacent to each other in pairs along the second direction Y in a column of light-emitting element groups 210 form a pixel group 220, and the two third color light-emitting elements 303 in the two light-emitting element groups 210 of a pixel group 220 are arranged close to each other along the second direction Y.

[0337] However, as Figure 36 shown, in a pixel group 220, the geometric center of the light-emitting area (corresponding to the opening C1) of the third color light-emitting element 303 in the upper light-emitting element group 210 along the second direction Y is offset relative to the geometric centers of the light-emitting areas (corresponding to the opening C1) of the first color light-emitting element 301 and the second color light-emitting element 302, and the geometric center of the light-emitting area (corresponding to the opening C1) of the third color light-emitting element 303 in the lower light-emitting element group 210 along the second direction Y is also offset relative to the geometric centers of the light-emitting areas (corresponding to the opening C1) of the first color light-emitting element 301 and the second color light-emitting element 302, which may cause color fringes and affect the display quality.

[0338] For this reason, further optionally, in combination with Figure 36 and Figure 37 shown, it can be found that Figure 33 That is Figure 37The layout structure corresponding to the arrangement of the light-emitting element groups 210 shown. For two columns of light-emitting element groups 210 adjacent along the first direction X, the i-th row light-emitting element group 210 and the (i + 1)-th row light-emitting element group 210 in one column of light-emitting element groups 210 form a pixel group 220, and the (i + 1)-th row light-emitting element group 210 and the (i + 2)-th row light-emitting element group 210 in the other column of light-emitting element groups 210 form a pixel group 220, where i is a positive integer. For the two light-emitting element groups 210 of a pixel group 220, the distance d1 between the geometric centers of the light-emitting regions (corresponding to the opening B1) of the first-color light-emitting elements 301 in one light-emitting element group 210 and the geometric centers of the light-emitting regions (corresponding to the opening B1) of the third-color light-emitting elements 303 in the second direction Y is greater than the distance d2 between the geometric centers of the light-emitting regions (corresponding to the opening B1) of the first-color light-emitting elements 301 in the other light-emitting element group 210 and the geometric centers of the light-emitting regions (corresponding to the opening B1) of the third-color light-emitting elements 303 in the second direction Y.

[0339] And, in combination with Figure 33 and Figure 37 shown, in one column of light-emitting element groups 210, the distance d3 between the geometric centers of the light-emitting regions corresponding to the opening B1 of the two third-color light-emitting elements 303 inside a pixel group 220 in the second direction Y is less than the distance d4 between the geometric centers of the light-emitting regions (corresponding to the opening B1) of the third-color light-emitting elements 103 in two adjacent pixel groups 220 in the second direction Y.

[0340] That is to say, in two columns of light-emitting element groups 210 adjacent along the first direction X, the pixel groups 220 are arranged in a staggered manner along the second direction Y. In two columns of light-emitting element groups 210 separated by one column of light-emitting element groups 210 along the first direction X, the pixel groups 220 are arranged in the same way along the second direction Y. With such a setting, the offset of the light-emitting regions of the third-color light-emitting elements 303 in different columns of pixel groups 220 is averaged, thereby improving the color edges and enhancing the display quality.

[0341] In the above embodiments, considering that in the display panel, the luminous efficiency of the blue light-emitting elements is lower than that of the red light-emitting elements and the green light-emitting elements. Therefore, optionally, as Figures 35 - 37 shown, the first-color light-emitting element 301 is one of the red light-emitting element 30-R and the green light-emitting element 30-G, the second-color light-emitting element 302 is the other of the red light-emitting element 30-R and the green light-emitting element 30-G, and the third-color light-emitting element 303 is the blue light-emitting element 30-B. With such a setting, the light-emitting region of the third-color light-emitting element 303 with a lower luminous efficiency can be increased, thereby extending the lifespan of the third-color light-emitting element 303 and the lifespan of the display panel.

[0342] The embodiment of the present application also provides a display panel, asFigure 1 As shown in the cross-sectional structure of the display panel, the display panel includes a substrate sub, a driving circuit layer 100 on one side of the substrate sub, and a light-emitting element layer 200 on the side of the driving circuit layer 100 facing away from the substrate sub. The driving circuit layer 100 includes a pixel circuit 10 and signal lines 20, and the light-emitting element layer 200 includes light-emitting elements 30.

[0343] Reference Figure 2 and Figure 3 According to the circuit structure of the pixel circuit 10 shown in

[0344] Optionally, Figure 1 the partial layout structure of the active layer poly in Figure 18 is as shown in Figure 1 the partial layout structure of the metal layer M1 in Figure 19 is as shown in Figure 1 the partial layout structure of the stack composed of the active layer poly and the metal layer M1 in Figure 20 is as shown in Figure 1 the partial layout structure of the metal layer MC in Figure 21 is as shown in Figure 1 the partial layout structure of the oxide layer IGZO in Figure 22 is as shown in Figure 1 the partial layout structure of the metal layer MG in Figure 23 is as shown in Figure 1 the partial layout structure of the stack composed of the metal layer MC, the oxide layer IGZO, and the metal layer MG in Figure 24 is as shown in Figure 1The partial layout structure of the middle metal layer M2 is as Figure 25 shown; Figure 1 The partial layout structures of the middle metal layer M3 and the metal layer M4 are as Figure 26 shown; Figure 1 The partial layout structures of the metal layer M4 and the metal layer RE are as Figure 33 shown.

[0345] As Figures 18 - 26 and Figure 33 shown, the display panel includes a plurality of pixel circuit groups 110 on one side of the substrate. The plurality of pixel circuit groups 110 are arranged in an array along the first direction X and the second direction Y, and the first direction X and the second direction Y intersect; moreover, the pixel circuit group 110 includes three pixel circuits 10 arranged along the first direction X, namely the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13.

[0346] Combined with Figure 11 the partial stacked (active layer poly to metal layer MG) layout structure of a group of pixel circuit groups 110 shown, it can be seen that in the pixel circuit group 110, the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, and the third pixel circuit 13 is not mirror-symmetrical with the adjacent pixel circuit along the first direction X.

[0347] Combined with Figure 2 , Figure 3 and Figure 11 shown, regardless of whether the pixel circuit 10 is the first pixel circuit 11, the second pixel circuit 12, or the third pixel circuit 13, the pixel circuit 10 includes a plurality of thin film transistors (T1-T8), a storage capacitor Cst, and key nodes (such as the first node N1, the second node N2, the third node N3, and the fourth node N4). In this application, the fact that the first pixel circuit 11 and the second pixel circuit 12 in the pixel circuit group 110 are mirror-symmetrical along the second direction Y mainly means that the thin film transistors (such as T1-T8), the storage capacitor Cst, and the key nodes (such as the first node N1, the second node N2, the third node N3, and the fourth node N4) in the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y.

[0348] It can be understood that the first pixel circuit 11 and the second pixel circuit 12 in the pixel circuit group 110 are mirror-symmetrical along the second direction Y. Thus, the first pixel circuit 11 and the second pixel circuit 12 that are mirror-symmetrical along the second direction Y can share some vias, saving the occupied space of the pixel circuit, improving the pixel density of the display panel, and thus improving the resolution of the display panel.

[0349] Moreover, as Figure 33As shown in the figure, the display panel includes a plurality of light-emitting element groups 210. The light-emitting element groups 210 are located on the side of the pixel circuit group 110 away from the substrate. The light-emitting element group 210 includes three light-emitting elements with different emission colors, namely a first light-emitting element 31, a second light-emitting element 32, and a third light-emitting element 33. The first pixel circuit 11 is electrically connected to the first light-emitting element 31, the second pixel circuit 12 is electrically connected to the second light-emitting element 32, and the third pixel circuit 13 is electrically connected to the third light-emitting element 33.

[0350] Exemplarily, the three light-emitting elements 30 of a light-emitting element group 210 are a red light-emitting element 30-R, a green light-emitting element 30-G, and a blue light-emitting element 30-B respectively. Thus, the display panel adopts a Real RGB pixel design. Each pixel is composed of three independent sub-pixels of red (R), green (G), and blue (B), without sharing sub-pixels, and directly generates the target color by mixing the three primary colors. Since each pixel in the display panel adopting the Real RGB pixel design completely contains the three primary colors, when displaying fine contents such as text and lines, the edges are sharp. Especially for medium-sized products, the display screen effect is more delicate; and, there is no sharing of sub-pixels, the color transition is natural, and there is no "mosquito net effect".

[0351] Optionally, as Figures 18 - 26 shown in the figure, in the pixel circuit group 110, the first pixel circuit 11 and the second pixel circuit 12 are adjacent to each other along the first direction Y, and the third pixel circuit 13 is adjacent to the first pixel circuit 11 or the second pixel circuit 12 along the first direction X.

[0352] Considering that a pixel in the display panel usually includes three sub-pixels of red (R), green (G), and blue (B), then, in a pixel, there are three implementation manners for which two-color sub-pixel pixel circuits are the first pixel circuit 11 and the second pixel circuit 12 that are adjacent and mirror-symmetric along the second direction Y, and which one-color sub-pixel pixel circuit is the third pixel circuit 13:

[0353] The first implementation manner is as Figure 12 shown in the figure. In a pixel, the pixel circuits of the two-color sub-pixels of red (R) and green (G) are the first pixel circuit 11 and the second pixel circuit 12 that are adjacent and mirror-symmetric along the second direction Y. The pixel circuit of the red (R) sub-pixel is one of the first pixel circuit 11 and the second pixel circuit 12, the pixel circuit of the green (G) sub-pixel is the other of the first pixel circuit 11 and the second pixel circuit 12, and the pixel circuit of the blue (B) sub-pixel is the third pixel circuit 13.

[0354] The second implementation manner is as Figure 13As shown in the figure, in a pixel, the pixel circuits of the green (G) and blue (B) sub-pixels are the adjacent first pixel circuit 11 and second pixel circuit 12 that are mirror-symmetrical along the second direction Y. The pixel circuit of the green (G) sub-pixel is one of the first pixel circuit 11 and the second pixel circuit 12, and the pixel circuit of the blue (B) sub-pixel is the other of the first pixel circuit 11 and the second pixel circuit 12. The pixel circuit of the red (R) sub-pixel is the third pixel circuit 13.

[0355] The third implementation mode is as Figure 14 As shown in the figure, in a pixel, the pixel circuits of the blue (B) and red (R) sub-pixels are the adjacent first pixel circuit 11 and second pixel circuit 12 that are mirror-symmetrical along the second direction Y. The pixel circuit of the blue (B) sub-pixel is one of the first pixel circuit 11 and the second pixel circuit 12, and the pixel circuit of the red (R) sub-pixel is the other of the first pixel circuit 11 and the second pixel circuit 12. The pixel circuit of the green (G) sub-pixel is the third pixel circuit 13.

[0356] Another alternative is, as Figure 9 and Figure 10 As shown in the figure, in the pixel circuit group 110, the third pixel circuit 13 can also be located between the first pixel circuit 11 and the second pixel circuit 12, which does not affect the mirror symmetry of the first pixel circuit 11 and the second pixel circuit 12 along the second direction Y, and the third pixel circuit 13 is not mirror-symmetrical with the adjacent first pixel circuit 11 and second pixel circuit 12 along the first direction X. Since the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, therefore, Figure 9 and Figure 10 substantially represent the same pixel circuit arrangement.

[0357] Considering that a pixel in a display panel usually includes red (R), green (G), and blue (B) sub-pixels, then, in a pixel, there are three implementation modes for which two sub-pixels' pixel circuits are the spaced-apart first pixel circuit 11 and second pixel circuit 12 that are mirror-symmetrical along the second direction Y, and which sub-pixel's pixel circuit is the third pixel circuit 13:

[0358] The first implementation mode is as Figure 15 As shown in the figure, in a pixel, the pixel circuits of the red (R) and green (G) sub-pixels are the spaced-apart first pixel circuit 11 and second pixel circuit 12 that are mirror-symmetrical along the second direction Y. The pixel circuit of the red (R) sub-pixel is one of the first pixel circuit 11 and the second pixel circuit 12, and the pixel circuit of the green (G) sub-pixel is the other of the first pixel circuit 11 and the second pixel circuit 12. The pixel circuit of the blue (B) sub-pixel is the third pixel circuit 13.

[0359] The second embodiment is as follows Figure 16 As shown, in one pixel, the pixel circuits of the two sub-pixels of green (G) and blue (B) are the first pixel circuit 11 and the second pixel circuit 12 that are spaced apart and mirror-symmetrical along the second direction Y. The pixel circuit of the green (G) sub-pixel is one of the first pixel circuit 11 and the second pixel circuit 12, and the pixel circuit of the blue (B) sub-pixel is the other of the first pixel circuit 11 and the second pixel circuit 12. The pixel circuit of the red (R) sub-pixel is the third pixel circuit 13.

[0360] The third embodiment is as follows Figure 17 As shown, in one pixel, the pixel circuits of the two sub-pixels of blue (B) and red (R) are the first pixel circuit 11 and the second pixel circuit 12 that are spaced apart and mirror-symmetrical along the second direction Y. The pixel circuit of the blue (B) sub-pixel is one of the first pixel circuit 11 and the second pixel circuit 12, and the pixel circuit of the red (R) sub-pixel is the other of the first pixel circuit 11 and the second pixel circuit 12. The pixel circuit of the green (G) sub-pixel is the third pixel circuit 13.

[0361] Referring to Figures 12 - 17 As shown, in the pixel circuit group 110, the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, so that the first pixel circuit 11 and the second pixel circuit 12 that are mirror-symmetrical along the second direction Y can share some vias, saving the occupied space of the pixel circuit, improving the pixel density of the display panel, and thus improving the resolution of the display panel. At the same time, the third pixel circuit 13 is set to be non-mirror-symmetrical with the pixel circuits adjacent along the first direction X (such as the first pixel circuit 11 and / or the second pixel circuit 12). In this way, the structures of the pixel circuits of the same-color sub-pixels are the same. For example, the structures of the pixel circuits of the red (R) sub-pixels are the same, the structures of the pixel circuits of the green (G) sub-pixels are the same, and the structures of the pixel circuits of the blue (B) sub-pixels are the same. Then, the directions in which the key nodes of the pixel circuits of the same-color sub-pixels shift due to process fluctuations are the same, thereby improving the display effect of the display panel.

[0362] It should be noted that the foregoing various embodiments of a display panel are also applicable to this type of display panel, that is, the various embodiments of this type of panel can refer to the foregoing display panel and will not be elaborated one by one. The following examples illustrate the situations of some key embodiments in the layout design of the pixel circuit 10, the signal line 20, and the light-emitting element 30.

[0363] Optionally, as Figures 35 - 37The arrangement structure of the light-emitting element group 210 shown, the light-emitting element group 210 is arranged in an array along the first direction X and the second direction Y; among the three light-emitting elements 30 of one light-emitting element group 210, two are the first-color light-emitting element 301 and the second-color light-emitting element 302, and the other is the third-color light-emitting element 303; wherein, the first-color light-emitting element 301 and the second-color light-emitting element 302 are alternately arranged along the second direction Y, and the third-color light-emitting element 303 is arranged along the first direction X relative to the first-color light-emitting element 301 and the second-color light-emitting element 302.

[0364] That is to say, the first-color light-emitting element 301 and the second-color light-emitting element 302 are alternately arranged in a column along the second direction Y, the third-color light-emitting element 303 is arranged in a column along the second direction Y, and the light-emitting element column formed by the first-color light-emitting element 301 and the second-color light-emitting element 302 and the light-emitting element column formed by the third-color light-emitting element 303 are alternately arranged along the first direction X.

[0365] As known from the foregoing, referring to Figure 1 shown, the first-color light-emitting element 301, the second-color light-emitting element 302, and the third-color light-emitting element 303 all include: an anode E1; a pixel definition layer PDL located on the side of the anode E1 facing away from the substrate sub; a light-emitting layer E2 covering the opening C1 of the pixel definition layer PDL, the opening C1 is provided in the pixel definition layer PDL and defines the light-emitting area of the color light-emitting element; and a cathode E3 located on the side of the light-emitting layer E2 facing away from the substrate sub; it can be understood that the deposition area of the light-emitting layer E2 is usually larger than the light-emitting area of the light-emitting element defined by the opening C1 of the pixel definition layer PDL, and in Figures 35 - 37 all, the opening C1 of the pixel definition layer PDL is used to represent the light-emitting area of the light-emitting element, and the light-emitting layer E2 is used to represent the deposition area of the light-emitting layer E2.

[0366] It should be noted that referring to Figure 1 shown, usually a fine metal mask (FMM) is used to selectively deposit the light-emitting layer E2 at the opening C1 of the pixel definition layer PDL to form the light-emitting element 30 of the corresponding color. It can be understood that an opening C2 is also provided on the FMM, and the opening C2 on the FMM corresponds to the deposition area of the light-emitting layer E2. The opening C2 on the FMM is usually larger than the opening C1 of the pixel definition layer PDL, but the true light-emitting area of the light-emitting element 30 is still defined by the opening C1 in the pixel definition layer PDL.

[0367] Comparing Figure 35 、 Figure 36 and Figure 37 it can be seen that, Figure 35In the arrangement structure of the light-emitting element group 210 shown, the opening C1 of the pixel definition layer PDL corresponding to the first-color light-emitting element 301 and the second-color light-emitting element 302 is in a groove shape, and the opening C1 of the pixel definition layer PDL corresponding to the third-color light-emitting element 303 is in a slit shape. At this time, when selectively depositing the light-emitting layer E2 of the third-color light-emitting element 303 at the opening C1 of the pixel definition layer PDL corresponding to the third-color light-emitting element 303 by using the FMM, the opening C2 on the FMM can correspond to the entire column of the openings C1 of the third-color light-emitting elements 303 in the pixel definition layer PDL. In this way, the light-emitting layer E2 of the entire column of the third-color light-emitting elements 303 is deposited, that is, the light-emitting layer E2 of the third-color light-emitting element 303 can be deposited across the light-emitting element group 210, thereby increasing the light-emitting area of the third-color light-emitting element 303 in the light-emitting element group 210. However, in this case, the FMM becomes a structure in which multiple slender metal thin films separated by one column of the third-color light-emitting elements 303 are arranged separately. Thus, it is difficult to fabricate and handle the FMM.

[0368] Therefore, optionally, as Figure 36 and Figure 37 shown, the opening C1 of the pixel definition layer PDL corresponding to the third-color light-emitting element 303 is also set to a groove shape, and two adjacent third-color light-emitting elements 303 along the second direction Y correspond to one opening C2 on the FMM. In this way, not only the strength of the FMM can be ensured, but also the light-emitting layer E2 of the third-color light-emitting element 303 can be deposited across two adjacent openings C1 of the pixel definition layer PDL along the second direction Y. That is, one opening C2 on the FMM exposes two adjacent openings C1 of the pixel definition layer PDL along the second direction Y, thereby increasing the light-emitting area of the third-color light-emitting element 303 and further extending the lifespan of the third-color light-emitting element 303.

[0369] For this purpose, optionally, in combination with Figures 36 - 37 shown, in a column of the light-emitting element group 210, the light-emitting element groups 210 adjacent to each other along the second direction Y form a pixel group 220, and the two third-color light-emitting elements 303 in the two light-emitting element groups 210 of one pixel group 220 are arranged close to each other along the second direction Y.

[0370] However, as Figure 36As shown, in a pixel group 220, the geometric center of the light-emitting region (corresponding to the opening C1) of the third-color light-emitting element 303 in the light-emitting element group 210 on the upper side in the second direction Y is offset relative to the geometric centers of the light-emitting regions (corresponding to the opening C1) of the first-color light-emitting element 301 and the second-color light-emitting element 302. The geometric center of the light-emitting region (corresponding to the opening C1) of the third-color light-emitting element 303 in the light-emitting element group 210 on the lower side in the second direction Y is also offset relative to the geometric centers of the light-emitting regions (corresponding to the opening C1) of the first-color light-emitting element 301 and the second-color light-emitting element 302, which may generate color fringes and affect the display quality.

[0371] Therefore, further optionally, in combination with Figure 36 and Figure 37 shown, it can be found that Figure 33 is Figure 37 the layout structure corresponding to the arrangement of the light-emitting element group 210 shown. For two columns of light-emitting element groups 210 adjacent in the first direction X, the i-th row light-emitting element group 210 and the (i + 1)-th row light-emitting element group 210 in one column of light-emitting element groups 210 form a pixel group 220, and the (i + 1)-th row light-emitting element group 210 and the (i + 2)-th row light-emitting element group 210 in the other column of light-emitting element groups 210 form a pixel group 220, where i is a positive integer; for the two light-emitting element groups 210 of a pixel group 220, the distance d1 in the second direction Y between the geometric centers of the light-emitting regions (corresponding to the opening B1) of the first-color light-emitting element 301 and the third-color light-emitting element 303 in one light-emitting element group 210 is greater than the distance d2 in the second direction Y between the geometric centers of the light-emitting regions (corresponding to the opening B1) of the first-color light-emitting element 301 and the third-color light-emitting element 303 in the other light-emitting element group 210.

[0372] Moreover, in combination with Figure 33 and Figure 37 shown, in one column of light-emitting element groups 210, the distance d3 in the second direction Y between the geometric centers of the light-emitting regions corresponding to the opening B1 of the two third-color light-emitting elements 303 inside a pixel group 220 is less than the distance d4 in the second direction Y between the geometric centers of the light-emitting regions (corresponding to the opening B1) of the third-color light-emitting elements 103 in two adjacent pixel groups 220.

[0373] That is to say, in two groups of light-emitting elements 210 adjacent along the first direction X, the pixel groups 220 are arranged in a staggered manner along the second direction Y. In two groups of light-emitting elements 210 separated by one group of light-emitting elements 210 along the first direction X, the pixel groups 220 are arranged in the same manner along the second direction Y. With such an arrangement, the offsets of the light-emitting regions of the third-color light-emitting elements 303 in different columns of pixel groups 220 are averaged, thereby improving the color edges and enhancing the display quality.

[0374] In the above embodiments, considering that in the display panel, the luminous efficiency of the blue light-emitting element is lower than that of the red light-emitting element and the green light-emitting element, therefore, optionally, as Figures 35 - 37 shown, the first-color light-emitting element 301 is one of the red light-emitting element 30-R and the green light-emitting element 30-G, the second-color light-emitting element 302 is the other of the red light-emitting element 30-R and the green light-emitting element 30-G, and the third-color light-emitting element 303 is the blue light-emitting element 30-B; with such an arrangement, the light-emitting region of the third-color light-emitting element 303 with a lower luminous efficiency can be increased, thereby prolonging the lifespan of the third-color light-emitting element 303 and the service life of the display panel.

[0375] Referring to Figure 2 and Figure 3 shown, the display panel includes a first reference voltage line Ref1, and the pixel circuit 10 includes an anode reset transistor T7. The anode reset transistor T7 is electrically connected between the first reference voltage line Ref1 and the anode of the light-emitting element 30. When the anode reset transistor T7 is turned on, the anode reset transistor T7 can transmit the reference voltage signal transmitted on the first reference voltage line Ref1 to the anode of the light-emitting element 30 to reset the anode of the light-emitting element 30.

[0376] Corresponding to the layout structure of the display panel, in combination with Figure 21 and ​ shown, the first reference voltage line Ref1 may include first sub-reference voltage lines Ref11 extending along the first direction X and arranged along the second direction Y, and second sub-reference voltage lines Ref12 extending along the second direction Y and arranged along the first direction X. ​ shows a partial layout structure schematic diagram of the first reference voltage line Ref1. In combination with ​ , ​ and ​As shown, in the first reference voltage line Ref1, the first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 are arranged in different layers. For example, the first sub-reference voltage line Ref11 is located in the metal layer MC, and the second sub-reference voltage line Ref12 is located in the metal layer M2. Moreover, the first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 are electrically connected. For example, the first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 are electrically connected through a via between the metal layer MC and the metal layer M2.

[0377] It can be understood that by setting the first reference voltage line Ref1 to include the first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 that extend in different directions and are cross-connected electrically, a first reference voltage line Ref1 with a grid structure is formed, so as to reduce the overall resistance of the first reference voltage line Ref1, thereby reducing the power consumption of the first reference voltage line Ref1, and improving the signal transmission stability of the first reference voltage line Ref1, which is beneficial to improving display effects such as the display uniformity of the display panel.

[0378] Combined with ​ As shown, in the pixel circuit group 110, the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 are arranged along the first direction X; the first pixel circuit 11 is arranged along the second direction Y into the first pixel circuit column 11B, the second pixel circuit 12 is arranged along the second direction Y into the second pixel circuit column 12B, and the third pixel circuit 13 is arranged along the second direction Y into the third pixel circuit column 13B. It can be understood that since the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, and the first pixel circuit 11 is arranged along the second direction Y into the first pixel circuit column 11B, and the second pixel circuit 12 is arranged along the second direction Y into the second pixel circuit column 12B, therefore, the first pixel circuit column 11B and the second pixel circuit column 12B are mirror-symmetrical along the second direction Y. Similarly, the third pixel circuit column 13B is not mirror-symmetrical with the pixel circuit column adjacent along the first direction X (such as the first pixel circuit column 11B and / or the second pixel circuit column 12B).

[0379] Optionally, as ​ and ​As shown, in the direction perpendicular to the plane of the substrate, the second sub-reference voltage line Ref12 is correspondingly arranged with the first pixel circuit column 11B or the second pixel circuit column 12B in a column of pixel circuit groups 110. That is to say, the second sub-reference voltage line Ref12 is correspondingly arranged with one of the two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y in a column of pixel circuit groups 110. In terms of position, the second sub-reference voltage line Ref12 overlaps with one of the two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y in a column of pixel circuit groups 110 in the direction perpendicular to the plane of the substrate, which is convenient for the periodic arrangement design of the second sub-reference voltage line Ref12 along the first direction X, is also beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0380] Moreover, in the direction perpendicular to the plane of the substrate, the second sub-reference voltage line Ref12 is correspondingly arranged with the first pixel circuit column 11B or the second pixel circuit column 12B in a column of pixel circuit groups 110. Thus, in terms of quantity, with the number of columns N10 of the pixel circuit groups 110 as a reference, the number of the second sub-reference voltage lines Ref11 can be equal to or less than the number of columns N10 of the pixel circuit groups 110, N11 ≤ N10. In this way, to a great extent, the arrangement density of the second sub-reference voltage line Ref12 extending along the second direction Y is reduced, which is beneficial to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0381] Reference ​ and ​ As shown, the display panel includes a bias voltage line DVH, and the pixel circuit 10 includes a driving transistor T3 and a bias transistor T8. The bias transistor T8 is electrically connected between at least one of the first pole and the second pole of the driving transistor T3 and the bias voltage line DVH. ​ and ​ Only the case where the bias transistor T8 is electrically connected between the first pole of the driving transistor T3 and the bias voltage line DVH is exemplified.

[0382] Corresponding to the layout structure of the display panel, as shown in ​ 、 ​ and ​ shown, where ​The layout structure of the bias voltage line DVH is also shown. It can be seen that the bias voltage line DVH includes a first sub-bias voltage line DVH1 extending along the first direction X and arranged along the second direction Y, and a second sub-bias voltage line DVH2 extending along the second direction Y and arranged along the first direction X. The first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 are arranged on different layers. For example, the first sub-bias voltage line DVH1 is located in the metal layer MG, and the second sub-bias voltage line DVH2 is located in the metal layer M2. The first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 are electrically connected. For example, the first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 are electrically connected through a via between the metal layer MG and the metal layer M2.

[0383] It can be understood that by setting the bias voltage line DVH to include the first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 that extend in different directions and are cross-connected electrically, a bias voltage line DVH with a grid structure is formed, so as to reduce the overall resistance of the bias voltage line DVH, thereby reducing the power consumption of the bias voltage line DVH, and improving the signal transmission stability of the bias voltage line DVH, which is beneficial to improving display effects such as the display uniformity of the display panel.

[0384] Combined with ​ As shown, in the pixel circuit group 110, the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 are arranged along the first direction X; the first pixel circuit 11 is arranged along the second direction Y to form a first pixel circuit column 11B, the second pixel circuit 12 is arranged along the second direction Y to form a second pixel circuit column 12B, and the third pixel circuit 13 is arranged along the second direction Y to form a third pixel circuit column 13B. It can be understood that since the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, and the first pixel circuit 11 is arranged along the second direction Y to form a first pixel circuit column 11B, and the second pixel circuit 12 is arranged along the second direction Y to form a second pixel circuit column 12B, therefore, the first pixel circuit column 11B and the second pixel circuit column 12B are mirror-symmetrical along the second direction Y. Similarly, the third pixel circuit column 13B is not mirror-symmetrical with the pixel circuit column adjacent along the first direction X (such as the first pixel circuit column 11B and / or the second pixel circuit column 12B).

[0385] Optionally, as ​ and Figure 27As shown, in the direction perpendicular to the plane of the substrate, the second sub-bias voltage line DVH2 is correspondingly arranged with the first pixel circuit column 11B or the second pixel circuit column 12B in a column of pixel circuit groups 110. That is to say, the second sub-bias voltage line DVH2 is correspondingly arranged with one of the two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y in a column of pixel circuit groups 110. In terms of position, the second sub-bias voltage line DVH2 intersects with one of the two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y in a column of pixel circuit groups 110 in the direction perpendicular to the plane of the substrate, so as to facilitate the periodic arrangement design of the second sub-bias voltage line DVH2 along the first direction X, and is also conducive to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0386] Moreover, in the direction perpendicular to the plane of the substrate, the second sub-bias voltage line DVH2 is correspondingly arranged with the first pixel circuit column 11B or the second pixel circuit column 12B in a column of pixel circuit groups 110. Thus, in terms of quantity, with the number of columns N10 of the pixel circuit groups 110 as a reference, the number of the second sub-bias voltage lines DVH2, N12, can be equal to or less than the number of columns N10 of the pixel circuit groups 110, N12 ≤ N10. In this way, to a great extent, the arrangement density of the second sub-bias voltage line DVH2 extending along the second direction Y is reduced, which is conducive to reducing the layout space of the pixel circuit 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0387] The cases where the first reference voltage line Ref1 and the bias voltage line DVH in the display panel are separately arranged are introduced above to reduce the layout space of the pixel circuit, increase the pixel density of the display panel, and improve the resolution of the display panel. Of course, the display panel can also include the first reference voltage line Ref1 and the bias voltage line DVH at the same time. Refer to Figure 2 and Figure 3 As shown, the pixel circuit 10 includes an anode reset transistor T7, a driving transistor T3, and a bias transistor T8. The anode reset transistor T7 is electrically connected between the first reference voltage line Ref1 and the anode of the light-emitting element 30. The bias transistor T8 is electrically connected between at least one of the first pole and the second pole of the driving transistor T3 and the bias voltage line DVH.

[0388] Corresponding to the layout structure of the display panel, in combination with Figure 21 、 Figure 25 and Figure 27As shown, the first reference voltage line Ref1 may include a first sub-reference voltage line Ref11 extending along the first direction X and arranged along the second direction Y, and a second sub-reference voltage line Ref12 extending along the second direction Y and arranged along the first direction X. The first sub-reference voltage line Ref11 and the second sub-reference voltage line Ref12 are arranged on different layers and are electrically connected.

[0389] Combined with Figure 23 、 Figure 25 and Figure 27 As shown, the bias voltage line DVH includes a first sub-bias voltage line DVH1 extending along the first direction X and arranged along the second direction Y, and a second sub-bias voltage line DVH2 extending along the second direction Y and arranged along the first direction X. The first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 are arranged on different layers and are electrically connected.

[0390] It can be understood that by setting the first reference voltage line Ref1 to include the first sub-reference signal line Ref11 and the second sub-reference signal line Ref12 that extend in different directions and are cross-connected electrically, the first reference voltage line Ref1 in a grid structure is formed, so as to reduce the overall resistance of the first reference voltage line Ref1, thereby reducing the power consumption of the first reference voltage line Ref1, and improving the signal transmission stability of the first reference voltage line Ref1, which is beneficial to improving display effects such as the display uniformity of the display panel; and by setting the bias voltage line DVH to include the first sub-bias voltage line DVH1 and the second sub-bias voltage line DVH2 that extend in different directions and are cross-connected electrically, the bias voltage line DVH in a grid structure is formed, so as to reduce the overall resistance of the bias voltage line DVH, thereby reducing the power consumption of the bias voltage line DVH, and improving the signal transmission stability of the bias voltage line DVH, which is beneficial to improving display effects such as the display uniformity of the display panel.

[0391] Optionally, as Figure 25 and Figure 27As shown, in the direction perpendicular to the plane of the substrate, the second sub-reference voltage line Ref12 is correspondingly arranged with one of the first pixel circuit column 11B and the second pixel circuit column 12B in a column of pixel circuit groups 110, that is, the second sub-reference voltage line Ref12 overlaps with one of the first pixel circuit column 11B and the second pixel circuit column 12B in a column of pixel circuit groups 110. The second sub-bias voltage line DVH2 is correspondingly arranged with the other of the first pixel circuit column 11B and the second pixel circuit column 12B in a column of pixel circuit groups 110, that is, the second sub-bias voltage line DVH2 overlaps with the other of the first pixel circuit column 11B and the second pixel circuit column 12B in a column of pixel circuit groups 110. That is to say, the second sub-reference voltage line Ref12 and the second sub-bias voltage line DVH2 are respectively correspondingly arranged in position with two columns of pixel circuits 10 that are mirror-symmetrical along the second direction Y in a column of pixel circuit groups 110, so as to facilitate the periodic arrangement design of the second sub-reference voltage line Ref12 and the second sub-bias voltage line DVH2 along the first direction X, which is also beneficial to reducing the layout space of the pixel circuits 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0392] Moreover, in the direction perpendicular to the plane of the substrate, the second sub-reference voltage line Ref12 is correspondingly arranged with one of the first pixel circuit column 11B and the second pixel circuit column 12B in a column of pixel circuit groups 110, and the second sub-bias voltage line DVH2 is correspondingly arranged with the other of the first pixel circuit column 11B and the second pixel circuit column 12B in a column of pixel circuit groups 110. Thus, in terms of quantity, with the number of columns N10 of the pixel circuit groups 110 as a reference, the number of the second sub-reference voltage lines Ref12, N11, can be equal to or less than the number of columns N10 of the pixel circuit groups 110, and the number of the second sub-bias voltage lines DVH2, N12, can be equal to or less than the number of columns N10 of the pixel circuit groups 110, N11≤N10, N12≤N10. In this way, to a great extent, the arrangement density of the signal lines extending along the second direction Y (such as the second sub-reference voltage line Ref12 and the second sub-bias voltage line DVH2) is reduced, which is beneficial to reducing the layout space of the pixel circuits 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0393] Reference Figure 2 and Figure 3As shown, the display panel further includes a second reference voltage line Ref2, and the pixel circuit 10 further includes a gate reset transistor T5. The gate reset transistor T5 is electrically connected between the second reference voltage line Ref2 and the gate of the driving transistor T3. When the gate reset transistor T5 is turned on, the gate reset transistor T5 transmits the reference voltage signal transmitted on the second reference voltage line Ref2 to the gate of the driving transistor T3 to reset the gate of the light-emitting element 30.

[0394] Optionally, as Figure 28 shown, Figure 28 FIG. shows a partial layout structure diagram of a first reference voltage line Ref1, a bias voltage line DVH, and a second reference voltage line Ref2 in a display panel provided by an embodiment of the present application. It can be seen that in addition to the first reference voltage line Ref1 and the bias voltage line DVH being in a grid structure, the second reference voltage line Ref2 is also in a grid structure. Specifically, as Figure 28 shown, the second reference voltage line Ref2 includes third sub-reference voltage lines Ref21 extending along the first direction X and arranged along the second direction Y, and fourth sub-reference voltage lines Ref22 extending along the second direction Y and arranged along the first direction X.

[0395] Optionally, in combination with Figure 19 , Figure 23 and Figure 28 shown, the third sub-reference voltage lines Ref21 and the fourth sub-reference voltage lines Ref22 are arranged in different layers. For example, the third sub-reference voltage lines Ref21 are located in the metal layer M1 and / or the oxide layer IGZO, the fourth sub-reference voltage lines Ref22 are located in the metal layer M2, and the third sub-reference voltage lines Ref21 and the fourth sub-reference voltage lines Ref22 are electrically connected. For example, the third sub-reference voltage lines Ref21 and the fourth sub-reference voltage lines Ref22 are electrically connected through vias between the metal layer where the third sub-reference voltage lines Ref21 are located and the metal layer M2.

[0396] It can be understood that by setting the second reference voltage line Ref2 to include third sub-reference voltage lines Ref21 and fourth sub-reference voltage lines Ref22 that extend in different directions and are cross-connected electrically, a second reference voltage line Ref2 in a grid structure is formed, so as to reduce the overall resistance of the second reference voltage line Ref2, thereby reducing the power consumption of the second reference voltage line Ref2, and improving the signal transmission stability of the second reference voltage line Ref2, which is beneficial to improving display effects such as the display uniformity of the display panel.

[0397] In combination with Figures 18 - 26 and Figure 28As shown, in the pixel circuit group 110, the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 are arranged along the first direction X; the first pixel circuit 11 is arranged along the second direction Y to form the first pixel circuit column 11B, the second pixel circuit 12 is arranged along the second direction Y to form the second pixel circuit column 12B, and the third pixel circuit 13 is arranged along the second direction Y to form the third pixel circuit column 13B. It can be understood that since the first pixel circuit 11 and the second pixel circuit 12 are mirror-symmetrical along the second direction Y, and the first pixel circuit 11 is arranged along the second direction Y to form the first pixel circuit column 11B, and the second pixel circuit 12 is arranged along the second direction Y to form the second pixel circuit column 12B, therefore, the first pixel circuit column 11B and the second pixel circuit column 12B are mirror-symmetrical along the second direction Y. Similarly, the third pixel circuit column 13B is not mirror-symmetrical with the adjacent pixel circuit column along the first direction X (such as the first pixel circuit column 11B and / or the second pixel circuit column 12B).

[0398] Optionally, as Figure 28 shown, in two adjacent columns of pixel circuit groups 110, the first pixel circuit column 11B in one column of pixel circuit groups 110 is correspondingly provided with the second sub-reference voltage line Ref12, and the second pixel circuit column 12B is correspondingly provided with the second sub-bias voltage line DVH2; in the other column of pixel circuit groups 110, the first pixel circuit column 11B is correspondingly provided with the second sub-reference voltage line Ref12, and the second pixel circuit column 12B is correspondingly provided with the fourth sub-reference voltage line Ref22; or, in two adjacent columns of pixel circuit groups 110, the first pixel circuit column 11B in one column of pixel circuit groups 110 is correspondingly provided with the second sub-bias voltage line DVH2, and the second pixel circuit column 12B is correspondingly provided with the second sub-reference voltage line Ref12; in the other column of pixel circuit groups 110, the first pixel circuit column 11B is correspondingly provided with the fourth sub-reference voltage line Ref22, and the second pixel circuit column 12B is correspondingly provided with the second sub-reference voltage line Ref12. Here, the corresponding setting of the pixel circuit column and the signal line means that they are correspondingly set in position, that is, they overlap in the direction perpendicular to the plane where the substrate is located.

[0399] That is to say, in two adjacent columns of pixel circuit groups 110, for two pixel circuits 10 that are mirror-symmetrical along the second direction Y in one column of pixel circuit groups 110, one second sub-reference voltage line Ref12 and one second sub-bias voltage line DVH2 are respectively provided; for two pixel circuits 10 that are mirror-symmetrical along the second direction Y in the other column of pixel circuit groups 110, one second sub-reference voltage line Ref12 and one second sub-reference voltage line Ref12 are respectively provided, so as to facilitate the periodic arrangement design of the second sub-reference voltage line Ref12, the second sub-bias voltage line DVH2, and the second sub-reference voltage line Ref12 along the first direction X. It is also beneficial to reduce the layout space of the pixel circuits 10, increase the pixel density of the display panel, and facilitate the realization of high-resolution and high-definition display.

[0400] Moreover, in two adjacent columns of pixel circuit groups 110, for two pixel circuits 10 that are mirror-symmetrical along the second direction Y in one column of pixel circuit groups 110, one second sub-reference voltage line Ref12 and one second sub-bias voltage line DVH2 are respectively provided; for two pixel circuits 10 that are mirror-symmetrical along the second direction Y in the other column of pixel circuit groups 110, one second sub-reference voltage line Ref12 and one second sub-reference voltage line Ref12 are respectively provided. Thus, with the number of columns N10 of the pixel circuit groups 110 as a reference, the total number N12 + N13 of the second sub-bias voltage lines DVH2 and the fourth sub-reference voltage lines Ref22 can be equal to or less than the number of columns N10 of the pixel circuit groups 110, N12 + N13 ≤ N10. In this way, to a great extent, the arrangement density of the second sub-bias voltage lines DVH2 and the fourth sub-reference voltage lines Ref22 extending along the second direction Y is reduced, which is beneficial to reducing the layout space of the pixel circuits 10, increasing the pixel density of the display panel, and facilitating the realization of high-resolution and high-definition display.

[0401] For example, along the first direction X, the second sub-bias voltage lines DVH2 and the fourth sub-reference voltage lines Ref22 are alternately arranged, and the second sub-reference voltage line Ref12 is located between the second sub-bias voltage lines DVH2 and the fourth sub-reference voltage lines Ref22; thereby, the distribution uniformity of the second sub-reference voltage line Ref12, the second sub-bias voltage line DVH2, and the fourth sub-reference voltage line Ref22 can be further improved, and then the wiring uniformity in the film layer can be improved, which is beneficial to improving the overall signal consistency of the display panel.

[0402] Figure 29 FIG. shows a top view schematic diagram of a display panel provided by an embodiment of the present application. As Figure 29 shown, the display panel includes a display area AA and a non-display area NA at least partially surrounding the display area AA. The display area AA includes a first display area AA1 and a second display area AA2 located on at least one side of the first display area AA1 along the first direction X. CombiningFigures 18 - 28 As shown, the pixel circuit 10 is located in the display area AA. The pixel circuits 10 are arranged in an array along the first direction X and the second direction Y. One column of pixel circuits 10 is correspondingly electrically connected to one data line DL.

[0403] As Figure 29 shown, the non-display area NA includes a fan-out area FA located on one side of the display area AA along the second direction Y and a pin area PA located on the side of the fan-out area FA away from the display area AA. The fan-out area FA includes multiple fan-out traces S1. The pin area PA is provided with multiple pins (pads), including data pins, power pins, etc. After the display panel is manufactured, the driver integrated circuit (Integrated Circuit, abbreviated as IC) is bonded to the data pins, power pins and other pins in the pin area PA. In practical applications, the pin area PA will be bent to the back of the display panel.

[0404] It can be understood that the data line DL in the display area AA is electrically connected to the fan-out trace S1 in the fan-out area FA, so that the data signal output by the driver integrated circuit IC is transmitted to the data line DL in the display area AA after passing through the data pin in the pin area PA and the fan-out trace S1 in the fan-out area FA, so as to drive the pixel circuit 10 in the display area AA to work, and further drive the light-emitting element 30 in the display area AA for display.

[0405] As Figure 29 shown, the first display area AA1 is located in the central area of the display area AA along the first direction X. The data line DL in the first display area AA1 can directly extend to the position of the fan-out area FA and be electrically connected to the fan-out trace S1 in the fan-out area FA.

[0406] The second display area AA2 is located in the left area or the right area of the display area AA along the second direction Y. In some existing display panels, the fan-out trace S1 in the fan-out area FA needs to be routed in the non-display area of the lower border of the display panel, so as to be electrically connected to the data line DL in the second display area AA2. However, in this way, the fan-out trace S1 electrically connected to the data line DL in the second display area AA2 will be arranged at the position of the lower left border or the lower right border of the display panel, so that the fan-out trace S1 occupies a large space along the first direction X, which is not conducive to narrowing the lower border of the display panel.

[0407] Therefore, optionally, in some embodiments of the present application, as Figure 29As shown, a first connection line segment DH1 and a second connection line segment DV1 are provided in the display area AA. The first connection line segment DH1 extends along the first direction X, and the second connection line segment DV1 extends along the second direction Y. Thus, the data signal line ND in the second display area AA2 is electrically connected to the fan-out trace S1 through the first connection line segment DH1 and the second connection line segment DV1. For example, the data line DL in the second display area AA2 can first pass through the first connection line segment DH1 extending along the first direction X, and then pass through the second connection line segment DV1 extending along the second direction Y to be electrically connected to the fan-out trace S1 in the fan-out area FA. In this way, there is no need to arrange the fan-out trace S1 near the lower left border and / or the lower right border of the display panel. Instead, the routing for transmitting the data signal to the data line DL in the second display area AA2 is performed in the display area AA, and part of the fan-out trace is arranged in the display area (Fanout in AA, FIAA), thereby providing a compression space for the lower border of the display panel, which is beneficial to realizing the narrow border of the display panel.

[0408] Figure 30 FIG. shows a partially enlarged top view schematic diagram of a display panel provided by an embodiment of the present application. As Figure 30 shown, considering the etching uniformity and the reflection effect uniformity of the display panel, the display area AA further includes a first non-connection line segment DH2. The first non-connection line segment DH2 is arranged in the same layer and insulated from the first connection line segment DH1. The first non-connection line segment DH2 extends along the first direction X. Thus, the first connection line segment DV1 and the first non-connection line segment DV2 form a first auxiliary trace D1. That is to say, the display area AA includes multiple first auxiliary traces D1 extending along the first direction X. At least part of the first auxiliary traces D1 includes the first connection line segment DH1, and the multiple first auxiliary traces D1 further include a first non-connection line segment DV2 arranged in the same layer and insulated from the first connection line segment DV1.

[0409] Similarly, the display area AA further includes a second non-connection line segment DV2. The second non-connection line segment DV2 is arranged in the same layer and insulated from the second connection line segment DV1. The second non-connection line segment DV2 extends along the second direction Y. Thus, the second connection line segment DV1 and the second non-connection line segment DV2 form a second auxiliary trace D2. That is to say, the display area AA includes multiple second auxiliary traces D2 extending along the second direction Y. At least part of the second auxiliary traces D2 includes the second connection line segment DV1, and the multiple second auxiliary traces D2 further include a second non-connection line segment DV2 arranged in the same layer and insulated from the second connection line segment DV1.

[0410] It should be noted that, as Figure 30As shown, in the first auxiliary trace D1, the first non - connection segment DH2 may include the entire segment that does not transmit data signals to the data line DL along the first direction X, or may include a partial segment within the entire segment along the first direction X that does not tran...

Claims

1. A display panel, characterized in that, Including: Substrate; A plurality of pixel circuit groups, located on one side of the substrate, the plurality of pixel circuit groups being arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting; The pixel circuit group includes at least three pixel circuits, the at least three pixel circuits including a first pixel circuit, a second pixel circuit, and a third pixel circuit, the first pixel circuit and the second pixel circuit being mirror-symmetrical along the second direction, and the third pixel circuit being non-mirror-symmetrical with the adjacent pixel circuit along the first direction.

2. The display panel according to claim 1, wherein In the pixel circuit group, the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged along the first direction; The display panel includes a plurality of light-emitting element groups, the light-emitting element groups being located on the side of the pixel circuit group away from the substrate, the light-emitting element groups including a first light-emitting element, a second light-emitting element, and a third light-emitting element with different light-emitting colors, the first pixel circuit being electrically connected to the first light-emitting element, the second pixel circuit being electrically connected to the second light-emitting element, and the third pixel circuit being electrically connected to the third light-emitting element.

3. The display panel according to claim 1, wherein The display panel includes a light-emitting element on the side of the pixel circuit away from the substrate, the light-emitting element including an anode, a light-emitting layer, and a cathode arranged in a direction away from the substrate; The display panel includes a first reference voltage line, and the pixel circuit includes an anode reset transistor, the anode reset transistor being electrically connected between the first reference voltage line and the anode of the light-emitting element; The first reference voltage line includes a first sub-reference voltage line extending along the first direction and arranged along the second direction, and a second sub-reference voltage line extending along the second direction and arranged along the first direction, the first sub-reference voltage line and the second sub-reference voltage line being arranged in different layers and electrically connected; The number of columns of the array formed by the plurality of pixel circuit groups is N10, the number of the second sub-reference voltage lines is N11, N11≤N10, and both N10 and N11 are positive integers.

4. The display panel according to claim 3, wherein In the pixel circuit group, the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged along the first direction; the first pixel circuit is arranged in a first pixel circuit column along the second direction, the second pixel circuit is arranged in a second pixel circuit column along the second direction, and the third pixel circuit is arranged in a third pixel circuit column along the second direction; In a direction perpendicular to the plane of the substrate, the second sub-reference voltage line is correspondingly arranged with the first pixel circuit column or the second pixel circuit column in a column of the pixel circuit group.

5. The display panel according to claim 4, characterized in that, The display panel includes data lines, the data lines including a first data line, a second data line, and a third data line extending along the second direction and arranged along the first direction, the first pixel circuit column being electrically connected to the first data line, the second pixel circuit column being electrically connected to the second data line, and the third pixel circuit column being electrically connected to the third data line; In a direction perpendicular to the plane of the substrate, the second sub-reference voltage line is correspondingly arranged with the first pixel circuit column in a column of the pixel circuit groups, and at least a part of the first data line electrically connected to the first pixel circuit column in a column of the pixel circuit groups overlaps with the second sub-reference voltage line; Alternatively, in a direction perpendicular to the plane of the substrate, the second sub-reference voltage line is correspondingly arranged with the second pixel circuit column in a column of the pixel circuit groups, and at least a part of the second data line electrically connected to the second pixel circuit column in a column of the pixel circuit groups overlaps with the second sub-reference voltage line.

6. The display panel according to claim 1, wherein The display panel includes a bias voltage line, the pixel circuit includes a driving transistor and a bias transistor, and the bias transistor is electrically connected between at least one of a first pole and a second pole of the driving transistor and the bias voltage line; The bias voltage line includes a first sub-bias voltage line extending along the first direction and arranged along the second direction, and a second sub-bias voltage line extending along the second direction and arranged along the first direction. The first sub-bias voltage line and the second sub-bias voltage line are arranged in different layers and are electrically connected; The number of columns of the array formed by the plurality of pixel circuit groups is N10, the number of the second sub-bias voltage lines is N12, N12 ≤ N10, and both N10 and N12 are positive integers.

7. The display panel according to claim 6, wherein In the pixel circuit group, the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged along the first direction; the first pixel circuit is arranged into a first pixel circuit column along the second direction, the second pixel circuit is arranged into a second pixel circuit column along the second direction, and the third pixel circuit is arranged into a third pixel circuit column along the second direction; In a direction perpendicular to the plane of the substrate, the second sub-bias voltage line is correspondingly arranged with the first pixel circuit column or the second pixel circuit column in a column of the pixel circuit groups.

8. The display panel according to claim 7, wherein The display panel includes data lines, and the data lines include a first data line, a second data line, and a third data line extending along the second direction and arranged along the first direction. The first pixel circuit column is electrically connected to the first data line, the second pixel circuit column is electrically connected to the second data line, and the third pixel circuit column is electrically connected to the third data line; In a direction perpendicular to the plane of the substrate, the second sub-bias voltage line is correspondingly arranged with the first pixel circuit column in a column of the pixel circuit groups, and at least a part of the first data line electrically connected to the first pixel circuit column in a column of the pixel circuit groups overlaps with the second sub-bias voltage line; Alternatively, in a direction perpendicular to the plane of the substrate, the second sub-bias voltage line is correspondingly arranged with the second pixel circuit column in a column of the pixel circuit groups, and at least a part of the second data line electrically connected to the second pixel circuit column in a column of the pixel circuit groups overlaps with the second sub-bias voltage line.

9. The display panel according to claim 1, wherein The display panel includes a light-emitting element located on a side of the pixel circuit away from the substrate. The light-emitting element includes an anode, a light-emitting layer, and a cathode arranged in a direction away from the substrate. The display panel includes a first reference voltage line and a bias voltage line. The pixel circuit includes an anode reset transistor, a driving transistor, and a bias transistor. The anode reset transistor is electrically connected between the first reference voltage line and the anode of the light-emitting element. The bias transistor is electrically connected between at least one of a first pole and a second pole of the driving transistor and the bias voltage line. The first reference voltage line includes first sub-reference voltage lines extending along the first direction and arranged along the second direction, and second sub-reference voltage lines extending along the second direction and arranged along the first direction. The first sub-reference voltage lines and the second sub-reference voltage lines are arranged in different layers and are electrically connected. The bias voltage line includes first sub-bias voltage lines extending along the first direction and arranged along the second direction, and second sub-bias voltage lines extending along the second direction and arranged along the first direction. The first sub-bias voltage lines and the second sub-bias voltage lines are arranged in different layers and are electrically connected. The number of columns of the array formed by the multiple pixel circuit groups is N10, the number of the second sub-reference voltage lines is N11, and the number of the second sub-bias voltage lines is N12. N11 ≤ N10, N12 ≤ N10, and N10, N11, and N12 are all positive integers.

10. The display panel according to claim 9, wherein, N11 = N12 = N10, and along the first direction, the second sub-reference voltage lines and the second sub-bias voltage lines are alternately arranged.

11. The display panel according to claim 10, wherein In the pixel circuit group, the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged along the first direction; the first pixel circuit is arranged in a first pixel circuit column along the second direction, the second pixel circuit is arranged in a second pixel circuit column along the second direction, and the third pixel circuit is arranged in a third pixel circuit column along the second direction. In a direction perpendicular to the plane of the substrate, the second sub-reference voltage line is correspondingly arranged with one of the first pixel circuit column and the second pixel circuit column in a column of the pixel circuit groups, and the second sub-bias voltage line is correspondingly arranged with the other of the first pixel circuit column and the second pixel circuit column in a column of the pixel circuit groups.

12. The display panel according to claim 11, wherein The display panel includes data lines. The data lines include first data lines, second data lines, and third data lines extending along the second direction and arranged along the first direction. The first pixel circuit column is electrically connected to the first data lines, the second pixel circuit column is electrically connected to the second data lines, and the third pixel circuit column is electrically connected to the third data lines. In a direction perpendicular to the plane of the substrate, the second sub-reference voltage line is correspondingly arranged with the first pixel circuit column in a column of the pixel circuit groups, and the second sub-reference voltage line overlaps at least partially with the first data line. The second sub-bias voltage line is correspondingly arranged with the second pixel circuit column in a column of the pixel circuit groups, and the second sub-bias voltage line overlaps at least partially with the second data line; Alternatively, in a direction perpendicular to the plane of the substrate, the second sub-reference voltage line is correspondingly arranged with the second pixel circuit column in a column of the pixel circuit groups, and the second sub-reference voltage line overlaps at least partially with the second data line. The second sub-bias voltage line is correspondingly arranged with the first pixel circuit column in a column of the pixel circuit groups, and the second sub-bias voltage line overlaps at least partially with the first data line.

13. The display panel according to claim 9, wherein The second sub-reference voltage line and the second sub-bias voltage line are arranged in the same layer.

14. The display panel according to claim 9, wherein The first sub-reference voltage line and the first sub-bias voltage line are arranged in different layers.

15. The display panel according to claim 9, wherein, Along the second direction, the first sub-reference voltage line and the first sub-bias voltage line are arranged alternately.

16. The display panel according to claim 9, wherein, The display panel includes a second reference voltage line. The pixel circuit includes a gate reset transistor, and the gate reset transistor is electrically connected between the second reference voltage line and the gate of the driving transistor; The second reference voltage line includes third sub-reference voltage lines extending along the first direction and arranged along the second direction. The third sub-reference voltage lines include third-one sub-reference voltage lines and third-two sub-reference voltage lines. The third-one sub-reference voltage lines and the third-two sub-reference voltage lines are arranged in different layers and are electrically connected; In a direction perpendicular to the plane of the substrate, the third-one sub-reference voltage line and the third-two sub-reference voltage line overlap at least partially.

17. The display panel according to claim 9, characterized in that, The display panel includes a second reference voltage line. The pixel circuit includes a gate reset transistor, and the gate reset transistor is electrically connected between the second reference voltage line and the gate of the driving transistor; The second reference voltage line includes third sub-reference voltage lines extending along the first direction and arranged along the second direction, and fourth sub-reference voltage lines extending along the second direction and arranged along the first direction. The third sub-reference voltage lines and the fourth sub-reference voltage lines are arranged in different layers and are electrically connected; The number of the fourth sub-reference voltage lines is N13, N12 + N13 ≤ N10, and N13 is a positive integer.

18. The display panel according to claim 17, wherein N11 = N10, N12 + N13 = N10; Along the first direction, the second sub-bias voltage line and the fourth sub-reference voltage line are arranged alternately, and the second sub-reference voltage line is located between the second sub-bias voltage line and the fourth sub-reference voltage line.

19. The display panel according to claim 18, wherein, In the pixel circuit group, the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged along the first direction; the first pixel circuits are arranged in a first pixel circuit column along the second direction, the second pixel circuits are arranged in a second pixel circuit column along the second direction, and the third pixel circuits are arranged in a third pixel circuit column along the second direction; In two adjacent columns of the pixel circuit group, the second sub-reference voltage line is correspondingly arranged for the first pixel circuit column in one column of the pixel circuit group, the second sub-bias voltage line is correspondingly arranged for the second pixel circuit column, the second sub-reference voltage line is correspondingly arranged for the first pixel circuit column in the other column of the pixel circuit group, and the fourth sub-reference voltage line is correspondingly arranged for the second pixel circuit column; Alternatively, in two adjacent columns of the pixel circuit group, the second sub-bias voltage line is correspondingly arranged for the first pixel circuit column in one column of the pixel circuit group, the second sub-reference voltage line is correspondingly arranged for the second pixel circuit column, the fourth sub-reference voltage line is correspondingly arranged for the first pixel circuit column in the other column of the pixel circuit group, and the second sub-reference voltage line is correspondingly arranged for the second pixel circuit column.

20. The display panel according to claim 17, wherein The third sub-reference voltage line includes a third-1 sub-reference voltage line and a third-2 sub-reference voltage line. The third-1 sub-reference voltage line, the third-2 sub-reference voltage line, and the fourth sub-reference voltage line are arranged in different layers from each other, and the third-1 sub-reference voltage line, the third-2 sub-reference voltage line, and the fourth sub-reference voltage line are electrically connected to each other; In a direction perpendicular to the plane of the substrate, the third-1 sub-reference voltage line and the third-2 sub-reference voltage line at least partially overlap.

21. The display panel according to claim 17, wherein The second sub-reference voltage line, the second sub-bias voltage line, and the fourth sub-reference voltage line are arranged in the same layer.

22. The display panel according to claim 16 or 17, characterized in that, The first sub-reference voltage line, the first sub-bias voltage line, and the third sub-reference voltage line are arranged in different layers from each other.

23. The display panel according to claim 16 or 17, characterized in that, Along the second direction, the third sub-reference voltage line, the first sub-reference voltage line, and the first sub-bias voltage line are arranged in sequence.

24. The display panel according to claim 6 or 9, characterized in that, The display panel includes a bias control line, and the bias control line is electrically connected to the gate of the bias transistor; The bias control line extends along the first direction and is arranged in a different layer from the first sub-bias voltage line; In a direction perpendicular to the plane of the substrate, the first sub-bias voltage line and the bias control line at least partially overlap.

25. The display panel according to claim 1, wherein, The display panel includes a display area and a fan-out area located on one side of the display area along the second direction. The pixel circuits are located in the display area, and the pixel circuits are arranged in an array along the first direction and the second direction. One column of pixel circuits is correspondingly electrically connected to a data line; The display area includes a first display area and a second display area located on at least one side of the first display area along the first direction; The fan-out area includes a plurality of fan-out traces, and the data line is electrically connected to the fan-out traces; The display area includes a plurality of first auxiliary traces extending along the first direction and a plurality of second auxiliary traces extending along the second direction. At least part of the first auxiliary traces include first connection segments, and at least part of the second auxiliary traces include second connection segments. The data lines in the second display area are electrically connected to the fan-out traces through the first connection segments and the second connection segments.

26. The display panel according to claim 25, wherein The second auxiliary traces are disposed on the same layer as the data lines, and the first auxiliary traces are disposed on a different layer from the second auxiliary traces.

27. The display panel according to claim 26, wherein The display panel includes a light-emitting element on a side of the pixel circuit facing away from the substrate. The light-emitting element includes an anode, a light-emitting layer, and a cathode disposed in a direction away from the substrate. The display panel includes a first reference voltage line. The pixel circuit includes an anode reset transistor electrically connected between the first reference voltage line and the anode of the light-emitting element. The first reference voltage line includes first sub-reference voltage lines extending along the first direction and arranged along the second direction. The first sub-reference voltage lines are disposed on a different layer from the first auxiliary traces. In a direction perpendicular to the plane of the substrate, at least part of the first auxiliary traces overlap with the first sub-reference voltage lines.

28. The display panel according to claim 27, wherein, The display panel includes a second reference voltage line. The pixel circuit includes a driving transistor and a gate reset transistor electrically connected between the second reference voltage line and the gate of the driving transistor. The second reference voltage line includes third sub-reference voltage lines extending along the first direction and arranged along the second direction. The display panel includes first scan lines extending along the first direction and arranged along the second direction. The first scan lines are electrically connected to the gates of the gate reset transistors. Along the second direction, the first scan lines, the third sub-reference voltage lines, and the first sub-reference voltage lines are arranged adjacent to each other in sequence.

29. The display panel according to claim 28, wherein The third sub-reference voltage lines include a third-one sub-reference voltage line and a third-two sub-reference voltage line disposed on different layers, and the third-one sub-reference voltage line and the third-two sub-reference voltage line are electrically connected. In a direction perpendicular to the plane of the substrate, at least part of the third-one sub-reference voltage line overlaps with the third-two sub-reference voltage line. The third-two sub-reference voltage line is located on a side of the third-one sub-reference voltage line facing away from the substrate, and the third-two sub-reference voltage line is located on a side of the first auxiliary traces close to the substrate.

30. The display panel according to claim 29, wherein The gate reset transistor includes a first oxide region located in the oxide layer. The first scan lines include a first sub-scan line and a second sub-scan line. In a direction perpendicular to the plane of the substrate, both the first sub-scan line and the second sub-scan line overlap with at least part of the first oxide region. The metal layer where the first sub-scan line is located is on a side of the oxide layer close to the substrate, and the metal layer where the second sub-scan line is located is on a side of the oxide layer facing away from the substrate. The third-secondary reference voltage line is located in the oxide layer.

31. The display panel according to claim 26, characterized in that, In the pixel circuit group, the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged along the first direction; the first pixel circuit is arranged into a first pixel circuit column along the second direction, the second pixel circuit is arranged into a second pixel circuit column along the second direction, the third pixel circuit is arranged into a third pixel circuit column along the second direction, the first pixel circuit column and the second pixel circuit column are mirror-symmetrical along a first virtual line, and the first virtual line extends along the second direction; The data lines include first data lines, second data lines, and third data lines that extend along the second direction and are arranged along the first direction. The first pixel circuit column is electrically connected to the first data lines, the second pixel circuit column is electrically connected to the second data lines, and the third pixel circuit column is electrically connected to the third data lines; The first data lines and the second data lines are mirror-symmetrical along the first virtual line; In a direction perpendicular to the plane of the substrate, the third data lines overlap with the third pixel circuit column.

32. The display panel according to claim 31, wherein Two of the second auxiliary traces are correspondingly provided for one column of the pixel circuit group; In a direction perpendicular to the plane of the substrate, among the two second auxiliary traces correspondingly provided for one column of the pixel circuit group, one of the second auxiliary traces overlaps with one of the first pixel circuit column and the second pixel circuit column, and the other second auxiliary trace overlaps with the other of the first pixel circuit column and the second pixel circuit column.

33. The display panel according to claim 32, wherein The first data lines and the second data lines correspondingly provided for one column of the pixel circuit group are located between the two second auxiliary traces correspondingly provided for this column of the pixel circuit group, or the two second auxiliary traces correspondingly provided for one column of the pixel circuit group are located between the first data lines and the second data lines correspondingly provided for this column of the pixel circuit group; The two second auxiliary traces correspondingly provided for one column of the pixel circuit group are mirror-symmetrical about the first virtual line.

34. The display panel according to claim 32, wherein The display panel includes a first power supply voltage line, and the first power supply voltage line includes first sub-power supply voltage lines that extend along the second direction and are arranged along the first direction. The first sub-power supply voltage lines are provided on the same layer as the data lines; The number of columns of the array formed by the multiple pixel circuit groups is N10, the number of the first sub-power supply voltage lines is N14, N14≤N10, and both N10 and N14 are positive integers.

35. The display panel according to claim 34, wherein, One of the first sub-power supply voltage lines is correspondingly provided for one column of the pixel circuit group. In a direction perpendicular to the plane of the substrate, the first sub-power supply voltage line at least partially overlaps with the third pixel circuit column.

36. The display panel according to claim 35, characterized in that, The first sub-power supply voltage line correspondingly provided for one column of the pixel circuit group is located between the first data lines, the second data lines, and the whole of the two second auxiliary traces correspondingly provided for this column of the pixel circuit group and the third data lines.

37. The display panel according to claim 35, wherein, The first power supply voltage line further includes second sub-power supply voltage lines extending along the first direction and arranged along the second direction. The second sub-power supply voltage lines are arranged on a different layer from the first sub-power supply voltage lines, and the second sub-power supply voltage lines are electrically connected to the first sub-power supply voltage lines.

38. The display panel according to claim 37, wherein The second sub-power supply voltage line includes a second-one power supply voltage line, which is arranged on the same layer as the first auxiliary trace, and the second-one power supply voltage line is electrically connected to the first sub-power supply voltage line.

39. The display panel according to claim 38, wherein, The second-one power supply voltage line includes a first main body portion and a first extension portion extending from the first main body portion along the second direction. The first extension portion overlaps with the first virtual line. The pixel circuit includes a driving transistor and a first light-emitting control transistor. The first extension portion is electrically connected to a first pole of the first light-emitting control transistor, and a second pole of the first light-emitting control transistor is electrically connected to a first pole of the driving transistor.

40. The display panel according to claim 39, wherein The first main body portion includes a plurality of first sub-portions and a plurality of second sub-portions. Along the second direction, the width of the second sub-portions is greater than the width of the first sub-portions. One first sub-portion and one second sub-portion are correspondingly provided for one pixel circuit. The display panel includes a second reference voltage line. The pixel circuit includes a gate reset transistor and a threshold compensation transistor. The gate reset transistor is electrically connected between the second reference voltage line and the gate of the driving transistor, and the threshold compensation transistor is electrically connected between the gate and the second pole of the driving transistor. In a direction perpendicular to the plane of the substrate, the second sub-portion covers at least one of the gate reset transistor and the threshold compensation transistor.

41. The display panel according to claim 40, wherein, In the pixel circuit group, the first sub-portion and the second sub-portion correspondingly provided for the first pixel circuit and the first sub-portion and the second sub-portion correspondingly provided for the second pixel circuit are arranged in a mirror image along the first virtual line. In the pixel circuit group, the first sub-portion and the second sub-portion correspondingly provided for the third pixel circuit and the first sub-portion and the second sub-portion correspondingly provided for the adjacent first pixel circuit or the second pixel circuit are arranged in a mirror image along the second direction.

42. The display panel according to claim 39, wherein The second sub-power supply voltage line further includes a second-two power supply voltage line. The second-two power supply voltage line, the second-one power supply voltage line, and the first sub-power supply voltage line are arranged on different layers from each other, and the second-two power supply voltage line is electrically connected to the second-one power supply voltage line. The pixel circuit includes a driving transistor and a storage capacitor. The second-two power supply voltage line includes a plurality of third sub-portions arranged along the first direction and connected in sequence. The third sub-portions are the first electrodes of the storage capacitor, and the second electrode of the storage capacitor is electrically connected to the gate of the driving transistor.

43. The display panel according to claim 42, wherein In a direction perpendicular to the plane of the substrate, the second-two power supply voltage line and the second-one power supply voltage line at least partially overlap. The second-secondary power supply voltage line is electrically connected to the second-primary power supply voltage line through a first via, and the first via overlaps with the first virtual line.

44. The display panel according to claim 42, wherein The second power supply voltage line further includes a second-tertiary power supply voltage line. The second-tertiary power supply voltage line, the second-secondary power supply voltage line, the second-primary power supply voltage line, and the first power supply voltage line are arranged on different layers from each other, and the second-tertiary power supply voltage line is electrically connected to the second-primary power supply voltage line through the first extension portion.

45. The display panel according to claim 44, wherein, The second-secondary power supply voltage line is located on the first metal layer, the second-tertiary power supply voltage line is located on the second metal layer, the second-primary power supply voltage line is located on the third metal layer, the first power supply voltage line is located on the fourth metal layer, and the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer are arranged in a direction away from the substrate. In the pixel circuit group, the first pole of the first light-emitting control transistor of the first pixel circuit and the second pixel circuit is electrically connected to the first extension portion and the second-tertiary power supply voltage line, and the first pole of the first light-emitting control transistor of the third pixel circuit is electrically connected to the second-tertiary power supply voltage line.

46. The display panel according to claim 45, wherein The display panel includes a bias voltage line. The pixel circuit includes a driving transistor and a bias transistor, and the bias transistor is electrically connected between at least one of the first pole and the second pole of the driving transistor and the bias voltage line. A fifth metal layer is further provided between the second metal layer and the third metal layer. The fifth metal layer includes a first connection portion, and the bias transistor is electrically connected to the driving transistor through the first connection portion. The display panel includes a light-emitting element on a side of the pixel circuit away from the substrate. The light-emitting element includes an anode, a light-emitting layer, and a cathode arranged in a direction away from the substrate. The pixel circuit includes a second light-emitting control transistor, and the second light-emitting control transistor is electrically connected between the second pole of the driving transistor and the anode of the light-emitting element. The display panel includes a light-emitting control line. The light-emitting control line is electrically connected to the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor. The light-emitting control line is located on the sixth metal layer, and the sixth metal layer is on a side of the first metal layer close to the substrate. In a direction perpendicular to the plane of the substrate, the light-emitting control line, the second-tertiary power supply voltage line, and the first connection portion overlap with each other.

47. The display panel according to claim 35, characterized in that, The display panel includes a light-emitting element on a side of the pixel circuit away from the substrate. The light-emitting element includes an anode, a light-emitting layer, and a cathode arranged in a direction away from the substrate. The light-emitting element includes a green light-emitting element. In a direction perpendicular to the plane of the substrate, the anode of the green light-emitting element at least partially overlaps with the first power supply voltage line, and the anode of the green light-emitting element does not overlap with the data line and the second auxiliary trace.

48. The display panel according to claim 47, wherein, The light-emitting element includes a red light-emitting element. In a direction perpendicular to the plane of the substrate, the anode of the red light-emitting element at least partially overlaps with the first sub-power voltage line, and the anode of the red light-emitting element does not overlap with the data line and the second auxiliary trace.

49. The display panel according to claim 47 or 48, characterized in that, The light-emitting element includes a blue light-emitting element. In a direction perpendicular to the plane of the substrate, the anode of the blue light-emitting element overlaps with at least one of the data line and the second auxiliary trace.

50. The display panel according to claim 47, wherein In a direction perpendicular to the plane of the substrate, the proportion of the area where the anode of the green light-emitting element overlaps with the first sub-power voltage line in the total area of the anode of the green light-emitting element is not less than 70%.

51. The display panel according to claim 1, wherein, The display panel includes a first power voltage line. The pixel circuit includes a first light-emitting control transistor, a driving transistor, and a storage capacitor. The first light-emitting control transistor is electrically connected between the first power voltage line and the first pole of the driving transistor, and the storage capacitor is electrically connected between the first power voltage line and the gate of the driving transistor. The first power voltage line includes first sub-power voltage lines extending along the second direction and arranged along the first direction. The number of columns of the array formed by the plurality of pixel circuit groups is N10, and the number of the first sub-power voltage lines is N14, where N14 ≤ N10, and both N10 and N14 are positive integers.

52. The display panel according to claim 51, wherein One first sub-power voltage line is correspondingly provided for one column of the pixel circuit groups. In a direction perpendicular to the plane of the substrate, the first sub-power voltage line at least partially overlaps with the third pixel circuit column.

53. The display panel according to claim 52, characterized in that, The first power voltage line further includes second sub-power voltage lines extending along the first direction and arranged along the second direction. The second sub-power voltage lines are provided on a different layer from the first sub-power voltage lines, and the second sub-power voltage lines are electrically connected to the first sub-power voltage lines.

54. The display panel according to claim 53, wherein The second sub-power voltage line includes a second-one sub-power voltage line. The second-one sub-power voltage line is provided on a different layer from the first sub-power voltage line, and the second sub-power voltage line is electrically connected to the first sub-power voltage line. The second-one sub-power voltage line includes a first main portion and a first extension portion extending from the first main portion along the second direction. In the pixel circuit group, the first pixel circuit, the second pixel circuit, and the third pixel circuit are arranged along the first direction, and the first pixel circuit and the second pixel circuit are mirror-symmetrical along a first virtual line. The first virtual line extends along the second direction, and the first extension portion overlaps with the first virtual line. The first extension portion is electrically connected to the first pole of the first light-emitting control transistor, and the second pole of the first light-emitting control transistor is electrically connected to the first pole of the driving transistor.

55. The display panel according to claim 54, wherein, The first main portion includes a plurality of first sub-portions and a plurality of second sub-portions. Along the second direction, the width of the second sub-portions is greater than the width of the first sub-portions. One first sub-portion and one second sub-portion are correspondingly provided for one pixel circuit. The display panel includes a second reference voltage line. The pixel circuit includes a gate reset transistor and a threshold compensation transistor. The gate reset transistor is electrically connected between the second reference voltage line and the gate of the driving transistor. The threshold compensation transistor is electrically connected between the gate of the driving transistor and the second pole. In a direction perpendicular to the plane of the substrate, the second sub - part covers at least one of the gate reset transistor and the threshold compensation transistor.

56. The display panel according to claim 55, characterized in that, In the pixel circuit group, the first sub - part and the second sub - part corresponding to the first pixel circuit and the first sub - part and the second sub - part corresponding to the second pixel circuit are arranged in a mirror image along the first virtual line. In the pixel circuit group, the first sub - part and the second sub - part corresponding to the third pixel circuit and the first sub - part and the second sub - part corresponding to the adjacent first pixel circuit or the second pixel circuit are arranged in a mirror image along the second direction.

57. The display panel according to claim 54, wherein The second sub - power supply voltage line further includes a second - two sub - power supply voltage line. The second - two sub - power supply voltage line, the second - one sub - power supply voltage line, and the first sub - power supply voltage line are arranged in different layers from each other, and the second - two sub - power supply voltage line is electrically connected to the second - one sub - power supply voltage line. The second - two sub - power supply voltage line includes a plurality of third sub - parts arranged in the first direction and connected in sequence. The third sub - part is the first electrode plate of the storage capacitor, and the second electrode plate of the storage capacitor is electrically connected to the gate of the driving transistor.

58. The display panel according to claim 57, characterized in that, In a direction perpendicular to the plane of the substrate, the second - two sub - power supply voltage line and the second - one sub - power supply voltage line overlap at least partially. The second - two sub - power supply voltage line and the second - one sub - power supply voltage line are electrically connected through a first via, and the first via overlaps with the first virtual line.

59. The display panel according to claim 57, wherein The second sub - power supply voltage line further includes a second - three sub - power supply voltage line. The second - three sub - power supply voltage line, the second - two sub - power supply voltage line, the second - one sub - power supply voltage line, and the first sub - power supply voltage line are arranged in different layers from each other, and the second - three sub - power supply voltage line is electrically connected to the second - one sub - power supply voltage line through the first extension part.

60. The display panel according to claim 59, wherein, The second - two sub - power supply voltage line is located on the first metal layer, the second - three sub - power supply voltage line is located on the second metal layer, the second - one sub - power supply voltage line is located on the third metal layer, the first sub - power supply voltage line is located on the fourth metal layer. The first metal layer, the second metal layer, the third metal layer, and the fourth metal layer are arranged in a direction away from the substrate. In the pixel circuit group, the first pole of the first light - emitting control transistor of the first pixel circuit and the second pixel circuit is electrically connected to the first extension part and the second - three sub - power supply voltage line, and the first pole of the first light - emitting control transistor of the third pixel circuit is electrically connected to the second - three sub - power supply voltage line.

61. The display panel according to claim 60, wherein, The display panel includes bias voltage lines. The pixel circuit includes a driving transistor and a bias transistor. The bias transistor is electrically connected between at least one of a first pole and a second pole of the driving transistor and the bias voltage line; A fifth metal layer is further disposed between the second metal layer and the third metal layer. The fifth metal layer includes a first connection portion. The bias transistor is electrically connected to the driving transistor through the first connection portion; The display panel includes a light-emitting element on a side of the pixel circuit facing away from the substrate. The light-emitting element includes an anode, a light-emitting layer, and a cathode disposed in a direction away from the substrate. The pixel circuit includes a second light-emitting control transistor. The second light-emitting control transistor is electrically connected between the second pole of the driving transistor and the anode of the light-emitting element; The display panel includes a light-emitting control line. The light-emitting control line is electrically connected to the gates of the first light-emitting control transistor and the second light-emitting control transistor. The light-emitting control line is located in a sixth metal layer. The sixth metal layer is located on a side of the first metal layer close to the substrate; In a direction perpendicular to the plane of the substrate, the light-emitting control line, the second-third sub-power voltage signal line, and the first connection portion overlap each other.

62. The display panel according to claim 52, wherein, The pixel circuits are arranged in an array along the first direction and the second direction. One column of the pixel circuits is correspondingly electrically connected to one data line; The display panel includes a light-emitting element on a side of the pixel circuit facing away from the substrate. The light-emitting element includes an anode, a light-emitting layer, and a cathode disposed in a direction away from the substrate; The light-emitting element includes a green light-emitting element. In a direction perpendicular to the plane of the substrate, the anode of the green light-emitting element at least partially overlaps with the first sub-power voltage line, and the anode of the green light-emitting element does not overlap with the data line.

63. The display panel according to claim 62, characterized in that, The light-emitting element includes a red light-emitting element. In a direction perpendicular to the plane of the substrate, the anode of the red light-emitting element at least partially overlaps with the first sub-power voltage line, and the anode of the red light-emitting element does not overlap with the data line.

64. The display panel according to claim 62 or 63, characterized in that, The light-emitting element includes a blue light-emitting element. In a direction perpendicular to the plane of the substrate, the anode of the blue light-emitting element overlaps with the data line.

65. The display panel according to claim 62, characterized in that, In a direction perpendicular to the plane of the substrate, the proportion of the overlapping area between the anode of the green light-emitting element and the first sub-power voltage line in the total area of the anode of the green light-emitting element is not less than 70%; 66. The display panel according to claim 1, wherein The display panel includes data lines. The pixel circuit includes a data writing transistor and a driving transistor. The data writing transistor is electrically connected between the data line and the first pole of the driving transistor; The display panel includes a first reference voltage line. The pixel circuit includes a gate reset transistor. The gate reset transistor is electrically connected between the first reference voltage line and the gate of the driving transistor; The pixel circuit includes a threshold compensation transistor, and the threshold compensation transistor is electrically connected between the gate electrode and the second electrode of the driving transistor; The gate reset transistor includes a first oxide region, the threshold compensation transistor includes a second oxide region, and the first oxide region and the second oxide region are located in an oxide layer; The first oxide region and the second oxide region are connected in the same layer, a connection region between the first oxide region and the second oxide region is electrically connected to the gate of the driving transistor through a second connection portion, and a protrusion is provided in the connection region between the first oxide region and the second oxide region; The display panel comprises a second scan line, wherein the second scan line is electrically connected to the gate of the data writing transistor; In a direction perpendicular to the plane where the substrate is located, the protruding portion at least partially overlaps with the second scanning line, and the protruding portion at least partially overlaps with the second connecting portion.

67. A display panel, characterized in that, include: substrate; A plurality of pixel circuit groups are located on one side of the substrate, and the plurality of pixel circuit groups are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect; The pixel circuit group includes three pixel circuits arranged along the first direction, namely a first pixel circuit, a second pixel circuit and a third pixel circuit, the first pixel circuit and the second pixel circuit are mirror-symmetrical along the second direction, and the third pixel circuit is not mirror-symmetrical with the pixel circuit adjacent to the first direction; The display panel includes a plurality of light-emitting element groups, wherein the light-emitting element groups are located on a side of the pixel circuit group away from the substrate, the light-emitting element groups include three light-emitting elements with different luminous colors, namely a first light-emitting element, a second light-emitting element and a third light-emitting element, the first pixel circuit is electrically connected to the first light-emitting element, the second pixel circuit is electrically connected to the second light-emitting element, and the third pixel circuit is electrically connected to the third light-emitting element.

68. The display panel according to claim 67, wherein, In the pixel circuit group, the first pixel circuit and the second pixel circuit are adjacently arranged along the first direction, and the third pixel circuit is adjacently arranged to the first pixel circuit or the second pixel circuit along the first direction.

69. The display panel according to claim 67, wherein The light emitting element groups are arranged in an array along the first direction and the second direction; Among the three light-emitting elements of one light-emitting element group, two are light-emitting elements of the first color and light-emitting elements of the second color, and the other is a light-emitting element of the third color; Wherein, the first color light emitting elements and the second color light emitting elements are alternately arranged along the second direction; The third color light emitting elements are arranged along the first direction relative to the first color light emitting elements and the second color light emitting elements.

70. The display panel according to claim 69, characterized in that, For two adjacent columns of light emitting element groups along the first direction, the light emitting element group in the i-th row and the light emitting element group in the i+1-th row in one column of the light emitting element groups constitute a pixel group, and the light emitting element group in the i+1-th row and the light emitting element group in the i+2-th row in the other column of the light emitting element groups constitute a pixel group, where i is a positive integer; The first color light-emitting element, the second color light-emitting element, and the third color light-emitting element each include: an anode; a pixel defining layer located on a side of the anode facing away from the substrate; a light-emitting layer covering an opening, the opening being provided in the pixel defining layer and defining a light-emitting region of the color light-emitting element; and a cathode located on a side of the light-emitting layer facing away from the substrate. For two of the light-emitting element groups of a pixel group, the distance in the second direction between the geometric centers of the light-emitting regions of the first color light-emitting elements in one of the light-emitting element groups and the geometric centers of the light-emitting regions of the third color light-emitting elements is greater than the distance in the second direction between the geometric centers of the light-emitting regions of the first color light-emitting elements in the other light-emitting element group and the geometric centers of the light-emitting regions of the third color light-emitting elements.

71. The display panel according to claim 70, wherein, In a column of the light-emitting element groups, the distance in the second direction between the geometric centers of the light-emitting regions of two of the third color light-emitting elements within a pixel group is less than the distance in the second direction between the geometric centers of the light-emitting regions of the third color light-emitting elements in two adjacent pixel groups.

72. The display panel according to claim 69, wherein, The first color light-emitting element is one of a red light-emitting element and a green light-emitting element, the second color light-emitting element is the other of the red light-emitting element and the green light-emitting element, and the third color light-emitting element is a blue light-emitting element.

73. The display panel according to claim 67, wherein The display panel includes a first reference voltage line, the light-emitting element includes an anode, a light-emitting layer, and a cathode provided in a direction away from the substrate, and the pixel circuit includes an anode reset transistor, the anode reset transistor being electrically connected between the first reference voltage line and the anode of the light-emitting element. The first reference voltage line includes first sub-reference voltage lines extending in the first direction and arranged in the second direction, and second sub-reference voltage lines extending in the second direction and arranged in the first direction, the first sub-reference voltage lines and the second sub-reference voltage lines being provided in different layers and electrically connected to each other. The first pixel circuits are arranged in a first pixel circuit column in the second direction, the second pixel circuits are arranged in a second pixel circuit column in the second direction, and the third pixel circuits are arranged in a third pixel circuit column in the second direction. In a direction perpendicular to the plane of the substrate, the second sub-reference voltage line is correspondingly provided with the first pixel circuit column or the second pixel circuit column in a column of the pixel circuit groups.

74. The display panel according to claim 67, wherein, The display panel includes a bias voltage line, the pixel circuit includes a driving transistor and a bias transistor, the bias transistor being electrically connected between at least one of a first pole and a second pole of the driving transistor and the bias voltage line. The bias voltage line includes a first sub-bias voltage line extending along the first direction and arranged along the second direction, and a second sub-bias voltage line extending along the second direction and arranged along the first direction. The first sub-bias voltage line and the second sub-bias voltage line are disposed in different layers and are electrically connected; The first pixel circuits are arranged in a first pixel circuit column along the second direction, the second pixel circuits are arranged in a second pixel circuit column along the second direction, and the third pixel circuits are arranged in a third pixel circuit column along the second direction; In a direction perpendicular to the plane of the substrate, the second sub-bias voltage line is correspondingly disposed with the first pixel circuit column or the second pixel circuit column in a column of the pixel circuit group; 75. The display panel according to claim 67, wherein The display panel includes a first reference voltage line and a bias voltage line. The light-emitting element includes an anode, a light-emitting layer, and a cathode disposed in a direction away from the substrate. The pixel circuit includes an anode reset transistor, a driving transistor, and a bias transistor. The anode reset transistor is electrically connected between the first reference voltage line and the anode of the light-emitting element. The bias transistor is electrically connected between at least one of the first pole and the second pole of the driving transistor and the bias voltage line; The first reference voltage line includes a first sub-reference voltage line extending along the first direction and arranged along the second direction, and a second sub-reference voltage line extending along the second direction and arranged along the first direction. The first sub-reference voltage line and the second sub-reference voltage line are disposed in different layers and are electrically connected; The bias voltage line includes a first sub-bias voltage line extending along the first direction and arranged along the second direction, and a second sub-bias voltage line extending along the second direction and arranged along the first direction. The first sub-bias voltage line and the second sub-bias voltage line are disposed in different layers and are electrically connected; The first pixel circuits are arranged in a first pixel circuit column along the second direction, the second pixel circuits are arranged in a second pixel circuit column along the second direction, and the third pixel circuits are arranged in a third pixel circuit column along the second direction; In a direction perpendicular to the plane of the substrate, the second sub-reference voltage line is correspondingly disposed with one of the first pixel circuit column and the second pixel circuit column in a column of the pixel circuit group, and the second sub-bias voltage line is correspondingly disposed with the other of the first pixel circuit column and the second pixel circuit column in a column of the pixel circuit group; 76. The display panel according to claim 75, wherein The display panel includes a second reference voltage line. The pixel circuit includes a gate reset transistor. The gate reset transistor is electrically connected between the second reference voltage line and the gate of the driving transistor; The second reference voltage line includes a third sub-reference voltage line extending along the first direction and arranged along the second direction, and a fourth sub-reference voltage line extending along the second direction and arranged along the first direction. The third sub-reference voltage line and the fourth sub-reference voltage line are disposed on different layers and are electrically connected; The first pixel circuits are arranged in a first pixel circuit column along the second direction, the second pixel circuits are arranged in a second pixel circuit column along the second direction, and the third pixel circuits are arranged in a third pixel circuit column along the second direction; In two adjacent columns of the pixel circuit groups, the second sub-reference voltage line is correspondingly provided for the first pixel circuit column in one column of the pixel circuit groups, the second sub-bias voltage line is correspondingly provided for the second pixel circuit column, the second sub-reference voltage line is correspondingly provided for the first pixel circuit column in the other column of the pixel circuit groups, and the fourth sub-reference voltage line is correspondingly provided for the second pixel circuit column; Alternatively, in two adjacent columns of the pixel circuit groups, the second sub-bias voltage line is correspondingly provided for the first pixel circuit column in one column of the pixel circuit groups, the second sub-reference voltage line is correspondingly provided for the second pixel circuit column, the fourth sub-reference voltage line is correspondingly provided for the first pixel circuit column in the other column of the pixel circuit groups, and the second sub-reference voltage line is correspondingly provided for the second pixel circuit column.

77. The display panel according to claim 67, wherein The display panel includes a display area and a fan-out area located on one side of the display area along the second direction. The pixel circuits are located in the display area and are arranged in an array along the first direction and the second direction. One column of the pixel circuits is correspondingly electrically connected to one data line; The display area includes a first display area and a second display area located on at least one side of the first display area along the first direction; the fan-out area includes a plurality of fan-out traces, and the data line is electrically connected to the fan-out traces; the display area includes a plurality of first auxiliary traces extending along the first direction and a plurality of second auxiliary traces extending along the second direction. At least part of the first auxiliary traces includes a first connection segment, and at least part of the second auxiliary traces includes a second connection segment. The data lines in the second display area are electrically connected to the fan-out traces through the first connection segment and the second connection segment; The first pixel circuits are arranged in a first pixel circuit column along the second direction, the second pixel circuits are arranged in a second pixel circuit column along the second direction, the third pixel circuits are arranged in a third pixel circuit column along the second direction. The first pixel circuit column and the second pixel circuit column are mirror-symmetrical along a first virtual line, and the first virtual line extends along the second direction; The data line includes a first data line, a second data line, and a third data line that extend along the second direction and are arranged along the first direction. The first pixel circuit column is electrically connected to the first data line, the second pixel circuit column is electrically connected to the second data line, and the third pixel circuit column is electrically connected to the third data line. The first data line and the second data line are mirror-symmetrical along the first virtual line. In a direction perpendicular to the plane of the substrate, the third data line overlaps with the third pixel circuit column. Two of the second auxiliary traces are correspondingly provided for one column of the pixel circuit groups. In a direction perpendicular to the plane of the substrate, among the two second auxiliary traces correspondingly provided for one column of the pixel circuit groups, one second auxiliary trace overlaps with one of the first pixel circuit column and the second pixel circuit column, and the other second auxiliary trace overlaps with the other of the first pixel circuit column and the second pixel circuit column.

78. The display panel according to claim 67, wherein The display panel includes a first power supply voltage line. The pixel circuit includes a first light-emitting control transistor, a driving transistor, and a storage capacitor. The first light-emitting control transistor is electrically connected between the first power supply voltage line and the first pole of the driving transistor, and the storage capacitor is electrically connected between the first power supply voltage line and the gate of the driving transistor. The first power supply voltage line includes a first sub-power supply voltage line that extends along the second direction and is arranged along the first direction. One first sub-power supply voltage line is correspondingly provided for one column of the pixel circuit groups. In a direction perpendicular to the plane of the substrate, the first sub-power supply voltage line at least partially overlaps with the third pixel circuit column.

79. The display panel according to claim 78, wherein The first power supply voltage line further includes a second sub-power supply voltage line that extends along the first direction and is arranged along the second direction. The second sub-power supply voltage line is provided on a different layer from the first sub-power supply voltage line, and the second sub-power supply voltage line is electrically connected to the first sub-power supply voltage line.

80. The display panel according to claim 78, wherein, The pixel circuits are arranged in an array along the first direction and the second direction. One data line is correspondingly electrically connected to one column of the pixel circuits. The light-emitting element includes an anode, a light-emitting layer, and a cathode that are arranged in a direction away from the substrate. The light-emitting element includes a green light-emitting element. In a direction perpendicular to the plane of the substrate, the anode of the green light-emitting element at least partially overlaps with the first sub-power supply voltage line, and the anode of the green light-emitting element does not overlap with the data line.

81. A display device, characterized in that, Including the display panel according to any one of claims 1-66, or including the display panel according to any one of claims 67-80.

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