Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and is used for optimizing the characteristics of some metal structures in the display panel. The display panel comprises a substrate; the pixel circuit is positioned on one side of the substrate; the first planarization layer is positioned on one side, far away from the substrate, of the pixel circuit; the first power supply metal is located on the side, away from the substrate, of the first planarization layer and electrically connected with the pixel circuit, the first power supply metal comprises a first sub-part and a second sub-part, the first sub-part comprises a first hole, the second sub-part comprises a second hole, and the area of the first hole is larger than that of the second hole; and the first metal is electrically connected with the first sub-part through at least two connecting via holes.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The display panel includes an organic film layer. At present, gas is generated in the manufacturing process of the organic film layer. To prevent gas accumulation, some exhaust holes are usually opened in the metal layer above the organic film layer. However, the provision of the exhaust holes may affect the performance of the metal, thereby reducing the reliability of the pixel circuit. Summary of the invention

[0003] Embodiments of the present invention provide a display panel and a display device, which are used to optimize the characteristics of some metal structures in the display panel.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0005] substrate;

[0006] A pixel circuit located on one side of the substrate;

[0007] A first planarization layer located on a side of the pixel circuit away from the substrate;

[0008] a first power metal located on a side of the first planarization layer away from the substrate, the first power metal being electrically connected to the pixel circuit, the first power metal comprising a first sub-portion and a second sub-portion, the first sub-portion comprising a first hole, the second sub-portion comprising a second hole, and an area of ​​the first hole being greater than an area of ​​the second hole;

[0009] A first metal, wherein the first metal is electrically connected to the first sub-section through at least two connecting vias.

[0010] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0011] The technical solution provided by the embodiment of the present invention has the following beneficial effects:

[0012] Different from the power signal lines in the traditional panel structure, in order to reduce the voltage drop of the power signal, the embodiment of the present invention designs the first power metal used to transmit the power signal as a large piece of metal on the entire surface, and in order to avoid conflict with other wiring, it is set above the first planarization layer.

[0013] The first planarization layer is an organic film layer. As mentioned in the background technology, some gas is generated during the manufacturing process of the organic film layer. Therefore, the embodiment of the present invention also provides some exhaust holes on the first power metal to exhaust the gas and avoid gas accumulation and pressure to cause film peeling.

[0014] Considering the limitation of the array process, the metal area should not be too large. Therefore, when designing the exhaust holes in the first power metal, the embodiment of the present invention also provides some large holes (first holes) and some small holes (second holes). Large areas of metal are prone to stress and deformation. The presence of large holes provides a certain space, so that the metal has a certain expansion and contraction room during the process, reducing the degree of deformation. However, the inventors have found that although designing large holes in the first power metal can overcome some process limitations, it will cause the equivalent square resistance of the first power metal at the large hole position to be significantly larger, thereby causing the problem of uneven voltage drop of the first power metal.

[0015] In this regard, the present application proposes that a first metal can be further added, and the first metal can be electrically connected to a first sub-portion with a hole in the first power metal through at least two connecting vias. In this way, the first metal can be used as a supplementary metal to form a parallel relationship with the first sub-portion, thereby reducing the equivalent square resistance of the first power metal at the large hole position and improving the overall voltage drop uniformity of the first power metal.

[0016] In summary, based on the technical solution provided by the embodiment of the present invention, the first power metal can simultaneously achieve multiple effects such as exhaust, overcome process limitations, and improve voltage drop uniformity. The film layer characteristics of the display panel and the reliability of the pixel circuit are better, thereby effectively improving the display uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0019] Figure 2 for Figure 1 Cross-sectional view along the A1-A2 direction;

[0020] Figure 3 Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0021] Figure 4 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0022] Figure 5 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0023] Figure 6 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0024] Figure 7 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0025] Figure 8 for Figure 7 A schematic diagram of the structure of the corresponding first power metal and the first metal;

[0026] Fig. 9 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0027] Fig.10 for Fig. 9 A schematic structural diagram of the corresponding first power metal;

[0028] Fig.11 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

[0029] Fig.12 A schematic diagram of the structure of the first power metal and the second power metal provided in an embodiment of the present invention;

[0030] Fig.13 for Fig.12 A schematic diagram of the structure of the first power metal;

[0031] Fig.14 for Fig.12 A schematic diagram of the structure of the second power metal;

[0032] Fig.15 A schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the present invention;

[0033] Fig.16 A schematic diagram of a film layer structure of a pixel circuit provided by an embodiment of the present invention;

[0034] Fig.17 A schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention;

[0035] Fig.18 A schematic diagram of the structure of a display device provided by an embodiment of the present invention;

[0036] Fig.19A schematic diagram of the structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0040] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0041] An embodiment of the present invention provides a display panel, such as Figure 1 and Figure 2 As shown, Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 2 for Figure 1 In the cross-sectional view along the A1 - A2 direction, the display panel includes a substrate 1 , a pixel circuit 2 , a first planarization layer 3 , a first power metal 4 and a first metal 5 .

[0042] Among them, the pixel circuit 2 is located on one side of the substrate 1. The first planarization layer 3 is located on the side of the pixel circuit 2 away from the substrate 1. The first planarization layer 3 is an organic film layer, which is used to improve the flatness of the film layer. The first power metal 4 is located on the side of the first planarization layer 3 away from the substrate 1. The first power metal 4 is electrically connected to the pixel circuit 2 and is used to provide a power signal to the pixel circuit 2. The first power metal 4 includes a first sub-section 6 and a second sub-section 7. The first sub-section 6 includes a first hole 8, and the second sub-section 7 includes a second hole 9. The area of ​​the first hole 8 is greater than the area of ​​the second hole 9. In addition, the first metal 5 is electrically connected to the first sub-section 6 through at least two connecting vias 10.

[0043] Different from the power signal lines in the traditional panel structure, in order to reduce the voltage drop of the power signal, the embodiment of the present invention designs the first power metal 4 used to transmit the power signal as a large piece of metal on the entire surface, and in order to avoid conflict with other wiring, it is set above the first planarization layer 3.

[0044] The first planarization layer 3 is an organic film layer. As mentioned in the background technology, some gas is generated during the manufacturing process of the organic film layer. Therefore, the embodiment of the present invention also provides some exhaust holes on the first power metal 4 to exhaust the gas and avoid gas accumulation and pressure to cause film peeling.

[0045] Considering the limitation of the array process, the metal area should not be too large. Therefore, in the embodiment of the present invention, when designing the exhaust holes in the first power metal 4, some large holes (first holes 8) and some small holes (second holes 9) are set at the same time. Large-area metal is prone to stress and deformation. The presence of large holes provides a certain space, so that the metal has a certain expansion and contraction room during the process, reducing the degree of deformation. However, the inventors have found that although designing large holes in the first power metal 4 can overcome some process limitations, it will cause the equivalent square resistance of the first power metal 4 at the large hole position to be significantly larger, thereby causing the problem of uneven voltage drop of the first power metal 4.

[0046] In this regard, the present application proposes that a first metal 5 can be further added, and the first metal 5 can be electrically connected to a first sub-portion 6 with a hole in the first power metal 4 through at least two connecting vias 10. In this way, the first metal 5 can be used as a supplementary metal to form a parallel relationship with the first sub-portion 6, thereby reducing the equivalent square resistance of the first power metal 4 at the large hole position and improving the overall voltage drop uniformity of the first power metal 4.

[0047] In summary, based on the technical solution provided by the embodiment of the present invention, the first power metal 4 can simultaneously achieve multiple effects such as exhaust, overcome process limitations, and improve voltage drop uniformity. The film layer characteristics of the display panel and the reliability of the pixel circuit 2 are both better, thereby effectively improving display uniformity.

[0048] In a possible implementation, Figure 3 and Figure 4 As shown, Figure 3 Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 4 Another structural schematic diagram of a display panel provided in an embodiment of the present invention, the display panel includes a circuit area 11 and a spacing area 12 alternately arranged along a first direction x, the circuit area 11 includes a plurality of circuit units 13 arranged along a second direction y, the circuit unit 13 includes a plurality of pixel circuits 2 arranged along the first direction x, and the first direction x intersects with the second direction y.

[0049] For example, the pixel circuit 2 includes a first pixel circuit electrically connected to a red light emitting element, a second pixel circuit electrically connected to a green light emitting element, and a third pixel circuit electrically connected to a blue light emitting element. The circuit unit 13 includes a first pixel circuit, a second pixel circuit, and a third pixel circuit arranged along a first direction x.

[0050] In a direction perpendicular to the plane of the substrate 1 , the first sub-portion 6 overlaps with the spacer region 12 , and at least a portion of the second sub-portion 7 overlaps with the circuit region 11 . The first metal 5 is located in the spacer region 12 .

[0051] When designing the distribution positions of the large holes and small holes in the first power metal 4, considering that the voltage drop at the location of the large holes will be larger, it is possible to choose to distribute the large holes in the spacing area 12 outside the pixel circuit 2, and distribute the small holes in the circuit area 11 where the pixel circuit 2 is located, thereby reducing the voltage drop of the first power signal transmitted at the location of the pixel circuit 2, and reducing the impact of the signal voltage drop on the operation of the pixel circuit 2. Moreover, compared with the circuit area 11, there are fewer wirings in the spacing area 12, and the large holes in the first power metal 4 are located in the spacing area 12, and the corresponding first metal 5 will also be distributed in the spacing area 12, which can not only provide sufficient wiring space for the first metal 5, but also reduce the coupling between the first metal 5 and other wirings, and reduce the impact of parasitic capacitance.

[0052] In one possible implementation, see again Figure 3 and Figure 4 The spacer 12 includes a first spacer 14 and a second spacer 15. The first spacer 14 includes at least one of a shift register 16 and a drive signal line 17. The drive signal line 17 is electrically connected to the shift register 16 and may include a clock signal line, a frame start signal line, etc. The first metal 5 is located in the second spacer 15.

[0053] in, Figure 3 and Figure 4 The first spacing area 14 includes a driving signal line 17 as an example. In this structure, the shift register 16 can be located between two adjacent circuit units 13 in the circuit area 11. More specifically, the shift register 16 includes a plurality of shift units arranged in cascade, and a single shift unit can be divided into a plurality of circuit modules. In the embodiment of the present invention, the entire shift unit can be located only between two adjacent circuit units 13, or a plurality of circuit modules in the shift unit can be dispersedly located between different adjacent circuit units 13.

[0054] Of course, in other feasible structures of the present invention, when the first spacing area 14 has enough space, the shift register 16 and the driving signal line 17 may also be included at the same time.

[0055] The embodiment of the present invention arranges the shift register 16 and the driving signal line 17 in the display area, which can avoid these structures from occupying space in the frame area, thus better realizing a narrow frame or even a frameless design. In particular, when the display panel is used in a spliced ​​display device, the visual seams between the display panels can be effectively weakened, and the display effect of the spliced ​​display device can be optimized.

[0056] In the embodiment of the present invention, along the first direction x, the widths of the first spacing area 14 and the second spacing area 15 may be equal. That is, when the shift register 16 is arranged in the display area, when designing the spacing area 12, the width of the spacing area 12 needs to be enlarged to accommodate the shift register 16 and / or the drive signal line 17, and the second spacing area 15 can be understood as a spacing area 12 having the same width as the first spacing area 14 and without the shift register 16 and the drive signal line 17.

[0057] Since there is no need to set the shift register 16 and the drive signal line 17 in the second spacing area 15, a part of the blank space will be left. The first metal 5 is set in the second spacing area 15. Firstly, it can realize the rational use of space, and secondly, it can balance the routing distribution in different spacing areas 12, which helps to improve the reflection uniformity, etc.

[0058] In addition, it should be noted that, for a conventional display panel, all the spacing areas 12 may have the same width. In this case, part of the spacing area 12 is the first spacing area 14, and the rest is the second spacing area 15. For a borderless display panel, the spacing area 12 may include a third spacing area 18 with a smaller width in addition to the first spacing area 14 and the second spacing area 15. For example, Figure 5 and Figure 6 As shown, Figure 5 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Figure 6 Another structural schematic diagram of a display panel provided by an embodiment of the present invention, for some panel structures adopting a borderless design, the border may be narrowed by shrinking the pixel circuit 2. At this time, the width of the spacer 12 at the border position may be compressed, so that the spacer 12 also includes a third spacer 18, and the third spacer 18 is located on the side of the first spacer 14 and the second spacer 15 close to the outer edge of the display panel, and along the first direction x, the width of the third spacer 18 is smaller than the width of the first spacer 14 and the width of the second spacer 15. Because the width of the third spacer 18 is small, for this reason, the first power metal 4 can be provided with some small holes at the third spacer 18, so that the size of the exhaust hole better matches the width of the third spacer 18. That is, in the direction perpendicular to the plane where the substrate 1 is located, part of the first sub-portion 6 overlaps with the circuit area 11, and part of the first sub-portion 6 overlaps with the third spacer 18.

[0059] Furthermore, the pixel circuit 2 is electrically connected to the data line Data, the data line Data is located in the spacing area 12, and the first metal 5 is disposed in the same layer as the data line Data to simplify the patterning process.

[0060] More specifically, the display panel includes a first metal layer, a second metal layer located on a side of the first metal layer away from the substrate, a third metal layer located on a side of the second metal layer away from the substrate, and a fourth metal layer located on a side of the third metal layer away from the substrate. The first metal layer includes structures such as the gate and scan line of the transistor, the second metal layer includes structures such as the plate of the storage capacitor, the third metal layer includes structures such as the data line Data and the first metal 5, and the fourth metal layer includes structures such as the first power metal 4.

[0061] In a circuit structure of the pixel circuit 2, the Fig.15 and Fig.16 , the pixel circuit 2 includes a pulse amplitude modulation circuit PAM and a pulse width modulation circuit PWM, the pulse amplitude modulation circuit PAM is electrically connected to the first data line PAM_Data, and the pulse width modulation circuit PWM is electrically connected to the second data line PWM_Data. That is, the data line Data includes the first data line PAM_Data and the second data line PWM_Data. The first data line PAM_Data and the second data line PWM_Data connected to the pixel circuit 2 in the circuit area 11 can be respectively located in the spacing area 12 on both sides of the circuit area 11. In the second spacing area 15, the first metal 5 is located between the first data line PAM_Data and the second data line PWM_Data.

[0062] In a possible implementation, Figure 7 and Figure 8 As shown, Figure 7 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Figure 8 for Figure 7 Corresponding to the schematic structural diagram of the first power metal 4 and the first metal 5 , the first sub-portion 6 includes a plurality of metal portions 19 arranged along the second direction y, and first holes 8 are included between adjacent metal portions 19 .

[0063] The first metal 5 is a linear structure extending along the second direction y, and at least a portion of the metal portion 19 is electrically connected to the first metal 5 through the connecting via 10 .

[0064] The first metal 5 is a linear structure, and its metal area can be increased within a limited space. Therefore, when it is electrically connected to the metal part 19 through the connecting via 10, the voltage drop at the position of the first sub-part 6 can be reduced to a greater extent, thereby better improving the voltage drop uniformity of the first power metal 4.

[0065] Further, see again Figure 7 and Figure 8 In at least part of the spacing area 12, at least two first metals 5 are arranged along the first direction x, so as to avoid the single first metal 5 from being too large in area and reduce the deformation problem caused by stress in the array process.

[0066] In one possible implementation, see again Figure 7 and Figure 8 The metal portion 19 includes a third hole 20, the area of ​​the third hole 20 is smaller than the area of ​​the first hole 8, for example, the size of the third hole 20 is equal to the size of the second hole 9. In this way, the third hole 20 can be used to discharge the gas at the metal portion 19, further avoiding the accumulation of gas generated in the process of the first planarization layer 3 and causing film peeling.

[0067] In one possible implementation, see again Figure 7 and Figure 8 , the pixel circuit 2 is electrically connected to the first signal line 21, and the first signal line 21 extends along the first direction x. Exemplarily, in combination Figure 15 to Figure 17 The first signal line 21 may include a first scan line PWM_S1, a second scan line PWM_S2, a first light emission control signal line PWM_EM, a second light emission control signal line PAM_EM, etc. The first metal 5 includes a fourth hole 22, and in a direction perpendicular to the plane where the substrate 1 is located, at least part of the fourth hole 22 overlaps with the first signal line 21, thereby reducing the coupling between the first metal 5 and the first signal line 21 and reducing the influence of parasitic capacitance on the signal.

[0068] It should be noted that the area of ​​the fourth hole 22 at different positions may be different. For example, when multiple first signal lines 21 are closely arranged, if an independent fourth hole 22 is set for each of these first signal lines 21, the spacing between adjacent fourth holes 22 will be very small, and the requirements for process conditions will be very high. Therefore, in the embodiment of the present invention, a fourth hole 22 with a larger longitudinal dimension can be set for these closely arranged first signal lines 21 to reduce the process difficulty of the via.

[0069] In addition, it should be noted that in the embodiments of the present invention, see Figure 7 and Figure 8 There may be only one first hole 8 between two adjacent metal parts 19, or there may be at least two first holes 8 between two adjacent metal parts 19. Fig. 9 and Fig.10 As shown, Fig. 9 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig.10 for Fig. 9The schematic diagram of the structure of the corresponding first power metal includes two first holes 8 between two adjacent metal parts 19, and the two first holes 8 are arranged along the first direction x. One of the first holes 9 overlaps with the first data line PAM_Data connected to the pixel circuit 2 on one side, and the other first hole 9 overlaps with the second data line PWM_Data connected to the pixel circuit 2 on the other side. Of course, in other structures, three or more first holes 9 may be included between two adjacent metal parts 19, and the embodiment of the present invention will not be schematically described one by one.

[0070] In a possible implementation, Figure 11 to Figure 14 As shown, Fig.11 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention, Fig.12 A schematic diagram of the structure of the first power metal 4 and the second power metal 24 provided in an embodiment of the present invention, Fig.13 for Fig.12 The structural diagram of the first power metal 4, Fig.14 for Fig.12 The display panel further includes a second planarization layer 23, a second power metal 24 and a light emitting element 25.

[0071] Among them, the second planarization layer 23 is located on the side of the first power metal 4 away from the substrate 1, and the second planarization layer 23 is an organic film layer, which is used to improve the planarization of the film layer. The second power metal 24 is located on the side of the second planarization layer 23 away from the substrate 1, and is used to increase the negative power supply voltage. The light-emitting element 25 is located on the side of the second power metal 24 away from the substrate 1, and the light-emitting element 25 is electrically connected to the pixel circuit 2 and the second power metal 24 respectively. In an embodiment of the present invention, the light-emitting element 25 can be a light-emitting diode (Light-Emitting Diode), such as a mini LED, a micro LED, etc.

[0072] The second power metal 24 includes a third sub-portion 26 and a fourth sub-portion 27, the third sub-portion 26 includes a fifth hole 28, the fourth sub-portion 27 includes a sixth hole 29, and the area of ​​the fifth hole 28 is greater than the area of ​​the sixth hole 29. In a direction perpendicular to the plane where the substrate 1 is located, the fifth hole 28 overlaps with a portion of the first sub-portion 6 where the first hole 8 is not provided.

[0073] Similar to the first power metal 4, in order to reduce the voltage drop of the negative power signal, the second power metal 24 used to transmit the negative power signal is also designed as a large piece of metal on the entire surface. In addition, the embodiment of the present invention also provides some exhaust holes on the second power metal 24 to discharge the gas and avoid the accumulation of gas to generate pressure and cause peeling of the film layer. Furthermore, considering the limitations of the array process, the embodiment of the present invention also provides some large holes (fifth hole 28) and some small holes (sixth hole 29) when designing the exhaust holes in the second power metal 24.

[0074] In the above structure, the fifth hole 28 in the second power metal 24 overlaps with the portion of the first sub-portion 6 where the first hole 8 is not provided, that is, the large holes in the first power metal 4 and the large holes in the second power metal 24 are alternately arranged, so that large holes can be provided at more positions, so that more gas can be discharged through the exhaust holes, thereby improving the exhaust effect.

[0075] Furthermore, combined with Figure 11 to Figure 14 The light emitting element 25 includes a first electrode 30 and a second electrode 31 . The first electrode 30 is electrically connected to the first connecting portion 32 , and the second electrode 31 is electrically connected to the second connecting portion 33 .

[0076] The first connection portion 32 and the second connection portion 33 are both arranged in the same layer as the second power metal 24, the second connection portion 33 is connected to the second power metal 24, the second power metal 24 has a first hollow 34, and the first connection portion 32 is located in the first hollow 34. The first connection portion 32 is electrically connected to the pixel circuit 2 through the third connection portion 35, the third connection portion 35 is arranged in the same layer as the first power metal 4, the first power metal 4 has a second hollow 36, and the third connection portion 35 is located in the second hollow 36.

[0077] The above arrangement is to arrange two auxiliary connection metals between the first electrode 30 and the pixel circuit 2, thereby reducing the via depth and improving the connection reliability. Furthermore, the two auxiliary connection metals are respectively in the same layer as the first power metal 4 and the second power metal 24, thereby achieving reasonable utilization of the film layer and simplifying the process flow.

[0078] In addition, the portion of the first connecting portion 32 overlapping with the first electrode 30 may not be provided with an exhaust hole, and the portion of the second connecting portion 33 overlapping with the second electrode 31 may not be provided with an exhaust hole, so as to increase the contact area between the connecting portion and the electrode and improve the connection stability between the connecting portion and the light-emitting element 25.

[0079] In a possible implementation, Figure 15 to Figure 17 As shown, Fig.15 A schematic diagram of a circuit structure of a pixel circuit 2 provided in an embodiment of the present invention is shown in FIG. Fig.16A schematic diagram of a film structure of a pixel circuit 2 provided in an embodiment of the present invention, Fig.17 A schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention, the pixel circuit 2 includes a pulse amplitude modulation circuit PAM and a pulse width modulation circuit PWM, the pulse amplitude modulation circuit PAM is configured to control the amplitude of the driving current based on the applied pulse amplitude modulation data, and the pulse width modulation circuit PWM is configured to control the pulse width of the driving current.

[0080] The pulse amplitude modulation circuit PAM includes a first power supply terminal PAM_vdd, the first power supply terminal PAM_vdd receives a first power supply signal, and the first power supply metal 4 transmits the first power supply signal, that is, the first power supply metal 4 is electrically connected to the pulse amplitude modulation circuit PAM in the pixel circuit 2.

[0081] In the pixel circuit 2, the pulse amplitude modulation circuit PAM can provide more stable and accurate brightness control, which can be used to better present details and avoid problems such as uneven brightness or color distortion. Therefore, compared with the pulse width modulation circuit PWM, the reliability and stability of the pulse amplitude modulation circuit PAM will have a more significant impact on the display effect.

[0082] To this end, in an embodiment of the present invention, the first power metal 4 is set as a power structure connected to the pulse amplitude modulation circuit PAM, so that its overall characteristics can be used to achieve a smaller load and improve the accuracy of the power voltage received by the pulse amplitude modulation circuit PAM.

[0083] In addition, the pulse width modulation circuit PWM is electrically connected to the first power line PWM_vdd. Figure 3 and Figure 4 , the first power line PWM_vdd extends along the second direction y and is located in the spacing area 12, and, see Fig.16 The display panel may further include a second power line PWM_vdd', which extends along the first direction x and is electrically connected to the first power line PWM_vdd, so as to reduce the overall wiring load.

[0084] Below Fig.15 Taking the structure shown in FIG. 1 as an example, the circuit structure of the pixel circuit 2 is described.

[0085] The pixel circuit 2 includes a pulse amplitude modulation circuit PAM and a pulse width modulation circuit PWM.

[0086] Wherein, the pulse width modulation circuit PWM includes:

[0087] The first driving transistor M1.

[0088] The first gate reset transistor M2 has a gate electrically connected to the first scan line PWM_S1 , a first electrode electrically connected to the first reset signal line PWM_REF, and a second electrode electrically connected to the gate of the first driving transistor M1 .

[0089] The first data writing transistor M3 has a gate electrically connected to the second scanning line PWM_S2 , a first electrode electrically connected to the second data line PWM_Data, and a second electrode electrically connected to the first electrode of the first driving transistor M1 .

[0090] The first compensation transistor M4 has a gate electrically connected to the second scan line PWM_S2 , a first electrode electrically connected to the second electrode of the first driving transistor M1 , and a second electrode electrically connected to the gate of the first driving transistor M1 .

[0091] The first capacitor C1 has a first plate electrically connected to the sweep signal line SWEEP, and a second plate electrically connected to the gate of the first driving transistor M1.

[0092] The control transistor M5 has a gate electrically connected to the second scan line PWM_S2 , a first electrode electrically connected to the ground signal line GND, and a second electrode electrically connected to the first electrode of the first capacitor C1 .

[0093] The first light emitting control transistor M6 has a gate electrically connected to the first light emitting control signal line PWM_EM, a first electrode electrically connected to the first power line PWM_vdd, and a second electrode electrically connected to the first electrode of the first driving transistor M1.

[0094] The second light emitting control transistor M7 has a gate electrically connected to the first light emitting control signal line PWM_EM, and a first electrode electrically connected to the second electrode of the first driving transistor M1.

[0095] The pulse amplitude modulation circuit PAM includes:

[0096] The second capacitor C2, the first electrode of the second capacitor C2 is electrically connected to the second electrode of the second light emitting control transistor M7.

[0097] The second driving transistor M8 has a gate electrically connected to the second electrode plate of the second capacitor C2.

[0098] The second gate reset transistor M9 has a gate electrically connected to the third scan line PAM_S1 , a first electrode electrically connected to the second reset signal line PAM_REF, and a second electrode electrically connected to the gate of the second driving transistor M8 .

[0099] The second data writing transistor M10 has a gate electrically connected to the fourth scan line PAM_S2 , a first electrode electrically connected to the first data line PAM_Data, and a second electrode electrically connected to the first electrode of the second driving transistor M8 .

[0100] The second compensation transistor M11 has a gate electrically connected to the fourth scan line PAM_S2 , a first electrode electrically connected to the second electrode of the second driving transistor M8 , and a second electrode electrically connected to the gate of the second driving transistor M8 .

[0101] The anode reset transistor M12 has a gate electrically connected to the fourth scan line PAM_S2 , a first electrode electrically connected to the first power signal line PVEE, and a second electrode electrically connected to the light emitting element 25 .

[0102] The third light emitting control transistor M13 has a gate electrically connected to the second light emitting control transistor PAM_EM, a first electrode electrically connected to the first power metal 4 , and a second electrode electrically connected to the first electrode of the second driving transistor M8 .

[0103] The fourth light emitting control transistor M14 has a gate electrically connected to the second light emitting control transistor PAM_EM, a first electrode electrically connected to the second electrode of the second driving transistor M8 , and a second electrode electrically connected to the light emitting element 25 .

[0104] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.18 and Fig.19 As shown, Fig.18 A schematic diagram of the structure of a display device provided by an embodiment of the present invention is shown in FIG. Fig.19 1 is a schematic diagram of a structure of a display device provided by an embodiment of the present invention, and the display device includes the above-mentioned display panel 100. Of course, Fig.18 and Fig.19 The display device shown is for illustration only and may be, for example, Fig.18 Any electronic device with a display function, such as a mobile phone, tablet computer, laptop computer, e-book or television, or the like, can also be Fig.19 The outdoor large screen and other splicing display devices shown.

[0105] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; A pixel circuit located on one side of the substrate; A first planarization layer located on a side of the pixel circuit away from the substrate; a first power metal located on a side of the first planarization layer away from the substrate, the first power metal being electrically connected to the pixel circuit, the first power metal comprising a first sub-portion and a second sub-portion, the first sub-portion comprising a first hole, the second sub-portion comprising a second hole, and an area of ​​the first hole being greater than an area of ​​the second hole; A first metal is electrically connected to the first sub-section through at least two connecting vias.

2. The display panel according to claim 1, characterized in that: The display panel comprises a circuit area and a spacer area alternately arranged along a first direction, the circuit area comprises a plurality of circuit units arranged along a second direction, the circuit unit comprises a plurality of pixel circuits arranged along the first direction, and the first direction intersects with the second direction; In a direction perpendicular to the plane where the substrate is located, the first sub-portion overlaps with the spacing area, and at least a portion of the second sub-portion overlaps with the circuit area; The first metal is located in the spacer region.

3. The display panel according to claim 2, characterized in that: The spacing region includes a first spacing region and a second spacing region, wherein the first spacing region includes at least one of a shift register and a driving signal line, the driving signal line is electrically connected to the shift register, and the first metal is located in the second spacing region.

4. The display panel according to claim 3, characterized in that: The pixel circuit is electrically connected to a data line, the data line is located in the spacing area, and the first metal is arranged in the same layer as the data line.

5. The display panel according to claim 2, characterized in that: The first sub-section includes a plurality of metal sections arranged along the second direction, and the first holes are located between adjacent metal sections; The first metal is a linear structure extending along the second direction, and at least a portion of the metal portion is electrically connected to the first metal through the connecting via.

6. The display panel according to claim 5, characterized in that: In at least a portion of the spacer region, at least two first metals are arranged along the first direction.

7. The display panel according to claim 5, characterized in that: The metal part includes a third hole having an area smaller than an area of ​​the first hole.

8. The display panel according to claim 2, characterized in that: The pixel circuit is electrically connected to a first signal line, and the first signal line extends along the first direction; The first metal includes a fourth hole, and in a direction perpendicular to a plane where the substrate is located, at least a portion of the fourth hole overlaps with the first signal line.

9. The display panel according to claim 1, characterized in that: The display panel further includes: A second planarization layer located on a side of the first power metal away from the substrate; A second power metal located on a side of the second planarization layer away from the substrate; a light emitting element located on a side of the second power metal away from the substrate, the light emitting element being electrically connected to the pixel circuit and the second power metal respectively; The second power metal includes a third sub-section and a fourth sub-section, the third sub-section includes a fifth hole, the fourth sub-section includes a sixth hole, and the area of ​​the fifth hole is greater than the area of ​​the sixth hole; In a direction perpendicular to the plane where the substrate is located, the fifth hole overlaps with a portion of the first sub-portion where the first hole is not provided.

10. The display panel according to claim 9, characterized in that: The light emitting element comprises a first electrode and a second electrode, the first electrode is electrically connected to the first connecting portion, and the second electrode is electrically connected to the second connecting portion; Wherein, the first connection portion and the second connection portion are both arranged in the same layer as the second power metal, the second connection portion is connected to the second power metal, the second power metal has a first hollow, and the first connection portion is located in the first hollow; The first connection portion is electrically connected to the pixel circuit via a third connection portion, the third connection portion is disposed in the same layer as the first power metal, the first power metal has a second hollow, and the third connection portion is located in the second hollow.

11. The display panel according to claim 1, characterized in that: The pixel circuit includes a pulse amplitude modulation circuit and a pulse width modulation circuit, the pulse amplitude modulation circuit is configured to control the amplitude of the driving current based on the applied pulse amplitude modulation data, and the pulse width modulation circuit is configured to control the pulse width of the driving current; The pulse amplitude modulation circuit includes a first power supply terminal, the first power supply terminal receives a first power supply signal, and the first power supply metal transmits the first power supply signal.

12. A display device, characterized in that: It comprises the display panel as claimed in any one of claims 1 to 11.

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