Display device and method for manufacturing display device

Abstract

The present disclosure relates to a display device and a method for manufacturing the display device, the display device including: a first pixel electrode disposed on a substrate; a pixel defining layer disposed on the substrate and exposing the first pixel electrode; a first light emitting layer disposed on the first pixel electrode; a first common electrode disposed on the first light emitting layer; a first bank layer disposed on the pixel defining layer; a second bank layer disposed on the first bank layer and including a side surface protruding from a side surface of the first bank layer; and a third bank layer disposed on the second bank layer and including a side surface protruding from a side surface of the first bank layer, where the second and third bank layers each include a transparent conductive oxide (TCO), and the second bank layer further includes zinc (Zn).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0095133 filed in the Korean Intellectual Property Office on July 21, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0004] With the development of the information society, more and more requirements are put forward for display devices for displaying images in various ways. For example, display devices can be applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, and an organic light-emitting display device. Among the flat panel display devices, in the light-emitting display device, since each of the multiple pixels of the display panel includes a light-emitting element that can emit light by itself, it is possible to display an image without a backlight portion that provides light to the display panel.

[0005] Recently, a display device may be applied in a glasses-type device for providing virtual reality and augmented reality. In order to be applied in a glasses-type device, the display device needs to be implemented in a very small size (e.g., about 2 inches or less), or needs to have a high number of pixels per inch (PPI) to be implemented in a high resolution. For example, the display device may have about 1,000 pixels per inch (PPI) or more.

[0006] In this way, when a display device is implemented in a very small size or has a high PPI, it may be difficult to implement light-emitting elements separated (i.e., spaced apart from each other) for each emission area through a mask process because the area of ​​the emission area in which the light-emitting element can be set is reduced. Summary of the invention

[0007] Aspects of the present disclosure provide a display device capable of forming light emitting elements spaced apart from each other for each emission region without a mask process.

[0008] Aspects of the present disclosure provide a display device having high light efficiency.

[0009] Aspects of the present disclosure also provide a display device in which emission variation that may occur in each pixel due to damage to a bank structure in an etching process performed during a manufacturing process of the display device can be reduced.

[0010] However, aspects of the present disclosure may not be limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0011] According to one aspect of the present disclosure, a display device may include: a first pixel electrode, disposed on a substrate; a pixel defining layer, disposed on the substrate and exposing the first pixel electrode; a first light-emitting layer, disposed on the first pixel electrode; a first common electrode, disposed on the first light-emitting layer; a first embankment layer, disposed on the pixel defining layer; a second embankment layer, disposed on the first embankment layer and including a side surface protruding from a side surface of the first embankment layer; and a third embankment layer, disposed on the second embankment layer and including a side surface protruding from the side surface of the first embankment layer, wherein the second embankment layer and the third embankment layer each include a transparent conductive oxide (TCO), and the second embankment layer also includes zinc (Zn).

[0012] The third bank layer may further include hydrogen.

[0013] A ratio of zinc (Zn) in the second bank layer with respect to the total number of atoms may be in the range of about 5 at % to about 50 at %.

[0014] In a plan view, the side surface of the second bank layer and the side surface of the third bank layer may be aligned with each other.

[0015] The second bank layer and the third bank layer may be amorphous, and a combined visible light transmittance of the second bank layer and the third bank layer may be about 85% or more.

[0016] The third bank layer may include hydrogen and indium tin oxide (ITO).

[0017] The thickness of the third bank layer may be greater than that of the second bank layer.

[0018] The sum of the thickness of the second bank layer and the thickness of the third bank layer may be about to about within the range.

[0019] The first bank layer may include metal.

[0020] The first common electrode may be in contact with the first bank layer.

[0021] The thickness of the first bank layer may be about to about within the range.

[0022] The display device may also include: a first organic pattern, arranged on the third embankment layer, the first organic pattern and the first light-emitting layer may include the same material; and a first electrode pattern, arranged on the first organic pattern, the first electrode pattern and the first common electrode may include the same material, wherein the first light-emitting layer and the first organic pattern may be spaced apart from each other, and the first common electrode and the first electrode pattern may be spaced apart from each other.

[0023] According to one aspect of the present disclosure, a display device includes: a first pixel electrode, which is arranged on a substrate; a pixel defining layer, which is arranged on the substrate and exposes the first pixel electrode; a first light-emitting layer, which is arranged on the first pixel electrode; a first common electrode, which is arranged on the first light-emitting layer; a first embankment layer, which is arranged on the pixel defining layer; a second embankment layer, which is arranged on the first embankment layer and includes a side surface protruding from a side surface of the first embankment layer; and a third embankment layer, which is arranged on the second embankment layer and includes a side surface protruding from the side surface of the first embankment layer, wherein the thickness of the first embankment layer may be greater than the sum of the thickness of the second embankment layer and the thickness of the third embankment layer, and the thickness of the third embankment layer may be greater than the thickness of the second embankment layer.

[0024] The first bank layer may include an opaque metal, and the second and third bank layers may each include a transparent conductive oxide (TCO).

[0025] The thickness of the first bank layer may be greater than or equal to about three times the sum of the thickness of the second bank layer and the thickness of the third bank layer.

[0026] The display device may also include: a second pixel electrode, arranged on the substrate, and the second pixel electrode and the first pixel electrode may be spaced apart from each other; a second light-emitting layer, arranged on the second pixel electrode; a second common electrode, arranged on the second light-emitting layer, and the second common electrode and the first common electrode may be spaced apart from each other; a first inorganic layer, arranged on each of the first common electrode and the third embankment layer; and a second inorganic layer, arranged on each of the second common electrode and the third embankment layer, wherein the first inorganic layer and the second inorganic layer may be spaced apart from each other, a portion of the third embankment layer may be exposed in a separation space between the first inorganic layer and the second inorganic layer, and a thickness of the second embankment layer overlapping with the first inorganic layer and a thickness of the second embankment layer overlapping with the second inorganic layer may be equal.

[0027] According to one aspect of the present disclosure, a method for manufacturing a display device may include: forming a plurality of pixel electrodes spaced apart from each other on a substrate; forming a sacrificial layer on the plurality of pixel electrodes; forming a pixel defining material layer on the sacrificial layer; forming a first embankment material layer on the pixel defining material layer; forming a second embankment material layer on the first embankment material layer; forming a third embankment material layer on the second embankment material layer; etching the second embankment material layer and the third embankment material layer in an area overlapping with the plurality of pixel electrodes; etching the first embankment material layer in the area overlapping with the plurality of pixel electrodes; etching a side surface of the first embankment material layer to partially expose a bottom surface of the second embankment material layer; etching the pixel defining material layer; etching the sacrificial layer to expose the plurality of pixel electrodes; forming a first light-emitting layer on one pixel electrode among the plurality of pixel electrodes; forming a first common electrode on the first light-emitting layer; and forming a first inorganic material layer on the first common electrode.

[0028] The forming of the third bank material layer on the second bank material layer may include sputtering in a mixed gas atmosphere including hydrogen and argon, and the third bank material layer may include hydrogen and indium tin oxide.

[0029] The etching of the second embankment material layer and the third embankment material layer in the area overlapping with the multiple pixel electrodes may include exposing a portion of the first embankment material layer by removing the second embankment material layer and the third embankment material layer via a wet etching technique, and the etching of the first embankment material layer in the area overlapping with the multiple pixel electrodes may include removing the exposed portion of the first embankment material layer via a dry etching technique.

[0030] The forming of the first light emitting layer on the one pixel electrode among the plurality of pixel electrodes may include forming a first organic pattern material layer on the third bank material layer, the first organic pattern material layer being spaced apart from the first light emitting layer. The forming of the first common electrode on the first light emitting layer may include forming a first electrode pattern material layer on the first organic pattern material layer, the first electrode pattern material layer being spaced apart from the first common electrode, and the forming of the first inorganic material layer on the first common electrode may include forming the first inorganic material layer seamlessly connected to the first common electrode and the first electrode pattern material layer.

[0031] According to the display device and the method for manufacturing the display device according to the embodiment, the second bank layer and the third bank layer including the transparent material may be included, so that the pixel gap may be reduced and the light efficiency may be improved.

[0032] In addition, according to the display device and the method for manufacturing the display device according to the embodiment, the second bank layer of the bank structure may not be damaged during the manufacturing process, so that the tip may be prevented from bending. The brightness difference between the light emitting elements may be reduced by ensuring sufficient contact area between the common electrode and the bank structure.

[0033] However, the effects according to the embodiments of the present disclosure may not be limited to the effects exemplified above, and various other effects may be included herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0035] Figure 1 is a perspective view showing a display device according to an embodiment;

[0036] Figure 2 yes Figure 1 A schematic cross-sectional view of a display device viewed from the side;

[0037] Figure 3 is a plan view showing the arrangement of a light emitting element, a pixel defining layer, a trace pattern, and a third bank layer in a display region of a display device according to an embodiment;

[0038] Figure 4 FIG. 1 is a diagram showing a portion of a display device according to an embodiment. Figure 3 A schematic cross-sectional view taken along line BB';

[0039] Figure 5 It is shown Figure 4 An enlarged view of the first emission region (specifically, region A1);

[0040] Figure 6 is an enlarged view showing a first emission region (specifically, region A1) according to an embodiment;

[0041] Figure 7 is a schematic cross-sectional view of a case where the second bank layer includes an opaque metal;

[0042] Figure 8 is a flow chart showing a manufacturing process of a display device according to an embodiment; and

[0043] Figures 9 to 18 are detailed schematic cross-sectional views sequentially illustrating a manufacturing process of a display device according to an embodiment. DETAILED DESCRIPTION

[0044] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of the apparatus or method disclosed herein. It is obvious that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive, nor do they have to limit the present disclosure. For example, the specific shape, configuration and characteristics of the embodiment can be used or implemented in another embodiment.

[0045] Unless otherwise specified, the illustrated embodiments will be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0046] The use of cross hatching and / or shading is usually provided in the drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. In the case where the embodiments may be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or two processes described in succession may be performed in an order opposite to the described sequence. In addition, the same reference numerals and / or reference numerals represent the same elements.

[0047] In the case where an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or directly coupled to the other element or layer, or there may be intervening elements or layers. However, in the case where an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without intervening elements. In addition, the first direction DR1, the second direction DR2 and the third direction DR3 are not limited to three axes of a rectangular coordinate system such as an x-axis, a y-axis and a z-axis, and may be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2 and the third direction DR3 may be perpendicular to each other, or may represent different directions that may not be perpendicular to each other.

[0048] For the purpose of this disclosure, "at least one of A and B" may be interpreted as only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0049] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0050] For descriptive purposes, spatially relative terms such as "under," "below," "below," "down," "above," "up," "above (throughout)," "higher," and "side" (e.g., as in "sidewall") may be used herein and thereby describe the relationship of one element to another element as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, the spatially relative terms are intended to also cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, an element or feature described as "under" or "beneath" other elements or features would then be positioned as "above" the other elements or features. Thus, the term "under" can cover both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or oriented at other orientations), and therefore, the spatially relative terms used herein are interpreted accordingly.

[0051] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "one (kind / person)" and "the (said)" are also intended to include plural forms. In addition, in the case of using the terms "comprises, comprising" and / or "includes, including" in this specification, it is explained that there are stated features, wholes, steps, operations, elements, components and / or groups thereof, but it is not excluded that there are or add one or more other features, wholes, steps, operations, elements, components and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than degree terms, and are therefore used to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0052] Various embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the shapes of the diagrams due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the embodiments disclosed herein should not necessarily be construed as limited to the shapes of the particular zones shown, but rather include shape deviations due to, for example, manufacturing. In this manner, the zones shown in the drawings may be schematic in nature, and the shapes of these zones may not reflect the shapes of the actual zones of the device, and therefore may not necessarily be intended to be limiting.

[0053] According to the practice in the art, some embodiments are described and shown in the accompanying drawings with respect to functional blocks, components and / or modules. It will be understood by those skilled in the art that these blocks, components and / or modules are physically implemented by electronic (or optical) circuits (such as, logic circuits, discrete components, microprocessors, hard-wired circuits, storage elements and wiring connections, etc.), and these blocks, components and / or modules can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, components and / or modules are implemented by microprocessors or other similar hardware, software (e.g., microcode) can be used to program and control blocks, components and / or modules to perform the various functions discussed herein, and blocks, components and / or modules can be optionally driven by firmware and / or software. It is also contemplated that each block, component and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing certain functions and processors (e.g., one or more programmed microprocessors and related circuits) for performing other functions. In addition, without departing from the scope of the inventive concept, each block, component and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, components and / or modules. In addition, without departing from the scope of the inventive concept, the blocks, components and / or modules of some embodiments can be physically combined into more complex blocks, components and / or modules.

[0054] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and in the context of the present disclosure, and should not be interpreted in an ideal or overly formal sense.

[0055] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0056] Figure 1 is a perspective view showing a display device according to an embodiment.

[0057] refer to Figure 1 The display device 10 according to the embodiment may be included in an electronic device and may provide an image displayed in the electronic device. The electronic device may refer to any electronic device that provides a display screen. Examples of electronic devices may include televisions, laptop computers, monitors, billboards, IoT devices, mobile phones, smart phones, tablet personal computers (PCs), electronic watches, smart watches, watch phones, head-mounted displays, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, game consoles, digital cameras, and video cameras that provide display screens.

[0058] The shape of the display device 10 may be variously modified. For example, in a plan view, the display device 10 may have a shape similar to a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2. The edge where the short side in the first direction DR1 and the long side in the second direction DR2 meet at the corner may be rounded to have a curvature, but may not be limited thereto and may be formed at a right angle. The planar shape of the display device 10 may not be limited to a quadrilateral shape and may be formed to have a shape similar to another polygonal shape, a circular shape, or an elliptical shape.

[0059] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400 (see FIG. Figure 2 ).

[0060] The display panel 100 may include a main area MA and a sub area SBA.

[0061] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0062] For example, the self-luminous element may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but may not be limited thereto.

[0063] A plurality of pixels, a plurality of scan lines, a plurality of data lines, and a plurality of power lines may be provided in the display area DA. Each of the plurality of pixels may be defined as a minimum unit for emitting light, and each of the plurality of self-luminous elements may be a pixel. The scan line may supply a scan signal received from a scan driver to a pixel. The data line may supply a data voltage received from a display driver 200 to a pixel. The power line may supply a power supply voltage received from a display driver 200 to a pixel.

[0064] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a scan driver supplying a scan signal to a scan line and a fan-out line connecting the display driver 200 to the display area DA.

[0065] The sub-region SBA may be a region extending from one side of the main region MA. The sub-region SBA may include a flexible material that may be bent, folded, or curled. For example, when the sub-region SBA is bent, the sub-region SBA may overlap the main region MA in the thickness direction DR3 (third direction DR3). The sub-region SBA may include a display driver 200 and a pad portion electrically connected to the circuit board 300. In an embodiment, the sub-region SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0066] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may supply a power voltage to a power line, and may supply a scan control signal to a scan driver. The display driver 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be disposed in a sub-region SBA, and may overlap with the main region MA in a thickness direction DR3 (third direction DR3) by bending of the sub-region SBA. For another example, the display driver 200 may be mounted on a circuit board 300.

[0067] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0068] Figure 2 yes Figure 1 Schematic cross-sectional view of a display device viewed from the side.

[0069] refer to Figure 2 , the display panel 100 may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL.

[0070] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but may not be limited thereto. In an embodiment, the substrate SUB may include a glass material or a metal material.

[0071] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may also include a scan line, a data line, a power line, a scan control line, a fan-out line connecting the display driver 200 to the data line, and a lead connecting the display driver 200 to the pad portion. Each of the plurality of thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, in the case where a scan driver is formed on one side of the non-display area NDA of the display panel 100, the scan driver may include a thin film transistor.

[0072] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, scan lines, data lines, and power lines of the thin film transistor layer TFTL may be disposed in the display area DA. The scan control lines and fan-out lines of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead lines of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0073] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements each including a first electrode, a second electrode and a light emitting layer for emitting light and a pixel defining layer defining pixels. The light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

[0074] In an embodiment, the light emitting layer may be an organic light emitting layer including an organic material. The light emitting layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the first electrode receives an anode voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may be respectively transmitted to the organic light emitting layer through the hole transport layer and the electron transport layer, and the holes and electrons may be combined with each other in the organic light emitting layer to emit light.

[0075] In an embodiment, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0076] The thin film encapsulation layer TFEL may cover the top surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EML.

[0077] The color filter layer CFL may be disposed on the thin film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters corresponding to the emission areas, respectively. Each of the plurality of color filters may selectively transmit light of a specific wavelength, and may block or absorb light of a different wavelength. The color filter layer CFL may absorb a portion of light from outside the display device 10 to reduce reflected light due to external light. Therefore, the color filter layer CFL may prevent color distortion caused by reflection of external light.

[0078] Since the color filter layer CFL may be disposed (eg, directly disposed) on the thin film encapsulation layer TFEL, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively small.

[0079] In some embodiments, the display device 10 may further include an optical device. The optical device may emit or receive light in infrared, ultraviolet, and visible light bands. For example, the optical device may be an optical sensor that detects light incident on the display device 10, such as a proximity sensor, an illumination sensor, a camera sensor, a fingerprint sensor, or an image sensor.

[0080] Figure 3 is a plan view showing the arrangement of a light emitting element, a pixel defining layer, a trace pattern, and a third bank layer in a display region of a display device according to an embodiment. Figure 3 The display device 10 (for example, see Figure 2 ) is a plan view of the arrangement of light emitting elements ED1, ED2 and ED3, a pixel defining layer PDL, trace patterns TRP1, TRP2 and TRP3, and a third bank layer BN3 in a display area DA of FIG.

[0081] refer to Figure 3, the third bank layer BN3 may cover the display area DA and may expose a portion of the display area DA. An opening may be formed in an area that may be exposed without being covered by the third bank layer BN3, and a pixel defining layer PDL and light emitting elements ED1, ED2, and ED3 may be disposed in each opening. The light emitting elements ED1, ED2, and ED3 may be disposed at the center of the opening, and the pixel defining layer PDL may be disposed along the periphery of the light emitting elements ED1, ED2, and ED3. The trace patterns TRP1, TRP2, and TRP3 may be disposed on the third bank layer BN3 along the periphery of an area that may be exposed without being covered by the third bank layer BN3. Although in Figure 3 It can be shown that the area exposed and not covered by the third bank layer BN3 has a circular shape, but the area may have a polygonal shape such as a triangle, a quadrilateral or a hexagon, and the shape of the trace patterns TRP1, TRP2 and TRP3 disposed at the periphery of the exposed area may also be changed. The trace patterns TRP1, TRP2 and TRP3 may be disposed at a level higher than that of the third bank layer BN3, and the pixel defining layer PDL and the light emitting elements ED1, ED2 and ED3 may be disposed at a level lower than that of the third bank layer BN3.

[0082] The regions that may be exposed without being covered by the third bank layer BN3 may be spaced apart from each other in the first direction DR1, and may also be spaced apart from each other in the second direction DR2. The shape and arrangement of the regions that may be exposed without being covered by the third bank layer BN3 may not be limited to Figure 3 and such areas may be Type layout.

[0083] Figure 4 is a schematic cross-sectional view showing a portion of a display device according to an embodiment. Specifically, Figure 4 is along Figure 3 A schematic cross-sectional view taken along line BB' of FIG. Figure 3 The organic encapsulation layer TFE2, the second inorganic encapsulation layer TFE3, the color filter CF including CF1, CF2 and CF3, the light blocking layer BM and the overcoat layer OC are shown in the plan view of FIG. Figure 4 The substrate SUB, the thin film transistor layer TFTL, the light emitting element layer EML (see FIG. Figure 2 ), thin film encapsulation layer TFEL and color filter layer CFL (see Figure 2 ) is a schematic cross section of a .

[0084] The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0085] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing air or moisture from penetrating. For example, the first buffer layer BF1 may include a plurality of inorganic layers alternately stacked on each other.

[0086] The lower metal layer BML may be disposed on the first buffer layer BF1. For example, the lower metal layer BML may be formed to include a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), an alloy thereof, or a combination thereof.

[0087] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing air or moisture from penetrating. For example, the second buffer layer BF2 may include a plurality of inorganic layers alternately stacked on each other.

[0088] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of each of the plurality of pixels. For example, the thin film transistor TFT may be a switching transistor or a driving transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0089] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the lower metal layer BML and the gate electrode GE in the thickness direction DR3, and may be insulated from the gate electrode GE by the gate insulating layer GI. In a portion of the semiconductor layer ACT, the material of the semiconductor layer ACT may be made into a conductor to form a source electrode SE and a drain electrode DE.

[0090] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT in the thickness direction DR3 with the gate insulating layer GI disposed therebetween.

[0091] The gate insulating layer GI may be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 to insulate the gate electrode GE from the semiconductor layer ACT. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0092] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may extend to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0093] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in the thickness direction DR3. The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0094] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may extend to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0095] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole provided in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0096] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0097] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0098] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED pass.

[0099] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED, a pixel defining layer PDL, a capping layer CAP, and a bank structure BNS. The light emitting element ED may include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3.

[0100] Figure 5 It is shown Figure 4 An enlarged view of the first emission area (specifically, area A1). Figure 6 is an enlarged view showing a first emission region (specifically, region A1 ) according to the embodiment. Figure 7 is a schematic cross-sectional view of a case where the second bank layer includes an opaque metal.

[0101] Apart from Figure 4 In addition, refer to Figure 5 , Figure 6 and Figure 7 , the display device 10 (for example, see Figure 2 ) may include a display area DA (eg, see Figure 2 ) in a plurality of emission areas EA1, EA2, and EA3. The emission areas EA1, EA2, and EA3 may include areas where light can be emitted from the light emitting elements ED1, ED2, and ED3 and pass through the color filter layer CFL in a third direction DR3. The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that are spaced apart from each other and emit light of the same or different colors.

[0102] In an embodiment, the area or size of the first emission area EA1, the area or size of the second emission area EA2, and the area or size of the third emission area EA3 may be the same. For example, in the display device 10, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have the same area. However, the present disclosure may not be limited to this. In the display device 10, the area or size of the first emission area EA1, the area or size of the second emission area EA2, and the area or size of the third emission area EA3 may be different from each other. For example, the area of ​​the second emission area EA2 may be larger than the area of ​​the first emission area EA1 and the area of ​​the third emission area EA3, and the area of ​​the third emission area EA3 may be larger than the area of ​​the first emission area EA1. The intensity of light emitted from the corresponding emission areas EA1, EA2, and EA3 may vary according to the areas of the emission areas EA1, EA2, and EA3, and the areas of the emission areas EA1, EA2, and EA3 may be adjusted to control the color of the image displayed in the display device 10. Although in Figure 4 The embodiment may illustrate that the emission areas EA1, EA2, and EA3 have the same area, but the present disclosure may not be limited thereto.

[0103] In the display device 10, the first emission area EA1, the second emission area EA2, and the third emission area EA3 disposed adjacent to each other may form a pixel group. The pixel group may include emission areas EA1, EA2, and EA3 that emit light of different colors to express a white grayscale. However, the present disclosure may not be limited thereto, and the combination of emission areas EA1, EA2, and EA3 constituting the pixel group may be variously modified according to the arrangement of the emission areas EA1, EA2, and EA3, the color of the light emitted from the emission areas EA1, EA2, and EA3, and the like.

[0104] The light emitting element layer EML (see Figure 2 ) may be defined along the boundary of the embankment structure BNS. The first embankment layer BN1, the second embankment layer BN2, and the third embankment layer BN3 of the embankment structure BNS may surround the emission areas EA1, EA2, and EA3. The openings may include the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0105] The display device 10 may include light emitting elements ED1, ED2, and ED3 disposed in different emission areas EA1, EA2, and EA3, respectively. The light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1 disposed in a first emission area EA1, a second light emitting element ED2 disposed in a second emission area EA2, and a third light emitting element ED3 disposed in a third emission area EA3.

[0106] The light-emitting elements ED1, ED2 and ED3 may include pixel electrodes AE1, AE2 and AE3, light-emitting layers EL1, EL2 and EL3, and common electrodes CE1, CE2 and CE3, respectively, and the light-emitting layers EL1, EL2 and EL3 respectively disposed in different emission regions EA1, EA2 and EA3 may emit light of different colors according to the materials of the light-emitting layers EL1, EL2 and EL3. For example, the first light-emitting element ED1 disposed in the first emission region EA1 may emit a red first light having a peak wavelength in the range of about 610nm to about 650nm, the second light-emitting element ED2 disposed in the second emission region EA2 may emit a green second light having a peak wavelength in the range of about 510nm to about 550nm, and the third light-emitting element ED3 disposed in the third emission region EA3 may emit a blue third light having a peak wavelength in the range of about 440nm to about 480nm. The first emission region EA1, the second emission region EA2 and the third emission region EA3 constituting the pixel may respectively include light-emitting elements ED1, ED2 and ED3 that emit light of different colors to express a white grayscale. The light-emitting layers EL1, EL2 and EL3 may include two or more materials that emit light of different colors, so that the light-emitting layers may emit mixed light. For example, the light-emitting layers EL1, EL2 and EL3 may include a red light-emitting material and a green light-emitting material to emit yellow light, or may include a red light-emitting material, a green light-emitting material and a blue light-emitting material to emit white light.

[0107] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer PAS2. The pixel electrodes AE1, AE2, and AE3 may be disposed in emission areas EA1, EA2, and EA3, respectively. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in the first emission area EA1, a second pixel electrode AE2 disposed in the second emission area EA2, and a third pixel electrode AE3 disposed in the third emission area EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be disposed spaced apart from each other on the second passivation layer PAS2. Although Figure 4 It can be shown that the first pixel electrode AE1, the second pixel electrode AE2 and the third pixel electrode AE3 can be spaced apart from each other in the first direction DR1, but the present disclosure may not be limited to this, and the first pixel electrode AE1, the second pixel electrode AE2 and the third pixel electrode AE3 can be spaced apart from each other in any direction in a plane formed by the first direction DR1 and the second direction DR2.

[0108] The pixel electrodes AE1, AE2, and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2. Edges of the pixel electrodes AE1, AE2, and AE3 spaced apart from each other may be covered by the pixel defining layer PDL so that the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be insulated from each other.

[0109] The pixel electrodes AE1, AE2 and AE3 may each include a transparent electrode material and / or a conductive metal material. The conductive metal material may be at least one of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), titanium (Ti) and titanium nitride (TiN). The transparent electrode material may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO) and indium tin zinc oxide (ITZO). The pixel electrodes AE1, AE2 and AE3 may have a multilayer structure including a transparent electrode material and a conductive metal material.

[0110] The pixel defining layer PDL may be disposed on the second passivation layer PAS2, the remaining pattern RP, and the pixel electrodes AE1, AE2, and AE3. The pixel defining layer PDL may be disposed on a portion of the second passivation layer PAS2, and may cover the side surfaces of the pixel electrodes AE1, AE2, and AE3 and the remaining pattern RP to partially expose the top surfaces of the pixel electrodes AE1, AE2, and AE3. For example, the pixel defining layer PDL may expose the first pixel electrode AE1 in the first emission area EA1, and the first light emitting layer EL1 may be disposed (e.g., directly disposed) on the first pixel electrode AE1. The pixel defining layer PDL may include a protruding portion overlapping the pixel electrodes AE1, AE2, and AE3 in the thickness direction DR3 and a main portion not overlapping the pixel electrodes AE1, AE2, and AE3.

[0111] The pixel defining layer PDL may include an inorganic insulating material. The pixel defining layer PDL may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, tantalum oxide, hafnium oxide, zinc oxide, and amorphous silicon, but the present disclosure may not be limited thereto. Zinc oxide may be ZnO 2 or ZnO.

[0112] According to an embodiment, the pixel defining layer PDL may be disposed on the pixel electrodes AE1, AE2, and AE3, and may be spaced apart from the top surfaces of the pixel electrodes AE1, AE2, and AE3. The protruding portion of the pixel defining layer PDL may not be in direct contact with the top surfaces of the pixel electrodes AE1, AE2, and AE3, while overlapping the pixel electrodes AE1, AE2, and AE3 in the thickness direction DR3, and a portion of the first light emitting layer EL1 of the first light emitting element ED1, a portion of the second light emitting layer EL2 of the second light emitting element ED2, and a portion of the third light emitting layer EL3 of the third light emitting element ED3 and / or a residual pattern RP may be disposed between the pixel defining layer PDL and the pixel electrodes AE1, AE2, and AE3. However, the pixel defining layer PDL may be in direct contact with the side surfaces of the pixel electrodes AE1, AE2, and AE3. The side surface PDL_IN1 of the protruding portion of the pixel defining layer PDL may protrude toward the emission areas EA1, EA2, and EA3 (e.g., toward the center of the emission areas EA1, EA2, and EA3) more than the side surface of the third bank layer BN3.

[0113] The residual pattern RP may be disposed on an edge of each of the pixel electrodes AE1, AE2, and AE3. Due to the residual pattern RP, the pixel defining layer PDL may not be in direct contact with the top surface of the pixel electrodes AE1, AE2, and AE3. The residual pattern RP may be formed by removing the sacrificial layer SFL (see FIG. 1 ) in the manufacturing process of the display device 10. Fig. 9 ) is formed by the portion of the pixel electrodes AE1, AE2 and AE3 disposed on the pixel electrodes AE1, AE2 and AE3. The remaining pattern RP may include an oxide semiconductor. For example, the remaining pattern RP may include an oxide semiconductor or a transparent conductive oxide (TCO). In an embodiment, the remaining pattern RP may include zinc (Zn), and specifically, may include at least one of zinc indium tin oxide (ZITO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO) and zinc tin oxide (ZTO). The remaining pattern RP may include a first (or inner) side surface facing the emission areas EA1, EA2 and EA3 and a second (or outer) side surface that may be opposite to the first (or inner) side surface, and as Figure 5 and Figure 6 As shown in the figure, the first side surface may be recessed compared to the side surface PDL_IN1 of the protruding portion of the pixel defining layer PDL. Although not shown in the drawings, the first side surface of the remaining pattern RP may be aligned with the side surface PDL_IN1 of the protruding portion of the pixel defining layer PDL, or may protrude toward the emission areas EA1, EA2, and EA3 more than the side surface PDL_IN1 of the protruding portion of the pixel defining layer PDL. The second side surface of the remaining pattern RP may contact the side surface PDL_IN2 of the main portion of the pixel defining layer PDL.

[0114] The light-emitting layers EL1, EL2, and EL3 may be disposed on the pixel electrodes AE1, AE2, and AE3, respectively. The light-emitting layers EL1, EL2, and EL3 may be organic light-emitting layers made of an organic material, and may be formed on the pixel electrodes AE1, AE2, and AE3, respectively, by a deposition process. When the thin film transistor TFT applies a voltage (e.g., a predetermined voltage or a selectable voltage) to the first pixel electrode AE1 of the first light-emitting element ED1, the second pixel electrode AE2 of the second light-emitting element ED2, and the third pixel electrode AE3 of the third light-emitting element ED3, and the first common electrode CE1 of the first light-emitting element ED1, the second common electrode CE2 of the second light-emitting element ED2, and the third common electrode CE3 of the third light-emitting element ED3 receive a common voltage or a cathode voltage, holes and electrons may be transferred to the light-emitting layers EL1, EL2, and EL3, respectively, through the hole transport layer and the electron transport layer, and the holes and electrons may be recombined with each other in the light-emitting layers EL1, EL2, and EL3 to emit light.

[0115] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, which are respectively disposed in different emission areas EA1, EA2, and EA3. The first light-emitting layer EL1 may be disposed on the first pixel electrode AE1 in the first emission area EA1, the second light-emitting layer EL2 may be disposed on the second pixel electrode AE2 in the second emission area EA2, and the third light-emitting layer EL3 may be disposed on the third pixel electrode AE3 in the third emission area EA3. The light-emitting layers EL1, EL2, and EL3 may emit light of different colors, or the light-emitting layers EL1, EL2, and EL3 may emit mixed light. In an embodiment, the first light-emitting layer EL1 may emit red light, the second light-emitting layer EL2 may emit green light, and the third light-emitting layer EL3 may emit blue light. In an embodiment, the first light-emitting layer EL1 may emit yellow light, which may be a mixed light of red light and green light, and the second light-emitting layer EL2 may emit blue light. In an embodiment, the first light-emitting layer EL1 may emit white light, which may be a mixed light of red light, green light, and blue light.

[0116] The light emitting layers EL1, EL2, and EL3 may be disposed on the top surface of the pixel defining layer PDL. The light emitting layers EL1, EL2, and EL3 may be disposed in the spaces between the pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL, respectively. The light emitting layers EL1, EL2, and EL3 may contact the pixel defining layer PDL, the residual pattern RP, and may contact the pixel electrodes AE1, AE2, and AE3, respectively.

[0117] The common electrodes CE1, CE2, and CE3 may be disposed on the light emitting layers EL1, EL2, and EL3, respectively. The common electrodes CE1, CE2, and CE3 may include a transparent conductive material so that light generated in the light emitting layers EL1, EL2, and EL3 may be emitted. The common electrodes CE1, CE2, and CE3 may receive a common voltage or a low potential voltage. In the case where the pixel electrodes AE1, AE2, and AE3 receive a voltage corresponding to the data voltage and the common electrodes CE1, CE2, and CE3 receive a low potential voltage, a potential difference may be formed between the pixel electrodes AE1, AE2, and AE3 and the common electrodes CE1, CE2, and CE3 so that the light emitting layers EL1, EL2, and EL3 may emit light.

[0118] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3 respectively disposed in different emission areas EA1, EA2, and EA3. The first common electrode CE1 may be disposed on the first light emitting layer EL1 in the first emission area EA1, the second common electrode CE2 may be disposed on the second light emitting layer EL2 in the second emission area EA2, and the third common electrode CE3 may be disposed on the third light emitting layer EL3 in the third emission area EA3. The first common electrode CE1, the second common electrode CE2, and the third common electrode CE3 may be spaced apart from each other.

[0119] The capping layer CAP may be disposed on the common electrodes CE1, CE2, and CE3. The capping layer CAP may include an organic or inorganic insulating material to cover the pattern disposed on the light emitting elements ED1, ED2, and ED3. The capping layer CAP may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air. In an embodiment, the capping layer CAP may include an organic material (such as a-NPD, NPB, TPD, m-MTDATA, Alq 3 , LiF and / or CuPc) or an inorganic material (such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride). Zinc oxide may be ZnO 2 or ZnO.

[0120] The display device 10 may include a dam structure BNS disposed on the pixel defining layer PDL. The dam structure BNS may have a structure in which dam layers BN1, BN2, and BN3 including different materials may be sequentially stacked on each other, may include an opening including emission areas EA1, EA2, and EA3, and may be disposed to overlap with a light blocking layer BM to be described later. The light emitting elements ED1, ED2, and ED3 of the display device 10 may be disposed to overlap with the opening of the dam structure BNS.

[0121] The bank structure BNS may include a first bank layer BN1, a second bank layer BN2, and a third bank layer BN3 that may be sequentially stacked on one another on the pixel defining layer PDL.

[0122] The first bank layer BN1 may be disposed on the pixel defining layer PDL. In a plan view, a side surface BN1_IN of the first bank layer BN1 may be recessed relative to a side surface PDL_IN1 of the pixel defining layer PDL in a direction opposite to a direction facing the center of the emission regions EA1, EA2, and EA3. A side surface BN1_IN of the first bank layer BN1 may be recessed relative to a side surface of a second bank layer BN2 to be described later in a direction opposite to a direction facing the emission regions EA1, EA2, and EA3.

[0123] According to an embodiment, the first bank layer BN1 may include a metal material. The first bank layer BN1 may include an opaque metal. In an embodiment, the first bank layer BN1 may include aluminum (Al).

[0124] In an embodiment, the thickness of the first bank layer BN1 may be about to about In the case where the above range is satisfied, the light emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 that may be spaced apart from each other may be formed by a deposition process and an etching process instead of a mask process.

[0125] According to an embodiment, the common electrodes CE1, CE2, and CE3 may be in contact with (e.g., directly in contact with) the side surface BN1_IN of the first bank layer BN1. The first common electrode CE1 of the first light emitting element ED1, the second common electrode CE2 of the second light emitting element ED2, and the third common electrode CE3 of the third light emitting element ED3 may be in contact with (e.g., directly in contact with) the first bank layer BN1, the first bank layer BN1 may include a metal material, and the common electrodes CE1, CE2, and CE3 may be electrically connected to each other through the first bank layer BN1.

[0126] The light emitting layers EL1, EL2, and EL3 may be in contact with (e.g., in direct contact with) the side surface BN1_IN of the first bank layer BN1. The contact area between the common electrodes CE1, CE2, and CE3 and the side surface BN1_IN of the first bank layer BN1 may be greater than the contact area between the light emitting layers EL1, EL2, and EL3 and the side surface BN1_IN of the first bank layer BN1. The common electrodes CE1, CE2, and CE3 may be disposed in a larger area on the side surface BN1_IN of the first bank layer BN1 than the light emitting layers EL1, EL2, and EL3, respectively, or may be disposed at a higher position on the side surface BN1_IN of the first bank layer BN1 than the light emitting layers EL1, EL2, and EL3, respectively. Since the first common electrode CE1 of the first light-emitting element ED1, the second common electrode CE2 of the second light-emitting element ED2 and the third common electrode CE3 of the third light-emitting element ED3 can be electrically connected to each other through the first bank layer BN1, it can be advantageous for the first common electrode CE1 of the first light-emitting element ED1, the second common electrode CE2 of the second light-emitting element ED2 and the third common electrode CE3 of the third light-emitting element ED3 to contact the first bank layer BN1 in a larger area.

[0127] The second bank layer BN2 may be disposed on the first bank layer BN1. The second bank layer BN2 may include a tip TIP which may be a region protruding compared to the first bank layer BN1. A side surface of the second bank layer BN2 may protrude toward the center of the emission regions EA1, EA2, and EA3 more than a side surface BN1_IN of the first bank layer BN1.

[0128] The third bank layer BN3 may be disposed on the second bank layer BN2. The third bank layer BN3 may include a tip TIP which may be a region protruding compared to the first bank layer BN1. A side surface of the third bank layer BN3 may protrude toward the center of the emission regions EA1, EA2, and EA3 more than a side surface BN1_IN of the first bank layer BN1.

[0129] In a plan view, the side surface of the second bank layer BN2 and the side surface of the third bank layer BN3 may be aligned with each other. The side surface of the second bank layer BN2 and the side surface of the third bank layer BN3 may be aligned to form an approximately flat surface in a direction perpendicular to the substrate SUB (e.g., the third direction DR3) (see FIG. Figure 5 ), or form a nearly flat surface in the inclined direction (see Figure 6 ). The present disclosure may not be limited thereto, and the side surface of the second bank layer BN2 and the side surface of the third bank layer BN3 may not be aligned.

[0130] Since the side surfaces of the second bank layer BN2 and the third bank layer BN3 have a shape protruding toward the center of the emission areas EA1, EA2, and EA3 than the side surface BN1_IN of the first bank layer BN1, an undercut structure of the first bank layer BN1 may be formed below the tip TIP of the second bank layer BN2 and the tip TIP of the third bank layer BN3. The second bank layer BN2 and the third bank layer BN3 may include the tip TIP, so that separated or spaced light emitting elements ED1, ED2, and ED3 may be formed without a mask process.

[0131] In the display device 10 according to the embodiment, the bank structure BNS may include a tip TIP protruding toward the center of the emission areas EA1, EA2, and EA3, and thus may be formed by a deposition process and an etching process instead of a mask process. In addition, it may be possible to form different layers separately in different emission areas EA1, EA2, and EA3 by a deposition process. For example, even if the first light-emitting layer EL1 of the first light-emitting element ED1, the second light-emitting layer EL2 of the second light-emitting element ED2, and the third light-emitting layer EL3 of the third light-emitting element ED3, and the common electrodes CE1, CE2, and CE3 may be formed by a deposition process without using a mask, the deposited material may be disconnected from the bank structure BNS disposed between the tip TIPs by the tip TIPs of the second bank layer BN2 and the tip TIPs of the third bank layer BN3, without being connected between the emission areas EA1, EA2, and EA3. By forming a material for forming a specific layer on the entire surface of the display device 10 and then removing the layer formed in the undesired area by etching, it may be possible to form different layers separately in different emission areas EA1, EA2, and EA3. In the display device 10, different light emitting elements ED1, ED2, and ED3 can be formed in different emission areas EA1, EA2, and EA3 respectively through deposition and etching processes without using a mask process, and unnecessary components in the display device 10 can be omitted to make the non-display area NDA (for example, see Figure 2 ) area is minimized.

[0132] The side surface shape of the bank structure BNS may be a structure formed due to the difference in etching rate during the etching process due to different materials of the first bank layer BN1, the second bank layer BN2, and the third bank layer BN3. According to an embodiment, the second bank layer BN2 and the third bank layer BN3 may each include a material having an etching rate lower than that of the first bank layer BN1, and the first bank layer BN1 may be further etched during the etching process to form an undercut structure under the tip TIP of the second bank layer BN2 and the tip TIP of the third bank layer BN3. In an embodiment, the first bank layer BN1 may include aluminum (Al), and the second bank layer BN2 and the third bank layer BN3 may include a transparent conductive oxide (TCO).

[0133] In the case where the second bank layer BN2 disposed on the first bank layer BN1 may be made of an opaque material such as titanium (Ti), a portion of light emitted from the light emitting elements ED1, ED2, and ED3 may be Figure 7 The tip TIP of the second bank layer BN2 shown in FIG. 1 is reflected and disappears. In addition, the opaque second bank layer BN2 becomes a useless space in the display device 10.

[0134] On the other hand, the second bank layer BN2 and the third bank layer BN3 may be formed by Figure 5 and Figure 6 In the case where the amorphous transparent material shown in is made, the light emitted from the light emitting elements ED1, ED2 and ED3 can pass through the second bank layer BN2 and the third bank layer BN3. The light efficiency can be improved and the useless space can be reduced, so that the pixel gap can be narrowed. The transmittance of the second bank layer BN2 and the third bank layer BN3 to visible light (i.e., light with a wavelength in the range of about 380nm to about 780nm) can be about 85% or more or about 89% or more. The transparent material that can be used for the second bank layer BN2 and the third bank layer BN3 can be a transparent conductive oxide (TCO), and can include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO) or a combination thereof. The transparent conductive oxide (TCO) has excellent adhesion to the first inorganic encapsulation layer TFE1, and therefore the transparent conductive oxide (TCO) can prevent the penetration of moisture from the outside air.

[0135] The second bank layer BN2 may include zinc (Zn). In an embodiment, the second bank layer BN2 may include at least one of zinc indium tin oxide (ZITO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), and zinc tin oxide (ZTO). The bottom surface of the tip TIP of the second bank layer BN2 may be continuously exposed and damaged in the etching process, so that the tip TIP may be bent. In the case where the second bank layer BN2 includes zinc (Zn), the second bank layer BN2 may not be etched by fluorine-based gases, so that the tip TIP can maintain the shape of the second bank layer BN2 without being damaged. Therefore, the second bank layer BN2 adjacent to the first emission area EA1, the second bank layer BN2 adjacent to the second emission area EA2, and the second bank layer BN2 adjacent to the third emission area EA3 may have the same thickness.

[0136] According to an embodiment, the ratio of zinc (Zn) contained in the second bank layer BN2 relative to the total number of atoms may be in the range of about 5 at % to about 50 at %. When the ratio of zinc (Zn) may be in the above range, the potential difference may be reduced, and thus corrosion between the first bank layer BN1 and the third bank layer BN3 may be prevented.

[0137] The third bank layer BN3 may include hydrogen. The third bank layer BN3 may be made of an amorphous material containing hydrogen between atoms of a transparent conductive oxide (TCO). In the case where hydrogen may be additionally included in argon in the sputtering process of the transparent conductive oxide (TCO), the hydrogen may be located between the atoms of the transparent conductive oxide (TCO). In an embodiment, the third bank layer BN3 may include hydrogen and indium tin oxide (ITO). In the case where the concentration of hydrogen used in the sputtering process increases, the ratio of hydrogen contained in the third bank layer BN3 may increase, and in the case where the concentration of hydrogen decreases, the ratio of hydrogen contained in the third bank layer BN3 may decrease.

[0138] The thickness of the third bank layer BN3 may be greater than that of the second bank layer BN2. In an embodiment, the third bank layer BN3 may have a thickness of about to about In the case of including only the transparent conductive oxide (TCO), there may be a limit to increasing the thickness while maintaining the amorphous characteristics, but in the case of including both the transparent conductive oxide (TCO) and hydrogen, the thickness can be increased.

[0139] The sum of the thickness of the second bank layer BN2 and the thickness of the third bank layer BN3 may be about to about The thickness of the first bank layer BN1 may be significantly greater than each of the thickness of the second bank layer BN2 and the thickness of the third bank layer BN3. The thickness of the first bank layer BN1 may be greater than the sum of the thickness of the second bank layer BN2 and the thickness of the third bank layer BN3. The thickness of the first bank layer BN1 may be greater than about three times the sum of the thickness of the second bank layer BN2 and the thickness of the third bank layer BN3. While satisfying the above range, the light emitting layers EL1, EL2 and EL3 and the common electrodes CE1, CE2 and CE3 may be smoothly spaced (or separated) from the trace patterns TRP1, TRP2 and TRP3 while ensuring a thin tip TIP.

[0140] The tip TIP of the second bank layer BN2 and the tip TIP of the third bank layer BN3 may overlap with the common electrodes CE1, CE2 and CE3 in a direction perpendicular to the substrate SUB (e.g., a third direction DR3). In addition, the tip TIP of the second bank layer BN2 and the tip TIP of the third bank layer BN3 may overlap with the light-emitting layers EL1, EL2 and EL3 in a direction perpendicular to the substrate SUB (e.g., a third direction DR3). In addition, the tip TIP of the second bank layer BN2 and the tip TIP of the third bank layer BN3 may overlap with the pixel defining layer PDL in a direction perpendicular to the substrate SUB (e.g., a third direction DR3). The common electrodes CE1, CE2 and CE3 may be formed below the bottom surface of the tip TIP of the second bank layer BN2. The maximum distance from the substrate SUB to the common electrodes CE1, CE2 and CE3 may be less than the maximum distance from the substrate SUB to the second bank layer BN2.

[0141] The display device 10 may include trace patterns TRP1, TRP2, and TRP3 that may be traces deposited on the bank structure BNS. The trace patterns TRP1, TRP2, and TRP3 may include organic patterns ELP1, ELP2, and ELP3, respectively, including electrode patterns CEP1, CEP2, and CEP3, respectively, and each including a cladding pattern CLP, and the trace patterns TRP1, TRP2, and TRP3 may surround the periphery of the emission areas EA1, EA2, and EA3, respectively, on the third bank layer BN3.

[0142] The trace patterns TRP1, TRP2, and TRP3 may be traces formed because the trace patterns TRP1, TRP2, and TRP3 may be disconnected in the emission areas EA1, EA2, and EA3 without being electrically connected to the light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the cladding layer CAP due to the tip TIP of the embankment structure BNS. The light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the cladding layer CAP may be formed in the openings, and by the tip TIP of the embankment structure BNS, the organic patterns ELP1, ELP2, and ELP3 may be electrically disconnected from the light-emitting layers EL1, EL2, and EL3, respectively, the electrode patterns CEP1, CEP2, and CEP3 may be electrically disconnected from the common electrodes CE1, CE2, and CE3, respectively, and the cladding pattern CLP and the cladding layer CAP may be electrically disconnected from each other. The trace patterns TRP1, TRP2, and TRP3 may be formed by patterning the emission areas EA1, EA2, and EA3 or the openings near the emission areas EA1, EA2, and EA3 or the openings.

[0143] The display device 10 according to the embodiment may include organic patterns ELP1, ELP2, and ELP3 including the same material and light-emitting layers EL1, EL2, and EL3, and the organic patterns ELP1, ELP2, and ELP3 are disposed on the bank structure BNS. Since the light-emitting layers EL1, EL2, and EL3 may be formed by a process of depositing a material on the entire surface of the display device 10, the material forming the light-emitting layers EL1, EL2, and EL3 may also be deposited on the bank structure BNS in addition to the emission areas EA1, EA2, and EA3.

[0144] For example, the display device 10 may include organic patterns ELP1, ELP2, and ELP3 disposed on the bank structure BNS. The organic patterns ELP1, ELP2, and ELP3 may include first, second, and third organic patterns ELP1, ELP2, and ELP3 disposed on the third bank layer BN3 of the bank structure BNS.

[0145] The first organic pattern ELP1 and the first light emitting layer EL1 of the first light emitting element ED1 may include the same material. The second organic pattern ELP2 and the second light emitting layer EL2 of the second light emitting element ED2 may include the same material, and the third organic pattern ELP3 and the third light emitting layer EL3 of the third light emitting element ED3 may include the same material. The organic patterns ELP1, ELP2, and ELP3 may be formed in a process of forming light emitting layers EL1, EL2, and EL3 including the same material as the organic patterns ELP1, ELP2, and ELP3, respectively. The organic patterns ELP1, ELP2, and ELP3 may be respectively disposed adjacent to emission areas EA1, EA2, and EA3 where the light emitting layers EL1, EL2, and EL3 may be respectively disposed.

[0146] The display device 10 according to the embodiment may include electrode patterns CEP1, CEP2, and CEP3, which include the same material as the common electrodes CE1, CE2, and CE3, respectively, and the electrode patterns CEP1, CEP2, and CEP3 are disposed on the embankment structure BNS. The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be disposed (e.g., directly disposed) on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, respectively. The arrangement relationship of the electrode patterns CEP1, CEP2, and CEP3 and the organic patterns ELP1, ELP2, and ELP3 may be the same as the arrangement relationship of the first light-emitting layer EL1 of the first light-emitting element ED1, the second light-emitting layer EL2 of the second light-emitting element ED2, the third light-emitting layer EL3 of the third light-emitting element ED3, and the common electrodes CE1, CE2, and CE3.

[0147] The display device 10 may include a cladding pattern CLP disposed on the embankment structure BNS. The cladding pattern CLP may be disposed (e.g., directly disposed) on the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3. The arrangement relationship of the cladding pattern CLP and the electrode patterns CEP1, CEP2, and CEP3 may be the same as the arrangement relationship of the first common electrode CE1 of the first light emitting element ED1, the second common electrode CE2 of the second light emitting element ED2, the third common electrode CE3 of the third light emitting element ED3, and the cladding layer CAP.

[0148] The thin film encapsulation layer TFEL may be disposed on the light emitting elements ED1, ED2, and ED3 and the embankment structure BNS, and may cover the light emitting elements ED1, ED2, and ED3 and the embankment structure BNS. The thin film encapsulation layer TFEL may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one organic layer to protect the light emitting element layer EML from foreign matter such as dust.

[0149] In an embodiment, the thin film encapsulation layer TFEL may include a first inorganic encapsulation layer TFE1 , an organic encapsulation layer TFE2 , and a second inorganic encapsulation layer TFE3 , which may be sequentially stacked on one another.

[0150] Each of the first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating material may be any one of silicon oxide, silicon nitride and silicon oxynitride, and may include, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. Zinc oxide may be ZnO 2 or ZnO.

[0151] The organic encapsulation layer TFE2 may include a polymer material. Examples of polymer materials may include acrylic resin, epoxy resin, polyimide, polyethylene, etc. or a combination thereof. For example, the organic encapsulation layer TFE2 may include an acrylic resin such as polymethyl methacrylate, polyacrylic acid, etc. or a combination thereof. The organic encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0152] The first inorganic encapsulation layer TFE1 may be disposed on the light emitting elements ED1, ED2, and ED3, the trace patterns TRP1, TRP2, and TRP3, and the embankment structure BNS. The first inorganic encapsulation layer TFE1 may include a first inorganic layer TL1, a second inorganic layer TL2, and a third inorganic layer TL3, and the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 are disposed to correspond to different emission areas EA1, EA2, and EA3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may include an inorganic insulating material to cover the light emitting elements ED1, ED2, and ED3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may respectively prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air. The first, second, and third inorganic layers TL1, TL2, and TL3 may be disposed to cover the organic patterns ELP1, ELP2, and ELP3, the electrode patterns CEP1, CEP2, and CEP3, and the capping pattern CLP, so that the pattern disposed on the bank structure BNS may be prevented from being peeled off during a manufacturing process of the display device 10.

[0153] Since the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be formed by a chemical vapor deposition (CVD) method, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can be formed along the step portion of the deposition layer. For example, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 can even form a thin film under the undercut structure of the tip TIP of the dam structure BNS.

[0154] The first inorganic layer TL1 may be disposed on the first light emitting element ED1 and the first electrode pattern CEP1. The first inorganic layer TL1 may be disposed to cover the first light emitting element ED1, the cladding layer CAP, and the first bank layer BN1 along the side surfaces of the first light emitting element ED1, the cladding layer CAP, and the first bank layer BN1 adjacent to the first common electrode CE1, and may also be disposed to cover the organic pattern ELP1, the first electrode pattern CEP1, and the cladding pattern CLP. However, the first inorganic layer TL1 may not overlap the second opening and the third opening, and may be disposed only on the first opening and the bank structure BNS around the first opening. Although in Figures 4 to 6 It can be shown that the first inorganic layer TL1 is sealed with uneven thickness along the outer surfaces of the first trace pattern TRP1 and the light emitting element ED1, but the first inorganic layer TL1 can be set with uniform thickness along the top surface and side surfaces of the first trace pattern TRP1, the side surface and bottom surface of the second bank layer BN2, the side surface of the first bank layer BN1, and the top surface of the first common electrode CE1.

[0155] The second inorganic layer TL2 may be disposed on the second light emitting element ED2 and the second electrode pattern CEP2. However, the second inorganic layer TL2 may not overlap the first and third openings, and may be disposed only on the second opening and the bank structure BNS around the second opening.

[0156] The third inorganic layer TL3 may be disposed on the third light emitting element ED3 and the third electrode pattern CEP3. However, the third inorganic layer TL3 may not overlap the first and second openings, and may be disposed only on the third opening and the bank structure BNS around the third opening.

[0157] The first inorganic layer TL1 may be formed after the first common electrode CE1 may be formed, the second inorganic layer TL2 may be formed after the second common electrode CE2 may be formed, and the third inorganic layer TL3 may be formed after the third common electrode CE3 may be formed. Therefore, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be disposed to cover different electrode patterns CEP1, CEP2, and CEP3 and the organic patterns ELP1, ELP2, and ELP3, respectively. Figure 3 In the plan view, Figure 4 The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may have boundaries that may be the same as or similar to the boundaries of the first trace pattern TRP1, the second trace pattern TRP2, and the third trace pattern TRP3, respectively, and the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may each have an area larger than the area of ​​the opening of the embankment structure BNS or may each have an area larger than the areas of the emission areas EA1, EA2, and EA3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be spaced apart from each other on the embankment structure BNS. Therefore, a portion of the second embankment layer BN2 may not overlap with the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3, and a portion of the top surface of the second embankment layer BN2 may be exposed in the separation space of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 without being covered by the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3. The exposed top surface of the second bank layer BN2 may directly contact the organic encapsulation layer TFE2 of the thin film encapsulation layer TFEL.

[0158] The light blocking layer BM may be disposed on the thin film encapsulation layer TFEL. The light blocking layer BM may include holes OPT1, OPT2, and OPT3 disposed to overlap the emission areas EA1, EA2, and EA3, respectively. For example, the first hole OPT1 may be disposed to overlap the first emission area EA1. The second hole OPT2 may be disposed to overlap the second emission area EA2, and the third hole OPT3 may be disposed to overlap the third emission area EA3. The area or size of the holes OPT1, OPT2, and OPT3 may be larger than the area or size of the emission areas EA1, EA2, and EA3, respectively. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM may be formed to be larger than the emission areas EA1, EA2, and EA3, respectively, so that the light emitted from the emission areas EA1, EA2, and EA3 can be visually recognized by the user not only from the front surface of the display device 10 but also from the side surface of the display device 10.

[0159] The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but they may not be limited thereto. The light blocking layer BM may prevent visible light from penetrating and mixing between the first emission area EA1, the second emission area EA2, and the third emission area EA3, which results in an improvement in the color reproducibility of the display device 10.

[0160] The display device 10 may include color filters CF1, CF2, and CF3 disposed on the emission areas EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 may be disposed to correspond to the emission areas EA1, EA2, and EA3, respectively. For example, the color filters CF1, CF2, and CF3 may be disposed on a light blocking layer BM including holes OPT1, OPT2, and OPT3 disposed to correspond to the emission areas EA1, EA2, and EA3, respectively. The holes OPT1, OPT2, and OPT3 of the light blocking layer BM may be formed to overlap with the emission areas EA1, EA2, and EA3, respectively, or to overlap with the opening of the embankment structure BNS, and may form a light exit area from which light emitted from the emission areas EA1, EA2, and EA3 may be emitted. The color filters CF1, CF2, and CF3 may have an area larger than that of the holes OPT1, OPT2, and OPT3 of the light blocking layer BM, respectively, and the color filters CF1, CF2, and CF3 may completely cover the light exit areas formed by the holes OPT1, OPT2, and OPT3, respectively.

[0161] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are arranged to correspond to different emission areas EA1, EA2, and EA3, respectively. The color filters CF1, CF2, and CF3 may include a colorant such as a dye or a pigment that absorbs light in a band other than light in a specific band, and the color filters CF1, CF2, and CF3 may be arranged to correspond to the color of the light emitted from the emission areas EA1, EA2, and EA3, respectively. For example, the first color filter CF1 may be a red color filter that may be arranged to overlap with the first emission area EA1 and transmit only a red first light. The second color filter CF2 may be a green color filter that may be arranged to overlap with the second emission area EA2 and transmit only a green second light, and the third color filter CF3 may be a blue color filter that may be arranged to overlap with the third emission area EA3 and transmit only a blue third light.

[0162] The color filters CF1, CF2 and CF3 may be spaced apart from other adjacent color filters CF1, CF2 and CF3 on the light blocking layer BM. The color filters CF1, CF2 and CF3 may have an area larger than the area of ​​the holes OPT1, OPT2 and OPT3 of the light blocking layer BM while covering the holes OPT1, OPT2 and OPT3 respectively, and may have an area sufficient to be spaced apart from other color filters CF1, CF2 and CF3 on the light blocking layer BM. However, the present disclosure may not be limited thereto. The color filters CF1, CF2 and CF3 may be arranged to partially overlap with other adjacent color filters CF1, CF2 and CF3. Different color filters CF1, CF2 and CF3 may be areas that do not overlap with the emission areas EA1, EA2 and EA3, and may overlap with each other on the light blocking layer BM described later. In the display device 10, the color filters CF1, CF2 and CF3 may be arranged to overlap with each other so that the intensity of the reflected light caused by the external light may be reduced. Furthermore, by adjusting the arrangement, shape, and area of ​​the color filters CF1, CF2, CF3 in a plan view, the color of the reflected light caused by the external light can be controlled.

[0163] An overcoat layer OC may be disposed on the color filters CF1, CF2, and CF3 to flatten the top ends of the color filters CF1, CF2, and CF3. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the overcoat layer OC may include a colorless light-transmitting organic material such as acrylic resin.

[0164] Hereinafter, a manufacturing process of the display device 10 according to the embodiment will be described with reference to other drawings.

[0165] Figure 8 is a flowchart showing a manufacturing process of a display device according to an embodiment, and Figures 9 to 18are detailed schematic cross-sectional views sequentially illustrating a manufacturing process of a display device according to an embodiment.

[0166] Figures 9 to 18 The formation of the light emitting element ED (see Figure 4 ) and thin film encapsulation layer TFEL (see Figure 4 ) and as a display device 10 (for example, see Figure 2 ) of the light emitting element layer EML (see Figure 2 ) of the bank structure BNS. Hereinafter, regarding the manufacturing process of the display device 10, the description of the forming process of each layer will be omitted, and reference will be made to Figures 9 to 18 Combined with Figures 4 to 6 Describe the order in which each layer is formed.

[0167] refer to Fig. 9 ,according to Figure 8 In step S10 , pixel electrodes AE1 , AE2 , and AE3 , a sacrificial layer SFL, a pixel defining material layer PDLL, and a plurality of bank material layers BNL1 , BNL2 , and BNL3 spaced apart from each other may be formed on the entire second passivation layer PAS2 .

[0168] Although not shown in the drawings, the thin film transistor layer TFTL may be disposed on the substrate SUB, and the structure of the thin film transistor layer TFTL may be the same as that described above with reference to FIG. Figure 4 The detailed description thereof will be omitted.

[0169] When forming the third bank material layer BNL3, a transparent conductive oxide (TCO) may be deposited by a sputtering process. The sputtering process may be performed under a mixed gas atmosphere including hydrogen and argon. Hydrogen may be introduced at a flow rate in a range of about 0.1 sccm to about 5 sccm.

[0170] refer to Fig.10 , a photoresist PR may be formed on the third bank material layer BNL3, and according to Figure 8 In step S20, a first etching process (first etching) using the photoresist PR as a mask for partially etching the second bank material layer BNL2 and the third bank material layer BNL3 may be performed. The photoresist PR may be disposed on the third bank material layer BNL3 to be spaced apart from each other and to expose regions overlapping the pixel electrodes AE1, AE2, and AE3.

[0171] In an embodiment, the first etching process (first etching) may be performed as wet etching. The second bank material layer BNL2 and the third bank material layer BNL3 may be anisotropically etched. The second bank material layer BNL2 and the third bank material layer BNL3 in the region overlapping with the pixel electrodes AE1, AE2, and AE3 may be removed, and the first bank material layer BNL1 in the region overlapping with the pixel electrodes AE1, AE2, and AE3 may be exposed.

[0172] refer to Fig.11 ,according to Figure 8 In step S30, the exposed first bank material layer BNL1 may be removed by a second etching process (second etching) to form a hole HOL. In an embodiment, the second etching process may be performed as anisotropic dry etching. The hole HOL may be formed in a region overlapping with the pixel electrodes AE1, AE2, and AE3, and the hole HOL may form an opening of the bank structure BNS.

[0173] refer to Fig.12 ,according to Figure 8 In step S40, an undercut structure of the first bank material layer BNL1 may be formed by a third etching process (third etching). The etching rate of the first bank material layer BNL1 may be higher than each of the etching rates of the second bank material layer BNL2 and the third bank material layer BNL3, and the side surfaces BN23_IN of the second bank material layer BNL2 and the third bank material layer BNL3 may be formed as a structure protruding toward the center of the hole HOL more than the side surface BN1_IN of the first bank material layer BNL1. The side surfaces BN23_IN of the second bank material layer BNL2 and the third bank material layer BNL3 may protrude toward the hole HOL more than the side surface BN1_IN of the first bank material layer BNL1 to form a tip TIP, and an undercut structure may be formed thereunder.

[0174] In an embodiment, the third etching process may be an isotropic wet etching process. The third etching process may use an alkali-based etchant. The bank structure BNS of the first bank layer BN1, the second bank layer BN2, and the third bank layer BN3 may be obtained by the third etching process.

[0175] Next, if Fig.13 As shown in Figure 8 In step S50, the pixel definition material layer PDLL may be removed by a fourth etching process (fourth etching) to expose the sacrificial layer SFL. Fig.14 As shown in Figure 8 In step S60, the sacrificial layer SFL may be etched through a fifth etching process (fifth etching) to expose the pixel electrodes AE1, AE2, and AE3.

[0176] The portion of the sacrificial layer SFL that may be exposed by the hole HOL and the portion of the sacrificial layer SFL between the first bank material layer BNL1 and the pixel electrodes AE1, AE2, and AE3 may be removed. However, the sacrificial layer SFL may not be completely removed and may remain as a portion of the remaining pattern RP between the pixel defining layer PDL and the pixel electrodes AE1, AE2, and AE3. A space as a portion remaining after the sacrificial layer SFL is removed may be formed between the pixel electrodes AE1, AE2, and AE3 and the pixel defining layer PDL disposed thereon. In a subsequent process, the light emitting layers EL1, EL2, and EL3 disposed on the pixel electrodes AE1, AE2, and AE3 may be formed to fill the space.

[0177] Next, if Fig.15 As shown in , the photoresist PR may be removed from the third bank layer BN3.

[0178] Next, if Fig.16 As shown in Figure 8 In step S70, a first light emitting layer EL1, a first common electrode CE1 and a cladding layer CAP may be deposited on the first pixel electrode AE1 to form a first light emitting element ED1. The first light emitting layer EL1, the first common electrode CE1 and the cladding layer CAP may be formed on the entire surface of the substrate SUB so that a trace pattern may be formed on the third bank layer BN3.

[0179] Due to the tip TIP of the second bank layer BN2 and the tip TIP of the third bank layer BN3, the first light emitting layer EL1 and the first organic pattern material layer ELPL1 may be spaced apart (or separated) from each other, the first common electrode CE1 and the first electrode pattern material layer CEPL1 may be spaced apart (or separated) from each other, and the capping layer CAP and the covering pattern material layer CLPL may be spaced apart (or separated) from each other. The first light emitting layer EL1 may be formed on the first pixel electrode AE1, and the first organic pattern material layer ELPL1 may be formed on the third bank layer BN3. Figure 8 In step S70 , a first common electrode CE1 may be formed on the first light emitting layer EL1 , and a first electrode pattern material layer CELP1 may be formed on the first organic pattern material layer ELPL1 .

[0180] The first light emitting layer EL1 and the first common electrode CE1 may be formed by a deposition process. In the opening, the deposition of the material may not be smooth due to the tip TIP of the second bank layer BN2 and the tip TIP of the third bank layer BN3. However, since the materials of the first light emitting layer EL1 and the first common electrode CE1 may be deposited in an inclined direction rather than in a direction perpendicular to the top surface of the substrate, the materials of the first light emitting layer EL1 and the first common electrode CE1 may be deposited even in a region hidden by the tip TIP of the second bank layer BN2 and the third bank layer BN3.

[0181] The deposition process for forming the common electrodes CE1, CE2, and CE3 may be performed at an angle inclined relatively closer to the horizontal direction compared to the deposition process for forming the light-emitting layers EL1, EL2, and EL3, respectively. Therefore, the common electrodes CE1, CE2, and CE3 may contact the side surface of the first bank layer BN1 with a larger area compared to the light-emitting layers EL1, EL2, and EL3, respectively. Optionally, the common electrodes CE1, CE2, and CE3 may be deposited to a higher position on the side surface of the first bank layer BN1 compared to the light-emitting layers EL1, EL2, and EL3, respectively. Different common electrodes CE1, CE2, and CE3 may be electrically connected to each other while contacting the first bank layer BN1 having high conductivity.

[0182] Next and if Fig.16 As shown in , a first inorganic material layer TLL1 covering the first light emitting element ED1 and the capping layer CAP may be formed. The first inorganic material layer TLL1 may be formed to completely and seamlessly cover the outer surface of the first light emitting element ED1, the bank layers BN1 and BN2, the capping layer CAP, and the trace pattern. Specifically, the first inorganic material layer TLL1 may be formed on the top surface of the first common electrode CE1, the side surface of the first bank layer BN1, the bottom surface of the second bank layer BN2, the top surface of the third bank layer BN3, and the top surface of the trace pattern.

[0183] refer to Fig.17 , a photoresist PR as a mask pattern may be formed on the first inorganic material layer TLL1, and according to Figure 8 In step S80, a sixth etching process (sixth etching) for removing the first inorganic material layer TLL1 and the trace pattern that may not be covered by the mask pattern may be performed. The photoresist PR may be disposed to overlap the first emission region EA1 and an edge region surrounding the first emission region EA1.

[0184] In an embodiment, the sixth etching process may be dry etching using a fluorine-based gas. Although the bottom surface of the tip TIP of the second bank layer BN2 of the second emission area EA2 and the third emission area EA3 may be exposed to the fluorine-based gas, the zinc (Zn) of the second bank layer BN2 may be stable and not react with the fluorine-based gas. Despite repeated etching processes, the shape of the tip TIP may be maintained without being damaged.

[0185] Next, the photoresist PR may be removed, and the Fig.16 The second light emitting element ED2 and the second inorganic layer TL2 may be formed on the second emission region EA2 by a process similar to the process of the first emission region EA1, and a trace pattern may be formed on the third bank layer BN3. The second light emitting layer EL2, the second common electrode CE2, the capping layer CAP and the second inorganic material layer may be formed on the first inorganic layer TL1 on the first emission region EA1. Fig.17 As shown in FIG. 1 , a photoresist PR as a mask pattern may be formed to overlap the second emission area EA2. The process of removing the second inorganic material layer and the trace pattern that may not be covered by the mask pattern may be repeated to obtain a second inorganic material layer as shown in FIG. Fig.18 The second light emitting element ED2 and the second trace pattern TRP2 are shown in FIG.

[0186] Although not shown in the drawings, the display device 10 may be manufactured by forming an organic encapsulation layer TFE2 and a second inorganic encapsulation layer TFE3 of a thin film encapsulation layer TFEL, a light blocking layer BM, a color filter layer CFL, and an overcoat layer OC on the light emitting elements ED1, ED2, and ED3 and the dam structure BNS. The description of the structures of the thin film encapsulation layer TFEL, the light blocking layer BM, the color filter layer CFL, and the overcoat layer OC may be the same as described above, so that a detailed description thereof will be omitted.

[0187] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications can be made to the embodiments without departing substantially from the principles of the invention. Therefore, the disclosed embodiments of the present disclosure may be used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, wherein: The display device comprises: A first pixel electrode is disposed on the substrate; a pixel defining layer, disposed on the substrate and exposing the first pixel electrode; A first light-emitting layer is disposed on the first pixel electrode; A first common electrode, disposed on the first light-emitting layer; A first bank layer is disposed on the pixel defining layer; a second bank layer disposed on the first bank layer and including a side surface protruding from a side surface of the first bank layer; and a third bank layer disposed on the second bank layer and including a side surface protruding from the side surface of the first bank layer, wherein The second bank layer and the third bank layer each include a transparent conductive oxide, and The second bank layer also includes zinc.

2. The display device according to claim 1, wherein: The third bank layer further includes hydrogen.

3. The display device according to claim 1, wherein: A ratio of zinc in the second bank layer relative to the total number of atoms is in a range of 5 at % to 50 at %.

4. The display device according to claim 1, wherein: The side surface of the second bank layer and the side surface of the third bank layer are aligned with each other in a plan view.

5. The display device according to claim 1, wherein: The second bank layer and the third bank layer are amorphous, and A combined visible light transmittance of the second bank layer and the third bank layer is 85% or more.

6. The display device according to claim 1, wherein: The third bank layer includes hydrogen and indium tin oxide.

7. The display device according to claim 1, wherein: The thickness of the third bank layer is greater than the thickness of the second bank layer.

8. The display device according to claim 1, wherein: The sum of the thickness of the second bank layer and the thickness of the third bank layer is to within the range.

9. The display device according to claim 1, wherein: The first bank layer includes metal.

10. The display device according to claim 1, wherein: The first common electrode contacts the first bank layer.

11. The display device according to claim 1, wherein: The thickness of the first bank layer is to within the range.

12. The display device according to claim 1, wherein: The display device further includes: a first organic pattern disposed on the third bank layer, wherein the first organic pattern and the first light emitting layer comprise the same material; and a first electrode pattern disposed on the first organic pattern, wherein the first electrode pattern and the first common electrode comprise the same material, wherein: The first light emitting layer and the first organic pattern are spaced apart from each other, and The first common electrode and the first electrode pattern are spaced apart from each other.

13. A display device, wherein: The display device comprises: A first pixel electrode is disposed on the substrate; a pixel defining layer, disposed on the substrate and exposing the first pixel electrode; A first light-emitting layer is disposed on the first pixel electrode; A first common electrode, disposed on the first light-emitting layer; A first bank layer is disposed on the pixel defining layer; a second bank layer disposed on the first bank layer and including a side surface protruding from a side surface of the first bank layer; and a third bank layer disposed on the second bank layer and including a side surface protruding from the side surface of the first bank layer, wherein The thickness of the first bank layer is greater than the sum of the thickness of the second bank layer and the thickness of the third bank layer, and The thickness of the third bank layer is greater than the thickness of the second bank layer.

14. The display device according to claim 13, wherein The first bank layer includes an opaque metal, and The second bank layer and the third bank layer each include a transparent conductive oxide.

15. The display device according to claim 13, wherein: The thickness of the first bank layer is greater than or equal to three times the sum of the thickness of the second bank layer and the thickness of the third bank layer.

16. The display device according to claim 13, wherein: The display device further includes: a second pixel electrode disposed on the substrate, wherein the second pixel electrode and the first pixel electrode are spaced apart from each other; A second light emitting layer is disposed on the second pixel electrode; a second common electrode disposed on the second light-emitting layer, wherein the second common electrode and the first common electrode are spaced apart from each other; a first inorganic layer disposed on each of the first common electrode and the third bank layer; and A second inorganic layer is disposed on each of the second common electrode and the third bank layer, wherein: The first inorganic layer and the second inorganic layer are spaced apart from each other, A portion of the third bank layer is exposed in a separation space between the first inorganic layer and the second inorganic layer, and A thickness of the second bank layer overlapping with the first inorganic layer is equal to a thickness of the second bank layer overlapping with the second inorganic layer.

17. A method for manufacturing a display device, wherein: The method comprises: forming a plurality of pixel electrodes spaced apart from each other on a substrate; forming a sacrificial layer on the plurality of pixel electrodes; forming a pixel defining material layer on the sacrificial layer; forming a first bank material layer on the pixel definition material layer; forming a second bank material layer on the first bank material layer; forming a third bank material layer on the second bank material layer; etching the second bank material layer and the third bank material layer in a region overlapping with the plurality of pixel electrodes; etching the first bank material layer in the region overlapping with the plurality of pixel electrodes; etching a side surface of the first bank material layer to partially expose a bottom surface of the second bank material layer; etching the pixel defining material layer; etching the sacrificial layer to expose the plurality of pixel electrodes; forming a first light emitting layer on one of the plurality of pixel electrodes; forming a first common electrode on the first light emitting layer; and A first inorganic material layer is formed on the first common electrode.

18. The method according to claim 17, wherein The forming of the third bank material layer on the second bank material layer includes performing sputtering in a mixed gas atmosphere including hydrogen and argon, and The third bank material layer includes hydrogen and indium tin oxide.

19. The method according to claim 17, wherein The etching of the second bank material layer and the third bank material layer in the region overlapping the plurality of pixel electrodes includes exposing a portion of the first bank material layer by removing the second bank material layer and the third bank material layer through a wet etching technique, and The etching of the first bank material layer in the region overlapping the plurality of pixel electrodes includes removing the exposed portion of the first bank material layer by a dry etching technique.

20. The method according to claim 17, wherein: The forming of the first light emitting layer on the one pixel electrode among the plurality of pixel electrodes comprises forming a first organic pattern material layer on the third bank material layer, the first organic pattern material layer being spaced apart from the first light emitting layer, The forming of the first common electrode on the first light emitting layer includes forming a first electrode pattern material layer on the first organic pattern material layer, the first electrode pattern material layer being spaced apart from the first common electrode, and The forming of the first inorganic material layer on the first common electrode includes forming the first inorganic material layer seamlessly connected to the first common electrode and the first electrode pattern material layer.

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