Display apparatus and method of manufacturing same

Abstract

A display apparatus and a method of manufacturing the same are provided. The display device includes: a substrate; a transistor disposed on the substrate; a via layer disposed over the transistor and including a contact hole extending to the transistor; a pixel electrode disposed on the via layer and connected to the transistor through the contact hole; a first bank layer disposed on the pixel electrode and extending in a first direction, and a second bank layer extending in a second direction crossing the first direction; a light emitting layer disposed on the pixel electrode; and a common electrode disposed on the light emitting layer, in which the second bank layer includes a first region that does not overlap with the contact hole and a second region that overlaps with the contact hole, and in which a width of the second region is greater than a width of the first region.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0002] As the information-oriented society develops, the demand for display devices continues to increase. For example, display devices are used by various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. The light-emitting display device includes an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and a micro-light-emitting display device including a micro-light-emitting element.

[0004] The organic light emitting element may include two electrodes with a light emitting layer interposed therebetween. Electrons and holes provided from the two electrodes are recombined in the light emitting layer to generate excitons, and the generated excitons are converted from an excited state to a ground state, thereby emitting light.

[0005] An organic light emitting display device including an organic light emitting element does not require a separate light source such as a backlight unit, and therefore, it consumes less power and can be light and thin, and exhibits desired characteristics such as a wide viewing angle, high brightness and contrast, and a fast response speed. Therefore, the organic light emitting display device is attracting attention as a next-generation display device. Summary of the invention

[0006] Aspects of the present disclosure provide a display device that can suppress reflection of external light and a method of manufacturing the display device.

[0007] It should be noted that the objects of the present disclosure are not limited to the above objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0008] According to one aspect of the present disclosure, a display device includes: a substrate; a transistor disposed on the substrate; a through-hole layer disposed above the transistor and including a contact hole extending to the transistor; a pixel electrode disposed on the through-hole layer and connected to the transistor through the contact hole; a first embankment layer and a second embankment layer, the first embankment layer being disposed on the pixel electrode and extending in a first direction, and the second embankment layer extending in a second direction intersecting the first direction; a light-emitting layer disposed on the pixel electrode; and a common electrode disposed on the light-emitting layer, wherein the second embankment layer includes a first area that does not overlap with the contact hole and a second area that overlaps with the contact hole, and wherein a width of the second area is greater than a width of the first area.

[0009] In an embodiment, the second region of the second bank layer overlaps the first bank layer.

[0010] In an embodiment, a distance from the contact hole to an edge of the second region is equal to or greater than 5 μm.

[0011] In an embodiment, a thickness of the second bank layer is greater than a thickness of the first bank layer.

[0012] In an embodiment, an angle between one side of the first region and one side of the second region contacting the one side of the first region is 90 degrees.

[0013] In an embodiment, an angle between one side of the first region and one side of the second region contacting the one side of the first region is greater than 90 degrees.

[0014] In an implementation, the second bank layer includes a light blocking material.

[0015] In an embodiment, the first bank layer has a thickness of 0.1 to 0.5 μm.

[0016] In an embodiment, the second bank layer has a thickness of 1 to 10 μm.

[0017] In an embodiment, the first bank layer has a water contact angle greater than zero and less than 90 degrees.

[0018] In an embodiment, the second bank layer has a water contact angle greater than 90 degrees and less than 180 degrees.

[0019] According to one aspect of the present disclosure, a display device includes: a substrate; a transistor disposed on the substrate; a through-hole layer disposed above the transistor and having a contact hole exposing the transistor; a pixel electrode disposed on the through-hole layer and connected to the transistor through the contact hole; a dam layer disposed on the pixel electrode; a light-emitting layer disposed on the pixel electrode; and a common electrode disposed on the light-emitting layer, wherein the dam layer includes a first dam portion that does not overlap with the contact hole and a second dam portion that overlaps with the contact hole, and wherein a width of the second dam portion is greater than a width of the first dam portion.

[0020] In an embodiment, a thickness of the second bank portion is greater than a thickness of the first bank portion.

[0021] In an embodiment, the bank layer includes a light blocking material.

[0022] In an embodiment, the bank layer has a water contact angle greater than 90 degrees and less than 180 degrees.

[0023] In an embodiment, the first bank portion has a thickness of 0.1 to 0.5 μm.

[0024] In an embodiment, the second bank portion has a thickness of 1 to 10 μm.

[0025] In an embodiment, the first bank portion and the second bank portion are formed as one body.

[0026] According to one aspect of the present disclosure, a method for manufacturing a display device includes: forming a transistor and a via layer on a substrate; etching the via layer to form a contact hole exposing the transistor; forming a pixel electrode on the via layer connected to the transistor through the contact hole; applying a dam material layer on the pixel electrode and using a mask to form a dam layer, the dam layer including a first dam portion that does not overlap with the contact hole and a second dam portion that overlaps with the contact hole; forming a light-emitting layer on the pixel electrode; and forming a common electrode on the light-emitting layer, wherein a width of the second dam portion is greater than a width of the first dam portion.

[0027] In an embodiment, the mask includes a light blocking portion, a transmissive portion and a semi-transparent portion, and wherein a portion of the embankment material layer in line with the transmissive portion is formed as a second embankment portion, and a portion of the embankment material layer in line with the semi-transparent portion is formed as a first embankment portion.

[0028] According to an embodiment of the present disclosure, the second bank layer or the second bank portion is disposed such that they overlap with a contact hole in a display device, thereby preventing light incident from the outside from being reflected by a pixel electrode disposed in the contact hole.

[0029] It should be noted that the effects of the present disclosure are not limited to those described above, and other effects of the present disclosure will be apparent to those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0031] Figure 1 is a plan view schematically showing a display device according to an embodiment of the present disclosure.

[0032] Figure 2 is a cross-sectional view schematically showing a display device according to an embodiment.

[0033] Figure 3 is a plan view schematically showing a circuit layer of a display device according to an embodiment of the present disclosure.

[0034] Figure 4 is an equivalent circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0035] Figure 5 is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0036] Figure 6 is a plan view showing a layout of pixels of a display device according to an embodiment of the present disclosure.

[0037] Figure 7 is a plan view showing a first bank of a display device according to an embodiment.

[0038] Figure 8 is a plan view showing a second bank of a display device according to an embodiment.

[0039] Fig. 9 It is along Figure 6 A cross-sectional view taken along line Q1-Q1'.

[0040] Fig.10 It is along Figure 6 A cross-sectional view taken along line Q2-Q2'.

[0041] Fig.11 It is along Figure 6 A cross-sectional view taken along line Q3-Q3'.

[0042] Fig.12 is a plan view schematically illustrating a contact hole and a second bank layer according to an embodiment.

[0043] Fig.13 is a plan view schematically showing a contact hole and a second bank layer according to another embodiment.

[0044] Fig.14 is a plan view schematically showing a contact hole and a second bank layer according to still another embodiment.

[0045] Fig.15 , Fig.16 , Fig.17 , Fig.18 and Fig.19 are cross-sectional views illustrating process steps of a method of manufacturing a display device according to an embodiment of the present disclosure.

[0046] Fig. 20 is a plan view showing a layout of pixels of a display device according to an embodiment of the present disclosure.

[0047] Fig.21 is a plan view showing a bank layer of a display device according to an embodiment of the present disclosure.

[0048] Fig. 22 It is along Fig. 20 A cross-sectional view taken along line Q4-Q4'.

[0049] Fig.23 It is along Fig. 20 A cross-sectional view taken along line Q5-Q5'.

[0050] Fig.24 and Fig.25are cross-sectional views illustrating process steps of a method of manufacturing a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] The inventive concept will now be described more fully below with reference to the accompanying drawings, in which embodiments of the inventive concept are shown. However, the inventive concept may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0052] It will be understood that when a first layer is referred to as being 'on' a second layer or substrate, the first layer may be directly on the second layer or substrate, or intervening layers may be present. Throughout the specification, the same reference numerals refer to the same components.

[0053] It will be understood that although ordinal terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited to any order by these terms. These terms are used to distinguish one element from another and are interchangeable. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0054] Each of the features of the various embodiments of the present disclosure can be combined or combined with each other in part or in whole, and various interconnections and drives are possible in technology. Each embodiment can be implemented independently of each other, or can be implemented together in association.

[0055] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0056] Figure 1 is a plan view schematically showing a display device according to an embodiment of the present disclosure.

[0057] refer to Figure 1 The display device 10 according to the embodiment of the present disclosure can be applied to smart phones, mobile phones, tablet PCs, personal digital assistants (PDAs), portable multimedia players (PMPs), television sets, game consoles, watch-type electronic devices, head-mounted displays, personal computer displays, laptop computers, car navigation systems, car instrument clusters, digital cameras, video cameras, outdoor billboards, electronic billboards, various medical devices, various home appliances (such as refrigerators and washing machines), Internet of Things (IoT) devices, etc. In the following description, a TV is described as an example of the display device 10. The TV may have a high resolution or ultra-high resolution such as HD, UHD, 4K, and 8K.

[0058] The display device 10 according to the embodiment can be classified differently by the way of displaying an image. Examples of the classification of the display device 10 may include an organic light-emitting display device (OLED), an inorganic light-emitting display device (inorganic EL), a quantum dot light-emitting display device (QED), a micro-LED display device (micro-LED), a nano-LED display device (nano-LED), a plasma display device (PDP), a field emission display device (FED), a cathode ray display device (CRT), a liquid crystal display device (LCD), an electrophoretic display device (EPD), etc. In the following description, an organic light-emitting display device and an inorganic light-emitting display device will be described as examples of the display device 10, and the organic light-emitting display device and the inorganic light-emitting display device will be simply referred to as a display device unless it is necessary to distinguish them. However, it should be understood that the embodiments of the present disclosure are not limited thereto, and any other display device listed above or known in the art may be adopted without departing from the scope of the present disclosure.

[0059] A first direction DR1, a second direction DR2, and a third direction DR3 are defined in the drawings. A display device 10 according to an embodiment of the present disclosure will be described with reference to the drawings. The first direction DR1 may be perpendicular to the second direction DR2. The third direction DR3 may be perpendicular to a plane defined by the first direction DR1 and the second direction DR2. The third direction DR3 may be perpendicular to each of the first direction DR1 and the second direction DR2. In the following description of the display device 10 according to an embodiment of the present disclosure, the third direction DR3 refers to a thickness direction of the display device 10.

[0060] When viewed from the top, the display device 10 may have a rectangular shape including a longer side in the first direction DR1 and a shorter side in the second direction DR2. Although the corners where the longer side and the shorter side of the display device 10 intersect may form a right angle, this is merely illustrative. The display device 10 may have rounded corners. When viewed from the top, the shape of the display device 10 is not limited to the shape shown. The display device 10 may have other shapes, such as a square, a rectangle with rounded corners (vertices), other polygons, and a circle.

[0061] The display surface may be located on one side of the third direction DR3 (i.e., thickness direction) of the display device 10. In the following description, the upper side of the display device 10 refers to the surface on which the image is displayed, and the upper surface of the display device 10 refers to the surface facing the positive third direction DR3, unless otherwise specifically stated. "Positive third direction DR3" refers to the direction in which the arrow points to the DR3 axis in the coordinates shown. "Negative third direction DR3" refers to the direction opposite to the direction in which the arrow points to the DR3 axis in the coordinates shown. The lower portion refers to the portion facing the negative third direction DR3, and similarly, the lower surface refers to the surface facing the negative third direction DR3. As used herein, the terms "left" side, "right" side, "upper" side, and "lower" side refer to the relative positions when the display device 10 is observed from the top. For example, the right side refers to one side in the first direction DR1, the left side refers to the other side in the first direction DR1, the upper side refers to one side in the second direction DR2, and the lower side refers to the other side in the second direction DR2.

[0062] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA may refer to an active area where an image is displayed, and the non-display area NDA may refer to a non-active area where an image is not displayed.

[0063] The shape of the display area DPA may be similar to the overall shape of the display device 10. For example, when viewed from the top, the display area DPA may have a rectangular shape. The display area DPA may occupy approximately the center of the display device 10.

[0064] The display area DPA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix. When viewed from the top, the shape of each of the pixels PX may be a rectangle or a square. However, it should be understood that the present disclosure is not limited thereto. The shape of each of the pixels PX may have a rhombus shape having sides inclined relative to one direction. The pixels PX may be arranged alternately in a stripe pattern or a pattern.

[0065] The non-display area NDA may be disposed around the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. The display area DPA may have a rectangular shape, and the non-display area NDA may be adjacent to four sides of the display area DPA. The non-display area NDA may form a frame of the display device 10.

[0066] In the non-display area NDA, a driving circuit or a driving element for driving the display area DPA may be provided. The non-display area NDA may include a first non-display area NDA1, a second non-display area NDA2, a third non-display area NDA3, and a fourth non-display area NDA4. According to an embodiment of the present disclosure, the pad area is provided so as to be aligned with the first longer side ( Figure 1 The first non-display area NDA1 adjacent to the lower side of the display device 10 and the second longer side ( Figure 1 The display substrate of the display device 10 is provided in a second non-display area NDA2 adjacent to the upper side of the display device 10. The external device EXD may be mounted on the pad electrode of the pad area. Examples of the external device EXD may include a connection layer, a printed circuit board, a driver chip DIC, a connector, a wire connection layer, etc. The scan driver SDR directly formed on the display substrate of the display device 10 may be provided in a first shorter side ( Figure 1 In the third non-display area NDA3 adjacent to the left side of the display.

[0067] Figure 2 is a cross-sectional view schematically showing a display device according to an embodiment. Figure 3 is a plan view schematically showing a circuit layer of a display device according to an embodiment of the present disclosure. Figure 4 is an equivalent circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0068] refer to Figure 2 According to an embodiment of the present disclosure, a display device 10 may include a substrate SUB, a circuit layer CIL disposed on the substrate SUB, an emission material layer EML disposed on the circuit layer CIL, an encapsulation layer TFE disposed on the emission material layer EML, a color conversion layer CCL disposed on the encapsulation layer TFE, and an optical function layer LFL disposed on the color conversion layer CCL.

[0069] refer to Figure 3 The circuit layer CIL may include a plurality of lines on the substrate SUB. The plurality of lines may include a scan line SCL, a sensing signal line SSL, a data line DTL, a reference voltage line RVL, a first power voltage line ELVDL, and the like.

[0070] The scan lines SCL and the sensing signal lines SSL may extend in the first direction DR1. The scan lines SCL and the sensing signal lines SSL may be connected to a scan driver SDR. The scan driver SDR may include a driver circuit formed by a circuit layer CIL. The scan driver SDR may be disposed in the third non-display area NDA3 on the substrate SUB, but the present disclosure is not limited thereto. The scan driver SDR may be disposed in the fourth non-display area NDA4, or in both the third non-display area NDA3 and the fourth non-display area NDA4. The scan driver SDR may be connected to a signal connection line CWWL. At least one end of the signal connection line CWWL may form a pad WPD_CW in the first non-display area NDA1 and / or the second non-display area NDA2, and may be connected to an external device EXD (see Figure 1 ).

[0071] The data line DTL and the reference voltage line RVL may extend in a second direction DR2 crossing the first direction DR1. The first power voltage line ELVDL may include a portion extending in the second direction DR2. The first power voltage line ELVDL may also include a portion extending in the first direction DR1. The first power voltage line ELVDL may have, but is not limited to, a mesh structure.

[0072] The wiring pad WPD may be disposed at at least one end of the data line DTL, the reference voltage line RVL, and the first power voltage line ELVDL. The wiring pad WPD may be disposed in the pad area PDA of the first non-display area NDA1. According to an embodiment of the present disclosure, the wiring pad WPD_DT of the data line DTL (hereinafter referred to as the data pad) may be disposed in the pad area PDA of the first non-display area NDA1. The wiring pad WPD_RV of the reference voltage line RVL (hereinafter referred to as the reference voltage pad) and the wiring pad WPD_ELVD of the first power voltage line ELVDL (hereinafter referred to as the first power voltage pad) may be disposed in the pad area PDA of the second non-display area NDA2. As another example, the data pad WPD_DT, the reference voltage pad WPD_RV, and the first power voltage pad WPD_ELVD may all be disposed in the same area (e.g., the first non-display area NDA1). As described above, the external device EXD (see Figure 1 ) can be mounted on the wiring pad WPD. The external device EXD can be mounted on the wiring pad WPD through an anisotropic conductive layer, ultrasonic bonding, etc.

[0073] Each of the pixels PX on the substrate SUB includes a plurality of sub-pixels, and each of the plurality of sub-pixels includes a pixel driver circuit. The above-mentioned line may extend around each of the pixels PX or sub-pixels to apply a drive signal to the pixel driver circuit. The pixel driver circuit may include a transistor and a capacitor. The number of transistors and capacitors of each pixel driver circuit may be changed in various ways. In the following description, as an example, a pixel driver circuit having a 3T1C structure including three transistors and one capacitor will be described. However, it should be understood that the present disclosure is not limited thereto. Various modifications having other structures (such as a 2T1C structure, a 7T1C structure, and a 6T1C structure) may be adopted.

[0074] Figure 4 is an equivalent circuit diagram of a sub-pixel of a display device according to an embodiment of the present disclosure.

[0075] refer to Figure 4 , each of the pixels PX of the display device 10 according to the embodiment includes a plurality of sub-pixels, and each of the sub-pixels includes three transistors DTR, STR1, and STR2 and one storage capacitor CST in addition to the light emitting element ED.

[0076] The light emitting element ED emits light having brightness proportional to the current supplied through the driving transistor DTR. The light emitting element ED may be implemented as an organic light emitting diode, a micro light emitting diode, a nano light emitting diode, or the like.

[0077] A first electrode (i.e., a pixel electrode) of the light emitting element ED can be connected to a source electrode of the driving transistor DTR, and a second electrode (i.e., a common electrode) thereof can be connected to a second power supply voltage line ELVSL, from which a low-level voltage (second power supply voltage) lower than a high-level voltage (first power supply voltage) of the first power supply voltage line ELVDL is applied.

[0078] The driving transistor DTR adjusts the current flowing from the first power supply voltage line ELVDL (from which the first power supply voltage is applied) to the light emitting element ED according to the voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DTR can be connected to the first source / drain electrode of the switching transistor STR1, its source electrode can be connected to the first electrode of the light emitting element ED, and its drain electrode can be connected to the first power supply voltage line ELVDL from which the first power supply voltage is applied.

[0079] The switching transistor STR1 is turned on by the scanning signal of the scanning line SCL to connect the data line DTL with the gate electrode of the driving transistor DTR. The gate electrode of the switching transistor STR1 can be connected to the scanning line SCL, its first source / drain electrode can be connected to the gate electrode of the driving transistor DTR, and its second source / drain electrode can be connected to the data line DTL.

[0080] The sensing transistor STR2 can be turned on by the sensing signal of the sensing signal line SSL to connect the reference voltage line RVL to the source electrode of the driving transistor DTR. The gate electrode of the sensing transistor STR2 can be connected to the sensing signal line SSL, its first source / drain electrode can be connected to the reference voltage line RVL, and its second source / drain electrode can be connected to the source electrode of the driving transistor DTR.

[0081] According to an embodiment of the present disclosure, the first source / drain electrode of each of the switch transistor STR1 and the sensing transistor STR2 may be a source electrode, and the second source / drain electrode thereof may be a drain electrode. However, it should be understood that the present disclosure is not limited thereto. The first source / drain electrode of each of the switch transistor STR1 and the sensing transistor STR2 may be a drain electrode, and the second source / drain electrode thereof may be a source electrode.

[0082] The storage capacitor CST may be formed between the gate electrode and the source electrode of the driving transistor DTR. The storage capacitor CST stores a voltage difference between a gate voltage and a source voltage of the driving transistor DTR.

[0083] The driving transistor DTR, the switching transistor STR1, and the sensing transistor STR2 may be implemented as thin film transistors. Figure 4 In the example shown in , the driving transistor DTR, the switching transistor STR1, and the sensing transistor STR2 are implemented as n-type metal oxide semiconductor field effect transistors (MOSFETs), but it should be noted that the present disclosure is not limited thereto. Specifically, the driving transistor DTR and the switching transistor STR1 and the sensing transistor STR2 can be implemented as p-type MOSFETs, or some of them can be implemented as n-type MOSFETs, while the other transistors can be implemented as p-type MOSFETs.

[0084] Hereinafter, the structure of the display area DPA of the display device 10 will be described in more detail.

[0085] Figure 5 is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0086] refer to Figure 5The display device 10 may include a substrate SUB, a circuit layer CIL disposed on the substrate SUB, an emission material layer EML disposed on the circuit layer CIL, an encapsulation layer TFE disposed on the emission material layer EML, and a color conversion layer CCL disposed on the encapsulation layer TFE.

[0087] The substrate SUB may be an insulating substrate. The substrate SUB may include a transparent material. For example, the substrate SUB may include a transparent insulating material such as glass and quartz. The substrate SUB may be a rigid substrate. However, the substrate SUB is not limited to those described above. The substrate SUB may include a plastic such as polyimide, or may be flexible so that it can be bent, curved, folded, or curled. A plurality of emission areas LA1, LA2, and LA3 and a non-emission area NLA may be defined in the substrate SUB.

[0088] The circuit layer CIL may be disposed on the substrate SUB. The circuit layer CIL may include switching elements T1, T2, and T3. According to an embodiment of the present disclosure, the first switching element T1 may be located in the first emission area LA1 of the substrate SUB, the second switching element T2 may be located in the second emission area LA2, and the third switching element T3 may be located in the third emission area LA3. However, it should be understood that the present disclosure is not limited thereto. In other embodiments, at least one of the first switching element T1, the second switching element T2, and the third switching element T3 may be located in the non-emission area NLA.

[0089] According to an embodiment of the present disclosure, each of the first switching element T1, the second switching element T2, and the third switching element T3 may be a thin film transistor including amorphous silicon, polycrystalline silicon, or an oxide semiconductor. Figure 3 The plurality of signal lines (e.g., gate lines, data lines, power lines, etc.) described above may be further disposed on the substrate SUB. In addition, the switching elements T1, T2, and T3 may include a first insulating layer 120. For example, the first insulating layer 120 may be a gate insulator or an interlayer dielectric layer of a thin film transistor. The gate insulator or the interlayer dielectric layer may include silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and silicon nitride (SiN x ) or a multilayer structure including multiple layers of the above materials.

[0090] The second insulating layer 130 may be disposed on the first switching element T1, the second switching element T2, and the third switching element T3. According to an embodiment of the present disclosure, the second insulating layer 130 may be a planarization layer. According to an embodiment of the present disclosure, the second insulating layer 130 may be formed as an organic layer. For example, the second insulating layer 130 may include an acrylic resin, an epoxy resin, an imide resin, an ester resin, etc. According to an embodiment of the present disclosure, the second insulating layer 130 may include a positive photoresist or a negative photoresist.

[0091] The emission material layer EML may be disposed on the second insulating layer 130. The emission material layer EML may include pixel electrodes AE1, AE2, and AE3, a light emitting layer OL, and a common electrode CE. In addition, the emission material layer EML may further include a bank layer 150.

[0092] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second insulating layer 130. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1, a second pixel electrode AE2, and a third pixel electrode AE3. The first pixel electrode AE1 may be disposed in the first emission area LA1 and may extend at least partially to the non-emission area NLA. The second pixel electrode AE2 may be disposed in the second emission area LA2 and may extend at least partially to the non-emission area NLA. The third pixel electrode AE3 may be disposed in the third emission area LA3 and may extend at least partially to the non-emission area NLA. The first pixel electrode AE1 may be connected to the first switching element T1 through the second insulating layer 130, the second pixel electrode AE2 may be connected to the second switching element T2 through the second insulating layer 130, and the third pixel electrode AE3 may be connected to the third switching element T3 through the second insulating layer 130.

[0093] According to an embodiment of the present disclosure, the widths or areas of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be different from each other. For example, the width of the first pixel electrode AE1 may be smaller than the width of the second pixel electrode AE2, and the width of the third pixel electrode AE3 may be smaller than the width of the second pixel electrode AE2, and may be larger than the width of the first pixel electrode AE1. Alternatively, the width of the first pixel electrode AE1 may be smaller than the width of the second pixel electrode AE2, and the width of the third pixel electrode AE3 may be smaller than the width of the second pixel electrode AE2, and may be smaller than the width of the first pixel electrode AE1. Alternatively, the width of the first pixel electrode AE1 may be smaller than the width of the second pixel electrode AE2, and the width of the third pixel electrode AE3 may be larger than the width of the second pixel electrode AE2 and the width of the first pixel electrode AE1. However, it should be understood that the present disclosure is not limited to the above-mentioned embodiment. According to another embodiment of the present disclosure, the widths or areas of the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be substantially all equal.

[0094] The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be reflective electrodes. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may have a material layer having a high work function (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium oxide (In 2 O 3 )) and a stacked structure of a reflective material layer (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof). The material layer with a high work function may be disposed on a layer higher than the reflective material layer so that it may be closer to the light emitting layer OL. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may have, but are not limited to, a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, and ITO / Ag / ITO.

[0095] The bank layer 150 may be located on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The bank layer 150 may include an opening extending to the first pixel electrode AE1, an opening extending to the second pixel electrode AE2, and an opening extending to the third pixel electrode AE3, and may define a first emission area LA1, a second emission area LA2, a third emission area LA3, and a non-emission area NLA. Specifically, an area of ​​the first pixel electrode AE1 that is not covered by the bank layer 150 and is exposed may be the first emission area LA1. An area of ​​the second pixel electrode AE2 that is not covered by the bank layer 150 and is exposed may be the second emission area LA2. An area of ​​the third pixel electrode AE3 that is not covered by the bank layer 150 and is exposed may be the third emission area LA3. Another area where the bank layer 150 is located may be the non-emission area NLA. The bank layer 150 may overlap with the light blocking layer BM of the color conversion layer CCL to be described later.

[0096] The light-emitting layer OL may be disposed on the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. In an embodiment in which the display device 10 is an organic light-emitting display device, the light-emitting layer OL may include an organic layer including an organic material. The organic layer includes an organic light-emitting layer, and in some implementations may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer as an auxiliary layer to promote light emission. According to an embodiment of the present disclosure, the light-emitting layer OL may have a column structure including a plurality of organic light-emitting layers overlapping each other in a thickness direction and a charge generation layer disposed therebetween. The organic light-emitting layers overlapping each other may emit light of the same wavelength or light of different wavelengths.

[0097] According to an embodiment of the present disclosure, the light emitting layer OL may be respectively disposed in each of the plurality of emission regions LA1, LA2, and LA3. The wavelengths of light emitted from the light emitting layer OL may be the same. For example, the light emitting layer OL may emit blue light or ultraviolet light from the plurality of emission regions LA1, LA2, and LA3.

[0098] The common electrode CE may be disposed on the light emitting layer OL. According to an embodiment of the present disclosure, the common electrode CE may be translucent or transmissive. If the common electrode CE is translucent, the common electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, or a compound or mixture thereof (e.g., a mixture of Ag and Mg), or a material having a multilayer structure such as LiF / Ca or LiF / Al. In addition, if the thickness of the common electrode CE is in the range of tens to hundreds of angstroms, the common electrode CE may be translucent.

[0099] When the common electrode CE is transmissive, the common electrode CE may include a transparent conductive oxide (TCO). For example, the common electrode CE may be made of tungsten oxide (W x O y ), titanium oxide (TiO 2 ), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), magnesium oxide (MgO), etc.

[0100] The first pixel electrode AE1, the light emitting layer OL, and the common electrode CE may form a first light emitting element ED1, the second pixel electrode AE2, the light emitting layer OL, and the common electrode CE may form a second light emitting element ED2, and the third pixel electrode AE3, the light emitting layer OL, and the common electrode CE may form a third light emitting element ED3. Each of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may emit source light. The source light may be provided to the color conversion layer CCL. The first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 may be organic light emitting diodes.

[0101] The encapsulation layer TFE may be disposed on the common electrode CE. The encapsulation layer TFE may be positioned to commonly cross the first emission area LA1, the second emission area LA2, the third emission area LA3, and the non-emission area NLA. According to an embodiment of the present disclosure, the encapsulation layer TFE may directly cover the common electrode CE.

[0102] According to an embodiment of the present disclosure, the encapsulation layer TFE may include a first inorganic encapsulation layer 171 , an organic encapsulation layer 173 , and a second inorganic encapsulation layer 175 sequentially stacked on the common electrode CE.

[0103] Each of the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 175 may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, silicon oxynitride (SiON), lithium fluoride, etc. The organic encapsulation layer 173 may include at least one of acrylic resin, methacrylate-based resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, and perylene resin. It should be noted that the structure of the encapsulation layer TFE is not limited to the above examples. The stacking structure of the encapsulation layer TFE can be changed in various ways.

[0104] The color conversion layer CCL may be disposed on the encapsulation layer TFE. The color conversion layer CCL may include a light blocking layer BM and a color filter layer 210.

[0105] The light blocking layer BM may be disposed on the encapsulation layer TFE. The light blocking layer BM may be disposed so that it overlaps with the bank layer 150 of the emission material layer EML. The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be, but is not limited to, carbon black, and the organic black pigment may include, but is not limited to, at least one of lactam black, perylene black, and aniline black. The light blocking layer BM may prevent visible light penetration and color mixing between the first emission area LA1, the second emission area LA2, and the third emission area LA3 to improve the color gamut of the display device 10.

[0106] The color filter layer 210 may be disposed on the light blocking layer BM and the encapsulation layer TFE. The color filter layer 210 may include a first color filter 211, a second color filter 213, and a third color filter 215.

[0107] The first color filter 211 may be located on the encapsulation layer TFE and may overlap the first emission area LA1. In addition, the first color filter 211 may overlap the first light emitting element ED1.

[0108] The first color filter 211 can selectively transmit light of a first color (e.g., blue light), and can block or absorb light of a second color (e.g., red light) and light of a third color (e.g., green light). According to an embodiment of the present disclosure, the first color filter 211 can be a blue color filter, and can include a blue colorant, such as a blue dye and a blue pigment. As used herein, a colorant encompasses a dye as well as a pigment.

[0109] The second color filter 213 may overlap the second emission area LA2 and may overlap the second light emitting element ED2. According to an embodiment of the present disclosure, one side of the second color filter 213 may overlap the non-emission area NLA and overlap a portion of the adjacent first color filter 211. The opposite side of the second color filter 213 may overlap the non-emission area NLA and overlap a portion of the adjacent third color filter 215.

[0110] The second color filter 213 may block or absorb light of the first color (e.g., blue light) and light of the third color (e.g., green light). The second color filter 213 may selectively transmit light of the second color (e.g., red light). For example, the second color filter 213 may be a red color filter and may include a red colorant such as a red dye and a red pigment.

[0111] The third color filter 215 may overlap the third emission area LA3 and may overlap the third light emitting element ED3. According to an embodiment of the present disclosure, one side of the third color filter 215 may overlap the non-emission area NLA and overlap a portion of the adjacent second color filter 213. In addition, the opposite side of the third color filter 215 may overlap the non-emission area NLA and overlap a portion of the adjacent first color filter 211.

[0112] The third color filter 215 may block or absorb the light of the first color and the light of the second color. The third color filter 215 may selectively transmit the light of the third color. For example, the third color filter 215 may be a green color filter and may include a green colorant such as a green dye and a green pigment.

[0113] The color conversion layer CCL may further include an overcoat layer 220. The overcoat layer 220 may be disposed on the first, second, and third color filters 211, 213, and 215, and may provide a flat surface to compensate for height differences therebetween.

[0114] The outer coating layer 220 may be made of an organic material. The outer coating layer 220 may be a colorless light-transmitting layer having no color in the visible light band. For example, the outer coating layer 220 may include a colorless light-transmitting organic material such as an acryl resin.

[0115] An anti-reflection layer or an anti-fingerprint layer may be further disposed on the color conversion layer CCL to prevent reflection of external light.

[0116] Figure 6 is a plan view showing a layout of pixels of a display device according to an embodiment of the present disclosure. Figure 7 is a plan view showing a first bank of a display device according to an embodiment. Figure 8 is a plan view showing a second bank of the display device according to the present embodiment. Fig. 9 It is along Figure 6 A cross-sectional view taken along line Q1-Q1'. Fig.10 It is along Figure 6 A cross-sectional view taken along line Q2-Q2'. Fig.11 It is along Figure 6 A cross-sectional view taken along line Q3-Q3'.

[0117] refer to Figures 6 to 11 , the display area DPA of the display device 10 may include a plurality of pixels PX. Each of the pixels PX refers to a repetitive minimum unit for displaying an image. The pixels PX each including a plurality of sub-pixels SP1, SP2, and SP3 may be sequentially and repeatedly arranged in rows and columns.

[0118] In order to display full color, each of the pixels PX may include a plurality of sub-pixels SP1, SP2, and SP3 that emit light of different colors. For example, each of the pixels PX may include a first sub-pixel SP1 responsible for emitting blue light, a second sub-pixel SP2 responsible for emitting red light, and a third sub-pixel SP3 responsible for emitting green light. One first sub-pixel SP1, one second sub-pixel SP2, and one third sub-pixel SP3 may be provided for each of the pixels PX.

[0119] The sub-pixels SP1, SP2, and SP3 may include emission areas LA1, LA2, and LA3 and non-emission areas NLA surrounding the emission areas LA1, LA2, and LA3. The non-emission area NLA may be located between the emission areas LA1, LA2, and LA3 of the sub-pixels SP1, SP2, and SP3. For example, an area between the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be the non-emission area NLA.

[0120] The sub-pixels SP1, SP2, and SP3 in each of the pixels PX may include emission areas LA1, LA2, and LA3, respectively. For example, the first sub-pixel SP1 may include a first emission area LA1, the second sub-pixel SP2 may include a second emission area LA2, and the third sub-pixel SP3 may include a third emission area LA3. The shapes and sizes of the emission areas LA1, LA2, and LA3 may be the same. However, it should be understood that the present disclosure is not limited thereto. The shapes and sizes of the emission areas LA1, LA2, and LA3 may be different from each other.

[0121] According to an embodiment of the present disclosure, the sub-pixels SP1, SP2, and SP3 may extend in the second direction DR2. For example, the first sub-pixel SP1 may extend in the second direction DR2, the second sub-pixel SP2 may extend in the second direction DR2, and the third sub-pixel SP3 may extend in the second direction DR2. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be sequentially and repeatedly arranged in the first direction DR1.

[0122] The buffer layer BF may be disposed on the substrate SUB. The buffer layer BF may be disposed over the entire surface of the substrate SUB. The buffer layer BF may prevent diffusion of impurity ions and may prevent penetration of moisture. The buffer layer BF may include silicon nitride, silicon oxide, silicon oxynitride, and the like.

[0123] The first semiconductor layer ACT1 and the second semiconductor layer ACT2 may be disposed on the buffer layer BF. The first semiconductor layer ACT1 may include a channel of the switching transistor STR1, and the second semiconductor layer ACT2 may include a channel of the driving transistor DTR. The first semiconductor layer ACT1 and the second semiconductor layer ACT2 may include polycrystalline silicon. Polycrystalline silicon may be formed by crystallizing amorphous silicon. When the first semiconductor layer ACT1 and the second semiconductor layer ACT2 are made of polycrystalline silicon, the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may have conductivity by doping the first semiconductor layer ACT1 and the second semiconductor layer ACT2 with ions. Therefore, the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may include source and drain regions of a plurality of transistors and a channel region. The source region and the drain region may be connected to both sides of each channel region.

[0124] According to another embodiment, the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may include single crystal silicon, low temperature polycrystalline silicon, amorphous silicon or an oxide semiconductor. The oxide semiconductor may include, for example, a binary compound (AB) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB x C y ) and quaternary compounds (AB x C y D z According to an embodiment of the present disclosure, the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may include an oxide including indium, tin, and zinc (ITZO) or an oxide including indium, gallium, and zinc (IGZO).

[0125] The gate insulator GI may be disposed on the first semiconductor layer ACT1 and the second semiconductor layer ACT2. The gate insulator GI may be disposed substantially over the entire surface of the substrate SUB. The gate insulator GI may include a silicon compound, a metal oxide, or the like. For example, the gate insulator GI may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. The gate insulator GI may be composed of a single layer or multiple layers of different materials stacked on each other.

[0126] The first gate electrode GE1 and the second gate electrode GE2 may be disposed on the gate insulator GI. The first gate electrode GE1 may overlap with the channel region of the first semiconductor layer ACT1, and the second gate electrode GE2 may overlap with the channel region of the second semiconductor layer ACT2. The first gate electrode GE1 and the second gate electrode GE2 may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first gate electrode GE1 and the second gate electrode GE2 may consist of a single layer or a multilayer.

[0127] The interlayer dielectric layer ILD may be disposed on the first gate electrode GE1, the second gate electrode GE2, and the gate insulator GI. The interlayer dielectric layer ILD may be disposed over the entire surface of the substrate SUB. The interlayer dielectric layer ILD may include the same material as the above-mentioned gate insulator GI, or may include one or more materials selected from the materials listed above as the material of the gate insulator GI.

[0128] The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may be disposed on the interlayer dielectric layer ILD. The first source electrode SE1 and the first drain electrode DE1 may be electrically connected to the first semiconductor layer ACT1 through a contact hole passing through the gate insulator GI and the interlayer dielectric layer ILD. The second source electrode SE2 and the second drain electrode DE2 may be electrically connected to the second semiconductor layer ACT2 through a contact hole passing through the gate insulator GI and the interlayer dielectric layer ILD.

[0129] The first semiconductor layer ACT1, the first gate electrode GE1, the first source electrode SE1, and the first drain electrode DE1 may form a switching transistor STR1. The second semiconductor layer ACT2, the second gate electrode GE2, the second source electrode SE2, and the second drain electrode DE2 may form a driving transistor DTR. However, it should be understood that the present disclosure is not limited thereto. The first semiconductor layer ACT1, the first gate electrode GE1, the first source electrode SE1, and the first drain electrode DE1 may form a sensing transistor STR2.

[0130] The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may include at least one metal selected from the group consisting of aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may be a single-layer or multi-layer structure. For example, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may be formed as a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0131] The via layer VIA may be disposed on the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2. The via layer VIA may provide a flat surface on elements having different heights in the display area DPA. The via layer VIA may include an organic insulating material such as polyacrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene (BCB).

[0132] The pixel electrodes AE1, AE2 and AE3 and the bank layer 150 may be disposed on the through-hole layer VIA. The pixel electrodes AE1, AE2 and AE3 may be connected to the driving transistor DTR thereunder through the contact holes CNT1, CNT2 and CNT3. Each of the contact holes CNT1, CNT2 and CNT3 may pass through the through-hole layer VIA to expose the second drain electrode DE2 of the driving transistor DTR. For example, the first pixel electrode AE1 may be connected to the second drain electrode DE2 of the driving transistor DTR through the first contact hole CNT1, the second pixel electrode AE2 may be connected to the second drain electrode DE2 of the driving transistor DTR through the second contact hole CNT2, and the third pixel electrode AE3 may be connected to the second drain electrode DE2 of the driving transistor DTR through the third contact hole CNT3. The contact holes CNT1, CNT2 and CNT3 may overlap with the pixel electrodes AE1, AE2 and AE3 and may be located in the non-emission area NLA.

[0133] The bank layer 150 may be disposed along the boundary of each sub-pixel SP1, SP2, and SP3. The bank layer 150 may be disposed on at least one of the pixel electrodes AE1, AE2, and AE3 and the through-hole layer VIA. The bank layer 150 may include openings OPN1, OPN2, and OPN3 that expose the pixel electrodes AE1, AE2, and AE3, respectively. The openings OPN1, OPN2, and OPN3 may include a first opening OPN1 that exposes the first pixel electrode AE1, a second opening OPN2 that exposes the second pixel electrode AE2, and a third opening OPN3 that exposes the third pixel electrode AE3. The non-emission area NLA and the emission areas LA1, LA2, and LA3 may be distinguished from each other by the bank layer 150. The bank layer 150 will be described in more detail later.

[0134] The light emitting layer OL may be disposed on each of the pixel electrodes AE1, AE2, and AE3 exposed by the bank layer 150. The light emitting layer OL may include an organic material layer. The organic material layer of the light emitting layer OL may include an organic emission layer and may further include a hole injection / transport layer and / or an electron injection / transport layer. The light emitting layer OL may be formed by, but not limited to, inkjet printing. The light emitting layers OL may be spaced apart from each other in the emission areas LA1, LA2, and LA3.

[0135] The common electrode CE may be disposed on the light emitting layer OL. The common electrode CE may be disposed across the pixel PX. The common electrode CE may cover the light emitting layer OL and may be disposed on the bank layer 150. The common electrode CE may contact not only the upper surface of the light emitting layer OL and the upper surface of the bank layer 150, but also the side surface of the bank layer 150.

[0136] The common electrode CE may include a material layer having a small work function, such as Li, Ca, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, F, and Ba, or a compound or mixture thereof (e.g., a mixture of Ag and Mg), or a material having a multilayer structure such as LiF / Ca or LiF / Al. The common electrode CE may also include a transparent metal oxide layer disposed on the material layer having a small work function. The pixel electrodes AE1, AE2, and AE3, the light-emitting layer OL, and the common electrode CE may form a corresponding light-emitting element.

[0137] Will further refer to Figure 12 to Figure 14 The bank layer 150 is described. Fig.12 is a plan view schematically illustrating a contact hole and a second bank layer according to an embodiment. Fig.13 is a plan view schematically showing a contact hole and a second bank layer according to another embodiment. Fig.14 is a plan view schematically showing a contact hole and a second bank layer according to still another embodiment.

[0138] Combination Figures 6 to 11 refer to Figure 12 to Figure 14 , the bank layer 150 may include a first bank layer BN1 and a second bank layer BN2.

[0139] The first bank layer BN1 may be disposed on the through hole layer VIA and the pixel electrodes AE1, AE2, and AE3. The first bank layer BN1 may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The first bank layer BN1 may separate the emission areas LA1, LA2, and LA3 of the sub-pixels SP1, SP2, and SP3 from each other in the second direction DR2. The first bank layer BN1 may partially cover the pixel electrodes AE1, AE2, and AE3 of the sub-pixels SP1, SP2, and SP3. For example, when viewed from the top, the first bank layer BN1 may overlap and cover the upper and lower portions of the first pixel electrode AE1 of the first sub-pixel SP1. In addition, the first bank layer BN1 may overlap the contact holes CNT1, CNT2, and CNT3 located between the emission areas LA1, LA2, and LA3 of the sub-pixels SP1, SP2, and SP3.

[0140] The second bank layer BN2 may be disposed on the through hole layer VIA, the first bank layer BN1, and the pixel electrodes AE1, AE2, and AE3. The second bank layer BN2 may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The second bank layer BN2 may intersect the first bank layer BN1. The second bank layer BN2 may separate the emission areas LA1, LA2, and LA3 of the sub-pixels SP1, SP2, and SP3 from each other in the first direction DR1. The second bank layer BN2 may partially cover the pixel electrodes AE1, AE2, and AE3 of the sub-pixels SP1, SP2, and SP3. For example, when viewed from the top, the second bank layer BN2 may overlap and cover the left and right portions of the first pixel electrode AE1 of the first sub-pixel SP1. In addition, the second bank layer BN2 may overlap the contact holes CNT1, CNT2, and CNT3 located between the emission areas LA1, LA2, and LA3 of the sub-pixels SP1, SP2, and SP3. In each of the contact holes CNT1 , CNT2 , and CNT3 , the first bank layer BN1 and the second bank layer BN2 may cross and overlap each other.

[0141] The first bank layer BN1 and the second bank layer BN2 may include an organic insulating material or an inorganic insulating material. For example, the first bank layer BN1 may include at least one of polyimide resin, acrylic resin, silicon compound, polyacrylic resin, etc. According to an embodiment of the present disclosure, the first bank layer BN1 may be made of a transparent insulating material through which light can pass.

[0142] The second bank layer BN2 may include a light blocking material to present a black color. The light blocking material may include a black pigment. The black pigment may include, for example, at least one selected from the group consisting of aniline black, perylene black, titanium black and carbon black. For example, the black pigment may be carbon black. Examples of carbon black may include channel black, furnace black, thermal black, lamp black, etc., and one type or a combination of two or more types may be used. However, it should be understood that the present disclosure is not limited thereto. The light blocking material may include an opaque material such as metal particles (e.g., nickel, aluminum, molybdenum and alloys thereof), metal oxide particles (e.g., chromium oxide) and metal nitride particles (e.g., chromium nitride).

[0143] Since the second bank layer BN2 blocks light, color mixing between adjacent sub-pixels SP1, SP2, and SP3 that may occur when light reflected from the pixel electrodes AE1, AE2, and AE3 intrudes into adjacent sub-pixels SP1, SP2, and SP3 can be prevented. In addition, the second bank layer BN2 can prevent light incident from the outside from being reflected by the pixel electrodes AE1, AE2, and AE3. According to an embodiment of the present disclosure, the second bank layer BN2 overlaps with the contact holes CNT1, CNT2, and CNT3, so that light reflected from the pixel electrodes AE1, AE2, and AE3 disposed in the contact holes CNT1, CNT2, and CNT3 can be further blocked.

[0144] According to an embodiment of the present disclosure, the first bank layer BN1 may have a lyophilic property, and the second bank layer BN2 may have a lyophobic property.

[0145] As used herein, a lyophobic element repels a solution and does not allow the solution to penetrate through. On the other hand, a lyophilic element has a high affinity for the solution. For example, the solution may have a low adhesion to a lyophobic surface, and the surface tension of the solution located on the lyophobic surface may increase. On the other hand, the solution may have a high adhesion to a lyophilic surface, and the surface tension of the solution located on the lyophilic surface may decrease.

[0146] When a solution is located on a lyophobic surface, the solution may have a contact angle greater than the contact angle of a solution located on a lyophilic surface. The contact angle may refer to the angle formed by the tangent line of the solution on the surface at the contact point and the surface. The contact angle may increase with the lyophobic property or surface tension. Although not limited thereto, for example, when water is located on a lyophobic surface, the contact angle of water on the surface may be greater than 90° and less than 180°. In addition, when water is located on a lyophilic surface, the contact angle of water on the surface may be greater than 0° and less than 90°.

[0147] As will be described later, in the process of manufacturing the display device, the light-emitting layer can be manufactured by an inkjet printing process in which ink containing a material for the light-emitting layer is ejected. For example, the ink can be ejected into the first sub-pixel SP1 that emits light of the same color extending in the second direction DR2. The ink ejected into the first sub-pixel SP1 is spread in the first emission area LA1 separated by the bank layer 150. Due to the liquid-phobic second bank layer BN2, the ink ejected into the first emission area LA1 can be prevented from flowing to the adjacent second sub-pixel SP2 and third sub-pixel SP3. The ink dispersed in each of the first emission areas LA1 can be uniformly spread to the first emission area LA1 adjacent in the second direction DR2 across the first bank layer BN1. Since the first bank layer BN1 is liquid-philic, the ink can be uniformly spread over the first bank layer BN1. Therefore, the ink ejected into the first emission area LA1 can be applied to the first emission area LA1 with a uniform thickness.

[0148] The first bank layer BN1 may have such a small thickness that ink can flow through them. The second bank layer BN2 may have a large thickness to prevent ink from overflowing to the surrounding sub-pixels. According to an embodiment of the present disclosure, the thickness TT1 of the first bank layer BN1 may be less than the thickness TT2 of the second bank layer BN2. In other words, the thickness TT2 of the second bank layer BN2 may be greater than the thickness TT1 of the first bank layer BN1. For example, the thickness of the first bank layer BN1 may be 0.5 μm or less, preferably, 0.1 to 0.5 μm. The thickness of the second bank layer BN2 may be 1 μm or more, preferably, 1 to 10 μm.

[0149] refer to Figure 12 to Figure 14 , the bank layer 150 may overlap with the contact holes CNT1, CNT2, and CNT3 to cover the contact holes CNT1, CNT2, and CNT3. According to an embodiment of the present disclosure, the second bank layer BN2 may have a wider area to block light reflected by the pixel electrodes AE1, AE2, and AE3 in the contact holes CNT1, CNT2, and CNT3.

[0150] Specifically, the second bank layer BN2 may include a first region B1 and a second region B2. The first region B1 may extend in the second direction DR2 and may be located between the emission regions LA1, LA2, and LA3. For example, the first region B1 may contact the side of the emission regions LA1, LA2, and LA3 extending in the second direction DR2. The first region B1 may not overlap with the contact holes CNT1, CNT2, and CNT3. The second region B2 may extend in the first direction DR1 and may be located at the boundary of the sub-pixels SP1, SP2, and SP3. For example, in the second region B2, the boundaries of the sub-pixels SP1, SP2, and SP3 contact each other. The second region B2 may overlap with the contact holes CNT1, CNT2, and CNT3. The second bank layer BN2 may have a symmetrical structure relative to the first direction DR1. If the second bank layer BN2 has an asymmetric structure, this may cause a difference in viewing angles from different directions. In order to make the viewing angles from different directions (for example, the left and right sides of the image surface) the same, the second bank layer BN2 may have a symmetrical structure relative to the first direction DR1 to obtain a better viewing angle.

[0151] According to an embodiment of the present disclosure, the width W1 of the first region B1 may be smaller than the width W2 of the second region B2. In other words, the width W2 of the second region B2 may be greater than the width W1 of the first region B1. The width W2 of the second region B2 may be greater than the width W1 of the first region B1 so that it covers each of the contact holes CNT1, CNT2, and CNT3.

[0152] Considering the margin of the contact holes CNT1, CNT2, and CNT3, the second region B2 of the second bank layer BN2 may have a large area. Fig.10 As shown in , the through-hole layer VIA in which the contact holes CNT1, CNT2 and CNT3 are formed can be made of an organic material so that the length of the side surface of the contact holes CNT1, CNT2 and CNT3 (i.e., the length of the inclined surface) can be long. The second region B2 of the second bank layer BN2 can have a large area with a margin covering the inclined surfaces of the contact holes CNT1, CNT2 and CNT3. According to an embodiment of the present disclosure, the distance D1 from the first contact hole CNT1 to the edge of the second region B2 can be equal to or greater than 5 μm (see Fig.12 ).

[0153] In addition, the second regions B2 of the second bank layer BN2 may be spaced apart from each other by a predetermined distance. The ejected ink may move between the second regions B2 of the second bank layer BN2. The distance D2 between the second regions B2 of the second bank layer BN2 may be equal to or greater than 10 μm to allow the ink to flow at a desired rate.

[0154] like Fig.12As shown in , an angle θ1 between one side of the first region B1 and one side of the second region B2 contacting one side of the first region B1 of the second bank BN2 may be equal to 90 degrees. For example, the shape of the second region B2 of the second bank BN2 may be rectangular when viewed from the top.

[0155] like Fig.13 As shown in , the angle θ1 between one side of the first area B1 and one side of the second area B2 in contact with one side of the first area B1 of the second bank layer BN2 may be greater than 90 degrees. For example, when viewed from the top, the shape of the second area B2 of the second bank layer BN2 may be an octagon. However, it should be understood that the present disclosure is not limited to this. When viewed from the top, the shape of the second area B2 of the second bank layer BN2 may be a quadrilateral, a hexagon, or other polygon. In this case, the fluidity of the ink diffusion from the emission areas LA1, LA2, and LA3 to the adjacent emission areas LA1, LA2, and LA3 can be improved.

[0156] However, it should be understood that the present disclosure is not limited thereto. Fig.14 As shown in FIG. 1 , the shape of the second region B2 of the second bank layer BN2 may be circular or elliptical when viewed from the top.

[0157] As described above, by changing the shape of the second region B2 of the second bank layer BN2 when viewed from the top, the rate at which ink diffuses between the emission areas LA1, LA2, and LA3 may be adjusted.

[0158] Hereinafter, a method of manufacturing the display device according to the above-described embodiment of the present disclosure will be described.

[0159] Figures 15 to 19 are cross-sectional views illustrating process steps of a method of manufacturing a display device according to an embodiment of the present disclosure. Figures 15 to 19 is shown corresponding to Fig.11 A cross-sectional view of the process steps of the structure.

[0160] refer to Figures 15 to 19 , a first bank layer BN1 is formed on the substrate SUB.

[0161] Specifically, a switch transistor STR1, a drive transistor DTR, a buffer layer BF, a gate insulator GI, an interlayer dielectric layer ILD, a via layer VIA, and a first pixel electrode AE1 are formed on a substrate SUB. The above elements can be formed by stacking using physical vapor deposition or chemical vapor deposition and patterning them by a photolithography process. After forming the switch transistor STR1 and the drive transistor DTR, a via material layer is applied. Then, the via material layer is partially etched to form a first contact hole CNT1 exposing the drive transistor DTR, thereby forming a via layer VIA.

[0162] The first bank layer BN1 may be formed by applying a first bank material on the first pixel electrode AE1 and the via layer VIA and patterning it through exposure and development processes using a mask. The first bank layer BN1 may be formed to overlap the first contact hole CNT1 through which the driving transistor DTR is connected to the first pixel electrode AE1.

[0163] Then, refer to Fig.16 and Fig.17 A material for a second bank is applied on the via layer VIA and the first bank layer BN1 to form a second bank material layer BML. The second bank material layer BML may include a light blocking material capable of exhibiting a liquid-repellent property and a fluorine-based compound or a siloxane-based compound.

[0164] A mask MS is aligned over the second bank material layer BML. The mask MS may include a light blocking portion R1 and a transmission portion R2 having different light transmittances. The light blocking portion R1 may block light to prevent the light from reaching the second bank material layer BML. The transmission portion R2 may transmit light so that the light reaches the second bank material layer BML. The transmittance of the transmission portion R2 may be greater than the transmittance of the light blocking portion R1.

[0165] Subsequently, light (e.g., ultraviolet (UV) light) is irradiated from above the mask MS. The ultraviolet (UV) light is blocked by the light blocking portion R1 of the mask MS and does not reach the second bank material layer BML in line with the light blocking portion R1. The ultraviolet (UV) light passes through the transmission portion R2 of the mask MS and reaches the second bank material layer BML aligned with the transmission portion R2.

[0166] In an embodiment, the second embankment material layer BML includes a positive photoresist or a negative photoresist (sensitizer). When the second embankment material layer BML includes a positive photoresist, the portion where the UV light is blocked by the light blocking portion R1 remains cured and cannot be well dissolved in a developer. On the other hand, the portion irradiated with UV light passing through the transmission portion R2 changes the chemical properties and dissolves well in a developer. By using a developer, the portion of the second embankment material layer BML exposed to the UV light can be selectively removed by chemical changes, leaving an unexposed portion. And when the second embankment material layer BML includes a negative photoresist, it can work in the opposite way. For example, the second embankment material layer BML includes a negative photoresist, and therefore, the portion of the second embankment material layer BML aligned with the light blocking portion R1 of the mask MS is removed, and the portion of the second embankment material layer BML aligned with the transmission portion R2 of the mask MS is retained. In this embodiment, it is shown as an example that the second embankment material layer BML includes a negative photoresist. In Fig.17The resulting second bank layer BN2 is shown in FIG. Therefore, a bank layer 150 including the first bank layer BN1 and the second bank layer BN2 may be formed.

[0167] Then, refer to Fig.18 and Fig.19 , a light emitting layer OL is formed by inkjet printing, and a common electrode CE is formed on the light emitting layer OL and the bank layer 150 .

[0168] Specifically, a material layer OLI for the light-emitting layer OL is disposed on the first pixel electrode AE1 exposed by the bank layer 150. The second bank layer BN2 of the bank layer 150 has a liquid-repellent property, resulting in a convex meniscus of the material layer OLI on the first pixel electrode AE1. The contact angle between the material layer OLI for the light-emitting layer OL and the second bank layer BN2 can be increased. The material layer OLI for the light-emitting layer OL does not flow to the liquid-repellent upper surface of the second bank layer BN2, and can be more accurately located on the first pixel electrode AE1 not covered by the second bank layer BN2. Although not shown in the drawings, the material layer OLI for the light-emitting layer OL can be uniformly distributed on the liquid-philic first bank layer BN1.

[0169] The material layer OLI for the light emitting layer OL can be ejected in the form of ink INK by an inkjet printing device (or a droplet ejecting device) and disposed on the first pixel electrode AE1 not covered by the bank layer 150. In this way, the light emitting layer OL can be more accurately formed at a desired position even in a high-resolution display device.

[0170] After inkjet printing the material layer OLI for the light emitting layer OL, the material layer OLI is dried to form the light emitting layer OL. Fig.19 As shown in , the drying process evaporates the solvent of the material layer OLI and may reduce the volume to form the light emitting layer OL.

[0171] Subsequently, a common electrode CE is formed on the light emitting layer OL and the bank layer 150. The common electrode CE may cover the light emitting layer OL and the bank layer 150.

[0172] Hereinafter, other embodiments of the present disclosure will be described. In the following description, the same or similar elements will be represented by the same or similar reference numerals, and redundant descriptions will be omitted or briefly described. The description will focus on the differences from the above embodiments.

[0173] Fig. 20 is a plan view showing a layout of pixels of a display device according to an embodiment of the present disclosure. Fig.21 is a plan view showing a bank layer of a display device according to an embodiment of the present disclosure. Fig. 22 It is along Fig. 20A cross-sectional view taken along line Q4-Q4'. Fig.23 It is along Fig. 20 A cross-sectional view taken along line Q5-Q5'.

[0174] Figure 20 to Figure 23 The implementation method and Figures 6 to 11 The embodiment of FIG. 1 is different in that the bank layer 150 is composed of a single layer.

[0175] Specifically, the bank layer 150 may be composed of a single layer. The bank layer 150 may include a first bank portion BP1 and a second bank portion BP2 that are distinguished, for example, by thickness. The first bank portion BP1 and the second bank portion BP2 may be integrated into one body.

[0176] The first bank portion BP1 may be disposed on the through hole layer VIA and the pixel electrodes AE1, AE2, and AE3. The first bank portion BP1 may be an island-shaped portion extending in the second direction DR2. The first bank portions BP1 may be spaced apart from each other in the first direction DR1 and the second direction DR2. The first bank portion BP1 may be disposed between the emission areas LA1, LA2, and LA3 of the sub-pixels SP1, SP2, and SP3 arranged in the second direction DR2. The first bank portion BP1 may partially cover the pixel electrodes AE1, AE2, and AE3 of the sub-pixels SP1, SP2, and SP3. For example, when viewed from the top, the first bank portion BP1 may overlap and cover the lower portion of the first pixel electrode AE1 of the first sub-pixel SP1. In addition, the first bank portion BP1 may not overlap the contact holes CNT1, CNT2, and CNT3 located between the emission areas LA1, LA2, and LA3 of the sub-pixels SP1, SP2, and SP3.

[0177] The second bank portion BP2 may be disposed on the via layer VIA, the first bank portion BP1, and the pixel electrodes AE1, AE2, and AE3. Fig.21 As shown in , the second bank portion BP2 may extend in the second direction DR2 and may be separated from each other in the first direction DR1 due to the presence of the emission areas LA1, LA2, and LA3 and the first bank portion BP1. The second bank portion BP2 may separate the emission areas LA1, LA2, and LA3 of the sub-pixels SP1, SP2, and SP3 from each other in the second direction DR2. The second bank portion BP2 may partially cover the pixel electrodes AE1, AE2, and AE3 of the sub-pixels SP1, SP2, and SP3. For example, when viewed from the top, the second bank portion BP2 may overlap and cover the left portion, the right portion, the upper portion, and the lower portion of the first pixel electrode AE1 of the first sub-pixel SP1. In addition, the second bank portion BP2 may overlap the contact holes CNT1, CNT2, and CNT3 located between the emission areas LA1, LA2, and LA3 of the sub-pixels SP1, SP2, and SP3.

[0178] The first and second bank portions BP1 and BP2 of the bank layer 150 may include an organic insulating material or an inorganic insulating material, and may include a light blocking material to present a black color.

[0179] When the bank layer 150 blocks light, color mixing between adjacent sub-pixels SP1, SP2, and SP3 that may occur when light reflected from the pixel electrodes AE1, AE2, and AE3 reaches adjacent sub-pixels SP1, SP2, and SP3 can be reduced or prevented. In addition, the bank layer 150 can prevent light from the outside from being reflected by the pixel electrodes AE1, AE2, and AE3. According to an embodiment of the present disclosure, the bank layer 150 overlaps with the contact holes CNT1, CNT2, and CNT3, so that light reflected from the pixel electrodes AE1, AE2, and AE3 disposed in the contact holes CNT1, CNT2, and CNT3 can be further blocked.

[0180] According to an embodiment of the present disclosure, the bank layer 150 may have a lyophobic property. Specifically, the first bank portion BP1 and the second bank portion BP2 of the bank layer 150 may have a lyophobic property. As described above, the ink ejected into the first sub-pixel SP1 is dispersed in the first emission area LA1 separated by the bank layer 150. By making the second bank portion BP2 lyophobic, the ink ejected into the first emission area LA1 can be prevented from overflowing into the adjacent second sub-pixel SP2 and third sub-pixel SP3. The ink dispersed in each of the first emission areas LA1 can be uniformly diffused to the adjacent first emission areas LA1 in the second direction DR2 across the first bank portion BP1. Although the first bank portion BP1 has a lyophobic property, the first bank portion BP1 is shallow in the third direction DR3, and thus the ink can easily overflow. Therefore, the ink ejected into the first emission area LA1 can be applied to the first emission area LA1 with a uniform thickness.

[0181] The first bank portion BP1 may be shallow enough to allow ink to overflow from the first bank portion BP1. The second bank layer BN2 may be thick enough to contain the ink and prevent the ink from overflowing onto surrounding sub-pixels. According to an embodiment of the present disclosure, the thickness TT3 of the first bank portion BP1 may be less than the thickness TT4 of the second bank portion BP2 (see Fig. 22 ). The thickness TT4 of the second bank portion BP2 may be greater than the thickness TT3 of the first bank portion BP1. For example, the thickness of the first bank portion BP1 may be equal to or less than 0.5 μm, and the thickness of the second bank portion BP2 may be equal to or greater than 1 μm. According to an embodiment of the present disclosure, the second bank portion BP2 having a larger thickness overlaps the contact holes CNT1, CNT2, and CNT3, so that light reflected from the pixel electrodes AE1, AE2, and AE3 in the contact holes CNT1, CNT2, and CNT3 can be effectively blocked.

[0182] The bank layer 150 may overlap the contact holes CNT1, CNT2, and CNT3 to cover the contact holes CNT1, CNT2, and CNT3. According to an embodiment of the present disclosure, the second bank portion BP2 may have a wider area to block light reflected by the pixel electrodes AE1, AE2, and AE3 in the contact holes CNT1, CNT2, and CNT3. The second bank portion BP2 may include a first region B1 and a second region B2 (see Fig.21 ). The first region B1 may not overlap with the contact holes CNT1, CNT2, and CNT3, and the second region B2 may overlap with the contact holes CNT1, CNT2, and CNT3. According to an embodiment of the present disclosure, the width W1 of the first region B1 may be smaller than the width W2 of the second region B2. In other words, the width W2 of the second region B2 may be larger than the width W1 of the first region B1. The width W2 of the second region B2 may be larger than the width W1 of the first region B1 so that it covers each of the contact holes CNT1, CNT2, and CNT3.

[0183] In addition, as mentioned above Figure 12 to Figure 14 As shown in FIG. 1 , when viewed from the top, the second area B2 of the second bank portion BP2 of the bank layer 150 may have a rectangular shape, a hexagonal shape, an octagonal shape, etc., so that ink may be more easily diffused from the emission areas LA1, LA2, and LA3 to adjacent areas.

[0184] Fig.24 and Fig.25 are cross-sectional views illustrating process steps of a method of manufacturing a display device according to an embodiment of the present disclosure. Fig.24 and Fig.25 Can correspond to the above reference Fig.23 The structure of the description.

[0185] refer to Fig.24 and Fig.25 A material for a bank is applied on the substrate SUB formed with the first pixel electrode AE1 and the via layer VIA to form a bank material layer BMLL. The bank material layer BMLL may include a light blocking material capable of exhibiting a liquid-repellent property and a fluorine-based compound or a siloxane-based compound.

[0186] A mask MS is aligned over the embankment material layer BMLL. The mask MS may include a light blocking portion R1, a transmission portion R2, and a semi-transparent portion R3 having different light transmittances. The light blocking portion R1 may block light to prevent the light from reaching the embankment material layer BMLL. The transmission portion R2 may transmit light so that the light reaches the embankment material layer BMLL. The semi-transparent portion R3 may partially transmit light so that some of the light reaches the embankment material layer BMLL. The transmittance of the transmission portion R2 may be greater than the transmittance of the semi-transparent portion R3.

[0187] Subsequently, light (e.g., ultraviolet (UV) light) is irradiated from above the mask MS. The ultraviolet (UV) light is blocked by the light blocking portion R1 of the mask MS and does not reach the bank material layer BMLL in a line with the light blocking portion R1. The ultraviolet (UV) light passes through the transmission portion R2 of the mask MS and reaches the bank material layer BMLL in a line with the transmission portion R2. The ultraviolet (UV) light partially passes through the semi-transparent portion R3 of the mask MS and reaches the bank material layer BMLL in a line with the semi-transparent portion R3.

[0188] In this case, the portion of the UV light blocked by the light blocking portion R1 remains solidified and well dissolved in the developer. The portion irradiated with the UV light passing through the transmission portion R2 changes the chemical properties and cannot be well dissolved in the developer. The portion partially irradiated with the UV light passing through the translucent portion R3 changes the chemical properties of only the lower portion. Therefore, the upper portion is easily well dissolved in the developer, while the lower portion is not dissolved. At this time, by using the developer, the portion of the embankment material layer BMLL that is completely exposed to the UV light and the portion that is partially exposed can be selectively retained due to the chemical change, thereby removing the blocked portion. Therefore, the portion of the embankment material layer BMLL that is aligned with the light blocking portion R1 of the mask MS is removed, the portion of the embankment material layer BMLL that is in a line with the transmission portion R2 is retained, and the portion of the embankment material layer BMLL that is in a line with the translucent portion R3 is partially removed, so that a structure as shown in FIG. Fig.25 Thus, the bank layer 150 including the first bank portion BP1 and the second bank portion BP2 may be formed. Figures 15 to 19 The subsequent processes are described to manufacture the display device 10 .

[0189] As described above, by forming the bank layer 150 including the first bank portion BP1 and the second bank portion BP2 having different thicknesses through a single mask process, manufacturing costs may be saved and productivity may be improved.

[0190] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiment without departing substantially from the principles of the present invention. Therefore, the preferred embodiments of the present invention disclosed are used only in a general and descriptive sense, and not for the purpose of limitation.

Claims

1. Display equipment, including: substrate; A transistor, disposed on the substrate; a via layer disposed above the transistor and comprising a contact hole extending to the transistor; a pixel electrode, disposed on the through-hole layer and connected to the transistor through the contact hole; a first bank layer and a second bank layer, wherein the first bank layer is disposed on the pixel electrode and extends in a first direction, and the second bank layer extends in a second direction intersecting the first direction; A light-emitting layer is disposed on the pixel electrode; as well as A common electrode is disposed on the light-emitting layer. wherein the second bank layer includes a first region not overlapping with the contact hole and a second region overlapping with the contact hole, and Wherein, the width of the second region is greater than the width of the first region.

2. The display device according to claim 1, wherein: The second region of the second bank layer overlaps with the first bank layer.

3. The display device according to claim 1, wherein: A distance from the contact hole to an edge of the second region is equal to or greater than 5 μm.

4. The display device according to claim 1, wherein: The thickness of the second bank layer is greater than that of the first bank layer.

5. The display device according to claim 1, wherein: An angle between one side of the first region and one side of the second region contacting the one side of the first region is 90 degrees.

6. The display device according to claim 1, wherein: An angle between one side of the first region and one side of the second region contacting the one side of the first region is greater than 90 degrees.

7. The display device according to claim 1, wherein: The second bank layer includes a light blocking material.

8. The display device according to claim 1, wherein: The first bank layer has a thickness of 0.1 to 0.5 μm.

9. The display device according to claim 1, wherein: The second bank layer has a thickness of 1 to 10 μm.

10. The display device according to claim 1, wherein: The first bank layer has a water contact angle greater than zero and less than 90 degrees.

11. The display device according to claim 1, wherein: The second bank layer has a water contact angle greater than 90 degrees and less than 180 degrees.

12. Display equipment, including: substrate; A transistor, disposed on the substrate; a through-hole layer disposed on the transistor and having a contact hole exposing the transistor; a pixel electrode, disposed on the through-hole layer and connected to the transistor through the contact hole; A bank layer, disposed on the pixel electrode; A light-emitting layer is disposed on the pixel electrode; as well as A common electrode is disposed on the light-emitting layer. wherein the bank layer includes a first bank portion that does not overlap with the contact hole and a second bank portion that overlaps with the contact hole, and Wherein, the width of the second bank portion is greater than the width of the first bank portion.

13. The display device according to claim 12, wherein: The second bank portion has a thickness greater than a thickness of the first bank portion.

14. The display device according to claim 12, wherein: The bank layer includes a light blocking material.

15. The display device according to claim 12, wherein: The bank layer has a water contact angle greater than 90 degrees and less than 180 degrees.

16. The display device according to claim 12, wherein: The first bank portion has a thickness of 0.1 to 0.5 μm.

17. The display device according to claim 12, wherein: The second bank portion has a thickness of 1 to 10 μm.

18. The display device according to claim 12, wherein: The first bank portion and the second bank portion are integrated into one body.

19. A method for manufacturing a display device, the method comprising: forming a transistor and a via layer on a substrate; etching the via layer to form a contact hole exposing the transistor; forming a pixel electrode on the through-hole layer and connected to the transistor through the contact hole; applying a bank material layer on the pixel electrode and using a mask to form a bank layer, the bank layer including a first bank portion not overlapping the contact hole and a second bank portion overlapping the contact hole; forming a light-emitting layer on the pixel electrode; as well as forming a common electrode on the light emitting layer, Wherein, the width of the second bank portion is greater than the width of the first bank portion.

20. The method according to claim 19, wherein: The mask includes a light blocking portion, a transmissive portion, and a semi-transparent portion, and A portion of the bank material layer aligned with the transmission portion is formed as the second bank portion, and a portion of the bank material layer aligned with the semi-transparent portion is formed as the first bank portion.

Images