Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a method for manufacturing the same. The display device includes: a substrate; a light emitting element layer disposed on the substrate and including a pixel electrode, an organic layer, and a common electrode; the light emitting device includes a light emitting element layer, an encapsulation layer disposed on the light emitting element layer, and a passivation layer disposed on the encapsulation layer. The contact angle between the surface of the passivation layer and water is in the range of 5-45 degrees.

Description

Technical Field

[0001] The present application relates to a display device and a method for manufacturing the display device. Background Art

[0002] With the development of multimedia, the importance of display devices is increasing. Accordingly, various types of display devices are being used, such as, for example, organic light emitting displays (OLEDs) and liquid crystal displays (LCDs).

[0003] With the development of display technology, research and development of display devices with flexible displays are being actively carried out. For some flexible displays, the display screen can be extended or shortened by folding, bending or sliding the display screen, which can greatly help to reduce the volume of the display device or change the design of the display device.

[0004] Some display devices are manufactured by performing a sheet unit process on a mother substrate including a plurality of cells corresponding to each display device to obtain a plurality of cells, and performing a module unit process on the obtained cells. In some cases, when a cell is transferred from the sheet unit process to the module unit process, an upper passivation layer may be formed on the cell surface to prevent physical and chemical scratches that may occur during the moving process, and then the cell may be moved. Summary of the invention

[0005] Aspects of the present disclosure provide a display device and a method for manufacturing the display device, which can reduce damage to a lower passivation layer and defects in peeling when an acid-resistant film or a passivation layer is peeled off.

[0006] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to aspects of the present disclosure, a display device includes a substrate, a light-emitting element layer disposed on the substrate and including a pixel electrode, an organic layer and a common electrode, an encapsulation layer disposed on the light-emitting element layer, and a passivation layer disposed on the encapsulation layer, wherein a contact angle between a surface of the passivation layer and water is in a range of 5° to 45°.

[0008] In an implementation, a surface of the passivation layer may have hydrophilicity.

[0009] In an implementation, the passivation layer may include one or more of an acrylic resin, an epoxy resin, and a urethane resin.

[0010] In an implementation, the passivation layer may be formed to have a thickness of 8 μm to 30 μm.

[0011] In an embodiment, the encapsulation layer may include a first encapsulation layer disposed on the light emitting element layer, a second encapsulation layer disposed on the first encapsulation layer, and a third encapsulation layer disposed on the second encapsulation layer, and the passivation layer contacts an upper surface of the third encapsulation layer.

[0012] According to aspects of the present disclosure, a method for manufacturing a display device includes forming a display layer on a mother substrate, applying a first coating layer on the display layer, forming a first passivation layer by sequentially performing a first UV curing process, a heat treatment process, and a plasma treatment process on the first coating layer, and forming a second passivation layer on the first passivation layer, wherein the plasma treatment process uses N 2 plasma.

[0013] In an embodiment, the first coating may be applied by an inkjet printing process.

[0014] In an embodiment, the first coating layer may be applied such that the thickness of the first coating layer may be 8 μm to 30 μm.

[0015] In an implementation, the cumulative amount of UV light of the first UV curing process may be 0.5J to 3J.

[0016] In an embodiment, the heat treatment process may be performed at a temperature ranging from 70° C. to 90° C. for 10 to 40 minutes.

[0017] In an embodiment, the plasma treatment process may be performed at a power of 1 kW to 5 kW, a voltage of 11 kV to 15 kV, and a speed of 60 mm / s to 260 mm / s.

[0018] In an embodiment, N 2 Plasma N 2 The flow rate of the gas can be 200LPM to 1200LPM.

[0019] In an implementation, the second passivation layer may be formed by applying a second coating layer on the first passivation layer and performing a second UV curing process.

[0020] In an embodiment, the method for manufacturing a display device may further include attaching an acid-resistant film to the second passivation layer, etching the mother substrate, performing a third UV curing process on the acid-resistant film, removing the acid-resistant film, cutting the mother substrate in units, and removing the second passivation layer.

[0021] In an implementation, the etching of the mother substrate may include spraying an etchant on the mother substrate to reduce a thickness of the mother substrate.

[0022] According to aspects of the present disclosure, a method for manufacturing a display device includes forming a display layer on a mother substrate, forming a first passivation layer by applying a first coating layer on the display layer and sequentially performing a first UV curing process, a first heat treatment process, and a first plasma treatment process on the first coating layer, forming a second passivation layer by applying a second coating layer on the first passivation layer and sequentially performing a second UV curing process, a second heat treatment process, and a second plasma treatment process on the second coating layer, and forming a third passivation layer on the second passivation layer, wherein the first plasma treatment process and the second plasma treatment process use N 2 plasma.

[0023] In an embodiment, the first plasma treatment process and the second plasma treatment process may be performed at a power of 1 kW to 5 kW, a voltage of 11 kV to 15 kV, and a speed of 60 mm / s to 260 mm / s.

[0024] In an embodiment, N 2 Plasma N 2 The flow rate of the gas can be 200LPM to 1200LPM.

[0025] In an embodiment, the method for manufacturing a display device may further include attaching an acid-resistant film to the third passivation layer and etching the mother substrate, performing a third UV curing process on the acid-resistant film, simultaneously removing the acid-resistant film and the third passivation layer, cutting the mother substrate in units, and removing the second passivation layer.

[0026] In an embodiment, forming the third passivation layer may include applying a third coating layer on the second passivation layer, wherein the first coating layer, the second coating layer, and the third coating layer are each applied by an inkjet printing process.

[0027] According to one or more embodiments of the display device and the method for manufacturing the display device, by increasing the curing rate of the first passivation layer by a UV curing process, a heat treatment process, and a plasma treatment process, the second passivation layer can be prevented from being torn when the second passivation layer is peeled off, or the first passivation layer and / or the encapsulation layer can be prevented from being torn.

[0028] However, the effects of the embodiments are not limited to those set forth herein. The above and other effects of the embodiments will become more apparent to those of ordinary skill in the art to which the embodiments pertain by referring to the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the present disclosure will become more apparent by describing embodiments thereof in detail with reference to the accompanying drawings, in which:

[0030] Figure 1 is a perspective view illustrating a display device according to an embodiment;

[0031] Figure 2 To observe from the side Figure 1 A cross-sectional view of a display device;

[0032] Figure 3 A plan view for explaining a display layer of a display device according to an embodiment;

[0033] Figure 4 A plan view for explaining a display area of ​​a display panel according to an embodiment;

[0034] Figure 5 for Figure 4 An enlarged plan view of area A;

[0035] Figure 6 For along Figure 5 A cross-sectional view taken along the line X1-X1';

[0036] Figure 7 A flowchart for explaining a method for manufacturing a display device according to an embodiment;

[0037] Figure 8 A flowchart for explaining the steps of forming a first passivation layer according to an embodiment;

[0038] Figures 9 to 20 A view for explaining an exemplary process of a method for manufacturing a display device according to an embodiment.

[0039] Fig.21 A flowchart for explaining a method for manufacturing a display device according to another embodiment;

[0040] Figure 22 to Figure 26 A view for explaining an exemplary process of a method for manufacturing a display device according to another embodiment;

[0041] Fig. 27 a graph for explaining a peeling force between a first passivation layer and a second passivation layer according to a distance from an end of the first passivation layer; and

[0042] Fig.28 Graph showing FT-IR analysis of the coating solution and the passivation layer. DETAILED DESCRIPTION

[0043] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. However, the present invention may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art.

[0044] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, the same reference numerals refer to the same or similar components.

[0045] It will be understood that although the terms "first" and "second" etc. can be used to describe various elements in this article, these elements are not limited by these terms. These terms as used in this article can distinguish an element from another element and are not limited by these terms. For example, without departing from the teachings of the present invention, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element. The term "about" or "approximately" as used in this article includes a narrative value and includes a suitable deviation range of a specific value determined by a person of ordinary skill in the art taking into account the measurement discussed and the error associated with the measurement of a specific number. For example, the term "about" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, or ± 5% of the narrative value.

[0046] Each of the features of the various embodiments of the present disclosure may be combined partially or completely or mutually combined, and various linkages and drives may be performed technically. Each embodiment may be implemented independently of each other, or may be implemented together.

[0047] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0048] Figure 1 is a perspective view illustrating a display device according to an embodiment.

[0049] refer to Figure 1 , the display device 10 may display a moving image or a still image. The display device 10 may refer to any electronic device that provides a display screen. For example, the display device 10 may include a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation (e.g., a vehicle navigation), a game console, a digital camera, a video camera, and a vehicle dashboard, etc. that provide a display screen. In this specification, the display device 10 may be a display device for a vehicle and may be provided in a vehicle, but is not limited thereto.

[0050] Examples of the display device 10 may include an inorganic light emitting diode display device, an organic light emitting diode display device, a quantum dot light emitting display device, a plasma display device, and a field emission display device. Hereinafter, an example of using an organic light emitting diode display device as a display device is explained, but the present disclosure is not limited thereto. Aspects of the present disclosure described with reference to an organic light emitting diode display device may be applied to other display devices as long as the same technical idea can be applied to other display devices.

[0051] The shape of the display device 10 may be variously changed. For example, the display device 10 may have a shape similar to a quadrilateral having sides in the first direction DR1 and sides in the second direction DR2 in a plan view. The corner where the side in the first direction DR1 and the side in the second direction DR2 intersect may be rounded to have a curvature, but is not limited thereto. For example, the corner may be formed as a right angle. The planar shape of the display device 10 is not limited to a quadrilateral, and the display device 10 may be formed as other polygons, a circle, or an ellipse.

[0052] The display device 10 may include a display area DA and a non-display area NDA. The display area DA is an area in which an image may be displayed, and the non-display area NDA is an area in which an image is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may generally occupy the center of the display device 10.

[0053] The display device 10 includes a display panel 100, a display driver 200, and a circuit board 300 (see Figure 2 ).

[0054] The display panel 100 may include a main area MA and a sub area SBA.

[0055] The main area MA may include a display area DA and a non-display area NDA disposed around the display area DA. The display area DA may include pixels capable of displaying an image. The display area DA may emit light from a plurality of light-emitting areas or a plurality of opening areas. For example, the display panel 100 may include: a pixel circuit including a switching element; a pixel defining film defining a light-emitting area or an opening area; and a self-luminous element.

[0056] For example, the self-luminous element may include at least one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0057] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver 210 (see FIG. 2 ) that supplies a gate signal to a gate line. Figure 3 ), and the non-display area NDA may include a fan-out line FOL (see FIG. 1 ) connecting the display driver 200 and the display area DA. Figure 3 ).

[0058] The sub-region SBA may be a region extending from one side of the main region MA. The sub-region SBA may include a flexible material that may be bent, folded, or rolled, etc. For example, when the sub-region SBA is bent, the sub-region SBA may overlap the main region MA in the thickness direction (third direction DR3). The sub-region SBA may include a display driver 200 and a display device connected to a circuit board 300 (see FIG. 2 ). Figure 2 In another embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be disposed in the non-display area NDA.

[0059] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may supply data voltages to the data lines. The display driver 200 may supply power voltages to the power lines and may supply power voltages to the gate driver 210 (see FIG. Figure 3 ) supplies a gate control signal. The display driver 200 may be formed as an integrated circuit (IC) and mounted by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be disposed in the sub-area SBA, and the display driver 200 may overlap with the main area MA in the thickness direction by bending the sub-area SBA. As another example, the display driver 200 may be mounted on the circuit board 300 (see Figure 2 )superior.

[0060] Later in Figure 2 The circuit board 300 illustrated in FIG. 1 may be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as, for example, a chip on film.

[0061] Figure 2 To observe from the side Figure 1 1 is a cross-sectional view of a display device 10 .

[0062] refer to Figure 2 The display panel 100 may include a substrate SUB, a display layer DU, and a passivation layer SIP disposed on the display layer DU. The display layer DU may include a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0063] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a glass substrate. However, the substrate SUB is not limited thereto and may be any suitable flexible substrate that can be bent, folded, or rolled up, etc. For example, the substrate SUB may include a polymer resin such as, for example, polyimide (PI), but is not limited thereto.

[0064] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may further include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 and the data line, and a lead connecting the display driver 200 and the pad portion. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0065] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistor of each pixel of the thin film transistor layer TFTL, the gate line, the data line, and the power line may be disposed in the display area DA. The gate control line and the fan-out line of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead line of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0066] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include: a plurality of light emitting elements including a first electrode, a second electrode, and a light emitting layer for emitting light; and a pixel defining film defining pixels. The plurality of light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

[0067] In an embodiment, the light emitting layer may be an organic light emitting layer including an organic material. The light emitting layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and may be recombined with each other in the organic light emitting layer to emit light.

[0068] In another embodiment, the light emitting element may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0069] The encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EML.

[0070] The passivation layer SIP may be disposed on the encapsulation layer TFEL. The passivation layer SIP may flatten the height difference of the display layer DU on the lower side of the passivation layer SIP (e.g., flatten the upper surface of the display layer DU and reduce the height difference of the upper surface of the display layer DU), and absorb a portion of light introduced from the outside to reduce reflected light caused by the external light.

[0071] Figure 3 1 is a plan view for explaining a display layer DU of the display device 10 according to the embodiment.

[0072] refer to Figure 3 , the display layer DU may include a display area DA and a non-display area NDA.

[0073] The display area DA may be disposed at the center of the display panel 100. A plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL may be disposed in the display area DA. Each of the plurality of pixels PX may be defined as a minimum unit emitting light.

[0074] The plurality of gate lines GL may supply the plurality of pixels PX with gate signals received from the gate driver 210. The plurality of gate lines GL may extend in a first direction DR1, and may be spaced apart from each other in a second direction DR2 intersecting the first direction DR1.

[0075] The plurality of data lines DL may supply the plurality of pixels PX with data voltages received from the display driver 200. The plurality of data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0076] The plurality of power lines VL may supply a power voltage received from the display driver 200 to the plurality of pixels PX. Here, the power voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a low potential voltage. The plurality of power lines VL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0077] The non-display area NDA may surround the display area DA. The gate driver 210, the fan-out line FOL, and the gate control line GCL may be disposed in the non-display area NDA. The gate driver 210 may generate a plurality of gate signals based on the gate control signal, and may sequentially supply the plurality of gate signals to the plurality of gate lines GL according to a set order.

[0078] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0079] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply a gate control signal received from the display driver 200 to the gate driver 210.

[0080] The sub-area SBA may include the display driver 200 and the pad area PA.

[0081] The display driver 200 may output a signal and a voltage for driving the display panel 100 to the fan-out line FOL. The display driver 200 may supply a data voltage to the data line DL through the fan-out line FOL. The data voltage may be supplied to a plurality of pixels PX, and the brightness of the plurality of pixels PX may be controlled. The display driver 200 may supply a gate control signal to the gate driver 210 through the gate control line GCL.

[0082] The pad area PA may be disposed at an edge of the sub-area SBA. The pad area PA may be electrically connected to the circuit board 300 (see FIG. 1 ) using a material such as an anisotropic conductive film or a self-assembled anisotropic conductive paste (SAP). Figure 2 The pad area PA may include a plurality of display pad portions DP. The plurality of display pad portions DP may be formed by the circuit board 300 (see Figure 2 ) is connected to the graphics system. A plurality of display pad portions DP may be connected to the circuit board 300 (see Figure 2 ) to receive digital video data, and can supply the digital video data to the display driver 200.

[0083] Figure 4 To explain the display panel 100 (see Figure 2 ) is a plan view of the display area DA.

[0084] refer to Figure 4 , the display panel 100 (see Figure 2 ) may include a plurality of pixels PX arranged in a first direction DR1 and a second direction DR2. Each of the plurality of pixels PX may have a planar shape such as, for example, a rectangle, a square, or a diamond. Figure 4 As shown in FIG, each of the plurality of pixels PX may have a planar shape such as, for example, a square. However, each of the plurality of pixels PX is not limited thereto and may have various shapes such as, for example, other polygons, circles, and ellipses in a plan view.

[0085] Some pixels PX may emit the first light, other pixels PX may emit the second light, and the remaining pixels PX may emit the third light. Here, the first light may be light included in a blue band, the second light may be light included in a red band, and the third light may be light included in a green band. The red band may be a band of about 600nm to 750nm, the green band may be a band of about 480nm to 560nm, and the blue band may be a band of about 370nm to 460nm, but the embodiments of the present specification are not limited thereto. In some embodiments, some pixels PX may also emit white light.

[0086] Each of the plurality of pixels PX may include at least one of an organic light emitting element including an organic material, an inorganic light emitting element including an inorganic semiconductor, a quantum dot light emitting element including a quantum dot light emitting layer, and a micro light emitting diode (LED) as a light emitting element emitting light. Hereinafter, it is mainly described that each of the plurality of pixels PX includes an organic light emitting element, but the present disclosure is not limited thereto.

[0087] Figure 5 for Figure 4 An enlarged plan view of area A. Figure 6 For along Figure 5 A cross-sectional view taken along line X1-X1'.

[0088] refer to Figure 5 and Figure 6 as well as Figure 2 , the display panel 100 of the display device 10 may include a substrate SUB, a display layer DU and a passivation layer SIP. The display layer DU may include a thin film transistor layer TFTL, a light emitting element layer EML and an encapsulation layer TFEL. The display panel 100 may include a passivation layer SIP on the encapsulation layer TFEL.

[0089] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0090] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the first buffer layer BF1 may include a plurality of inorganic films alternately stacked.

[0091] The lower metal layer BML may be disposed on the first buffer layer BF1. The lower metal layer BML may prevent light incident from below the lower metal layer BML from being incident on the semiconductor layer ACT of the thin film transistor TFT. The lower metal layer BML may be formed as a single layer structure or a multilayer structure of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0092] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic film capable of preventing air or moisture from penetrating. For example, the second buffer layer BF2 may include a plurality of inorganic films alternately stacked.

[0093] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of each of the plurality of pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0094] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the lower metal layer BML and the gate electrode GE in the thickness direction, and the semiconductor layer ACT may be insulated from the gate electrode GE by the gate insulating layer GI. In a portion of the semiconductor layer ACT, the material of the semiconductor layer ACT may be made into a conductor to form a source electrode SE and a drain electrode DE. For example, the conductive material of the semiconductor layer ACT may form the source electrode SE and the drain electrode DE.

[0095] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT with the gate insulating layer GI interposed therebetween.

[0096] The gate insulating layer GI may be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2, and the gate insulating layer GI may insulate the semiconductor layer ACT and the gate electrode GE from each other. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0097] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may communicate with the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0098] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in a thickness direction. The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0099] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may communicate with the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0100] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 may be inserted into a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI, and contact the drain electrode DE of the thin film transistor TFT.

[0101] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0102] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the pixel electrode AE ​​of the light emitting element ED to each other. The second connection electrode CNE2 may be inserted into a contact hole formed in the first passivation layer PAS1 and contact the first connection electrode CNE1.

[0103] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include a contact hole through which the pixel electrode AE ​​of the light emitting element ED passes.

[0104] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED and a pixel defining layer PDL. The light emitting element ED may include a pixel electrode AE, an organic layer EL, and a common electrode CE.

[0105] The pixel electrode AE ​​may be disposed on the second passivation layer PAS2. The pixel electrode AE ​​may be disposed to overlap any one of the openings OPE1, OPE2, and OPE3 of the pixel defining film PDL. The pixel electrode AE ​​may be electrically connected to the drain electrode DE of the thin film transistor TFT through the second connection electrode CNE2 and the first connection electrode CNE1.

[0106] The organic layer EL may be disposed on the pixel electrode AE. For example, the organic layer EL may be an organic light emitting layer formed of an organic material, but is not limited thereto. In the case where the organic layer EL corresponds to the organic light emitting layer, when the thin film transistor TFT applies a predetermined voltage to the pixel electrode AE ​​of the light emitting element ED and the common electrode CE of the light emitting element ED receives a common voltage or a cathode voltage, holes and electrons may move to the organic layer EL through the hole transport layer and the electron transport layer, respectively, and the holes and electrons may be recombined with each other in the organic layer EL to emit light.

[0107] The common electrode CE may be disposed on the organic layer EL. For example, the common electrode CE may be implemented in the form of an electrode common to all pixels, rather than being divided for each of the plurality of pixels. The common electrode CE may be disposed on the organic layer EL in the first to third light emitting regions EA1, EA2, and EA3, and the common electrode CE may be disposed on the pixel defining film PDL in regions other than the first to third light emitting regions EA1, EA2, and EA3.

[0108] The common electrode CE may receive a common voltage or a low potential voltage. In the case where the pixel electrode AE ​​receives a voltage corresponding to the data voltage and the common electrode CE receives a low potential voltage, a potential difference is formed between the pixel electrode AE ​​and the common electrode CE, and the organic layer EL may emit light.

[0109] The pixel defining film PDL may be disposed on a portion of the second passivation layer PAS2 and the pixel electrode AE. The pixel defining film PDL may define the first to third light emitting regions EA1, EA2, and EA3. In an embodiment, the respective sizes (e.g., areas) of the first to third light emitting regions EA1, EA2, and EA3 may be the same. In another embodiment, the respective sizes (e.g., areas) of the first to third light emitting regions EA1, EA2, and EA3 may be different from each other. For example, the area of ​​the first light emitting region EA1 may be greater than the area of ​​each of the second light emitting region EA2 and the third light emitting region EA3, and the area of ​​the second light emitting region EA2 may be greater than the area of ​​the third light emitting region EA3. The intensity of light emitted from the light emitting regions EA1, EA2, and EA3 may be changed according to the size (e.g., area) of the light emitting regions EA1, EA2, and EA3, and the color of the image displayed on the display device 10 may be controlled by adjusting the size (e.g., area) of the light emitting regions EA1, EA2, and EA3.

[0110] The pixel defining film PDL may separate and insulate the pixel electrodes AE of the plurality of light emitting elements ED from each other. The pixel defining film PDL may transmit light or block light. In an example in which the pixel defining film PDL transmits light, the pixel defining film PDL may include polyimide (PI). In an example in which the pixel defining film PDL blocks light, the pixel defining film PDL may include a light absorbing material to prevent light reflection. For example, the pixel defining film PDL may include a polyimide (PI)-based binder and a mixture of red, green and blue pigments. Alternatively, the pixel defining film PDL may include a cardo-based binder resin and a mixture of a lactam black pigment and a blue pigment. Alternatively, the pixel defining film PDL may include carbon black.

[0111] The encapsulation layer TFEL may be disposed on the common electrode CE so that the encapsulation layer TFEL covers the plurality of light emitting elements ED. The encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The encapsulation layer TFEL may include at least one organic film to protect the light emitting element layer EML from foreign matter, such as dust.

[0112] In an embodiment, the encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be inorganic encapsulation layers, and the second encapsulation layer TFE2 disposed therebetween may be an organic encapsulation layer.

[0113] Each of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating material may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0114] The second encapsulation layer TFE2 may include a polymer material. Examples of polymer materials may include acrylic resins, epoxy resins, polyimide, polyethylene, etc. For example, the second encapsulation layer TFE2 may include an acrylic resin, such as polymethyl methacrylate resin or polyacrylic acid resin. The second encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0115] The passivation layer SIP may be disposed on the encapsulation layer TFEL. The passivation layer SIP may be in direct contact with the upper surface of the third encapsulation layer TFE3 of the encapsulation layer TFEL. The passivation layer SIP may flatten the height difference of the upper surface of the lower layer (e.g., the third encapsulation layer TFE3), protect the lower layer, and reduce the reflection of external light. The passivation layer SIP may be disposed in the display area DA and the non-display area NDA, and may be completely disposed on the substrate SUB. The passivation layer SIP may include one or more of an acrylic resin, an epoxy resin, and an urethane resin. In an embodiment, the passivation layer SIP may include an acrylic resin, such as isobornyl acrylate (IBOA).

[0116] The passivation layer SIP may have a predetermined thickness (e.g., a thickness of 8 μm to 30 μm) for planarization. The passivation layer SIP may be formed by an inkjet printing process. For example, the passivation layer SIP may be applied by an inkjet printing process and formed by a UV curing process. In an embodiment, the passivation layer SIP may be finally cured by heat treatment and plasma treatment after the UV curing process.

[0117] The surface of the passivation layer SIP can be modified by plasma treatment. The surface of the passivation layer SIP may have hydrophilicity. The hydrophilicity described in this article means having a characteristic of having excellent affinity for a predetermined solution, and as a characteristic different from hydrophilicity, hydrophobicity means a characteristic that a predetermined solution is repelled and water cannot penetrate well. For example, a predetermined solution has a high surface binding ability with a surface having hydrophilicity, and a predetermined solution disposed on a surface having hydrophilicity may have a reduced surface tension. In contrast, a predetermined solution has a low surface binding ability with a surface having hydrophobicity, and a predetermined solution disposed on a surface having hydrophobicity may have an increased surface tension.

[0118] In an example in which the surface of the passivation layer SIP is hydrophobic, the predetermined solution may have a contact angle greater than the contact angle when it is hydrophilic. The contact angle may refer to the angle formed between the tangent of the surface of the predetermined solution and a surface at a point where the predetermined solution contacts a surface on which the predetermined solution is disposed. The contact angle may increase with an increase in hydrophobicity or an increase in surface tension. For example, for a surface having hydrophobicity as described herein, when water is disposed on the surface, the contact angle of water on the surface may be in the range of greater than 90° and less than 180°, but is not limited thereto. In some aspects, for a surface having hydrophilicity, when water is disposed on the surface, the contact angle of water on the surface may be in the range of greater than 0° and less than 90°.

[0119] According to one or more embodiments of the present disclosure, the surface of the passivation layer SIP has hydrophilicity, and the contact angle between the surface of the passivation layer SIP and water may be in the range of 5° to 45°. Since the surface of the passivation layer SIP has hydrophilicity, the coating solution to be applied to the coating layer of the passivation layer SIP in the manufacturing method described herein may be uniformly applied.

[0120] Hereinafter, a method for manufacturing a display device described herein will be described with reference to other drawings.

[0121] Figure 7 A flowchart for explaining a method for manufacturing a display device according to an embodiment. Figure 8 A flowchart illustrating steps of forming a first passivation layer according to an embodiment.

[0122] refer to Figure 7 and Figure 8 , a method for manufacturing a display device according to an embodiment may include forming a display layer DU on a mother substrate MSUB (S100), forming a first passivation layer SIP on the display layer DU (S110), forming a second passivation layer DIP on the first passivation layer SIP (S120), attaching an acid-resistant film UNF to the second passivation layer DIP (S130), etching the mother substrate MSUB (S140), performing a UV curing process on the acid-resistant film UNF (S150), removing the acid-resistant film UNF (S160), cutting the mother substrate MSUB in units (S170), and removing the second passivation layer DIP.

[0123] In some embodiments, forming the first passivation layer SIP on the display layer DU (S110) may include applying a first coating layer COL1 on the display layer DU (S200), performing a UV curing process on the first coating layer COL1 (S210), performing a heat treatment process on the first coating layer COL1 (S220), and performing a plasma treatment process on the first coating layer COL1 (S230).

[0124] Figures 9 to 20 A view for explaining an exemplary process of a method for manufacturing a display device according to an embodiment.

[0125] In the following, we will combine Figure 7 and Figure 8 describe Figures 9 to 20 A method for manufacturing a display device.

[0126] refer to Fig. 9, the method for manufacturing a display device may include forming a display layer DU on a mother substrate MSUB (S100). As described herein, the mother substrate MSUB may be a glass substrate. The mother substrate MSUB may be a substrate on which a unit region (a plurality of units to be formed in the unit region) is formed so as to obtain a plurality of display devices 10 at a time. The unit region may be a region corresponding to one display device 10. The mother substrate MSUB may be a substrate SUB (see Figure 2 ), and aspects of the present disclosure support cutting the mother substrate MSUB in units through a cutting process described later herein. A plurality of display devices 10 may be arranged in a grid pattern and disposed on the mother substrate MSUB.

[0127] The display layer DU may be arranged in a plurality of unit areas. The display layer DU is as described herein with reference to Figure 6 In the following drawings, one unit area will be explained and described, and the exemplary aspects described with reference to the unit area can be applied to multiple unit areas described herein.

[0128] refer to Fig.10 , the method for manufacturing a display device may include forming a first passivation layer SIP on the display layer DU (S110). The first passivation layer SIP may be formed by applying a first coating layer COL1 on the display layer DU.

[0129] Specifically, for example, the method for manufacturing a display device may include applying a first coating layer COL1 to the display layer DU (S200). The first coating layer COL1 may be formed by applying a coating solution for forming a first passivation layer SIP. The coating solution may include an acrylic resin, such as isobornyl acrylate (IBOA). In some embodiments, the coating solution may include a photoinitiator, a solvent, an additive, and the like. The method for manufacturing a display device may include forming the first coating layer COL1 by an inkjet printing process. For example, the method for manufacturing a display device may include forming the first coating layer COL1 by aligning an inkjet device IPT with the display layer DU and spraying a coating solution while the inkjet device IPT moves in one direction. The first coating layer COL1 may be formed to have a thickness of 8 μm to 30 μm.

[0130] refer to Fig.10, the method for manufacturing a display device may include performing a UV curing process on the first coating layer COL1 (S210). In the UV curing process, the method for manufacturing a display device may include emitting UV light (e.g., irradiating the first coating layer COL1 with UV light), while aligning a UV emitting device UVT with the first coating layer COL1, and moving the UV emitting device UVT in one direction. In an embodiment, the first coating layer COL1 is an air-curing type, and the UV curing process may be performed in an air atmosphere at room temperature. In some embodiments, the UV curing process may use a UV lamp light source capable of emitting light of a wavelength of 365nm, 385nm, or 395nm, and in this example case, the UV lamp light source may emit UV light alone, or in combination with one or more other UV lamp light sources (not shown) to emit UV light. In some embodiments, the cumulative amount of UV light associated with the UV curing process may be in the range of 0.5J to 3J. The first coating layer COL1 may be cured in the UV curing process.

[0131] refer to Fig.11 , the method for manufacturing a display device may include performing a heat treatment process on the first coating layer COL1 (S220). The heat treatment process may be performed using an oven or an infrared ray emitting device IRT (also referred to herein as an IR emitting device IRT). For example, the method for manufacturing a display device may include emitting IR light (e.g., irradiating the first coating layer COL1 with IR light) while aligning the IR emitting device IRT with the first coating layer COL1 and moving the IR emitting device IRT in one direction. The heat treatment process may be performed at a temperature range of 70° C. to 90° C. for about 10 minutes to about 40 minutes.

[0132] In this embodiment, since the heat treatment process is performed after the UV curing process, some unreacted materials in the first coating layer COL1 in the UV curing process may be cross-linked and the remaining solvent may be removed. Therefore, for example, the curing rate of the first coating layer COL1 may be increased.

[0133] refer to Fig.12 The method for manufacturing a display device may include performing a plasma treatment process on the first coating layer COL1 (S230). The method for manufacturing a display device may include performing a plasma treatment process in an atmospheric pressure or vacuum atmosphere. The plasma treatment process may use N 2 Plasma or O 2 plasma, and in some example embodiments, N 2 In this embodiment, N 2 Plasma is described as an example.

[0134] In the plasma treatment process, the method for manufacturing a display device may include irradiating plasma while aligning the plasma device PLT to the first coating layer COL1 and moving the plasma device PLT in one direction. The method for manufacturing a display device may include performing the plasma treatment process at a power in the range of 1 kilowatt (kW) to 5 kW, a voltage in the range of 11 kilovolts (kV) to 15 kV, and a speed of 60 millimeters (mm) / second (s) to 260 mm / s. In this example, N 2 The flow rate of the gas is in the range of 200 liters per minute (LPM) to 1200 LPM, and the flow rate of the clean dry air (CDA) may be in the range of 2 LPM to 9 LPM. For example, in some embodiments, the plasma treatment process may be performed in which N 2 The flow rate of the gas is within a range of 200 LPM to 1200 LPM and the flow rate of the clean dry air (CDA) is within a range of 2 LPM to 9 LPM.

[0135] When the first coating layer COL1 is subjected to the plasma treatment process, unreacted materials remaining on the surface of the first coating layer COL1 may be removed, and the surface energy may be increased. Since the unreacted materials of the first coating layer COL1 are removed, the curing rate of the first coating layer COL1 may be further increased. In some aspects, since the surface energy of the first coating layer COL1 is increased, the surface of the first coating layer COL1 may have hydrophilicity.

[0136] As described herein, since the UV curing process, the heat treatment process, and the plasma treatment process are performed on the first coating layer COL1, the first passivation layer SIP formed through these processes may have an improved curing rate.

[0137] refer to Fig.13 and Fig.14 , a method for manufacturing a display device may include forming a second passivation layer DIP on the first passivation layer SIP (later in Fig.15 Specifically, for example, the method for manufacturing a display device may include forming a second passivation layer DIP by a UV curing process after applying a second coating layer COL2 onto the first passivation layer SIP. The second coating layer COL2 may serve as a passivation layer capable of protecting a layer on the lower side of the second coating layer COL2.

[0138] The second coating layer COL2 may include an acrylic resin similar to or the same as the acrylic resin described with reference to the first coating layer COL1. The method for manufacturing a display device may include applying the second coating layer COL2 by an inkjet printing process. For example, the method for manufacturing a display device may include applying the second coating layer COL2 to a thickness of 80 μm to 150 μm using an inkjet device IPT (e.g., such that the thickness of the second coating layer COL2 is 80 μm to 150 μm). A UV curing process of the second coating layer COL2 may be performed using a UV emitting device UVT. The UV curing process of the second coating layer COL2 may be performed under UV curing conditions similar to or the same as the UV curing conditions of the aforementioned first coating layer COL1.

[0139] refer to Fig.15 , the method for manufacturing a display device may include attaching an acid-resistant film UNF to the second passivation layer DIP (S130). The acid-resistant film UNF is used to prevent the display layer DU from being damaged by an etchant in the process of etching the mother substrate MSUB, and its example aspects will be described later in this article. The method for manufacturing a display device may include attaching an acid-resistant film UNF so that the acid-resistant film UNF completely covers the display layer DU, the first passivation layer SIP, and the second passivation layer DIP disposed on the mother substrate MSUB. The process of attaching the acid-resistant film UNF may be performed by a lamination process. The method for manufacturing a display device may include adhering the acid-resistant film UNF to the mother substrate MSUB, the display layer DU, the first passivation layer SIP, and the second passivation layer DIP by an adhesive, such as, for example, a pressure-sensitive adhesive (PSA).

[0140] The method for manufacturing a display device may include etching the mother substrate MSUB (S140). In the process of etching the mother substrate MSUB, the method for manufacturing a display device may include reducing the thickness of the mother substrate MSUB by spraying an etchant on the mother substrate MSUB. When the etchant is sprayed onto the mother substrate MSUB, the thickness of the mother substrate MSUB may be reduced, and the display layer DU may be protected from the etchant by the acid-resistant film UNF.

[0141] refer to Fig.16, the method for manufacturing a display device may include performing a UV curing process (S150) on the acid-resistant film UNF. When the acid-resistant film UNF is irradiated with UV, the PSA can be UV-cured and the adhesion can be reduced. That is, for example, by irradiating the acid-resistant film UNF with UV in the UV curing process, the adhesion of the PSA can be reduced, so that the peeling of the acid-resistant film UNF described later can be easily performed. For example, the reduced adhesion of the PSA supports a more effective peeling of the acid-resistant film UNF. The UV curing process can be performed by emitting UV light (for example, irradiating the acid-resistant film UNF with UV light) while moving the UV emitting device UVT in one direction. It should be understood that the mention of easier peeling of the film from another film can refer to reducing or preventing damage (such as tearing) to the film and / or another film.

[0142] refer to Fig.17 , the method for manufacturing a display device may include removing the acid-resistant film UNF (S160). The method for manufacturing a display device may include stripping and removing the acid-resistant film UNF using a stripping device. When the PSA with reduced adhesion is separated from the mother substrate MSUB, the display layer DU, the first passivation layer SIP, and the second passivation layer DIP, the acid-resistant film UNF may be stripped.

[0143] refer to Fig.18 , the method for manufacturing a display device may include cutting the mother substrate MSUB in units (S170). The method for manufacturing a display device may include cutting the mother substrate MSUB into a plurality of units. The cutting process may be performed using a cutting member WH (e.g., a cutting wheel or a laser). Through the cutting process, a plurality of display devices 10 in units may be separated from the mother substrate MSUB.

[0144] refer to Fig.19 and Fig. 20 , the method for manufacturing a display device may include removing the second passivation layer DIP (S180). The display device 10 separated from the mother substrate MSUB may include a display layer DU, a first passivation layer SIP, and a second passivation layer DIP on the substrate SUB. The second passivation layer DIP is used as a passivation layer for protecting the lower layer in the above process, and in some embodiments, the method for manufacturing a display device may include removing the second passivation layer DIP after performing the above process.

[0145] In some cases, when the curing rate of the first passivation layer SIP is low, during the UV irradiation process of the second passivation layer DIP, the uncured material of the first passivation layer SIP may be bonded to the second passivation layer DIP. That is, for such an example case, since the first passivation layer SIP and the second passivation layer DIP are bonded to each other, when the second passivation layer DIP is peeled off due to the uncured material, the first passivation layer SIP may be torn, or the encapsulation layer TFEL may be torn together with the first passivation layer SIP.

[0146] By increasing the curing rate of the first passivation layer SIP through the UV curing process, the heat treatment process, and the plasma treatment process according to example embodiments described herein, the first passivation layer SIP may be prevented from being torn when the second passivation layer DIP is peeled off.

[0147] Accordingly, the display device 10 in which the display layer DU and the first passivation layer SIP are disposed on the substrate SUB may be manufactured by removing the second passivation layer DIP.

[0148] Hereinafter, a method for manufacturing a display device according to another embodiment will be described with reference to other drawings.

[0149] Fig.21 A flowchart for illustrating a method for manufacturing a display device according to another embodiment. In some embodiments, the method described herein Figure 7 and Figure 8 A first passivation layer is formed on the display layer ( Figure 7 After S110 in Fig.21 Hereinafter, descriptions overlapping with those of the above-mentioned embodiments will be omitted or simplified.

[0150] refer to Fig.21 According to another embodiment, a method for manufacturing a display device may include applying a second coating layer COL2 on a first passivation layer SIP (S300), performing a UV curing process on the second coating layer COL2 (S310), performing a heat treatment process on the second coating layer COL2 (S320), forming a second passivation layer DIP1 by performing a plasma treatment process on the second coating layer COL2 (S330), forming a third passivation layer DIP2 by applying a third coating layer COL3 on the second passivation layer DIP1 and performing a UV curing process (340), attaching an acid-resistant film UNF to the third passivation layer DIP2 and etching a mother substrate MSUB (S350), performing a UV curing process on the acid-resistant film UNF (S360), removing the acid-resistant film UNF and the third passivation layer DIP2 at the same time (S370), cutting the mother substrate MSUB in units (S380), and removing the second passivation layer DIP1 (S390).

[0151] Figure 22 to Figure 26 A view for explaining an exemplary process of a method for manufacturing a display device according to another embodiment.

[0152] In the following, we will combine Fig.21 To describe Figure 22 to Figure 26 A method for manufacturing a display device.

[0153] refer to Fig. 22, the method for manufacturing a display device may include applying a second coating layer COL2 on the first passivation layer SIP (S300). As referred to herein Figures 10 to 12 As described, the first passivation layer SIP may be formed by performing a UV curing process, a heat treatment process, and a plasma treatment process. The second coating layer COL2 may be applied to the mother substrate MSUB. For example, the second coating layer COL2 may be applied to the upper surface of the first passivation layer SIP in the display layer DU and the first passivation layer SIP sequentially formed on the mother substrate MSUB.

[0154] The second coating layer COL2 may include an acrylic resin similar to or the same as the acrylic resin described with reference to the first passivation layer SIP. The method for manufacturing a display device may include applying the second coating layer COL2 by an inkjet printing process. For example, an inkjet device IPT (see Fig.13 ) The second coating layer COL2 is applied to a thickness of 80 μm to 150 μm (eg, applied so that the thickness of the second coating layer COL2 is 80 μm to 150 μm).

[0155] refer to Fig.23 , the method for manufacturing a display device may include performing a UV curing process on a second coating layer COL2 ( S310 ), performing a heat treatment process on the second coating layer COL2 ( S320 ), and forming a second passivation layer DIP1 by performing a plasma treatment process on the second coating layer COL2 ( S330 ).

[0156] The UV curing process, heat treatment process and plasma treatment process of the second coating COL2 can be the same as those described in the present invention. Figures 10 to 12 The UV curing process, heat treatment process and plasma treatment process of the first coating COL1 described above are similar or substantially the same. For example, a UV emitting device UVT can be used for the UV curing process, and an IR emitting device IRT (see Fig.12 ) is subjected to a heat treatment process, and the N 2 Plasma is used to perform a plasma treatment process.

[0157] In some aspects, the techniques described herein for performing a UV curing process, a heat treatment process, and a plasma treatment process on each of the first passivation layer SIP and the second passivation layer DIP1 can improve the curing rate of each of the first passivation layer SIP and the second passivation layer DIP1. In particular, by improving the curing rate of the second passivation layer DIP1, the second passivation layer DIP1 and the third passivation layer DIP2 (see FIG. 1 ) described later herein can be prevented or reduced. Fig.24 ) between the peeling defects.

[0158] refer to Fig.23, the method for manufacturing a display device may include forming a third passivation layer DIP2 by applying a third coating layer COL3 on the second passivation layer DIP1 and performing a UV curing process (S340). The method for manufacturing a display device may include applying a material to form the third coating layer COL3 by an inkjet printing process, wherein the material is similar to or the same as the material applied to form the second passivation layer DIP1. The method for manufacturing a display device may include curing the third coating layer COL3 by irradiating the third coating layer COL3 with UV light having a cumulative amount of UV light ranging from 0.5J to 3J using a UV emitting device UVT. In some examples, unlike the curing of the first passivation layer SIP and the second passivation layer DIP1 described above, the third coating layer COL3 may be cured by a UV curing process to form the third passivation layer DIP2, and other processes described with reference to the curing of the first passivation layer SIP and the second passivation layer DIP1 are not required. Accordingly, for example, because adhesion between the third passivation layer DIP2 and the second passivation layer DIP1 is relatively low, when the acid-resistant film UNF described later is peeled off, the third passivation layer DIP2 may be easily peeled off from the second passivation layer DIP1 .

[0159] refer to Fig.24 , the method for manufacturing a display device may include attaching an acid-resistant film UNF to the third passivation layer DIP2 and etching the mother substrate MSUB (S350). The method for manufacturing a display device may include attaching the acid-resistant film UNF so that the acid-resistant film UNF completely covers the display layer DU, the first passivation layer SIP, the second passivation layer DIP1, and the third passivation layer DIP2 disposed on the mother substrate MSUB. In some embodiments, the process of attaching the acid-resistant film UNF may be performed by a lamination process.

[0160] In the process of etching the mother substrate MSUB, the method for manufacturing a display device may include reducing the thickness of the mother substrate MSUB by spraying an etchant on the mother substrate MSUB. When the etchant is sprayed onto the mother substrate MSUB, the thickness of the mother substrate MSUB may be reduced, and the display layer DU may be protected from the etchant by the acid-resistant film UNF.

[0161] refer to Fig.25 , the method for manufacturing a display device may include performing a UV curing process on the acid-resistant film UNF (S360). When the acid-resistant film UNF is irradiated with UV light, the PSA disposed on one surface of the acid-resistant film UNF is UV-cured, and its adhesion is reduced, so that the acid-resistant film UNF can be easily peeled off. The UV curing process can be performed by emitting UV light (irradiating the acid-resistant film UNF with UV light) while moving the UV emitting device UVT in one or more directions (e.g., one direction).

[0162] refer to Fig.26, the method for manufacturing a display device may include removing the acid-resistant film UNF and the third passivation layer DIP2 at the same time (S370). The method for manufacturing a display device may include stripping and removing the acid-resistant film UNF using a stripping device. When the acid-resistant film UNF is stripped, the third passivation layer DIP2 may be stripped together with the acid-resistant film UNF. As described herein, because the curing rate of the third passivation layer DIP2 is relatively low, the third passivation layer DIP2 may be easily separated from the second passivation layer DIP1. Accordingly, when the acid-resistant film UNF is stripped, the third passivation layer DIP2 adhered to the acid-resistant film UNF may be stripped together with the acid-resistant film UNF.

[0163] The display device according to the embodiment can be manufactured by cutting the mother substrate MSUB in units (S380) and removing the second passivation layer DIP1 (S390). Figures 18 to 20 The cutting process and the process of removing the second passivation layer DIP1 are described, so a description thereof will be omitted.

[0164] In some cases, when the curing rate of the above-mentioned first passivation layer SIP is low, during the UV irradiation process of the second passivation layer DIP1, the uncured material of the first passivation layer SIP may be combined with the second passivation layer DIP1. Accordingly, when the acid-resistant film UNF is peeled off, the first passivation layer SIP and the second passivation layer DIP1 may be torn together. According to one or more embodiments of the present disclosure described herein, the curing rate can be increased by performing a UV curing process, a heat treatment process, and a plasma treatment process on each of the first passivation layer SIP and the second passivation layer DIP1, and the first passivation layer SIP and the second passivation layer DIP1 can be prevented from being damaged by further forming a third passivation layer DIP2 on the second passivation layer DIP1, which supports the simultaneous peeling of the third passivation layer DIP2 when the acid-resistant film UNF is peeled off.

[0165] Table 1 below shows example results of performing a UV curing process, a heat treatment process, and a plasma treatment process on a first passivation layer, forming a second passivation layer on the first passivation layer, and then stripping the second passivation layer.

[0166] [Table 1]

[0167]

[0168] Referring to Table 1 above, when the UV curing process of 1.5J, the heat treatment process of 80℃ / 30min and the use of N 2When the first passivation layer is formed by a plasma treatment process using plasma, it is confirmed that the second passivation layer is well stripped without damaging the first passivation layer. In contrast, for example, under other process conditions, the second passivation layer is torn, so that the stripping cannot be properly performed (for example, the first passivation layer is damaged due to the stripping of the second passivation layer) or the first passivation layer and the encapsulation layer are stripped together.

[0169] Table 2 below shows the contact angles between the surface of the first passivation layer and water before and after the plasma treatment (also referred to as "contact angle of the surface").

[0170] Specifically, for example, acrylic resin is coated on the substrate, and a UV curing process, a heat treatment process, and a N 2 Plasma treatment process of plasma In this example, the plasma treatment process is performed at different speeds of 60 mm / s and 250 mm / s respectively.

[0171] [Table 2]

[0172]

[0173] Referring to Table 2 above, it is confirmed that after the surface of the first passivation layer is subjected to the plasma treatment process, the contact angle between the surface of the first passivation layer and water is in the range of 5° to 45°. From this result, it can be seen that as a result of the plasma treatment process of the surface of the first passivation layer as described herein, the surface has hydrophilicity.

[0174] Fig. 27 FIG. 1 is a graph illustrating a peeling force between a first passivation layer and a second passivation layer according to a distance from an end of the first passivation layer. Fig. 27 In the comparative example, a PET film is formed as the second passivation layer, and in the example embodiment, an acrylic resin coating is applied by an inkjet printing process to form the second passivation layer. In the example embodiment, the first passivation layer is subjected to a UV curing process, a heat treatment process, and a plasma treatment process according to the process conditions explained in #7 of Table 1 above.

[0175] refer to Fig. 27 , in the area of ​​the graph corresponding to the distance range of 100 mm to 200 mm from the end of the first passivation layer, the peeling forces of the second passivation layer in the example embodiment and the comparative example were approximately 7.02 gf / inch and approximately 6.78 gf / inch, respectively, showing similar levels to each other.

[0176] Through this result, in the example embodiment in which the first passivation layer is subjected to a UV curing process, a heat treatment process, and a plasma treatment process and the second passivation layer is formed by an inkjet printing process, it is confirmed that the second passivation layer is easily separated due to a weak peeling force, as in the comparative example in which a PET film is attached to the first passivation layer.

[0177] Fig.28 Figure 1 is a graph of FT-IR analysis of the coating solution and the passivation layer. Fig.28 , the horizontal axis represents the wave number, and the vertical axis represents the absorbance unit.

[0178] refer to Fig.28 , it can be seen that the 1230cm -1 The wave number of 1120cm indicates the COC bond. -1 The wave number of 810cm indicates the C=C bond. -1 At the wave number of , the absorbance unit of the passivation layer is reduced compared to the absorbance unit of the coating solution. The curing rate of the passivation layer can be obtained by calculating the ratio of the absorbance unit of the passivation layer to the absorbance unit of the coating solution at each wave number. It can be seen that the curing rate of the passivation layer formed by performing the UV curing process, the heat treatment process and the plasma treatment process on the coating solution increases. The lower the absorbance, the higher the curing rate. Fig.28 It is shown that the absorbance of the passivation layer is lower than that of the coating solution, and thus the curing rate of the protective layer formed by performing the UV curing process, the heat treatment process, and the plasma treatment process on the coating solution increases.

[0179] At the end of the detailed description, those skilled in the art will recognize that many variations and modifications may be made to the exemplary embodiments without departing substantially from the principles of the invention. Therefore, the exemplary embodiments of the present invention disclosed are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, comprising: substrate; A light emitting element layer, disposed on the substrate and comprising a pixel electrode, an organic layer and a common electrode; An encapsulation layer, disposed on the light-emitting element layer; as well as A passivation layer is disposed on the encapsulation layer, The contact angle between the surface of the passivation layer and water is in the range of 5° to 45°. 2 . The display device according to claim 1 , wherein the surface of the passivation layer has hydrophilicity. 3 . The display device according to claim 1 , wherein the passivation layer comprises one or more of an acrylic resin, an epoxy resin, and a urethane resin. 4 . The display device according to claim 1 , wherein the passivation layer is formed to have a thickness of 8 μm to 30 μm.

5. The display device according to claim 1, wherein the encapsulation layer comprises a first encapsulation layer disposed on the light emitting element layer, a second encapsulation layer disposed on the first encapsulation layer, and a third encapsulation layer disposed on the second encapsulation layer, and The passivation layer contacts an upper surface of the third encapsulation layer.

6. A method for manufacturing a display device, the method comprising: forming a display layer on a mother substrate; applying a first coating layer on the display layer; Forming a first passivation layer by sequentially performing a first UV curing process, a heat treatment process, and a plasma treatment process on the first coating layer; as well as forming a second passivation layer on the first passivation layer, The plasma treatment process uses N2 plasma. The method of claim 6 , wherein the first coating is applied by an inkjet printing process. 8 . The method according to claim 6 , wherein the first coating layer is applied such that the thickness of the first coating layer is 8 μm to 30 μm. 9 . The method according to claim 6 , wherein the cumulative amount of UV light in the first UV curing process is 0.5 J to 3 J.

10. The method according to claim 6, wherein the heat treatment process is performed at a temperature range of 70°C to 90°C for 10 minutes to 40 minutes. 11 . The method according to claim 6 , wherein the plasma treatment process is performed at a power of 1 kW to 5 kW, a voltage of 11 kV to 15 kV, and a speed of 60 mm / s to 260 mm / s. 12 . The method according to claim 6 , wherein a flow rate of the N 2 gas of the N 2 plasma is 200 LPM to 1200 LPM. 13 . The method according to claim 6 , wherein the second passivation layer is formed by applying a second coating layer on the first passivation layer and performing a second UV curing process.

14. The method according to claim 6, further comprising: attaching an acid-resistant film to the second passivation layer; etching the mother substrate; Performing a third UV curing process on the acid-resistant film; removing the acid-resistant film; cutting the mother substrate in units; as well as The second passivation layer is removed. 15 . The method of claim 14 , wherein the etching of the mother substrate comprises spraying an etchant on the mother substrate to reduce a thickness of the mother substrate.

16. A method for manufacturing a display device, the method comprising: forming a display layer on a mother substrate; forming a first passivation layer by applying a first coating layer on the display layer and sequentially performing a first UV curing process, a first heat treatment process, and a first plasma treatment process on the first coating layer; forming a second passivation layer by applying a second coating layer on the first passivation layer and sequentially performing a second UV curing process, a second heat treatment process, and a second plasma treatment process on the second coating layer; as well as forming a third passivation layer on the second passivation layer, The first plasma treatment process and the second plasma treatment process use N2 plasma. 17 . The method according to claim 16 , wherein the first plasma treatment process and the second plasma treatment process are performed at a power of 1 kW to 5 kW, a voltage of 11 kV to 15 kV, and a speed of 60 mm / s to 260 mm / s.

18. The method according to claim 16, wherein the flow rate of the N2 gas of the N2 plasma is 200 LPM to 1200 LPM.

19. The method according to claim 16, further comprising: attaching an acid-resistant film to the third passivation layer and etching the mother substrate; Performing a third UV curing process on the acid-resistant film; Simultaneously removing the acid-resistant film and the third passivation layer; cutting the mother substrate in units; as well as The second passivation layer is removed.

20. The method of claim 16, wherein forming the third passivation layer comprises applying a third coating layer on the second passivation layer, and wherein the first coating layer, the second coating layer, and the third coating layer are each applied by an inkjet printing process.

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