Semiconductor detector, CT scanning apparatus and detector position error measurement system

Abstract

The application relates to a semiconductor detector, a CT scanning device and a detector position error measurement system. The semiconductor detector is applied to the CT scanning device and comprises a base structure, a protection layer and an engraved layer. The base structure comprises a semiconductor crystal layer and an electrode layer group, the electrode layer group comprises a planar electrode layer and a pixel electrode layer, the semiconductor crystal layer has a first surface and a second surface which are oppositely arranged along the thickness direction of the semiconductor crystal layer, the planar electrode layer is arranged on the first surface, and the pixel electrode layer comprises a plurality of pixel electrodes which are arranged on the second surface at intervals. The protection layer is arranged on at least part of the surface of the base structure. The engraved layer is formed on the side of the protection layer which is away from the base structure, and the engraved layer carries engraved information. The semiconductor detector can be engraved with marks on the surface without affecting the performance of the semiconductor detector, so that the crystal direction and other information of each semiconductor detector can be quickly identified during the installation process, and the installation efficiency is improved. After the installation is completed, the information of each semiconductor detector can be identified and traced according to the mark information.

Description

Technical Field

[0001] This application relates to the field of medical device technology, and in particular to semiconductor detectors, CT scanning equipment, and detector position error measurement systems. Background Technology

[0002] A semiconductor detector is a radiation detector that uses semiconductor materials as the detection medium. It has two electrodes with a bias voltage applied between them. When an incident particle enters the sensitive area of ​​the semiconductor detector, an electron-hole pair is generated. After a voltage is applied to the electrodes, charge carriers drift towards the electrodes, inducing a charge on the collecting electrode. This generates a signal pulse in the external circuit, which is then amplified and analyzed by the instrument. A typical structure of a semiconductor detector used in CT scanning equipment consists of a planar electrode on one side of a semiconductor photosensitive crystal (including but not limited to cadmium zinc telluride, cadmium telluride, gallium arsenide, silicon, germanium, etc.) that absorbs X-rays, and a pixel electrode on the other side.

[0003] CT scanning equipment requires the assembly of multiple semiconductor detectors. For example, a 64-slice CT scanner may require hundreds of semiconductor detectors. During manufacturing, the crystals of these detectors need to be installed in predetermined positions and orientations. However, in related technologies, it is difficult to imprint markings on the surface of the semiconductor detectors without affecting their performance. This makes it difficult to quickly identify the crystal orientation and other information of each detector during installation, impacting installation efficiency. Furthermore, it is difficult to identify and trace the information of each detector after installation. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor detector, CT scanning equipment, and detector position error measurement system to mark the surface of the semiconductor detector without affecting its performance. This facilitates the rapid identification of information such as the crystal orientation of each semiconductor detector during installation, thereby improving installation efficiency. Furthermore, after installation, the information of each semiconductor detector can be identified and traced based on the marking information, enabling the identification of the root cause of subsequent faults and the summarization of experience.

[0005] A semiconductor detector for use in a CT scanning device, the semiconductor detector comprising:

[0006] A substrate structure includes a semiconductor crystal layer and an electrode layer group. The electrode layer group includes a planar electrode layer and a pixel electrode layer. The semiconductor crystal layer has a first surface and a second surface that are disposed opposite to each other along its own thickness direction. The planar electrode layer is disposed on the first surface. The pixel electrode layer includes a plurality of pixel electrodes that are disposed at intervals on the second surface.

[0007] A protective layer is disposed on at least a portion of the surface of the substrate structure; and

[0008] An imprint layer is formed on the side of the protective layer opposite to the substrate structure, and the imprint layer carries imprint information.

[0009] The aforementioned semiconductor detector has a protective layer on at least a portion of the substrate structure's surface. This layer protects and isolates the substrate structure, preventing contamination or mechanical damage during the formation of the imprinting layer. It also minimizes the impact of external air and moisture on the detector's surface, thus maintaining optimal performance. The imprinting layer is formed on the side of the protective layer facing away from the substrate structure, i.e., on its outer surface. By pre-selecting markings, the imprinting layer can carry information such as crystal orientation, pixel electrode positions, and electrode arrangement, marking each semiconductor detector. This allows for rapid installation by identifying these markings, improving efficiency and accuracy. After installation, the marking information allows for traceability of each semiconductor detector, enabling troubleshooting and analysis of potential problems, and ultimately, experience gained.

[0010] In one embodiment, the electrode layer group includes a circuit connection area for connection to an external circuit, and a non-circuit connection area located outside the circuit connection area. The protective layer is conductive and covers the circuit connection area and / or the non-circuit connection area.

[0011] In one embodiment, the protective layer is made of metal or doped semiconductor.

[0012] In one embodiment, the electrode layer group includes a circuit connection region for connection to an external circuit, and a non-circuit connection region located outside the circuit connection region. The semiconductor crystal layer has an exposed surface not covered by the electrode layer group. The protective layer is insulating and covers the non-circuit connection region and / or the exposed surface.

[0013] In one embodiment, the protective layer is made of at least one of polymer materials, silicone, aluminides, carbides, oxides, nitrides, borides, fluorides, and ceramics.

[0014] In one embodiment, the protective layer has a Mohs hardness of not less than 5;

[0015] And / or, the thickness of the protective layer ranges from 10 nm to 500 μm;

[0016] And / or, the thermal conductivity of the protective layer is less than 100 W / m·K;

[0017] And / or, the protective layer has a transmittance of less than 0.5 for visible light and a transmittance of greater than 0.1 for infrared light.

[0018] In one embodiment, the thickness of the imprinted layer ranges from 10 nm to 200 μm;

[0019] And / or, the etched layer has a transmittance of less than 0.5 for visible light and a transmittance of greater than 0.1 for infrared light;

[0020] And / or, the material of the imprinted layer is at least one of ink, polymer material, ceramic, metal oxide, carbide, and semiconductor material.

[0021] A CT scanning device includes a plurality of semiconductor detectors; at least one of the semiconductor detectors includes:

[0022] A substrate structure includes a semiconductor crystal layer and an electrode layer group. The electrode layer group includes a planar electrode layer and a pixel electrode layer. The semiconductor crystal layer has a first surface and a second surface that are disposed opposite to each other along its own thickness direction. The planar electrode layer is disposed on the first surface. The pixel electrode layer includes a plurality of pixel electrodes that are disposed at intervals on the second surface.

[0023] A protective layer is provided on the planar electrode layer;

[0024] A protective layer is provided on the pixel electrode layer or a protective layer is provided between at least two adjacent pixel electrodes;

[0025] The protective layer is used to shield the semiconductor detector from external interference.

[0026] In the aforementioned CT scanning equipment, at least one semiconductor detector has a protective layer disposed on the planar electrode layer, the pixel electrode layer, or between at least two adjacent pixel electrodes. This layer protects and isolates the substrate structure, preventing contamination or mechanical damage to the substrate surface during the formation of the imprint layer. It also minimizes the impact of external air and moisture on the detector surface, thus maintaining optimal detector performance. The imprint layer is formed on the side of the protective layer facing away from the substrate structure, i.e., on the outer surface of the protective layer. By pre-selecting the imprint layer, it can carry imprint information such as crystal orientation, pixel electrode position, and electrode arrangement, thereby marking each semiconductor detector. This allows for rapid installation by identifying these markings, improving installation efficiency and accuracy. After installation, the marking information can be used to identify and trace the information of each semiconductor detector, enabling troubleshooting and analysis of potential problems, and allowing for the summarization of best practices.

[0027] A detector position error measurement system, the detector position error measurement system comprising:

[0028] A scanning device is used to scan the engraved information;

[0029] A controller, communicatively connected to the scanning device, is capable of obtaining pixel electrode position errors based on the imprinting information.

[0030] The aforementioned detector position error measurement system can scan the imprint information carried by the imprint layer through a scanning device. The controller can calculate the pixel electrode position based on the specific geometric correspondence between the imprint information and the pixel electrode position, and then compare it with the preset pixel electrode target position to obtain the pixel electrode position error and determine whether the flip-chip result meets the requirements.

[0031] In one embodiment, the controller obtains the first position coordinates of the imprinted layer based on the imprinting information, and obtains the second position coordinates of the pixel electrode based on the first position coordinates and the coordinate transformation relationship between the imprinted layer and the corresponding pixel electrode;

[0032] The controller compares the second position coordinates with the preset position coordinates of the pixel electrode to obtain the pixel electrode position error. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the substrate structure of a semiconductor detector in one embodiment of this application.

[0034] Figure 2 This is a schematic diagram of the substrate structure of a semiconductor detector in one embodiment of this application from another perspective.

[0035] Figure 3 This is a front view of a semiconductor detector in one embodiment of this application.

[0036] Figure 4 This is a schematic diagram of a semiconductor detector in one embodiment of this application.

[0037] Figure 5 This is a schematic diagram of a detector position error measurement system in one embodiment of this application.

[0038] Figure label:

[0039] 10. Semiconductor detectors;

[0040] 100. Substrate structure; 110. Semiconductor crystal layer; 111. First surface; 112. Second surface; 113. Exposed surface; 120. Planar electrode layer; 130. Pixel electrode layer; 131. Pixel electrode;

[0041] 200. Protective layer;

[0042] 300. Engraving layer;

[0043] 400. Scanning device. Detailed Implementation

[0044] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0045] In the description of this application, it should be understood that if terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" appear, these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0046] Furthermore, where the terms "first" and "second" appear, these terms are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, where the term "multiple" appears, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0047] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0048] In this application, unless otherwise expressly specified and limited, the use of descriptions such as "above" or "below" the second feature indicates that the first and second features are in direct contact or indirect contact via an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. Similarly, "below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0049] It should be noted that if an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. If an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. If so, the terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used in this application are for illustrative purposes only and do not represent the only possible implementation.

[0050] A semiconductor detector is a radiation detector that uses semiconductor material as the detection medium. It has two electrodes with a bias voltage applied between them. When an incident particle enters the sensitive region of the semiconductor detector, electron-hole pairs are generated. After a voltage is applied to the electrodes, charge carriers drift towards the electrodes, inducing charges on the collecting electrodes. This generates a signal pulse in the external circuit, which is then amplified and analyzed by the instrument. A typical structure of a semiconductor detector consists of a planar electrode on one side of a semiconductor photosensitive crystal that absorbs X-rays (including but not limited to cadmium zinc telluride, cadmium telluride, gallium arsenide, silicon, germanium, etc.) and a pixel electrode on the other side.

[0051] For CT scanning equipment, such as photon counting detectors or scintillator detectors, multiple semiconductor detectors need to be assembled. For example, a 64-slice CT scanner requires hundreds of semiconductor detectors. During manufacturing, the crystals of these semiconductor detectors need to be installed in predetermined positions and orientations. In related technologies, it is difficult to imprint markings on the surface of the semiconductor detectors without affecting their performance. This makes it difficult to quickly identify the crystal orientation and other information of each semiconductor detector during installation, affecting installation efficiency. Furthermore, after installation, it is difficult to identify and trace the information of each semiconductor detector.

[0052] Based on this, embodiments of this application provide a semiconductor detector, a CT scanning device, and a method for manufacturing a semiconductor detector, so as to enable marking on the surface of the semiconductor detector without affecting its performance, thereby facilitating the rapid identification of information such as the crystal orientation of each semiconductor detector during installation, thereby improving installation efficiency and accuracy; and after installation, the information of each semiconductor detector can be identified and traced according to the marking information, so as to trace the source of the problem in the event of subsequent failures, find the cause of the problem, and summarize experience based on this.

[0053] See Figures 1 to 4 This application provides a semiconductor detector 10 that is used in a CT scanning device. The semiconductor detector 10 includes a substrate structure 100, a protective layer 200, and an imprint layer 300. The substrate structure 100 includes a semiconductor crystal layer 110 and an electrode layer group, which includes a planar electrode layer 120 and a pixel electrode layer 130. The semiconductor crystal layer 110 has a first surface 111 and a second surface 112 disposed opposite to each other along its thickness direction. The planar electrode layer 120 is disposed on the first surface 111, and the pixel electrode layer 130 includes a plurality of pixel electrodes 131 spaced apart on the second surface 112. The protective layer 200 is disposed on at least a portion of the surface of the substrate structure 100. The imprint layer 300 is formed on the side of the protective layer 200 facing away from the substrate structure 100, and carries imprint information.

[0054] The aforementioned semiconductor detector 10 has a protective layer 200 on at least a portion of the surface of the substrate structure 100. This layer protects and isolates the substrate structure 100 from contamination or mechanical damage during the formation of the imprint layer 300, minimizing changes in the detector's surface condition due to external air and moisture, thus maintaining optimal detector performance. The imprint layer 300 is formed on the side of the protective layer 200 away from the substrate structure 100, i.e., on the outer surface of the protective layer 200. The imprint layer 300 can be pre-selected to carry imprint information such as crystal orientation, pixel electrode 131 position, and electrode arrangement, thereby marking each semiconductor detector 10. This allows for rapid installation of the semiconductor detectors 10 by identifying these markings, improving installation efficiency and accuracy. After installation, the information of each semiconductor detector 10 can be identified and traced based on the marking information, enabling troubleshooting and analysis of potential problems, and allowing for the summarization of best practices.

[0055] From the perspective of the attached diagram, the first surface 111 is the top surface of the semiconductor crystal layer 110, and the second surface 112 is the bottom surface of the semiconductor crystal layer 110.

[0056] See Figures 1 to 4In some embodiments, the electrode layer group includes a circuit connection area for connection to an external circuit and a non-circuit connection area located outside the circuit connection area. The protective layer 200 is conductive and covers the circuit connection area and / or the non-circuit connection area.

[0057] Specifically, according to the operating principle of semiconductor detectors, a voltage needs to be applied between the pixel electrode layer 130 and the planar electrode layer 120 to allow charge carriers to drift between the electrodes. Both the planar electrode layer 120 and the pixel electrode layer 130 have portions for connection to external circuits to apply bias voltage; these portions are called circuit connection areas. When the protective layer 200 is made of a conductive material, if it covers the circuit connection areas, the connection to the external circuit can be achieved through the conductive protective layer 200 without affecting the application of bias voltage between the pixel electrode layer 130 and the planar electrode layer 120. If the protective layer 200 covers the non-circuit connection areas, the pixel electrode layer 130 and the planar electrode layer 120 can still be connected to the external circuit normally through the circuit connection areas, without affecting the application of bias voltage between them. The protective layer 200 can also simultaneously cover both circuit connection areas and non-circuit connection areas, allowing for multiple etched areas.

[0058] See Figures 1 to 4 In some embodiments, the protective layer 200 is laid on the side of the planar electrode layer 120 opposite to the first surface 111, and the etched layer 300 is formed on the side of the protective layer 200 opposite to the planar electrode layer 120.

[0059] From the perspective of the attached figures, the protective layer 200 is laid on the top surface of the planar electrode layer 120, and the marking layer 300 is formed on the top surface of the protective layer 200. Typically, the planar electrode layer 120 has a relatively small thickness. In the above embodiment, the protective layer 200 is laid on the outer surface of the planar electrode layer 120, thereby protecting and isolating the planar electrode layer 120 during the formation of the marking layer 300, preventing mechanical damage or contamination during the marking process, and thus enabling marking without affecting the performance of the semiconductor detector.

[0060] See Figures 1 to 4 In some embodiments, the protective layer 200 is laid on the side of the pixel electrode layer 130 opposite to the second surface 112, and the etched layer 300 is formed on the side of the protective layer 200 opposite to the pixel electrode layer 130.

[0061] From the perspective of the attached figures, the protective layer 200 is laid on the bottom surface of the pixel electrode layer 130, and the imprinting layer 300 is formed on the bottom surface of the protective layer 200. In the above embodiment, the protective layer 200 is laid on the outer surface of the pixel electrode layer 130, thereby protecting and isolating the pixel electrode layer 130 when the imprinting layer 300 is formed, so as to prevent mechanical damage or contamination to the pixel electrode layer 130 during the imprinting process, thereby achieving imprinting and marking without affecting the performance of the semiconductor detector.

[0062] Typically, there are other structures outside the pixel electrode layer 130 or the planar electrode layer 120. In some embodiments, the outer structures may be made of transparent material to facilitate observation of the imprinted information on the pixel electrode layer 130.

[0063] Furthermore, in some embodiments, the conductive protective layer 200 is made of metal or doped semiconductor.

[0064] See Figures 1 to 4 In some embodiments, the electrode layer group includes a circuit connection area for connection to an external circuit, and a non-circuit connection area located outside the circuit connection area. The protective layer 200 is insulating and covers the non-circuit connection area.

[0065] Understandably, when the protective layer 200 is made of an insulating material, in order not to affect the application of bias voltage between the pixel electrode layer 130 and the planar electrode layer 120, the protective layer 200 can only be set in the non-circuit connection area to ensure that the external circuit can be normally connected to the circuit connection area.

[0066] See Figures 1 to 4 In some embodiments, the semiconductor crystal layer 110 has an exposed surface 113 not covered by the electrode layer group, and the protective layer 200 is insulating and covers the exposed surface 113.

[0067] Specifically, the semiconductor crystal layer 110 has an exposed surface 113 that is not covered by the planar electrode layer 120 and the pixel electrode layer 130. The protective layer 200 is laid on the exposed surface 113 and is insulating. The etched layer 300 is formed on the side of the protective layer 200 away from the exposed surface 113.

[0068] In the embodiment shown in the attached figures, the exposed surface 113 is a plurality of sidewalls of the semiconductor crystal layer 110. A protective layer 200 can be deposited on one or more sidewalls of the semiconductor crystal layer 110, and an etched layer 300 can be formed on the outer sidewall of the protective layer 200. The protective layer 200 provides insulation, thereby preventing the introduction of additional leakage current when a voltage is applied between the pixel electrode layer 130 and the planar electrode layer 120.

[0069] In the above embodiments, by providing a protective layer 200 on the exposed surface 113, the exposed surface 113 can be protected and isolated when the imprinting layer 300 is formed, so as to prevent damage or contamination to the exposed surface 113 during the imprinting process, which would affect the crystal performance. This allows for imprinting and marking without affecting the performance of the semiconductor detector.

[0070] In some embodiments, the protective layer 200 may also cover both the non-circuit connection area and the exposed surface 113 simultaneously, with multiple markings.

[0071] Furthermore, in some embodiments, the insulating protective layer 200 is made of at least one of polymer materials, silicone, aluminides, carbides, oxides, nitrides, borides, fluorides, and ceramics.

[0072] See Figures 1 to 4 In some embodiments, the protective layer 200 has a Mohs hardness of not less than 5. This ensures that the protective layer 200 has sufficiently high hardness, thereby better protecting its inner structure during the engraving process and preventing mechanical damage.

[0073] In some embodiments, the thickness of the protective layer 200 ranges from 10 nm to 500 μm. This ensures the protective layer 200 has a sufficiently large thickness to better protect its inner structure during the imprinting process, preventing mechanical damage, and also to better isolate air and moisture, preventing them from penetrating the protective layer 200 and affecting the detector surface condition.

[0074] In some embodiments, the thermal conductivity of the protective layer 200 is less than 100 W / m·K. Having a low thermal conductivity in the protective layer 200 reduces the transfer of heat generated during the etching process to the semiconductor crystal layer 110, thus preventing damage to the semiconductor crystal layer 110.

[0075] In some embodiments, the protective layer 200 has a transmittance of less than 0.5 for visible light and a transmittance of greater than 0.1 for infrared light. Generally, infrared light can improve the operational stability of the detector. By selecting a material for the protective layer 200 that has high transmittance for infrared light, the operational stability of the detector can be further improved.

[0076] In some embodiments, when the protective layer 200 is made of oxide, it can form tellurium (Te) oxide as a passivation layer on the detector surface. The resistivity of the passivation layer is higher than that of the semiconductor crystal layer 110, thereby reducing the leakage current of the detector.

[0077] In some embodiments, the thickness of the imprinted layer 300 ranges from 10 nm to 200 μm.

[0078] When the above range is met, the engraving information formed is clearer, and it is less likely to damage the protective layer 200.

[0079] In some embodiments, the etched layer 300 has a transmittance of less than 0.5 for visible light and a transmittance of greater than 0.1 for infrared light. Generally, infrared light can improve the operational stability of the detector. By selecting the material of the etched layer 300 to have high transmittance for infrared light, the operational stability of the detector can be further improved.

[0080] In some embodiments, the material of the embossing layer 300 is at least one of ink, polymer material, ceramic, metal oxide, carbide, and semiconductor material.

[0081] In some embodiments, the imprinting information carried by the imprinting layer 300 may be of various types, such as crystal number, orientation mark with a specific geometric correspondence to crystal orientation and electrode arrangement, and positioning mark with a specific geometric correspondence to crystal pixel electrode position.

[0082] See Figures 1 to 4 One embodiment of this application provides a detector flip-chip system including an identification device and a transport device. The identification device is used to identify imprint information. The transport device is communicatively connected to the identification device and is capable of transporting the semiconductor detector 10 to the target flip-chip position based on the imprint information.

[0083] The aforementioned detector flip-chip system can identify the imprint information carried on the imprint layer 300 through an identification device. The transport device can then transport the semiconductor detector 10 to the pre-set target flip-chip position based on this imprint information, thereby quickly completing the installation of each semiconductor detector 10 and improving installation efficiency.

[0084] Specifically, the transport device includes a robotic arm and grippers or suction cups connected to the robotic arm. After the identification device identifies the engraving information on each semiconductor detector, the robotic arm drives the grippers or suction cups to transport each semiconductor detector to the target flip-chip position on the substrate for flip-chip bonding. The identification device can be a CCD camera or a laser scanner, etc.

[0085] See Figures 1 to 5 An embodiment of this application provides a detector position error measurement system including a scanning device 400 and a controller. The scanning device 400 is used to scan imprint information, and the controller is communicatively connected to the scanning device 400. The controller can obtain the pixel electrode position error based on the imprint information.

[0086] The aforementioned detector position error measurement system can scan the imprint information carried by the imprint layer 300 through the scanning device 400. The controller can calculate the position of the pixel electrode 131 based on the specific geometric correspondence between the imprint information and the pixel electrode position, and then compare it with the preset pixel electrode target position to obtain the pixel electrode position error and determine whether the flip position meets the requirements.

[0087] In some embodiments, the controller obtains the first position coordinates of the imprint layer 300 based on the imprint information, and obtains the second position coordinates of the pixel electrode 131 based on the first position coordinates and the coordinate transformation relationship between the imprint layer 300 and the corresponding pixel electrode 131.

[0088] The controller compares the second position coordinates with the preset position coordinates of the pixel electrode 131 to obtain the pixel electrode position error.

[0089] The scanning device 400 is a camera that transmits the scanned imprint information to the controller. The coordinate transformation relationship between the imprint layer 300 and the corresponding pixel electrode 131 is known. The imprint information carries the first position coordinates of the imprint layer 300. The controller performs coordinate transformation based on the first position coordinates and the aforementioned coordinate transformation relationship to obtain the second position coordinates of the corresponding pixel electrode 131. The preset position coordinates of the pixel electrode 131 are also known. By comparing the second position coordinates with the preset position coordinates, the pixel electrode position error can be obtained.

[0090] Specifically, for each pixel electrode 131, a specific etched pattern is designed, such as a cross shape or a grid shape, and the relationship function between the position of the etched pattern and the position of the pixel electrode 131 is known. Specifically, assume the position coordinates of the i-th pixel electrode 131 are (x... i ,y i The corresponding position coordinates of the engraved pattern are (p i ,q i ), function (p i ,q i )=f[(x i ,y i [It is known.] By scanning the imprinting information carried by the imprinting layer 300 using the scanning device 400, the position coordinates (p) of the i-th imprinted pattern can be obtained. i ,q i Based on the inverse function of the relationship between the position of the etched pattern and the position of the pixel electrode 131, the controller calculates the actual position coordinates of each pixel electrode 131 of the detector, i.e., (x... i ,y i )=f -1 [(p i ,q i The controller will (x)i ,y i The position coordinates of the pixel electrode 131 and the preset position coordinates of the pixel electrode 131 are compared to obtain the pixel electrode position error and determine whether the flip position meets the requirements.

[0091] See Figures 1 to 4 An embodiment of this application provides a CT scanning device including a plurality of semiconductor detectors 10; at least one semiconductor detector 10 includes a substrate structure 100, including a semiconductor crystal layer 110 and an electrode layer group, the electrode layer group including a planar electrode layer 120 and a pixel electrode layer 130, the semiconductor crystal layer 110 having a first surface 111 and a second surface 112 disposed opposite to each other along its own thickness direction, the planar electrode layer 120 being disposed on the first surface 111, and the pixel electrode layer 130 including a plurality of pixel electrodes 131 spaced apart on the second surface 112. A protective layer 200 is disposed on the planar electrode layer 120; a protective layer 200 is disposed on the pixel electrode layer 130 or a protective layer 200 is disposed between at least two adjacent pixel electrodes 131; the protective layer 200 is used to shield the effect of external interference on the performance of the semiconductor detector 10.

[0092] In the aforementioned CT scanning equipment, at least one semiconductor detector 10 has a protective layer 200 on the planar electrode layer 110, or the pixel electrode layer 130, or between at least two adjacent pixel electrodes 131. This protective layer isolates the substrate structure 100, preventing contamination or mechanical damage to the surface of the substrate structure 100 during the formation of the imprint layer 300. It also minimizes the impact of external air and moisture on the detector surface, thus maintaining optimal detector performance. The imprint layer 300 is formed on the side of the protective layer 200 away from the substrate structure 100, i.e., on the outer surface of the protective layer 200. The imprint layer 300 can be pre-selected to carry imprint information such as crystal orientation, pixel electrode 131 position, and electrode arrangement, thereby marking each semiconductor detector 10. This allows for rapid installation of the semiconductor detectors 10 by identifying these markings during installation, improving installation efficiency and accuracy. After installation, the information of each semiconductor detector 10 can be identified and traced according to the marking information, so that in the event of subsequent failures, the root cause of the problem can be found and the experience can be summarized.

[0093] See Figures 1 to 4 The method for manufacturing a semiconductor detector 10 provided in one embodiment of this application includes:

[0094] S100. A protective layer 200 is prepared on the surface of the substrate structure 100 of the semiconductor detector 10.

[0095] S200, an imprint layer 300 is formed on the side of the protective layer 200 away from the substrate structure 100, and the imprint layer 300 carries imprint information.

[0096] The manufacturing method of the semiconductor detector 10 described above involves preparing a protective layer 200 on the surface of the substrate structure 100. This layer protects and isolates the substrate structure 100 from contamination or mechanical damage during the formation of the imprint layer 300, minimizing changes in the detector's surface state due to external air and moisture, thus maintaining optimal detector performance. The side of the protective layer 200 facing away from the substrate structure 100 is imprinted to form the imprint layer 300. This imprint layer 300 can be pre-selected to carry imprint information such as crystal orientation, pixel electrode 131 position, and electrode arrangement, thereby marking each semiconductor detector 10. This allows for rapid installation of the semiconductor detectors 10 by identifying these markings, improving installation efficiency and accuracy. After installation, the information of each semiconductor detector 10 can be identified and traced based on the marking information, enabling troubleshooting and analysis of potential problems, and allowing for the summarization of lessons learned.

[0097] In some embodiments, the protective layer 200 is prepared by spraying, brushing, spin coating, vapor deposition or sputtering processes.

[0098] For example, an oxide film is prepared on the surface of the substrate structure 100 as a protective layer 200 by magnetron sputtering, preferably aluminum oxide; sputtering pressure is 0.1-2.0 Pa, preferably 0.8 Pa; sputtering power is 10-500 W, preferably 100 W; film thickness is 10 nm-500 μm, preferably 50 μm.

[0099] For example, a protective layer 200 is prepared on the surface of the substrate structure 100 by a spraying process. The protective layer 200 is made of polymer material and has a thickness of 50 μm.

[0100] In some embodiments, the imprinted layer 300 is formed by spraying or laser processing.

[0101] For example, the imprint layer 300 is prepared by spraying, and the material is methyl ethyl ketone (MEK) ink. The thickness of the imprint layer 300 is 50 μm.

[0102] For example, the imprinted layer 300 is prepared by laser processing, the laser is a CO2 laser with a wavelength of 9.3 μm, the material of the imprinted layer 300 is a metal oxide, and the thickness of the imprinted layer 300 is 5 μm.

[0103] In some embodiments, the imprinted layer 300 may chemically react with the protective layer 200, thereby altering the surface profile, hardness, light reflection characteristics, or light transmission characteristics of the protective layer 200 (in the case of laser imprinting).

[0104] For example, if the imprint layer 300 is formed by laser processing and the protective layer 200 is made of aluminum oxide, when the laser acts on the surface of the protective layer 200, the temperature in a small local area will rise rapidly, causing the aluminum oxide to melt and vaporize, resulting in an imprint layer 300 with a depth of about 5 μm.

[0105] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor detector (10) used in a CT scanning device, characterized in that, The semiconductor detector (10) includes: A substrate structure (100) includes a semiconductor crystal layer (110) and an electrode layer group, wherein the electrode layer group includes a planar electrode layer (120) and a pixel electrode layer (130), the semiconductor crystal layer (110) has a first surface (111) and a second surface (112) disposed opposite to each other along its own thickness direction, the planar electrode layer (120) is disposed on the first surface (111), and the pixel electrode layer (130) includes a plurality of pixel electrodes (131) disposed at intervals on the second surface (112); A protective layer (200) is disposed on at least a portion of the surface of the substrate structure (100); and An imprint layer (300) is formed on the side of the protective layer (200) away from the substrate structure (100). The imprint layer (300) carries imprint information, including crystal orientation, pixel electrode position and electrode arrangement.

2. The semiconductor detector (10) according to claim 1, characterized in that, The electrode layer group includes a circuit connection area for connection to an external circuit, and a non-circuit connection area located outside the circuit connection area. The protective layer (200) is conductive and covers the circuit connection area and / or the non-circuit connection area.

3. The semiconductor detector (10) according to claim 2, characterized in that, The protective layer (200) is made of metal or doped semiconductor.

4. The semiconductor detector (10) according to claim 1, characterized in that, The electrode layer group includes a circuit connection area for connection to an external circuit and a non-circuit connection area located outside the circuit connection area. The semiconductor crystal layer (110) has an exposed surface (113) not covered by the electrode layer group. The protective layer (200) is insulating and covers the non-circuit connection area and / or the exposed surface (113).

5. The semiconductor detector (10) according to claim 4, characterized in that, The protective layer (200) is made of at least one of polymer materials, aluminides, carbides, oxides, nitrides, borides, fluorides, and ceramics.

6. The semiconductor detector (10) according to any one of claims 1 to 5, characterized in that, The Mohs hardness of the protective layer (200) is not less than 5; And / or, the thickness of the protective layer (200) ranges from 10 nm to 500 μm; And / or, the thermal conductivity of the protective layer (200) is less than 100 W / (m·K); And / or, the protective layer (200) has a transmittance of less than 0.5 for visible light and a transmittance of greater than 0.1 for infrared light.

7. The semiconductor detector (10) according to any one of claims 1 to 5, characterized in that, The thickness of the etched layer (300) ranges from 10 nm to 200 μm; And / or, the etched layer (300) has a transmittance of less than 0.5 for visible light and a transmittance of greater than 0.1 for infrared light; And / or, the material of the etched layer (300) is at least one of ink, polymer material, ceramic, metal oxide, carbide, and semiconductor material.

8. A CT scanning device, characterized in that, The CT scanning device includes a plurality of semiconductor detectors (10); at least one of the semiconductor detectors (10) includes: A substrate structure (100) includes a semiconductor crystal layer (110) and an electrode layer group, wherein the electrode layer group includes a planar electrode layer (120) and a pixel electrode layer (130), the semiconductor crystal layer (110) has a first surface (111) and a second surface (112) disposed opposite to each other along its own thickness direction, the planar electrode layer (120) is disposed on the first surface (111), and the pixel electrode layer (130) includes a plurality of pixel electrodes (131) disposed at intervals on the second surface (112); A protective layer (200) is provided on the planar electrode layer (120); A protective layer (200) is provided on the pixel electrode layer (130) or a protective layer (200) is provided between at least two adjacent pixel electrodes (131); The protective layer (200) is used to shield the effects of external interference on the performance of the semiconductor detector (10); An imprint layer (300) is formed on the side of the protective layer (200) away from the substrate structure (100). The imprint layer (300) carries imprint information, including crystal orientation, pixel electrode position and electrode arrangement.

9. A detector position error measurement system based on the semiconductor detector (10) according to any one of claims 1 to 7, characterized in that, The detector position error measurement system includes: A scanning device (400) is used to scan the engraving information; A controller, communicatively connected to the scanning device (400), is capable of obtaining pixel electrode position errors based on the imprinting information.

10. The detector position error measurement system for the semiconductor detector (10) according to claim 9, characterized in that, The controller obtains the first position coordinates of the etched layer (300) based on the etched information, and obtains the second position coordinates of the pixel electrode (131) based on the first position coordinates and the coordinate transformation relationship between the etched layer (300) and the corresponding pixel electrode (131). The controller compares the second position coordinates with the preset position coordinates of the pixel electrode (131) to obtain the pixel electrode position error.

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