DPHY transmitter signal generator based on FPGA

Abstract

The present invention provides an FPGA-based DPHY transmitter signal generator. The signal generator includes: a lane controller, a storage module, a digital-to-analog conversion module, a buffer, an analog switch, and an external data memory. The lane controller is implemented based on the FPGA and can generate a write control signal, a read control signal, a conversion start signal, and a switch control signal. The storage module is used to store waveform data and includes a first waveform memory, a second waveform memory, and a third waveform memory. The digital-to-analog conversion module includes a first digital-to-analog converter, a second digital-to-analog converter, a third digital-to-analog converter, and a fourth digital-to-analog converter. The analog switch receives a single-ended positive signal, a single-ended negative signal, a differential positive output signal, a differential negative output signal, and a switch control signal. The external data memory stores waveform data used to generate the DPHY signal. The present invention solves the problem of poor portability of existing signal generators.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a DPHY sending unit signal generator based on FPGA. Background Art

[0002] MIPI International Organization proposed a standard for portable mobile products. DPHY is a physical interface standard under the MIPI Alliance and is generally used in camera and display interfaces. The DPHY interface consists of a clock interface lane and a data lane. The speed of each lane varies depending on the standard. DPHY V1.2 has a maximum speed of up to 2.5Gbps. Each lane can select a different data rate based on different applications. To suit high-bandwidth applications, multiple data lanes can be selected for parallel data transmission. The highest resolution supports HD 1080p, 2K, and 4K applications. Figure 1 It is a typical DPHY Lane signal. The main difference between the clock Lane and the data Lane is whether the high-speed signal is a clock signal or a data signal. The entire DPHY Lane signal includes a high-speed part and a low-speed part. The high-speed rate is higher than 80M and less than 2.5Gbps, and the low-speed rate is less than 20Mbps. The high-speed and low-speed signal amplitudes are also different. The low-speed is about 1.2V, the high-speed differential Vpp is about 250mV, and the differential common mode VCM is about 200mV.

[0003] The DPHY signal in the MIPI signal chain is generally generated by a general-purpose arbitrary waveform generator or a dedicated DPHY signal generator. However, both solutions are very expensive and have limited usage scenarios. They can generally only be used in laboratories. They are large in size and power consumption, and are also complicated to use. In order to be able to use a DPHY TX (transmitter unit) signal generator to conduct on-site testing of the DPHY receiving interface performance in a smaller space (especially in field application scenarios), a convenient and modular DPHY TX signal module is required. This module can be quickly expanded to a multi-channel TX signal generator and can easily be built into a multi-channel DPHY TX signal generator device through software updates. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a DPHY transmitting unit signal generator based on FPGA, so as to solve the problem of poor convenience of the existing signal generator.

[0005] To achieve the above objectives and other related objectives, the present invention provides a DPHY sending unit signal generator based on FPGA, the signal generator comprising: a Lane controller, a storage module, a digital-to-analog conversion module, a buffer, an analog switch and an external data memory.

[0006] The Lane controller is implemented based on FPGA and can generate write control signals, read control signals, conversion start signals and switch control signals;

[0007] The storage module is used to store waveform data, and realizes writing of waveform data from the external data memory to the storage module under the action of the write control signal, and realizes writing of waveform data from the storage module to the digital-to-analog conversion module under the action of the read control signal, and includes a first waveform memory, a second waveform memory and a third waveform memory;

[0008] The digital-to-analog conversion module includes a first digital-to-analog converter, a second digital-to-analog converter, a third digital-to-analog converter, and a fourth digital-to-analog converter, wherein the first digital-to-analog converter receives waveform data read from the first waveform memory and converts it under the action of the conversion start signal to output a single-ended positive signal, the second digital-to-analog converter receives waveform data read from the second waveform memory and converts it under the action of the conversion start signal to output a single-ended negative signal, the third digital-to-analog converter receives waveform data read from the third waveform memory and converts it under the action of the conversion start signal to output an analog output signal, and the fourth digital-to-analog converter receives amplitude value configuration data and converts it to obtain a common-mode signal under the action of the conversion start signal;

[0009] The buffer receives the analog output signal and the common mode signal, and obtains a differential positive output signal and a differential negative output signal;

[0010] The analog switch receives the single-ended positive signal, the single-ended negative signal, the differential positive output signal, the differential negative output signal, and the switch control signal, and under the action of the switch control signal, outputs a low-speed signal when receiving the single-ended positive signal and the single-ended negative signal, and outputs a high-speed signal when receiving the differential positive output signal and the differential negative output signal;

[0011] The external data memory stores waveform data for generating a DPHY signal, and before the Lane controller starts the DPHY signal, the waveform data is written into the external data memory by the Lane controller;

[0012] The low-speed signal and the high-speed signal are two components of a DPHY signal.

[0013] Optionally, the signal generator further includes an SPI Slave, a register group, a DDR3 controller and a direct memory access, the SPI Slave receives instructions from a host computer to enable the signal generator to generate a complete DPHY signal, the register group is connected to the SPI Slave and the Lane controller; the DDR3 controller is connected to the register group, the direct memory access and the external data storage, and the direct memory access is connected to the register group and the Lane controller; wherein the waveform data is written from the host computer to the external data storage through the SPI Slave, the register group and the DDR3 controller.

[0014] Optionally, an output rate of the single-ended positive signal and the single-ended negative signal is less than 20 MHz.

[0015] Optionally, the buffer includes a differential buffer or two independent single-ended buffers.

[0016] Alternatively, the buffer may be replaced by a differential amplifier.

[0017] Optionally, the analog switch is a high-speed double-pole double-throw analog switch.

[0018] Optionally, the high-speed double-pole double-throw analog switch is formed by two high-speed single-pole double-throw analog switches in parallel.

[0019] Optionally, the analog switch has a first switch chip SW1 and a second switch chip W2, and the first switch chip SW1 includes a SW1_IN1 terminal, a SW1_IN2 terminal, a SW1_OUT terminal, a SW1_A terminal and a SW1_B terminal, and the second switch chip SW2 includes a SW2_IN1 terminal, a SW2_IN2 terminal, a SW2_OUT terminal, a SW2_A terminal and a SW2_B terminal. In the low-speed part of the DPHY signal, the SW1_IN1 terminal is connected to the SW1_OUT terminal, and the SW2_IN1 terminal is connected to the SW2_OUT terminal. In the high-speed part of the DPHY signal, the SW1_IN2 terminal is connected to the SW1_OUT terminal, and the SW2_IN2 terminal is connected to the SW2_OUT terminal; the SW1_A terminal and the SW2_A terminal receive a first switch control signal, and the SW1_B terminal and the SW2_B terminal receive a second switch control signal, wherein the first switch control signal and the second switch control signal are two signals of the switch control signal.

[0020] Optionally, the third waveform memory is connected to the third digital-to-analog converter via a high-speed interface.

[0021] Optionally, the conversion start signal is a clock signal.

[0022] Optionally, the first waveform memory and the second waveform memory both read out the waveform data therein through a parallel interface, and the parallel data output of the waveform data is synchronized with the read control signal.

[0023] Optionally, the storage module reads the waveform data in a parallel data input manner, and the parallel data input of the waveform data is synchronized with the write control signal.

[0024] Optionally, the fourth digital-to-analog converter receives amplitude value configuration data via a parallel data input method.

[0025] Optionally, the first, second and third waveform memories each include a read channel and a write channel, and the rate of the read channel and the rate of the write channel are completely asynchronous.

[0026] As described above, the FPGA-based DPHY transmitting unit signal generator of the present invention uses FPGA as a Lane controller in the hardware. The programmability of FPGA can easily adapt to different protocols and easily generate standard and abnormal DPHY physical links for testing the functions and performance and abnormal functions of the DPHY receiving unit. Since a digital-to-analog converter is used as the signal amplitude control of the Lane physical signal, it is easy to cover the standard signal amplitude range. The use of a digital-to-analog converter makes it easy to control the rising edge or falling edge of the Lane signal, and the timing signal that meets the protocol is also easy to control through the FPGA. The present invention can also generate non-standard or abnormal signals. The above scheme can meet the standard requirements of the DPHY transmitting unit signal. Moreover, the present invention can be quickly expanded into a multi-channel transmitting unit signal generator through software updates. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Shown is a schematic diagram of existing MIPIDPHY Lane signals.

[0028] Figure 2 Shown is a schematic diagram of a DPHY sending unit signal generator of the present invention.

[0029] Figure 3 Display as Figure 2 Detailed schematic diagram of the signal generator shown.

[0030] Figure 4 Shown is a schematic diagram of the connection relationship of the analog switch of the present invention. DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different perspectives and applications without departing from the spirit of the present invention.

[0032] See also Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation, the form, quantity, and proportion of each component in actual implementation may be arbitrarily changed, and the component layout may also be more complex.

[0033] like Figure 2 As shown, this embodiment provides a DPHY sending unit signal generator based on FPGA, the signal generator includes: a Lane controller, a storage module, a digital-to-analog conversion module, a buffer, an analog switch and an external data memory DDR3,

[0034] The Lane controller is implemented based on FPGA and can generate write control signals, read control signals, conversion start signals and switch control signals;

[0035] The storage module is used to store waveform data, and realizes writing of waveform data from the external data memory to the storage module under the action of the write control signal, and realizes writing of waveform data from the storage module to the digital-to-analog conversion module under the action of the read control signal, and includes a first waveform memory, a second waveform memory and a third waveform memory;

[0036] The digital-to-analog conversion module includes a first digital-to-analog converter, a second digital-to-analog converter, a third digital-to-analog converter, and a fourth digital-to-analog converter, wherein the first digital-to-analog converter receives waveform data read from the first waveform memory and converts the waveform data under the action of the conversion start signal ST to output a single-ended positive signal LP_P, the second digital-to-analog converter receives waveform data read from the second waveform memory and converts the waveform data under the action of the conversion start signal ST to output a single-ended negative signal LP_N, the third digital-to-analog converter receives waveform data read from the third waveform memory and converts the waveform data under the action of the conversion start signal ST to output an analog output signal, and the fourth digital-to-analog converter receives amplitude value configuration data and converts the waveform data under the action of the conversion start signal ST to obtain a common-mode signal VCOM;

[0037] The buffer receives the analog output signal and the common mode signal VCOM, and obtains a differential positive output signal P and a differential negative output signal N;

[0038] The analog switch receives the single-ended positive signal LP_P, the single-ended negative signal LP_N, the differential positive output signal P, the differential negative output signal N, and the switch control signal, and under the action of the switch control signal, outputs a low-speed signal when receiving the single-ended positive signal LP_P and the single-ended negative signal LP_N, and outputs a high-speed signal when receiving the differential positive output signal P and the differential negative output signal N;

[0039] The external data memory DRR3 stores waveform data for generating a DPHY signal, and before the Lane controller starts the DPHY signal, the waveform data is written into the external data memory DDR3 through the Lane controller;

[0040] The low-speed signal and the high-speed signal are two components of a DPHY signal.

[0041] like Figure 2 and Figure 3 As shown, in this embodiment, the write control signal includes a first write control signal Wr1, a second write control signal Wr2, and a third write control signal Wr3; the read control signal includes a first read control signal Rd1, a second read control signal Rd2, and a third read control signal Rd3. The data written to the first waveform memory is represented as WBM1, the data written to the second waveform memory is represented as WBM2, and the data written to the third waveform memory is represented as WBM3. Furthermore, in this embodiment, the waveform data is a data file pre-edited according to the time and amplitude signals of the DPHY waveform. The bit width of the waveform data determines the resolution of the output signal and matches the input bit width of the first, second, and third DACs.

[0042] Specifically, the conversion start signal ST is a clock signal. In this embodiment, the frequency of the conversion start signal ST is 60 MHz.

[0043] Specifically, the third waveform memory is connected to the third digital-to-analog converter via a high-speed interface. In this embodiment, the high-speed interface is a JESD204B interface.

[0044] Specifically, the first waveform memory and the second waveform memory both read out the waveform data therein through a parallel interface, and the parallel data output of the waveform data is synchronized with the read control signal.

[0045] Specifically, the storage module reads the waveform data in a parallel data input manner, and the parallel data input of the waveform data is synchronized with the write control signal.

[0046] Specifically, the fourth digital-to-analog converter receives the amplitude value configuration data through a parallel data input method.

[0047] Specifically, the first, second and third waveform memories each include a read channel and a write channel, and the rate of the read channel is completely asynchronous with the rate of the write channel.

[0048] Specifically, the output rate of the single-ended positive signal LP_P and the single-ended negative signal LP_N is less than 20 MHz.

[0049] In this embodiment, in order to simulate the rise time and fall time of the single-ended positive signal LP_P and the single-ended negative signal LP_N, it is necessary to use the digital-to-analog converter that supports a rate of 5 times or more.

[0050] Specifically, the buffer includes a differential buffer or two independent single-ended buffers.

[0051] In this embodiment, the differential buffer can output a fully symmetrical high-speed differential signal. For independent adjustment, two independent single-ended buffers can also be selected, and the bias and amplitude can be controlled independently.

[0052] Specifically, the buffer may be replaced by a differential amplifier.

[0053] Specifically, the analog switch is a high-speed double-pole double-throw analog switch.

[0054] More specifically, the high-speed double-pole double-throw analog switch is formed by two high-speed single-pole double-throw analog switches in parallel.

[0055] As an example, the analog switch has a first switch chip SW1 and a second switch chip W2, and the first switch chip SW1 includes SW1_IN1, SW1_IN2, SW1_OUT, SW1_A and SW1_B, and the second switch chip SW2 includes SW2_IN1, SW2_IN2, SW2_OUT, SW2_A and SW2_B. In the low-speed part of the DPHY signal, the SW1_IN1 is connected to the SW1_OUT, and the SW2_IN1 is connected to the SW2_OUT. In the high-speed part of the DPHY signal, the SW1_IN2 is connected to the SW1_OUT, and the SW2_IN2 is connected to the SW2_OUT. The SW1_A and SW2_A terminals receive a first switch control signal, and the SW1_B and SW2_B terminals receive a second switch control signal, wherein the first switch control signal and the second switch control signal are two signals of the switch control signal.

[0056] In this embodiment, the DPHY Lane output signal is divided into a low-speed signal and a high-speed signal through the analog switch. The high-speed signal is synchronized with the low-speed signal through the Lane controller, and then the DPHY Lane signal is synthesized through the analog switch in a time-sharing manner.

[0057] like Figure 4 As shown, in this embodiment, the output end of the analog switch includes a DPHY LANE differential positive end and a DPHY LANE differential negative end.

[0058] Specifically, the signal generator further includes an SPI Slave, a register group, a DDR3 controller, and a direct memory access (DMA). The SPI Slave receives instructions from a host computer to enable the signal generator to generate a complete DPHY signal. The register group is connected to the SPI Slave and the Lane controller. The DDR3 controller is connected to the register group, the direct memory access (DMA), and the external data memory (DDR3). The external data memory (DMA) is connected to the register group and the Lane controller. The waveform data is written from the host computer to the external data memory via the SPI Slave, the register group, and the DDR3 controller.

[0059] In this embodiment, the common-mode signal VCOM is controlled as follows: the SPI slave receives instructions from the host computer, receives the amplitude configuration data required to control the common-mode signal VCOM, writes the data into the register group, and then directly outputs the data to the fourth digital-to-analog converter via the lane controller. When the lane controller outputs a start control signal ST4 to the fourth digital-to-analog converter, conversion of the common-mode signal VCOM is achieved. It should be noted that, in this embodiment, for the fourth digital-to-analog converter, the start control signal ST4 and the conversion start signal ST are the same.

[0060] In this embodiment, the high-speed channel HS generation scheme is as follows: the SPI Slave receives instructions from the host computer and receives parameters that need to be controlled, such as execution time, number of DPHY waveform cycles, and register configuration parameters of the DDR3 controller and DMA. After receiving this information, it is first written to the register group and then to the registers of the DDR3 controller and DMA. Finally, it receives a start instruction to generate a DPHY signal and activates DMA through the Lane controller to write the DDR3 waveform data to the third waveform memory. It also controls the read function of the third waveform memory. The read data is written to the third digital-to-analog converter via the high-speed interface JESD204B to generate the high-speed HS analog signal. The Lane controller controls the waveform memory to write to the full or empty state, ensuring the continuity of the waveform memory data and the high-speed HS analog signal.

[0061] The low-speed channel LP generation scheme is essentially the same as the high-speed HS generation principle. Under the centralized control of the Lane controller, waveform data is read from the external DDR3 memory, and the first and second DACs generate a single-ended positive signal LP_P and a single-ended negative signal LP_N. Since the low-speed signal frequency supports up to 20MHz, and the standard requires the slowest rise or fall time of the low-speed signal LP (20ns), a 125MHz DAC can be selected to achieve finer rise and fall times. For example, Analog Devices' 125MHz 8-bit AD9114 dual low-power, 8-bit TxDAC DAC can meet these requirements.

[0062] Furthermore, in this embodiment, the signal amplitude of the high-speed signal is approximately 250mV, the common-mode signal VCOM is approximately 200mV, and the maximum supported rate is 2.5Gbps. Moreover, the common-mode signal is a static signal and does not require dynamic changes. Generally, initialization once after power-on is sufficient to meet the requirements. In order to meet the maximum rate of 2.5GHz signal bandwidth specified by the DPHY V1.2 standard, the third digital-to-analog converter can be selected from Analog Devices' AD9163, which has 8 bits and a bandwidth of 3GHz, and the buffer can be selected from ADA4961, which has a bandwidth of 3.2GHz. Moreover, in this embodiment, the Lane controller is implemented using an FPGA, which requires a maximum speed of 2.5GHz. Taking 1080p@60Hz and an 8-bit waveform memory as an example, the peak bandwidth for writing data requires 20Gbps. To meet the 20Gbps single-channel bandwidth data, the Xilinx FPGA Kintex Ultra FPGAKU060 chip can be selected. This chip includes 663K D flip-flops, 330K LUTs, 38Mb of memory, 32 high-speed transceivers GTH / GTY, 12 CMT clock management units, and supports up to 520 IOs to meet the required data bandwidth, high-speed interface, internal memory, high-speed clock and rich IO requirements.

[0063] In summary, the FPGA-based DPHY transmitter signal generator of the present invention uses an FPGA as a lane controller in hardware. The FPGA's programmability easily adapts to different protocols, making it easy to generate standard and abnormal DPHY physical links for testing the functionality, performance, and abnormal functions of the DPHY receiver. The use of a digital-to-analog converter (DAC) to control the amplitude of the lane physical signal easily covers the standard signal amplitude range. The DAC also makes it easy to control the rising or falling edges of the lane signal, and the FPGA can easily control the timing signals that meet the protocol. Non-standard or abnormal signals can also be generated. This solution can meet the standard requirements of DPHY transmitter signals. Furthermore, the present invention can be quickly expanded to a multi-channel transmitter signal generator through software updates. Therefore, the present invention effectively overcomes the shortcomings of the prior art and has high industrial application value.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A DPHY transmitter signal generator based on FPGA, characterized in that: The signal generator includes: a Lane controller, a storage module, a digital-to-analog conversion module, a buffer, an analog switch and an external data storage. The Lane controller is implemented based on FPGA and can generate write control signals, read control signals, conversion start signals and switch control signals; The storage module is used to store waveform data, and realizes writing of waveform data from the external data memory to the storage module under the action of the write control signal, and realizes writing of waveform data from the storage module to the digital-to-analog conversion module under the action of the read control signal, and includes a first waveform memory, a second waveform memory and a third waveform memory; The digital-to-analog conversion module includes a first digital-to-analog converter, a second digital-to-analog converter, a third digital-to-analog converter, and a fourth digital-to-analog converter, wherein the first digital-to-analog converter receives waveform data read from the first waveform memory and converts it under the action of the conversion start signal to output a single-ended positive signal, the second digital-to-analog converter receives waveform data read from the second waveform memory and converts it under the action of the conversion start signal to output a single-ended negative signal, the third digital-to-analog converter receives waveform data read from the third waveform memory and converts it under the action of the conversion start signal to output an analog output signal, and the fourth digital-to-analog converter receives amplitude value configuration data and converts it to obtain a common-mode signal under the action of the conversion start signal; The buffer receives the analog output signal and the common mode signal, and obtains a differential positive output signal and a differential negative output signal; The analog switch receives the single-ended positive signal, the single-ended negative signal, the differential positive output signal, the differential negative output signal, and the switch control signal, and under the action of the switch control signal, outputs a low-speed signal when receiving the single-ended positive signal and the single-ended negative signal, and outputs a high-speed signal when receiving the differential positive output signal and the differential negative output signal; The external data memory stores waveform data for generating a DPHY signal, and before the Lane controller starts the DPHY signal, the waveform data is written into the external data memory by the Lane controller; The low-speed signal and the high-speed signal are two components of a DPHY signal.

2. The FPGA-based DPHY transmitting unit signal generator according to claim 1, characterized in that: The signal generator also includes an SPI Slave slave, a register group, a DDR3 controller and a direct memory access. The SPI Slave slave receives instructions from a host computer to enable the signal generator to generate a complete DPHY signal. The register group is connected to the SPI Slave slave and the Lane controller; the DDR3 controller is connected to the register group, the direct memory access and the external data storage, and the direct memory access is connected to the register group and the Lane controller. The waveform data is written from the host computer to the external data storage through the SPI Slave slave, the register group and the DDR3 controller.

3. The FPGA-based DPHY transmitting unit signal generator according to claim 1, wherein: The output rate of the single-ended positive signal and the single-ended negative signal is less than 20 MHz.

4. The FPGA-based DPHY transmitting unit signal generator according to claim 1, characterized in that: The buffer includes a differential buffer or two independent single-ended buffers.

5. The FPGA-based DPHY transmitting unit signal generator according to claim 4, characterized in that: The buffer may be replaced by a differential amplifier.

6. The FPGA-based DPHY transmitting unit signal generator according to claim 1, characterized in that: The analog switch is a high-speed double-pole double-throw analog switch.

7. The FPGA-based DPHY transmitting unit signal generator according to claim 6, characterized in that: The high-speed double-pole double-throw analog switch is formed by two high-speed single-pole double-throw analog switches in parallel.

8. The FPGA-based DPHY transmitting unit signal generator according to claim 7, characterized in that: The analog switch has a first switch chip SW1 and a second switch chip W2, and the first switch chip SW1 includes SW1_IN1, SW1_IN2, SW1_OUT, SW1_A and SW1_B. The second switch chip SW2 includes SW2_IN1, SW2_IN2, SW2_OUT, SW2_A and SW2_B. In the low-speed part of the DPHY signal, the SW1_IN1 is connected to the SW1_OUT, and the SW2_IN1 is connected to the SW2_OUT. In the high-speed part of the DPHY signal, the SW1_IN2 is connected to the SW1_OUT, and the SW2_IN2 is connected to the SW2_OUT. The SW1_A and SW2_A terminals receive a first switch control signal, and the SW1_B and SW2_B terminals receive a second switch control signal. The first switch control signal and the second switch control signal are two signals of the switch control signal.

9. The FPGA-based DPHY transmitting unit signal generator according to claim 1, characterized in that: The third waveform memory is connected to the third digital-to-analog converter via a high-speed interface.

10. The FPGA-based DPHY transmitting unit signal generator according to claim 1, characterized in that: The conversion start signal is a clock signal.

11. The FPGA-based DPHY transmitting unit signal generator according to claim 1, characterized in that: The first waveform memory and the second waveform memory both read out the waveform data therein through a parallel interface, and the parallel data output of the waveform data is synchronized with the read control signal.

12. The FPGA-based DPHY transmitting unit signal generator according to claim 1, characterized in that: The storage module reads the waveform data in a parallel data input manner, and the parallel data input of the waveform data is synchronized with the write control signal.

13. The FPGA-based DPHY transmitting unit signal generator according to claim 11, characterized in that: The fourth digital-to-analog converter receives amplitude value configuration data through a parallel data input method.

14. The FPGA-based DPHY transmitting unit signal generator according to claim 1, characterized in that: The first, second and third waveform memories each include a read channel and a write channel, and the rate of the read channel is completely asynchronous with the rate of the write channel.

Images