Interrupt management control method and system for CPU (Central Processing Unit), and electronic equipment

Abstract

The invention discloses an interrupt management control method and system for a CPU and electronic equipment, and relates to the technical field of integrated chips. The method comprises the following steps: the interrupt cache unit receives a plurality of interrupt control signals sent by a plurality of interrupt sources; when the core processing unit is in an idle low-power-consumption state, the interrupt priority of each interrupt control signal is judged according to the priority mark signal; according to the periodic interrupt enable signal, in the enable period, the cached interrupt control signal is sent to the corresponding core processing unit through the interrupt controller; the core processing unit performs interrupt processing in response to the interrupt control signal. According to the invention, a plurality of cached interrupt control signals can be transmitted in the enable period of the periodic interrupt enable signal in a centralized manner, and the core processing unit is prevented from being frequently awakened from a low-power-consumption state, so that the CPU performance is improved, and the CPU power consumption is reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated chip technology, and in particular to a method for managing and controlling CPU interrupts, a system thereof, and electronic equipment. Background Art

[0002] In electronic systems, the power consumption of the CPU accounts for a large proportion of the power consumption of the entire electronic system. Therefore, controlling the power consumption of the CPU is very important for optimizing the power consumption of electronic systems. The industry usually uses CPUIdle technology to reduce the power consumption of the CPU during operation. CPUIdle technology is a low-power consumption technology for CPU during operation. The operating system usually puts the CPU into a low-power state (i.e., CPUIdle state) when the CPU executes an idle thread (i.e., when it is idle or has nothing to do). However, entering and exiting the CPUIdle state consumes additional power. The operating system needs to carefully estimate whether the power consumption saved during the residence time after the CPU enters the CPUIdle state is greater than the additional power consumption paid for entering and exiting the CPUIdle state. Entering and exiting the CPUIdle state involves operations such as switching the CPU power supply, clearing the cache, and multi-core consistency. Its wake-up delay is usually large, so a longer CPUIdle state residence time is the key to saving CPU power consumption.

[0003] Electronic systems usually trigger a large number of asynchronous interrupts when running. These asynchronous interrupts will frequently wake up the CPU at unexpected times, waking up the CPU from the CPUIdle state, thereby reducing the CPU's residence time in the CPUIdle state. If a large number of asynchronous interrupts frequently wake up the CPU from the CPUIdle state, the power consumption paid will be greater than the power saved, resulting in increased CPU power consumption. On the other hand, frequent asynchronous interrupts will interrupt the CPU execution pipeline, cool the CPU instruction and data caches, and clear the CPU branch prediction cache, resulting in reduced CPU performance. Summary of the invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a CPU interrupt management control method and system, and an electronic device, which can centrally send multiple cached interrupt control signals during the enable period of a periodic interrupt enable signal, thereby avoiding frequent awakening of the core processing unit from a low power consumption state, thereby improving CPU performance and reducing CPU power consumption.

[0005] In a first aspect, an embodiment of the present application provides an interrupt management control method for a CPU, comprising: being applied to an interrupt management control system, the interrupt management control system comprising: a plurality of interrupt sources, an interrupt cache unit, an interrupt controller, and a central processing unit; the output ends of the plurality of interrupt sources are connected to the input ends of the interrupt cache unit, the output ends of the interrupt cache unit are connected to the input ends of the interrupt controller, the output ends of the interrupt controller are connected to the input ends of the central processing unit; the central processing unit comprises a plurality of core processing units;

[0006] The method comprises:

[0007] The interrupt buffer unit receives a plurality of interrupt control signals sent by the plurality of interrupt sources;

[0008] When the core processing unit is in an idle low power consumption state, the interrupt cache unit determines the interrupt priority of each of the interrupt control signals according to the priority flag signal;

[0009] The interrupt cache unit caches the interrupt control signal with a low interrupt priority during a non-enabled period according to a periodic interrupt enable signal, and sends the cached interrupt control signal to the corresponding core processing unit through the interrupt controller during an enabled period;

[0010] The interrupt controller sends the received interrupt control signal to the corresponding core processing unit, so that the core processing unit performs interrupt processing in response to the interrupt control signal.

[0011] In a second aspect, an embodiment of the present application provides an interrupt management control system, comprising: a plurality of interrupt sources, an interrupt cache unit, an interrupt controller, and a central processing unit; the output ends of the plurality of interrupt sources are connected to the input end of the interrupt cache unit, the output end of the interrupt cache unit is connected to the input end of the interrupt controller, the output end of the interrupt controller is connected to the input end of the central processing unit; the central processing unit comprises a plurality of core processing units;

[0012] Among them, the interrupt cache unit is used to: receive multiple interrupt control signals issued by the multiple interrupt sources; when the core processing unit is in an idle low-power state, determine the interrupt priority of each of the interrupt control signals according to the priority flag signal; according to the periodic interrupt enable signal, cache the interrupt control signal with a low interrupt priority during the non-enabled period, and during the enabled period, send the cached interrupt control signal to the corresponding core processing unit through the interrupt controller; the core processing unit is used to perform interrupt processing in response to the interrupt control signal.

[0013] In a third aspect, an embodiment of the present application provides an electronic device comprising at least one processor and a memory for communicating with the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the interrupt management control method for the CPU as described in any one of the embodiments of the first aspect.

[0014] The embodiment of the present application includes: an interrupt management control system includes: multiple interrupt sources, an interrupt cache unit, an interrupt controller, and a central processing unit; the output ends of the multiple interrupt sources are connected to the input ends of the interrupt cache unit, the output ends of the interrupt cache unit are connected to the input ends of the interrupt controller, and the output ends of the interrupt controller are connected to the input ends of the central processing unit; the central processing unit includes multiple core processing units; in the process of using the interrupt management control system to manage the CPU interrupt, first, the interrupt cache unit receives multiple interrupt control signals sent by multiple interrupt sources; then, when the core processing unit is in an idle low-power state, the interrupt cache unit determines the interrupt priority of each interrupt control signal according to the priority flag signal; then, the interrupt cache unit caches the interrupt control signal with a low interrupt priority during the non-enabled period according to the periodic interrupt enable signal, and during the enabled period, sends the cached interrupt control signal to the corresponding core processing unit through the interrupt controller; in this way, the interrupt control signal is cached during the non-enabled period of the periodic interrupt enable signal, and the cached multiple interrupt control signals are collectively sent during the enabled period of the periodic interrupt enable signal, so as to avoid frequently waking up the core processing unit from the idle low-power state in a very short time, which is beneficial to improving CPU performance and reducing CPU power consumption. Finally, the core processing unit performs interrupt processing in response to the interrupt control signal; this prolongs the core processing unit's residence time in the idle low-power state, so that the power consumption paid by the core processing unit to wake up the idle low-power state is less than the power consumption saved in the idle low-power state, so that the CPU maintains low power consumption and effectively improves CPU performance. That is to say, the embodiment of the present application can concentrate the cached multiple interrupt control signals during the enable period of the periodic interrupt enable signal, avoid frequently waking up the core processing unit from the low-power state, thereby improving CPU performance and reducing CPU power consumption.

[0015] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the overall structure of an interrupt management control system provided by an embodiment of the present application;

[0017] Figure 2 is a schematic diagram of a specific structure of an interrupt cache unit provided by an embodiment of the present application;

[0018] Figure 3 is a schematic diagram of a specific structure of an interrupt cache unit provided by another embodiment of the present application;

[0019] Figure 4 is a specific structural diagram of a first cache logic unit provided by an embodiment of the present application;

[0020] Figure 5 is a specific structural diagram of a second cache logic unit provided by an embodiment of the present application;

[0021] Figure 6 It is a waveform diagram of an interrupt control signal sent by a first cache logic unit and a second cache logic unit provided by an embodiment of the present application;

[0022] Figure 7 It is a flowchart of a method for controlling interrupt management of a CPU provided by an embodiment of the present application;

[0023] Figure 8 It is a schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0025] It should be understood that in the description of the present application, the orientation descriptions, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0026] It should be noted that although a logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of the present application, a number of means one or more, and a plurality of means two or more. The description of "first" and "second" is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0028] First, some terms used in this application are explained:

[0029] CPU, or Central Processing Unit, is one of the core hardware of a computer, responsible for executing instructions in programs and processing data.

[0030] The present application discloses a method for managing and controlling interrupts of a CPU, and a system and electronic device thereof, and relates to the field of integrated chip technology. The method includes: an interrupt cache unit receives multiple interrupt control signals sent by multiple interrupt sources; when a core processing unit is in an idle low-power state, the interrupt priority of each interrupt control signal is determined according to a priority flag signal; according to a periodic interrupt enable signal, an interrupt control signal with a low interrupt priority is cached during a non-enabled period, and during an enabled period, the cached interrupt control signal is sent to the corresponding core processing unit through an interrupt controller; the interrupt controller sends the received interrupt control signal to the corresponding core processing unit so that the core processing unit performs interrupt processing in response to the interrupt control signal. The cached multiple interrupt control signals can be concentrated and sent during the enable period of the periodic interrupt enable signal, avoiding frequent awakening of the core processing unit from a low-power state, thereby improving CPU performance and reducing CPU power consumption.

[0031] The embodiments of the present application are further described below in conjunction with the accompanying drawings.

[0032] like Figure 1 As shown, Figure 1 This is a schematic diagram of the overall structure of an interrupt management control system provided by an embodiment of the present application. The embodiment of the present application provides an interrupt management control system, including: multiple interrupt sources, an interrupt cache unit, an interrupt controller, and a central processing unit; the output ends of the multiple interrupt sources are connected to the input ends of the interrupt cache unit, the output ends of the interrupt cache unit are connected to the input ends of the interrupt controller, and the output ends of the interrupt controller are connected to the input ends of the central processing unit; the central processing unit includes multiple core processing units.

[0033] It is understandable that the interrupt source refers to the interrupt control signal sent by various devices. The interrupt source of the present application includes all interrupt control signals in the electronic system. Specifically, the interrupt control signal includes a level interrupt signal and an edge interrupt signal.

[0034] It is understandable that the interrupt controller is responsible for specific interrupt enabling, routing, priority management and other functions, and sends the interrupt control signal to a specific core processing unit.

[0035] It can be understood that the central processing unit is used to respond to and process the interrupt control signal sent to the central processing unit, and notify the corresponding interrupt source after completing the interrupt processing: the interrupt is completed.

[0036] In the process of using the interrupt management control system provided according to the embodiment of the present application to manage the CPU interrupt, the interrupt cache unit is used to: receive multiple interrupt control signals sent by multiple interrupt sources; when the core processing unit is in an idle low-power state, determine the interrupt priority of each interrupt control signal according to the priority flag signal; according to the periodic interrupt enable signal, cache the interrupt control signal with a low interrupt priority during the non-enabled period, and send the cached interrupt control signal to the corresponding core processing unit through the interrupt controller during the enabled period. In this way, the interrupt control signal is cached during the non-enabled period of the periodic interrupt enable signal, and the cached multiple interrupt control signals are sent centrally during the enabled period of the periodic interrupt enable signal, so as to avoid frequently waking up the core processing unit from the idle low-power state in a very short time, which is conducive to improving the CPU performance and reducing the CPU power consumption. The core processing unit is used to perform interrupt processing in response to the interrupt control signal; in this way, the core processing unit's residence time in the idle low-power state is extended, so that the power consumption paid by the core processing unit waking up the idle low-power state is less than the power consumption saved in the idle low-power state, so that the CPU maintains a lower power consumption and effectively improves the CPU performance. Therefore, the interrupt management and control system provided in the embodiment of the present application is capable of caching discrete random interrupt control signals, so that the interrupts of the electronic system are sent to the CPU according to a predetermined cycle, eliminating the situation where asynchronous interrupts unexpectedly wake up the CPU in the CPUIdle state, and ensuring that the CPU stays in the CPUIdle state for a sufficiently long time, thereby further enhancing the power saving effect of the CPUIdle technology and reducing CPU power consumption.

[0037] According to some embodiments of the present application, Figure 2 and Figure 3 As shown, the interrupt cache unit includes: an interrupt cache logic module, a counter, a CPU state logic operation module, or a logic operation module, and a routing module.

[0038] According to some embodiments of the present application, specifically, the connection relationship between the modules in the interrupt cache unit is as follows: the input end of the interrupt cache logic module is connected to the output end of the interrupt source; the output end of the interrupt cache logic module is connected to the input end of the interrupt controller; the output end of the counter is connected to the input end of the interrupt cache logic module; the input end of the CPU state logic operation module is used to input the CPU state flag signal of each core processing unit; the OR logic operation module includes a first input end and a second input end, the first input end is used to input the priority flag signal of the interrupt control signal, and the second input end is connected to the output end of the CPU state logic operation module; the routing module includes a first signal input end, a second signal input end, a routing enable end, and a routing output end; the first signal input end is connected to the output end of the interrupt cache logic module, the second signal input end is connected to the output end of the interrupt source, the routing enable end is connected to the output end of the OR logic operation module, and the routing output end is connected to the input end of the interrupt controller.

[0039] It can be understood that the interrupt buffer unit is mainly responsible for re-managing the interrupts, which further explains the functions of each module in the interrupt buffer unit.

[0040] Specifically, the counter Counter is used to enable the counting function when the luster is powered on, and generate a periodic interrupt enable signal; the interrupt enable signal includes: enable high level and low level. The interrupt enable signal is valid at a high level, so that the interrupt control signal can only be sent to the interrupt controller during the enable period determined by the enable high level of the interrupt enable signal. It should be noted that the low level of the interrupt enable signal corresponds to the non-enable period, and the enable high level of the interrupt enable signal corresponds to the enable period.

[0041] It can be understood that the function of the counter Counter can be configured. Therefore, the present application does not impose specific restrictions on the frequency, duty cycle, etc. of the interrupt enable signal generated by the counter Counter, and can be designed based on the actual required residence time of the core processing unit in the idle low-power state.

[0042] Specifically, the interrupt cache logic module is used to: unconditionally cache all input interrupt control signals irq_in[n:0], and receive the interrupt enable signal generated by the counter counter when counting ends, and output the intermediate variable irq_reg[n:0] in response to the high level of the interrupt enable signal.

[0043] Specifically, Figure 3 As shown, the routing module of the interrupt buffer unit includes a plurality of multiplexers MUX. A corresponding multiplexer MUX is provided corresponding to each input interrupt control signal (irq_in[0], irq_in[1], ..., irq_in[n]).

[0044] For example, Figure 3 As shown, a multiplexer MUX includes: a first signal input terminal A1, a second signal input terminal A2, a routing enable terminal B, and a routing output terminal C. The first signal input terminal A1 is connected to the output terminal of the interrupt cache logic module, and the first signal input terminal A1 is used to receive an interrupt control signal irq_in[0] output by an interrupt cache logic module. The second signal input terminal A2 is connected to the output terminal of the interrupt source, and the second signal input terminal A2 is used to receive an interrupt control signal irq_in[0] output by an interrupt source. The routing enable terminal B is connected to the output terminal of the OR logic operation module, and the routing output terminal C is connected to the input terminal of the interrupt controller. The routing enable terminal B is used to receive the routing enable signal output by the OR logic operation module. When the routing enable signal is 0, the path between the first signal input terminal A1 and the routing output terminal C is turned on, and the routing output terminal C outputs the interrupt control signal irq_in[0] (i.e., the interrupt control signal irq_in[0] output by the interrupt cache logic module) received by the first signal input terminal A1. Figure 3 The routing output terminal C shown in the figure outputs the signal irq_o[0]). When the routing enable signal is 1, the path between the second signal input terminal A2 and the routing output terminal C is connected, and the routing output terminal C outputs the interrupt control signal irq_in[0] (i.e. Figure 3 The routing output terminal C shown outputs the signal irq_o[0]).

[0045] The specific value of the routing enable signal is determined by the OR logic operation module based on the input priority flag signal priority_irq[n:0] and the output value of the CPU state logic operation module; wherein the output value of the CPU state logic operation module is determined by multiple CPU state flag signals.

[0046] Specifically, the software in the electronic system configures the interrupt priority for each input interrupt control signal (irq_in[0], irq_in[1], ..., irq_in[n]). When the priority flag signal is 1, it indicates that the interrupt priority is high priority; when the priority flag signal is 0, it indicates that the interrupt priority is low priority. The input priority flag signal priority_irq[n:0] comes from the register configured by the software.

[0047] When the priority flag signal is high priority, the interrupt cache unit will automatically select to directly output the input interrupt control signal without delay; when the interrupt priority of an interrupt control signal is low priority, it will go through the interrupt cache path (that is, output after passing through the interrupt cache logic module).

[0048] In one embodiment, referring to Figure 3The interrupt cache unit includes multiple OR logic operation modules, and the two input terminals of each OR logic operation module are respectively connected to the register outputting the priority flag signal and the output terminal of the CPU state logic operation module. When the interrupt priority of an interrupt control signal is high priority, that is, the priority flag signal is 1, at this time, no matter whether the output value of the CPU state logic operation module is 1 or 0, the routing enable signal output by the OR logic operation module after the logic operation is 1, and the multiplexer connects the path between the second signal input terminal A2 and the routing output terminal C in response to the routing enable signal with a value of 1, and outputs the interrupt control signal irq_in[0] output by the interrupt source and received by the second signal input terminal A2.

[0049] Specifically, Figure 3 As shown, the CPU state logic operation module includes: an AND logic operation module and multiple non-logic operation modules; the output end of each non-logic operation module is connected to the input end of the AND logic operation module, the input end of each non-logic operation module is used to input the CPU state flag signal, and the output end of the AND logic operation module is used to output the operation value.

[0050] In one embodiment, when all CPU status flag signals Core0_wfi to CoreN_wfi are 0, that is, all core processing units are in a non-idle state, then after logical operations of the non-logical operation module and the logical operation module in sequence, the output value is 1; at this time, no matter whether the priority flag signal is 1 or 0, or the routing enable signal output by the logical operation module after the logical operation is 1, the multiplexer connects the path between the second signal input terminal A2 and the routing output terminal C in response to the routing enable signal with a value of 1, and outputs the interrupt control signal irq_in[0] output by the interrupt source and received by the second signal input terminal A2.

[0051] When the interrupt priority of an interrupt control signal is low priority, that is, the priority flag signal is 0; when at least one CPU status flag signal is 1, the output value is 0 after the logical operation of the non-logical operation module and the logical operation module in sequence; in this case, the routing enable signal output by the or logic operation module is 0, and the multiplexer connects the path between the first signal input terminal A1 and the routing output terminal C in response to the routing enable signal with a value of 0, and outputs the interrupt control signal irq_in[0] received by the first signal input terminal A1 and output by the interrupt cache logic module.

[0052] The interruption buffering logic module provided by the embodiment of the present application is further described. The interruption buffering logic module further includes: a first buffering logic unit and a second buffering logic unit.

[0053] Specifically, Figure 4As shown, the first cache logic unit is: an AND logic gate; the first input end of the AND logic gate is used to receive a level interrupt signal, the second input end of the AND logic gate is used to receive an interrupt enable signal, and the output end of the AND logic gate is connected to the interrupt controller.

[0054] The functions of the first cache logic unit include: for a level interrupt signal, the level interrupt signal pulled up during the non-enable period of the interrupt enable signal can only be sent to the interrupt controller during the enable period of the interrupt enable signal; this process is specifically referred to Figure 6 Schematic diagram of the process of caching and sending level interrupt signal [0].

[0055] The function of the first cache logic unit also includes: for the level interrupt signal, the level interrupt signal pulled up during the enabling period of the interrupt enable signal can be directly sent to the interrupt controller; this process, specifically refer to Figure 6 Schematic diagram of the process of caching and sending level interrupt signals [1].

[0056] Specifically, Figure 5 As shown, the second cache logic unit includes: an edge capturer and a pulse generator. The edge capturer and the pulse generator are connected to each other, the signal input end of the edge capturer is used to receive an edge interrupt signal, the signal input end of the pulse generator is used to receive an interrupt enable signal, and the signal output end of the pulse generator is connected to the interrupt controller.

[0057] The functions of the second cache logic unit include: for edge interrupt signals, if one or more edge interrupt signals are received during the non-enabled period of the previous interrupt enable signal, an edge interrupt notification is uniformly issued at the rising edge of the interrupt enable signal of this cycle (i.e., the edge where the low level jumps to the enabled high level) to notify the downstream to centrally process the accumulated edge interrupt signals of the previous cycle.

[0058] Specifically, the edge capturer is responsible for counting the edge interrupt signals in the previous cycle to obtain the interrupt cache quantity value, and at the rising edge of the interrupt enable signal, notifies the pulse generator of the interrupt cache quantity value so that the pulse generator determines whether to issue an edge interrupt signal.

[0059] Specifically, the pulse generator is responsible for deciding whether to send an edge interrupt signal based on the capture result of the edge capturer (i.e., the interrupt cache quantity value) at the rising edge of the interrupt enable signal; when the interrupt cache quantity value is zero, it is decided not to send an edge interrupt signal; when the interrupt cache quantity value is not zero, it is decided to send an edge interrupt signal. When it is decided to send an edge interrupt signal, the pulse generator sends an edge interrupt notification to the interrupt controller to notify the interrupt controller to centrally process the accumulated edge interrupt signals of the previous cycle and send them to the core processing unit; then the interrupt cache quantity value of the edge capturer is cleared. For details, please refer to Figure 6The process of caching and sending edge interrupt signals is shown in FIG.

[0060] The interrupt cache unit provided in the embodiment of the present application is mainly responsible for temporarily intercepting and caching the discrete interrupt control signals received within the configurable fixed time period, and then issuing and releasing the cache uniformly at the end of the countdown, so as to ensure that the interrupt control signals received by the central processing unit are received at fixed intervals, so as to avoid the CPU from being awakened at any time, and finally prolong the time when the CPU is in the CPUIdle low power consumption state (i.e., idle low power consumption state) to save CPU power consumption. At the same time, the interrupt priority should be taken into account. Some interrupt control signals require the central processing unit to respond immediately without delay (for example, when the smart driving is detected that a pedestrian suddenly runs a red light in front, it is necessary to actively brake to avoid danger). Therefore, each interrupt control signal must support the software-configurable interrupt priority. The interrupt priority has only two types: high priority and low priority. The high-priority interrupt is directly issued without caching, and the low-priority interrupt is uniformly sent through the interrupt cache unit. The software only configures a small number of necessary interrupts with high priority, and the default is ordinary low priority. Finally, when all the core processing units that are powered on are in a non-CPUIdle state (i.e., a non-idle state), the interrupt control signal should not be cached but should be directly issued to improve CPU efficiency, because in this case, the cache operation will not have power consumption benefits but only efficiency costs.

[0061] Those skilled in the art will appreciate that the system structure shown in the figure does not constitute a limitation on the embodiments of the present application, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0062] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0063] Those skilled in the art will appreciate that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0064] Based on the above system structure, various embodiments of the CPU interrupt management control method of the present application are proposed below.

[0065] like Figure 7 As shown, Figure 7The following is a flow chart of the steps of a method for controlling CPU interrupt management provided by an embodiment of the present application, which is applied to Figure 1 The interrupt management control system shown includes: multiple interrupt sources, an interrupt cache unit, an interrupt controller, and a central processing unit; the output ends of the multiple interrupt sources are connected to the input ends of the interrupt cache unit, the output ends of the interrupt cache unit are connected to the input ends of the interrupt controller, and the output ends of the interrupt controller are connected to the input ends of the central processing unit; the central processing unit includes multiple core processing units. The interrupt management control method for the CPU may include but is not limited to steps S110 to S140.

[0066] Step S110: the interrupt buffer unit receives a plurality of interrupt control signals sent by a plurality of interrupt sources.

[0067] Step S120: When the core processing unit is in an idle low power consumption state, the interrupt cache unit determines the interrupt priority of each interrupt control signal according to the priority flag signal.

[0068] Step S130: the interrupt cache unit caches the interrupt control signal with a low interrupt priority during the non-enabled period according to the periodic interrupt enable signal, and sends the cached interrupt control signal to the corresponding core processing unit through the interrupt controller during the enabled period.

[0069] Step S140: the core processing unit performs interrupt processing in response to the interrupt control signal.

[0070] It is understandable that the interrupt source refers to the interrupt control signal sent by various devices. Specifically, the interrupt control signal includes a level interrupt signal and an edge interrupt signal.

[0071] It can be understood that the interrupt enable signal is a periodic signal used for timing control so that the interrupt control signal is sent out during the period when the periodic interrupt enable signal is enabled.

[0072] It can be understood that the working state of the core processing unit includes: an idle low power consumption state (CPUIdle) and a non-idle state (ie, a non-CPUIdle state).

[0073] According to some embodiments of the present application, after step S110, after the interrupt cache unit receives multiple interrupt control signals issued by multiple interrupt sources, the method also includes: determining the working status of each core processing unit according to the CPU status flag signal of each core processing unit; wherein, when the CPU status flag signal is 0, the core processing unit is in a non-idle state; when the CPU status flag signal is 1, the core processing unit is in an idle low-power state; when all core processing units are in a non-idle state, the interrupt cache unit sends the received multiple interrupt control signals directly to the interrupt controller without delay.

[0074] Specifically, the function of judging the working status of the core processing unit is: Figure 2 The CPU state logic operation module of the interrupt cache unit is implemented.

[0075] It is understandable that when all powered-on core processing units are in a non-CPUIdle state (i.e., a non-idle state), the interrupt control signal should not be cached but should be directly sent down to improve CPU efficiency, because in this case, the cache operation will not have power consumption benefits but only efficiency costs. The embodiment of the present application provides a reliable reference for the subsequent determination of the method of sending the interrupt control signal by judging the working state of the core processing unit.

[0076] According to some embodiments of the present application, the interrupt priority is a high priority or a low priority, and the high priority has a higher priority than the low priority; further illustrating step S120, wherein the interrupt cache unit determines the interrupt priority of each interrupt control signal according to the priority flag signal, including: when the priority flag signal is 1, determining that the interrupt priority of the interrupt control signal is a high priority; when the priority flag signal is 0, determining that the interrupt priority of the interrupt control signal is a low priority. The embodiments of the present application provide a reliable reference for subsequent classification and processing of interrupt control signals based on different interrupt priorities to improve the reliability of the CPU.

[0077] According to some embodiments of the present application, after step S120, after determining the interrupt priority of each interrupt control signal according to the priority flag signal, the method further includes: when the interrupt priority is high, the interrupt cache unit directly sends the high priority interrupt control signal to the interrupt controller without delay; the interrupt controller sends the high priority interrupt control signal to the corresponding core processing unit. It can be understood that the embodiments of the present application take into account the interrupt priority in the process of interrupt management, and directly send the interrupt control signal that requires the central processing unit to respond immediately to the interrupt control signal that cannot be delayed (such as when the smart driving detects that a pedestrian suddenly runs a red light in front, and active braking is required to avoid danger) to the core processing unit, so that the CPU can respond in time to improve the reliability of interrupt management.

[0078] Through step S110 to step S140, in the process of using the interrupt management control system to manage the CPU interrupt, first, the interrupt cache unit receives multiple interrupt control signals sent by multiple interrupt sources; then, when the core processing unit is in an idle low-power state, the interrupt cache unit determines the interrupt priority of each interrupt control signal according to the priority flag signal; then, the interrupt cache unit caches the interrupt control signal with a low interrupt priority during the non-enabled period according to the periodic interrupt enable signal, and sends the cached interrupt control signal to the corresponding core processing unit through the interrupt controller during the enabled period; in this way, the interrupt control signal is cached during the non-enabled period of the periodic interrupt enable signal, and the cached multiple interrupt control signals are collectively sent during the enabled period of the periodic interrupt enable signal, so as to avoid frequently waking up the core processing unit from the idle low-power state in a very short time, which is beneficial to improving CPU performance and reducing CPU power consumption. Finally, the core processing unit performs interrupt processing in response to the interrupt control signal; this prolongs the core processing unit's residence time in the idle low-power state, so that the power consumption paid by the core processing unit to wake up the idle low-power state is less than the power consumption saved in the idle low-power state, so that the CPU maintains low power consumption and effectively improves CPU performance. Therefore, the embodiment of the present application can concentrate the cached multiple interrupt control signals during the enable period of the periodic interrupt enable signal, avoid frequently waking up the core processing unit from the low-power state, thereby improving CPU performance and reducing CPU power consumption.

[0079] According to some embodiments of the present application, the interrupt control signal includes: a level interrupt signal; the interrupt cache unit includes: an interrupt cache logic module; the interrupt cache logic module includes: a first cache logic unit; further explanation of step S130, step S130: the interrupt cache unit caches the interrupt control signal with a low interrupt priority during the non-enabled period according to the periodic interrupt enable signal, and during the enabled period, sends the cached interrupt control signal to the corresponding core processing unit through the interrupt controller, including but not limited to steps S131 to S133.

[0080] Step S131: the first cache logic unit receives an interrupt enable signal and a level interrupt signal simultaneously.

[0081] Step S132: In response to the low level of the interrupt enable signal, the received level interrupt signal is buffered.

[0082] Step S133: In response to the high level of the interrupt enable signal, all level interrupt signals currently cached and currently initiated are sent to the corresponding core processing unit through the interrupt controller.

[0083] Specifically, Figure 4As shown, the first cache logic unit is an AND logic gate, which is used to: cache the level interrupt signal during the non-enable period of the interrupt enable signal; and directly send the currently cached and currently received level interrupt signal to the interrupt controller during the enable period of the interrupt enable signal.

[0084] The embodiment of the present application uses the first cache logic unit to cache the level interrupt signal through steps S131 to S133, and concentrates on sending the cached and currently received level interrupt signal during the period when the periodic interrupt enable signal is enabled, thereby avoiding the core processing unit from waking up from a low power consumption state in a very short time, thereby improving processor performance and reducing processor power consumption.

[0085] According to some embodiments of the present application, the interrupt control signal includes: an edge interrupt signal; the interrupt cache unit includes: an interrupt cache logic module; the interrupt cache logic module includes: a second cache logic unit; further explanation of step S130, step S130: the interrupt cache unit caches the interrupt control signal with a low interrupt priority during the non-enabled period according to the periodic interrupt enable signal, and during the enabled period, sends the cached interrupt control signal to the corresponding core processing unit through the interrupt controller, including but not limited to steps S134 to S136.

[0086] Step S134: the second cache logic unit receives the interrupt enable signal and the edge interrupt signal simultaneously.

[0087] Step S135: in response to the low level of the interrupt enable signal in the previous cycle, interrupt caching and edge capture processing are performed on the edge interrupt signal, the edge interrupt signal is cached and the interrupt cache quantity value is obtained by counting.

[0088] Step S136: In response to the rising edge of the interrupt enable signal of the current cycle, and when the interrupt buffer quantity value is not zero, all edge interrupt signals buffered in the previous cycle pass through the core processing unit corresponding to the interrupt controller, and the interrupt buffer quantity value is cleared.

[0089] Specifically, Figure 5 As shown, the second cache logic unit includes: an edge capturer and a pulse generator; the edge capturer is used to count the edge interrupt signals in the previous cycle to obtain the interrupt cache quantity value, and at the rising edge of the interrupt enable signal, the interrupt cache quantity value is notified to the pulse generator so that the pulse generator determines whether to issue an edge interrupt signal.

[0090] The pulse generator is used to determine whether to send an edge interrupt signal according to the capture result of the edge capturer (ie, the interrupt buffer quantity value) at the rising edge of the interrupt enable signal.

[0091] The embodiment of the present application uses the second cache logic unit through steps S134 to S136, and the edge capturer and the pulse generator cooperate with each other to cache the edge interrupt signal, and concentrate on sending the cached edge interrupt signal during the period when the periodic interrupt enable signal is enabled, so as to avoid the core processing unit waking up from a low power consumption state in a very short time, thereby improving processor performance and reducing processor power consumption.

[0092] It can be understood that the embodiment of the present application caches discrete interrupt control signals, thereby preventing the CPU from being awakened within a short period of time after entering an idle low-power state, ensuring that the CPU has a longer residence time in the idle low-power state, thereby ensuring the good optimization effect of CPUIdle technology on CPU power consumption.

[0093] It can be understood that step S140 includes: the core processing unit performs interrupt processing in response to the interrupt control signal, including but not limited to: reading the interrupt number of the current interrupt sent by the interrupt controller; processing the current interrupt; clearing the interrupt suspension signal of the interrupt source (for the level interrupt signal); notifying the entire link that the interrupt processing has been completed, so that the system is capable of receiving the next interrupt.

[0094] like Figure 8 As shown, Figure 8 The present invention also provides an electronic device, including: a processor 801 , a memory 802 , an input / output interface 803 , a communication interface 804 , and a bus 805 .

[0095] The processor 801 may be implemented by a general core processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0096] The memory 802 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 802 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 802, and the processor 801 calls and executes the method of the embodiments of this application;

[0097] Input / output interface 803, used to implement information input and output;

[0098] The communication interface 804 is used to realize the communication interaction between the present apparatus and other devices. The communication can be realized through a wired manner (such as USB, network cable, etc.) or a wireless manner (such as mobile network, WI FI, Bluetooth, etc.);

[0099] A bus 805 that transmits information between the various components of the device (e.g., the processor 801, the memory 802, the input / output interface 803, and the communication interface 804);

[0100] The processor 801 , the memory 802 , the input / output interface 803 and the communication interface 804 are connected to each other in communication within the device via a bus 805 .

[0101] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the present application.

Claims

1. A method for managing and controlling CPU interruption, characterized in that: Applied to an interrupt management control system, the interrupt management control system comprises: a plurality of interrupt sources, an interrupt cache unit, an interrupt controller, and a central processing unit; the output ends of the plurality of interrupt sources are connected to the input end of the interrupt cache unit, the output end of the interrupt cache unit is connected to the input end of the interrupt controller, the output end of the interrupt controller is connected to the input end of the central processing unit; the central processing unit comprises a plurality of core processing units; The method comprises: The interrupt buffer unit receives a plurality of interrupt control signals sent by the plurality of interrupt sources; When the core processing unit is in an idle low power consumption state, the interrupt cache unit determines the interrupt priority of each of the interrupt control signals according to the priority flag signal; The interrupt cache unit caches the interrupt control signal with a low interrupt priority during a non-enabled period according to a periodic interrupt enable signal, and sends the cached interrupt control signal to the corresponding core processing unit through the interrupt controller during an enabled period; The core processing unit performs interrupt processing in response to the interrupt control signal.

2. The CPU interrupt management control method according to claim 1, characterized in that: The interrupt control signal includes: a level interrupt signal; the interrupt cache unit includes: an interrupt cache logic module; the interrupt cache logic module includes: a first cache logic unit; The interrupt cache unit caches the interrupt control signal with a low interrupt priority during a non-enabled period according to a periodic interrupt enable signal, and sends the cached interrupt control signal to the corresponding core processing unit through the interrupt controller during an enabled period, including: The first cache logic unit receives the interrupt enable signal and the level interrupt signal simultaneously; In response to the low level of the interrupt enable signal, buffering the received level interrupt signal; In response to the high level of the interrupt enable signal, all the level interrupt signals currently cached and currently initiated are sent to the corresponding core processing unit through the interrupt controller.

3. The CPU interrupt management control method according to claim 1, characterized in that: The interrupt control signal includes: an edge interrupt signal; the interrupt cache unit includes: an interrupt cache logic module; the interrupt cache logic module includes: a second cache logic unit; The interrupt cache unit caches the interrupt control signal with a low interrupt priority during a non-enabled period according to a periodic interrupt enable signal, and sends the cached interrupt control signal to the corresponding core processing unit through the interrupt controller during an enabled period, including: The second cache logic unit receives the interrupt enable signal and the edge interrupt signal simultaneously; In response to the low level of the interrupt enable signal in the previous cycle, interrupt caching and edge capture processing are performed on the edge interrupt signal, the edge interrupt signal is cached and the interrupt cache quantity value is obtained by counting; In response to the rising edge of the interrupt enable signal of the current cycle, and when the interrupt cache quantity value is not zero, all the edge interrupt signals cached in the previous cycle pass through the core processing unit corresponding to the interrupt controller, and the interrupt cache quantity value is cleared.

4. The CPU interrupt management control method according to claim 1, characterized in that: The interrupt priority is a high priority or a low priority, and the high priority has a higher priority than the low priority; The interrupt cache unit determines the interrupt priority of each of the interrupt control signals according to the priority flag signal, including: When the priority flag signal is 1, determining that the interrupt priority of the interrupt control signal is a high priority; When the priority flag signal is 0, it is determined that the interrupt priority of the interrupt control signal is a low priority.

5. The CPU interrupt management control method according to claim 4, characterized in that: After determining the interrupt priority of each of the interrupt control signals according to the priority flag signal, the method further includes: When the interrupt priority is a high priority, the interrupt cache unit directly sends the high priority interrupt control signal to the interrupt controller without delay; The interrupt controller sends the high priority interrupt control signal to the corresponding core processing unit.

6. The CPU interrupt management control method according to claim 1, characterized in that: After the interrupt cache unit receives the multiple interrupt control signals sent by the multiple interrupt sources, the method further includes: Determine the working state of each core processing unit according to the CPU state flag signal of each core processing unit; wherein, when the CPU state flag signal is 0, the core processing unit is in a non-idle state; when the CPU state flag signal is 1, the core processing unit is in the idle low power consumption state; When all the core processing units are in a non-idle state, the interrupt cache unit directly sends the received multiple interrupt control signals to the interrupt controller without delay.

7. An interrupt management control system, characterized in that: include: Multiple interrupt sources, interrupt buffer units, interrupt controllers, and central processing units; The output ends of the plurality of interrupt sources are connected to the input end of the interrupt cache unit, the output end of the interrupt cache unit is connected to the input end of the interrupt controller, the output end of the interrupt controller is connected to the input end of the central processing unit; the central processing unit includes a plurality of core processing units; Among them, the interrupt cache unit is used to: receive multiple interrupt control signals issued by the multiple interrupt sources; when the core processing unit is in an idle low-power state, determine the interrupt priority of each of the interrupt control signals according to the priority flag signal; according to the periodic interrupt enable signal, cache the interrupt control signal with a low interrupt priority during the non-enabled period, and during the enabled period, send the cached interrupt control signal to the corresponding core processing unit through the interrupt controller; the core processing unit is used to perform interrupt processing in response to the interrupt control signal.

8. The interrupt management control system according to claim 7, characterized in that: The interrupt cache unit includes: an interrupt cache logic module, the input end of the interrupt cache logic module is connected to the output end of the interrupt source; the output end of the interrupt cache logic module is connected to the input end of the interrupt controller; the interrupt cache logic module also includes: a first cache logic unit and a second cache logic unit.

9. The interrupt management control system according to claim 8, characterized in that: The interrupt buffer unit also includes: A counter, wherein an output end of the counter is connected to an input end of the interrupt buffer logic module; A CPU state logic operation module, wherein the input end of the CPU state logic operation module is used to input the CPU state flag signal of each core processing unit; or a logic operation module, comprising a first input terminal and a second input terminal, wherein the first input terminal is used to input the priority flag signal of the interrupt control signal; and the second input terminal is connected to the output terminal of the CPU state logic operation module; The routing module includes a first signal input terminal, a second signal input terminal, a routing enable terminal, and a routing output terminal; the first signal input terminal is connected to the output terminal of the interrupt cache logic module, the second signal input terminal is connected to the output terminal of the interrupt source, the routing enable terminal is connected to the output terminal of the OR logic operation module, and the routing output terminal is connected to the input terminal of the interrupt controller.

10. An electronic device, characterized in that: It includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the interrupt management control method for the CPU as described in any one of claims 1 to 6.

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