Time sequence control circuit of display device and display device

Abstract

The invention discloses a time sequence control circuit of display equipment and the display equipment. The time sequence control circuit of the display equipment comprises a frequency detection circuit, a cache circuit and a clock generation circuit, wherein the frequency detection circuit is configured to perform frequency detection on a synchronizing signal corresponding to image data sent by the image processor to obtain a frequency marking signal, and the frequency marking signal represents the frame rate of the image data; the cache circuit is configured to cache image data; the clock generation circuit is coupled to the frequency detection circuit and is configured to generate a target pixel clock according to the frequency flag signal, and the target pixel clock is used for enabling the display panel to display the image data according to the refresh rate corresponding to the target pixel clock. By means of the mode, the frame rate of the image data can be dynamically detected, then the refresh rate of the display panel is dynamically updated / switched, the power consumption of the time sequence control circuit is reduced, and matching of the frame rate and the refresh rate is achieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, in particular to a timing control circuit of a display device and a display device. Background Art

[0002] In the display system, the frame rate at which the image processor outputs image data to the display panel is affected by the load of the image processor itself and fluctuates all the time. When the load of the image processor is high, the frame rate of the output image data is low, and when the load of the image processor is low, the frame rate of the output image data is high. At this time, it is very easy for the screen to freeze, tear, etc. to occur due to the mismatch between the refresh rate of the display panel and the frame rate of the image data, which greatly affects the user experience.

[0003] At present, the technologies to solve the mismatch between frame rate and refresh rate mainly include VRR (Variable Refresh Rate) technology and SDRRS (Seamless Dynamic Refresh Rate Switching) technology. VRR technology controls the output frame rate of the image processor by scaling the V blank time while keeping the active frame length unchanged, during which the pixel clock remains unchanged. SDRRS technology changes the pixel clock of the image processor by sending a command to the timing control circuit through the image processor to achieve the purpose of changing the refresh rate and reducing power consumption. Although VRR technology can solve the problem of mismatch between frame rate and refresh rate, since VRR technology simply extends Vblank, when the frame rate is low, the pixel clock is still the same as the frequency at the highest frame rate. For mobile application scenarios such as laptops, it cannot achieve the purpose of significant reduction. Although SDRRS technology can change the timing control circuit by changing the pixel clock of the image processor, when the clock of the image processor changes during the operation of the interface in the receiving circuit, the initialization step of the receiving circuit needs to be re-performed, so it is only suitable for certain specific applications.

[0004] Therefore, it is urgent to provide a technical solution to solve the problems of excessive power consumption of VRR technology and the need to reinitialize the receiving circuit when changing the clock of the image processor in SDRRS technology. Summary of the invention

[0005] The present application provides a timing control circuit of a display device and a display device, which can dynamically detect the frame rate of image data, and then dynamically update / switch the refresh rate of the display panel, reduce the power consumption of the timing control circuit, and achieve matching of the frame rate and the refresh rate.

[0006] In order to solve the above technical problems, a technical solution adopted in the present application is: a timing control circuit of a display device is provided, which timing control circuit includes a frequency detection circuit, a cache circuit and a clock generation circuit; wherein the frequency detection circuit is configured to perform frequency detection on a synchronization signal corresponding to image data sent by an image processor to obtain a frequency flag signal, and the frequency flag signal represents the frame rate of the image data; the cache circuit is configured to cache the image data; the clock generation circuit is coupled to the frequency detection circuit, and is configured to generate a target pixel clock according to the frequency flag signal, and the target pixel clock is used to enable the display panel to display the image data according to the refresh rate corresponding to the target pixel clock.

[0007] Among them, the synchronization signal includes a frame synchronization signal and a line synchronization signal; the frequency detection circuit includes: a first frequency detection circuit, configured to perform frequency detection on the frame synchronization signal corresponding to the image data sent by the image processor according to the first frame rate control method, and obtain a first frequency mark signal; a second frequency detection circuit, configured to perform frequency detection on the line synchronization signal corresponding to the image data sent by the image processor according to the second frame rate control method, and obtain a second frequency mark signal; the clock generation circuit is coupled to the first frequency detection circuit and the second frequency detection circuit respectively, and is configured to generate a target pixel clock according to the first frequency mark signal or the second frequency mark signal.

[0008] Among them, the timing control circuit also includes: a receiving circuit, coupled to the first frequency detection circuit and the second frequency detection circuit, configured to receive image data sent by the image processor, and select the first frequency detection circuit or the second frequency detection circuit to perform frequency detection on the synchronization signal corresponding to the image data according to the frame rate control method corresponding to the image data.

[0009] Among them, the cache circuit includes: a first cache circuit, coupled to the receiving circuit and the first frequency detection circuit, configured to cache image data when the receiving circuit selects the first frequency detection circuit for frequency detection; a second cache circuit, coupled to the receiving circuit and the second frequency detection circuit, configured to cache image data when the receiving circuit selects the second frequency detection circuit for frequency detection.

[0010] The first cache circuit adopts frame cache, and the second cache circuit adopts double-line cache.

[0011] The timing control circuit further includes: a first selection circuit, which is respectively coupled to the first cache circuit and the second cache circuit and is configured to select to read cached image data from the first cache circuit or the second cache circuit according to the target pixel clock according to the first control signal.

[0012] Among them, the timing control circuit also includes: a second selection circuit, the first input end of the second selection circuit is coupled to the first frequency detection circuit, the second input end of the second selection circuit is coupled to the second frequency detection circuit, the output end of the second selection circuit is coupled to the clock generation circuit, and the second selection circuit is configured to select the first frequency mark signal or the second frequency mark signal output according to the second control signal.

[0013] Wherein, the clock generating circuit is configured to generate a current target pixel clock with a frequency less than the frequency of the previous target pixel clock when the frame rate deviation corresponding to the current first frequency marker signal and the previous first frequency marker signal is greater than a threshold, or when the frame rate deviation corresponding to the current second frequency marker signal and the previous second frequency marker signal is greater than a threshold; and to generate a current target pixel clock with a frequency equal to the frequency of the previous target pixel clock when the frame rate deviation corresponding to the current first frequency marker signal and the previous first frequency marker signal is less than a threshold, or when the frame rate deviation corresponding to the current second frequency marker signal and the previous second frequency marker signal is less than a threshold.

[0014] Among them, the first frequency detection circuit is also configured to determine the time difference between adjacent synchronization signals according to the reference clock to determine the first frequency marker signal corresponding to the current synchronization signal; the second frequency detection circuit is also configured to determine the time difference between adjacent synchronization signals according to the reference clock to determine the second frequency marker signal corresponding to the current synchronization signal.

[0015] In order to solve the above technical problem, another technical solution adopted by the present application is: to provide a display device, which includes the above timing control circuit.

[0016] The beneficial effect of the present application is as follows: Different from the prior art, the timing control circuit of the present application includes a frequency detection circuit, a buffer circuit and a clock generation circuit, the frequency detection circuit is configured to perform frequency detection on the synchronization signal corresponding to the image data sent by the image processor to obtain a frequency mark signal, the frequency mark signal represents the frame rate of the image data, the buffer circuit is configured to cache the image data, the clock generation circuit is coupled to the frequency detection circuit, the clock generation circuit is configured to generate a target pixel clock according to the frequency mark signal, and the target pixel clock is used to make the display panel display the image data according to the refresh rate corresponding to the target pixel clock. Through the above method, compared with the image processor actively sending a corresponding command to the timing control circuit to update the refresh rate of the display panel, the present application can dynamically detect the frame rate of the image data by using the frequency detection circuit, and then generate a corresponding pixel clock according to the detected frame rate, and then dynamically update / switch the refresh rate of the display device according to the pixel clock, which can reduce the power consumption of the timing control circuit when the frame rate of the image data is reduced, and achieve the matching between the frame rate of the image data and the refresh rate of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0018] Figure 1 is a structural schematic diagram of a first embodiment of a timing control circuit provided by the present application;

[0019] Figure 2 is a structural schematic diagram of a second embodiment of a timing control circuit provided by the present application;

[0020] Figure 3 is a schematic diagram of an embodiment of a first frame rate control method provided by the present application;

[0021] Figure 4 is a schematic diagram of an embodiment of a second frame rate control method provided by the present application;

[0022] Figure 5 is a structural schematic diagram of a third embodiment of a timing control circuit provided by the present application;

[0023] Figure 6 is a schematic diagram of a first embodiment of frequency conversion provided by the present application;

[0024] Figure 7 is a schematic diagram of a second embodiment of frequency conversion provided by the present application;

[0025] Figure 8 is a structural schematic diagram of a first embodiment of a display device provided by the present application;

[0026] Fig. 9 is a structural schematic diagram of a second embodiment of a display device provided by the present application;

[0027] Fig.10 It is a structural schematic diagram of the third embodiment of the display device provided in this application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] See also Figure 1 , Figure 11 is a schematic diagram of the structure of the first embodiment of the timing control circuit provided in the present application. The timing control circuit 10 includes a frequency detection circuit 101, a cache circuit 102 and a clock generation circuit 103.

[0030] The frequency detection circuit 101 is configured to perform frequency detection on a synchronization signal corresponding to image data sent by an image processor to obtain a frequency mark signal, which represents the frame rate of the image data; the cache circuit 102 is configured to cache image data, and the cache circuit 102 caches data according to the signal of the frequency detection circuit 101. When the frame rate changes after the frequency detection circuit 101 performs frequency detection, the cache circuit 102 is controlled to cache; the clock generation circuit 103 is coupled to the frequency detection circuit 101, and the clock generation circuit 103 is configured to generate a target pixel clock according to the frequency mark signal, and the target pixel clock is used to enable the display panel to display image data according to the refresh rate corresponding to the target pixel clock.

[0031] The image processor is a GPU (Graphics Processing Unit), and the timing control circuit 10 is a TCON (Timing Controller).

[0032] In some embodiments, the synchronization signal includes a frame synchronization signal and a line synchronization signal. Figure 2 , the frequency detection circuit 101 includes a first frequency detection circuit 201 and a second frequency detection circuit 202. The first frequency detection circuit 201 is configured to perform frequency detection on a frame synchronization signal corresponding to image data sent by the image processor in accordance with a first frame rate control method, and obtain a first frequency mark signal; the second frequency detection circuit 202 is configured to perform frequency detection on a line synchronization signal corresponding to image data sent by the image processor in accordance with a second frame rate control method, and obtain a second frequency mark signal. At this time, the clock generation circuit 103 is coupled to the first frequency detection circuit 201 and the second frequency detection circuit 202, respectively, and the clock generation circuit 103 is configured to generate a target pixel clock according to the first frequency mark signal or the second frequency mark signal.

[0033] The first frame rate control mode is to keep the effective data length of the original image data unchanged, and to change the frame rate by extending or shortening the VBlank (field blanking) time to obtain new image data. V Blank refers to the time interval for the scanning point to return from the lower right corner of the image to the upper left corner of the image after scanning a frame and start scanning a new frame.

[0034] like Figure 3As shown in the figure, if 60FPS (FPS: Frames Per Second, the number of frames transmitted per second, referred to as frame rate) is changed to 30FPS, the length of the valid data of the next frame of 30FPS needs to be kept the same as the length of the valid data of the next frame of 60FPS. At this time, the frame rate is changed by extending the time of VFP (Vertical synchronizing Front Porch) and VBP (Verticalsynchronizing Back Porch). If 30FPS is changed to 60FPS, the length of the valid data of the next frame of 30FPS needs to be kept the same as the length of the valid data of the next frame of 60FPS. At this time, the frame rate is changed by shortening the time of VFP and VBP. Among them, Active frame represents the valid frame, and 1920×1200 represents the resolution of the display device / display panel.

[0035] The second frame rate control mode is to keep the effective data length of the image data unchanged, and to change the frame rate by extending or shortening the HBlank (line blanking) time to obtain image data. HBlank refers to the time difference from the end of the previous line to the beginning of the next line.

[0036] like Figure 4 As shown in the figure, if 60FPS is changed to 30FPS, the length of the next line of valid data at 30FPS needs to be the same as that of the next line of valid data at 60FPS. At this time, the frame rate is changed by extending the time of VFP, VBP and Active frame. If 30FPS is changed to 60FPS, the length of the next line of valid data at 30FPS needs to be the same as that of the next line of valid data at 60FPS. At this time, the frame rate is changed by shortening the time of VFP, VBP and Active frame.

[0037] It can be understood that the first frame rate control method is to change the frame rate by extending or shortening the time of VFP and VBP; the second frame rate control method is to change the frame rate by extending or shortening the time of VFP, VBP and Active frame. Both the first frame rate control method and the second frame rate control method are control methods in which the image processor controls the frame rate of the output image data. In other words, the frame rate of the image data is determined by the image processor, and the image processor can control the frame rate of the image data to increase or decrease.

[0038] Different from the prior art, the timing control circuit 10 provided in the present application includes a frequency detection circuit 101, a cache circuit 102 and a clock generation circuit 103. The frequency detection circuit 101 is configured to perform frequency detection on the synchronization signal corresponding to the image data sent by the image processor to obtain a frequency mark signal, which represents the frame rate of the image data. The cache circuit 102 is configured to cache the image data. The clock generation circuit 103 is coupled to the frequency detection circuit 101. The clock generation circuit 103 is configured to generate a target pixel clock according to the frequency mark signal. The target pixel clock is used to make the display panel display the image data according to the refresh rate corresponding to the target pixel clock. In the above manner, a dynamic frame rate detection mechanism is adopted, and the frame rate of the current image processor can be obtained and the refresh rate of the display panel can be switched without the image processor sending a command, thereby reducing the power consumption of the timing control circuit 10.

[0039] Furthermore, the two frame rate control methods provided in the present application, namely, using V Blank extension and H Blank extension for processing respectively, can be adapted to a variety of image processors.

[0040] In some embodiments, see Figure 2 The timing control circuit 10 also includes a receiving circuit 104, which is coupled to the first frequency detection circuit 201 and the second frequency detection circuit 202. The receiving circuit 104 is configured to receive image data sent by the image processor, and select the first frequency detection circuit 201 or the second frequency detection circuit 202 to perform frequency detection on the synchronization signal corresponding to the image data according to the frame rate control method corresponding to the image data.

[0041] The receiving circuit 104 and the image processor are connected via an eDP (Embedded DisplayPort) interface, which has the characteristics of high bandwidth, good integration, and reduced device complexity. In other embodiments, other interfaces may be used for connection, which is not limited here.

[0042] Optionally, when the synchronization signal is a frame synchronization signal, the first frequency detection circuit 201 is selected to perform frequency detection on the frame synchronization signal corresponding to the image data; when the synchronization signal is a line synchronization signal, the second frequency detection circuit 202 is selected to perform frequency detection on the line synchronization signal corresponding to the image data.

[0043] In some embodiments, the first frequency detection circuit 201 is further configured to determine the time difference between adjacent synchronization signals according to the reference clock to determine the first frequency mark signal corresponding to the current synchronization signal; the second frequency detection circuit 202 is further configured to determine the time difference between adjacent synchronization signals according to the reference clock to determine the second frequency mark signal corresponding to the current synchronization signal. The reference clock is set in the timing control circuit 10, and the reference clock can be an oscillator of the timing control circuit 10.

[0044] Specifically, the first frequency detection circuit 201 performs frequency detection on the frame synchronization signal corresponding to the image data, and the specific process of obtaining the first frequency mark signal includes: when receiving the current frame synchronization signal, using the reference clock to determine the first time, when receiving the next frame synchronization signal, using the reference clock to determine the second time, based on the first time and the second time, determining the time difference between the two frame synchronization signals, and then determining the first frequency mark signal corresponding to the current frame synchronization signal according to the time difference. The first frequency mark signal can be set according to the corresponding frame rate, such as the first frequency mark signal corresponding to 60FPS is 0, the first frequency mark signal corresponding to 45FPS is 1, and the first frequency mark signal corresponding to 30FPS is 2.

[0045] For example, for the first frame rate control mode (i.e., V Blank extension), OSC (Oscillator) is used to represent the reference clock, and Vsync is used to represent the frame synchronization signal. The timing control circuit 10 uses the internal OSC as the reference clock to measure the time difference between the two Vsyncs. When Vsync is pulled high, the counter starts counting until the next Vsync arrives, then the counter stops counting, and then the frame rate of the current frame is calculated based on the count value. After the frame rate is calculated, the counter is cleared to restart counting.

[0046] Specifically, the second frequency detection circuit 202 performs frequency detection on the line synchronization signal corresponding to the image data, and the specific process of obtaining the second frequency mark signal includes: when receiving the current line synchronization signal, using the reference clock to determine the first time, when receiving the next line synchronization signal, using the reference clock to determine the second time, based on the first time and the second time, determine the time difference between the two line synchronization signals, and then determine the second frequency mark signal corresponding to the current line synchronization signal according to the time difference. The second frequency mark signal can be set according to the corresponding frame rate, such as the second frequency mark signal corresponding to 60FPS is 0, the second frequency mark signal corresponding to 45FPS is 1, and the second frequency mark signal corresponding to 30FPS is 2.

[0047] For example, for the second frame rate control mode (i.e., H blank extension), OSC is used to represent the reference clock, and Hsync is used to represent the horizontal synchronization signal. The timing control circuit 10 uses the internal OSC as the reference clock to measure the time difference between two Hsyncs. When Hsync is pulled high, the counter starts counting until the next Hsync arrives, then the counter stops counting, and then the frame rate of the current frame is calculated according to the count value. After the frame rate is calculated, the counter is cleared to restart counting.

[0048] In some embodiments, see Figure 2 , the cache circuit 102 includes a first cache circuit 203 and a second cache circuit 204. The first cache circuit 203 is coupled to the receiving circuit 104 and the first frequency detection circuit 201, and the first cache circuit 203 is configured to cache image data when the receiving circuit 104 selects the first frequency detection circuit 201 for frequency detection; the second cache circuit 204 is coupled to the receiving circuit 104 and the second frequency detection circuit 202, and the second cache circuit 204 is configured to cache image data when the receiving circuit 104 selects the second frequency detection circuit 202 for frequency detection. The image data is RGB data.

[0049] The first cache circuit 203 uses a frame cache, and the second cache circuit 204 uses a dual-line cache. The frame cache performs cache in a write-and-read cycle; the dual-line cache performs cache in an alternating manner by writing to cache 1 and then writing to cache 2, and reading from cache 1 and then reading from cache 2, that is, caching is performed in an alternating manner. At this time, the process of writing to cache 2 and reading from cache 1 may overlap in time, and even the subsequent process of writing to cache 1 and reading from cache 2 may overlap in time.

[0050] It is worth noting that in other embodiments, when the synchronization signal is a frame synchronization signal, it corresponds to the first frequency detection circuit 201 and the first buffer circuit 203; when the synchronization signal is a line synchronization signal, it corresponds to the first frequency detection circuit 201 and the second frequency detection circuit 202, and the second buffer circuit 204. That is, when the second buffer circuit 204 is used, the first frequency detection circuit 201 and the second frequency detection circuit 202 need to be used at the same time, and when the first buffer circuit 203 is used, only the first frequency detection circuit 201 needs to be used. At this time, the receiving circuit 104 can process the image data to obtain parallel RGB data, so as to send the parallel RGB data to the first detection circuit 101 and / or the second detection circuit, and the corresponding buffer circuit.

[0051] In addition, for the first frame rate control method, when the frame rate of the image data output by the image processor drops below 30FPS, the frame cache is used to cache the valid frame data; for the second frame rate control method, when the frame rate of the image data output by the image processor drops below 30FPS, a double-line cache is used to store the valid line data to avoid problems such as data loss caused by fast reading and slow writing.

[0052] Different from the prior art, the timing control circuit 10 provided in the present application can adopt a dynamic frame rate detection mechanism, which can obtain the frame rate of the current image processor and switch the refresh rate of the display panel without sending a command from the image processor end, thereby reducing the power consumption of the timing control circuit 10.

[0053] In some embodiments, see Figure 5 The timing control circuit 10 further includes a first selection circuit 105 and a second selection circuit 106. The first selection circuit 105 is coupled to the first cache circuit 203 and the second cache circuit 204 respectively, and the first selection circuit 105 is configured to select to read the cached image frame number data from the first cache circuit 203 or the second cache circuit 204 according to the target pixel clock according to the first control signal. The first input end of the second selection circuit 106 is coupled to the first frequency detection circuit 201, the second input end of the second selection circuit 106 is coupled to the second frequency detection circuit 202, the output end of the second selection circuit 106 is coupled to the clock generation circuit 103, and the second selection circuit 106 is configured to select the first frequency mark signal or the second frequency mark signal for output according to the second control signal. The first control signal and the second control signal are from the command register, and the first selection circuit 105 and the second selection circuit 106 are multiplexers.

[0054] Specifically, the first buffer circuit 203 / the second buffer circuit 204 writes the image data at a first speed, and the first selection circuit 105 reads the buffered image data from the first buffer circuit 203 / the second buffer circuit 204 at a second speed different from the first speed.

[0055] In practical applications, in order to avoid problems such as image data loss caused by fast writing and slow reading when the frame rate of image data changes, the first speed is set to be greater than the second speed. For example, the first speed is x, and the second speed is 0.5x, 0.25x or 0.2x.

[0056] It is worth noting that the clock generating circuit 103 is configured to generate a current target pixel clock with a frequency less than the frequency of the previous target pixel clock when the frame rate deviation between the current first frequency marker signal and the previous first frequency marker signal is greater than a threshold, or when the frame rate deviation between the current second frequency marker signal and the previous second frequency marker signal is greater than a threshold; and to generate a current target pixel clock with a frequency equal to the frequency of the previous target pixel clock when the frame rate deviation between the current first frequency marker signal and the previous first frequency marker signal is less than a threshold, or when the frame rate deviation between the current second frequency marker signal and the previous second frequency marker signal is less than a threshold. The threshold can be set according to actual conditions.

[0057] For example, the frequency detection circuit 101 detects that the frame rate of the image data output by the image processor drops from 60 FPS to 30 FPS or lower. Figure 3 At this time, the frequency detection circuit 101 will control the clock generation circuit 103 to automatically generate a target pixel clock. When the frequency of the target pixel clock (0.5T) is half of the frequency of the previous target pixel clock (T), the frame rate of the image data remains unchanged. At this time, the problem of fast writing and slow reading will arise, and the image data is easily lost. Therefore, the cache circuit 102 needs to be used for caching.

[0058] When the buffer circuit 102 is the frame buffer of the first buffer circuit 203, the frame buffer is enabled when the frequency of the target pixel clock drops to half the frequency of the previous target pixel clock (i.e. 0.5T), the receiving circuit 104 writes the image data at a speed of x, and the timing control circuit 10 reads the image data from the receiving circuit 104 at a speed of 0.5x. Since Vblank is extended to twice the original value at 30Hz, the timing control circuit 10 has enough time to read all valid data and display it on the control panel, ensuring data continuity. When the frequency detection circuit 101 detects that the deviation between the frame rate of the image data and 60Hz is small, the frequency of the current target pixel clock is not changed, and only V blank is extended or shortened to synchronize the frequency of the input frame.

[0059] When the timing control circuit 10 changes from 60Hz to 30Hz, the image data will not be lost due to the presence of frame buffer. When it changes from 30Hz to 60Hz, the timing control circuit 10 can only read half of the valid image data, because the frame rate of the current frame has risen to 60FPS, and the frequency in the timing control circuit 10 needs to be switched to 60Hz when the frame synchronization signal of the next frame arrives, which results in the target pixel clock (0.5T) used in the current frame time can only read half of the valid image data. However, for image display, the loss of one frame of image data will not have a significant impact on the senses.

[0060] When the cache circuit 102 is the second cache circuit 204, i.e., the dual-line cache, the dual-line cache is enabled when the frequency (0.5T) of the target pixel clock drops to half the frequency (T) of the previous target pixel clock. The dual-line cache includes cache 1 and cache 2. The receiving circuit 104 writes the image data into cache 1 at a speed of x. The timing control circuit 10 reads the data from cache 1 at a speed of 0.5x. When cache 1 is written, cache 2 is written next. When the timing control circuit 10 finishes reading the data from cache 1, it immediately reads the data in cache 2. The process is repeated until the entire frame of data is read. Since H blank is extended to twice the original value at 30 Hz, the timing control circuit 10 has enough time to read out all valid data and display it on the control panel, thereby ensuring data continuity. When the frequency detection circuit 101 detects that the deviation between the frame rate of the image data and 60 Hz is small, the frequency of the current target pixel clock is not changed. Only H blank is extended or shortened to synchronize the frequency of the input frame.

[0061] When the timing control circuit 10 changes from 60Hz to 30Hz, due to the existence of double-line buffer, the frequency detection circuit 101 detects that the frame rate of the current frame is 30FPS when the first line of valid data is detected, so the frequency of the timing control circuit 10 is set to 30Hz before the second line of valid data begins. Since the frequency of the timing control circuit 10 is still at 60Hz when the first line of valid data arrives, the target pixel clock has not changed, and the first line of valid data can still be read completely. When the second line of valid data arrives, the target pixel clock (0.5T) has dropped to half of the previous target pixel clock (T), but through the double-line buffer, the timing control circuit 10 can read all valid data completely until the end of the whole frame. When the operating frequency of the timing control circuit 10 is 30Hz, the frame rate of the image processor will be increased to 60Hz. The frequency detection circuit 101 detects that the current frame rate has become 60FPS when the first line of valid data ends, so the frequency of the timing control circuit 10 is switched to 60Hz before the second line of valid data begins. Because when the first line of valid data arrives, the timing control circuit 10 is still in the 30Hz state, and the target pixel clock is 1 / 2 of the 60Hz state, the first line of valid data cannot be fully read, and the first line of display will show abnormality. When the second line of valid data arrives, the frequency of the target pixel clock switches back to 60Hz, and all valid data from the second line to the end of the frame can be fully read.

[0062] In some embodiments, for the first frame rate control method, such as Figure 6As shown, 30hz_vsync_flag, 45hz_vsync_flag and 60hz_vsync_flag are all frequency flag signals, idle, 30Hz State, 45Hz State and 60Hz State are all states of the timing control circuit 10, wherein idle represents an idle state, and the timing control circuit 10 can perform frequency conversion according to the received frequency flag signal.

[0063] In some embodiments, for the second frame rate control method, such as Figure 7 As shown, 30hz_hsync_flag, 45hz_hsync_flag and 60hz_hsync_flag are all frequency flag signals, idle, 30Hz State, 45Hz State and 60Hz State are all states of the timing control circuit 10, wherein idle represents an idle state, and the timing control circuit 10 can perform frequency conversion according to the received frequency flag signal.

[0064] See also Figure 8 , Figure 8 1 is a schematic diagram of the structure of the first embodiment of the display device provided in the present application. The display device 80 includes the timing control circuit 10 described in any of the above embodiments, which will not be described in detail here.

[0065] For further information, see Fig. 9 , Fig. 9 1 is a schematic diagram of the structure of the second embodiment of the display device 80 provided by the present application, and the display device 80 includes an image processor 801, a timing control circuit 10, an image quality IP management module 107, a sending circuit 108 and a display panel 109. Among them, the timing control circuit 10 at least includes a frequency detection circuit 101, a buffer circuit 102, a clock generation circuit 103, a receiving circuit 104, a first selection circuit 105, and a second selection circuit 106. Among them, the frequency detection circuit 101 includes a first frequency detection circuit 201 and a second frequency detection circuit 202; the buffer circuit 102 includes a first buffer circuit 203 and a second buffer circuit 204.

[0066] Among them, the input end of the receiving circuit 104 is connected to the image processor 801, and the output end of the receiving circuit 104 is respectively connected to the first frequency detection circuit 201, the second frequency detection circuit 202, the first cache circuit 203 and the second cache circuit 204. The receiving circuit 104 is configured to receive the image data sent by the image processor 801, and when the frame rate control mode is the first frame rate control mode, the image data is input into the first frequency detection circuit 201, so as to use the first frequency detection circuit 201 to perform frequency detection on the frame synchronization signal corresponding to the image data to obtain a first frequency mark signal; or when the frame rate control mode is the second frame rate control mode, the image data is input into the second frequency detection circuit 202, so as to use the second frequency detection circuit 202 to perform frequency detection on the line synchronization signal corresponding to the image data to obtain a second frequency mark signal.

[0067] The input end of the first selection circuit 105 is coupled to the first buffer circuit 203, the second buffer circuit 204 and the command register, and the output end is coupled to the image quality IP management module 107. The first selection circuit 105 is configured to select the first buffer circuit 203 or the second buffer circuit 204 to read the buffered image data according to the pixel clock according to the first control signal sent by the command register. The command register can be set in the display device 80 or the timing control circuit 10.

[0068] The input end of the second selection circuit 106 is coupled to the first frequency detection circuit 201, the second frequency detection circuit 202 and the command register, the output end of the second selection circuit 106 is coupled to the clock generation circuit 103, and the second selection circuit 106 is configured to select the first frequency mark signal or the second frequency mark signal for output according to the second control signal sent by the command register.

[0069] The functions / roles of the first cache circuit 203 , the second cache circuit 204 and the clock generating circuit 103 in the display device 80 may refer to the above embodiments, which will not be described in detail here.

[0070] The output end of the image quality IP management module 107 is also coupled to the clock generation circuit 103 . The output end of the image quality IP management module 107 is coupled to the sending circuit 108 . The image quality IP management module 107 includes an IP for processing image data.

[0071] In some embodiments, see Fig.10The timing control circuit 10 further includes a read / write control circuit 110 and a video signal generating circuit 111. The read / write control circuit 110 is coupled to the receiving circuit 104 and the image quality IP management module 107. The video signal generating circuit 111 is coupled to the receiving circuit 104 and the image quality IP management module 107. The read / write control circuit 110 can be built into the cache circuit 102, or can be independent of the cache circuit 102, that is, the read / write control circuit 110 is coupled to the cache circuit 102; the video signal generating circuit 111 can be independent of the cache circuit 102, that is, the video signal generating circuit 111 is coupled to the cache circuit 102. In other words, the read / write control circuit 110, the video signal generating circuit 111 and the cache circuit 102 can be integrated on a single chip.

[0072] In some embodiments, see Fig.10 The timing control circuit 10 further includes a clock switching circuit 112, which is coupled to the frequency detection circuit 101 and the clock generation circuit 103. The clock switching circuit 112 is used to receive the target pixel clock sent by the clock generation circuit 103, and send the target pixel clock to the display panel 109, so that the display panel 109 displays the image data according to the refresh rate corresponding to the target pixel clock. Among them, the proportion of the pixel clock transmitted between the clock switching circuit 112 and the clock generation circuit 103 includes at least 1, 1 / 2, 1 / 4 and 1 / 8, that is, when the cache circuit 102 writes the image data to the corresponding pixel clock x, the target pixel clock generated by the clock generation circuit 103 is x, 1 / 2x, 1 / 4x or 1 / 8x.

[0073] In some embodiments, the timing control circuit 10 further includes a first data strobe circuit and a second data strobe circuit (not shown). The first data strobe circuit is coupled to the frequency detection circuit 101, the buffer circuit 102, the receiving circuit 104, the read / write control circuit 110 and the video signal generating circuit 111, and is used to select a corresponding synchronization signal according to the selected frame rate control mode, and send the synchronization signal to the frequency detection circuit 101, so that the frequency detection circuit 101 performs frequency detection on the synchronization signal to obtain a frequency mark signal; the second data strobe circuit is coupled to the image quality IP management module 107, the first selection circuit 105, the clock generating circuit 103 / clock switching circuit 112, the buffer circuit 102, the read / write control circuit 110 and the video signal generating circuit 111, and is used to generate a valid data signal.

[0074] Different from the prior art, the display device 80 provided in the present application includes at least an image processor 801, a timing control circuit 10, an image quality IP management module 107, a sending circuit 108 and a display panel 109. The display panel 109 of the display device 80 will not have screen freezes, screen tearing and other phenomena.

[0075] In summary, the timing control circuit 10 provided in the present application can adjust the target pixel clock to reduce the power consumption of the timing control circuit 10 when detecting that the frame rate of the image data output by the image processor 801 decreases / increases, and when detecting that the frame rate of the image data is restored, the target pixel clock is restored, that is, the frame rate of the image data can be dynamically detected, and then the refresh rate of the display panel 109 can be dynamically updated / switched, thereby reducing the power consumption of the timing control circuit 10, achieving the matching of the frame rate and the refresh rate, and ensuring that the display panel 109 displays the image uninterruptedly. In addition, two frame rate control methods are provided, which can be applicable to a variety of image processors 801.

[0076] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A timing control circuit for a display device, characterized in that: The timing control circuit comprises: A frequency detection circuit is configured to perform frequency detection on a synchronization signal corresponding to the image data sent by the image processor to obtain a frequency marker signal; the frequency marker signal represents a frame rate of the image data; A cache circuit configured to cache the image data; The clock generating circuit is coupled to the frequency detecting circuit and is configured to generate a target pixel clock according to the frequency mark signal, wherein the target pixel clock is used to enable the display panel to display the image data according to a refresh rate corresponding to the target pixel clock.

2. The timing control circuit according to claim 1, characterized in that: The synchronization signal includes a frame synchronization signal and a line synchronization signal; The frequency detection circuit comprises: A first frequency detection circuit is configured to perform frequency detection on a frame synchronization signal corresponding to image data sent by the image processor in a first frame rate control manner to obtain a first frequency mark signal; A second frequency detection circuit is configured to perform frequency detection on a line synchronization signal corresponding to the image data sent by the image processor in a second frame rate control manner to obtain a second frequency mark signal; The clock generating circuit is coupled to the first frequency detecting circuit and the second frequency detecting circuit respectively, and is configured to generate the target pixel clock according to the first frequency marker signal or the second frequency marker signal.

3. The timing control circuit according to claim 2, characterized in that: The timing control circuit also includes: A receiving circuit is coupled to the first frequency detection circuit and the second frequency detection circuit, and is configured to receive the image data sent by the image processor, and select the first frequency detection circuit or the second frequency detection circuit to perform frequency detection on the synchronization signal corresponding to the image data according to a frame rate control method corresponding to the image data.

4. The timing control circuit according to claim 3, characterized in that: The cache circuit comprises: A first buffer circuit is coupled to the receiving circuit and the first frequency detection circuit, and is configured to buffer the image data when the receiving circuit selects the first frequency detection circuit to perform frequency detection; The second buffer circuit is coupled to the receiving circuit and the second frequency detection circuit, and is configured to buffer the image data when the receiving circuit selects the second frequency detection circuit to perform frequency detection.

5. The timing control circuit according to claim 4, characterized in that: The first cache circuit adopts a frame cache, and the second cache circuit adopts a dual-line cache.

6. The timing control circuit according to claim 4, characterized in that: The timing control circuit also includes: a first selection circuit, which is coupled to the first cache circuit and the second cache circuit respectively, and is configured to select the cached image data to be read from the first cache circuit or the second cache circuit according to the target pixel clock according to a first control signal.

7. The timing control circuit according to claim 3, characterized in that: The timing control circuit also includes: a second selection circuit, a first input end of the second selection circuit is coupled to the first frequency detection circuit, a second input end of the second selection circuit is coupled to the second frequency detection circuit, an output end of the second selection circuit is coupled to the clock generation circuit, and the second selection circuit is configured to select the first frequency mark signal or the second frequency mark signal for output according to a second control signal.

8. The timing control circuit according to claim 7, characterized in that: The clock generating circuit is configured to generate a current target pixel clock with a frequency lower than the frequency of the previous target pixel clock when a frame rate deviation corresponding to the current first frequency marker signal and the previous first frequency marker signal is greater than a threshold, or when a frame rate deviation corresponding to the current second frequency marker signal and the previous second frequency marker signal is greater than a threshold; And when the frame rate deviation corresponding to the current first frequency marker signal and the previous first frequency marker signal is less than the threshold, or when the frame rate deviation corresponding to the current second frequency marker signal and the previous second frequency marker signal is less than the threshold, the frequency of the current target pixel clock generated is equal to the frequency of the previous target pixel clock.

9. The timing control circuit according to claim 2, characterized in that: The first frequency detection circuit is further configured to determine a first frequency marker signal corresponding to a current synchronization signal by determining a time difference between adjacent synchronization signals according to a reference clock; The second frequency detection circuit is further configured to determine a second frequency marker signal corresponding to a current synchronization signal by determining a time difference between adjacent synchronization signals according to the reference clock.

10. A display device, characterized in that: The display device comprises the timing control circuit as claimed in any one of claims 1 to 9.

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