Gate driving circuit and display panel

Abstract

The application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a plurality of cascaded shift registers. An Nth shift register comprises a stage transmission signal selection module, an up pull control module, a first filtering module, a second filtering module and a first output module. The first filtering module filters out a first part of a second pulse of a second node appearing later in a frame. The second filtering module filters out a second part of a first pulse of the second node appearing earlier in the frame and a third part of the second pulse appearing later. A first part of the first pulse with a fixed width is reserved. Then, the first output module is controlled to output a gate driving signal with the pulse with the fixed width at a corresponding time. After the improvement, the gate driving circuit can be suitable for the driving requirements of a back end.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate drive circuit and a display panel. BACKGROUND

[0002] In the display panel, the gate drive circuit usually provides the required gate drive signal for the transistor corresponding to the pixel circuit.

[0003] However, the pulse of the gate drive signal provided by the gate drive circuit cannot always meet the driving timing of the pixel circuit in terms of time and width. Therefore, this becomes one of the reasons for improving the gate drive circuit. SUMMARY

[0004] The present application provides a gate drive circuit and a display panel to alleviate the technical problem that the pulse of the gate drive signal is difficult to meet the requirements in terms of time and width.

[0005] In a first aspect, the present application provides a gate drive circuit, which comprises a plurality of cascaded shift registers, an Nth shift register comprising a stage transmission signal selection module, a pull-up control module, a first filter module, a second filter module and a first output module, the stage transmission signal selection module being electrically connected between a first node and a first wiring; the pull-up control module controls the potential of a second node according to the potential of the first node and the potential of a first clock signal; the first filter module is electrically connected between the second node and a third node, and the control end of the first filter module is connected to a reset signal; the second filter module is electrically connected between the first filter module and the third node, and the control end of the second filter module is connected to a filter control signal having a plurality of pulses in a frame; and the first output module outputs a first gate drive signal according to the potential of the third node and the potential of a fourth node.

[0006] In a second aspect, the present application provides a display panel, which comprises a pixel circuit and the gate drive circuit in at least one of the embodiments described above, the pixel circuit comprising a write transistor for controlling the input of a data signal and a compensation transistor for controlling the input of the data signal to the gate of a drive transistor; the output end of the first output module is electrically connected to the gate of the write transistor, and the output end of the second output module is electrically connected to the gate of the compensation transistor.

[0007] The gate drive circuit and the display panel provided by the present application can filter out the first part of the second pulse of the second node appearing later in a frame through the first filter module, filter out the second part of the first pulse of the second node appearing first in a frame and the second part of the second pulse appearing later, retain the first part of the fixed width in the first pulse, and then control the first output module to output the gate drive signal with the pulse of the fixed width at the corresponding time. After the improvement, it can meet the driving requirements of the back end. Attached Figure Description

[0008] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0009] Figure 1 This is a schematic diagram of the pixel circuit in related technologies.

[0010] Figure 2 for Figure 1 Timing diagram of the pixel circuit.

[0011] Figure 3 This is a schematic diagram of a first structure of the gate drive circuit provided in an embodiment of this application.

[0012] Figure 4 for Figure 3 The timing diagram of the gate drive circuit is shown.

[0013] Figure 5 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the first stage of the process.

[0014] Figure 6 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the second stage of the process.

[0015] Figure 7 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the third stage of the process.

[0016] Figure 8 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the fourth stage of the process.

[0017] Figure 9 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the fifth stage of the process.

[0018] Figure 10 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the sixth stage of the process.

[0019] Figure 11 for Figure 3 The gate drive circuit shown is in Figure 4 A schematic diagram of the seventh stage of the process.

[0020] Figure 12 forFigure 3 The state diagram of the gate drive circuit in the eighth stage is shown in FIG. 8. Figure 4 The state diagram of the gate drive circuit in the ninth stage is shown in FIG. 9.

[0021] Figure 13 The state diagram of the gate drive circuit in the tenth stage is shown in FIG. 10. Figure 3 The state diagram of the gate drive circuit in the eleventh stage is shown in FIG. 11. Figure 4

[0022] Figure 14 The state diagram of the gate drive circuit in the twelfth stage is shown in FIG. 12. Figure 3 The state diagram of the gate drive circuit in the thirteenth stage is shown in FIG. 13. Figure 4

[0023] Figure 15 The state diagram of the gate drive circuit in the fourteenth stage is shown in FIG. 14. Figure 3 The state diagram of the gate drive circuit in the fifteenth stage is shown in FIG. 15. Figure 4

[0024] Figure 16 The state diagram of the gate drive circuit in the sixteenth stage is shown in FIG. 16. Figure 3 The state diagram of the gate drive circuit in the seventeenth stage is shown in FIG. 17. Figure 4

[0025] Figure 17 The state diagram of the gate drive circuit in the eighteenth stage is shown in FIG. 18. Figure 3 The state diagram of the gate drive circuit in the nineteenth stage is shown in FIG. 19. Figure 4

[0026] Figure 18 The state diagram of the gate drive circuit in the twentieth stage is shown in FIG. 20. Figure 3 The state diagram of the gate drive circuit in the twenty-first stage is shown in FIG. 21. Figure 4

[0027] Figure 19 The state diagram of the gate drive circuit in the twenty-second stage is shown in FIG. 22. Figure 3 The state diagram of the gate drive circuit in the twenty-third stage is shown in FIG. 23. Figure 4

[0028] Figure 20 The second structure diagram of the gate drive circuit provided by the embodiments of the present application is shown in FIG. 24.

[0029] Figure 21 The timing diagram of the gate drive circuit is shown in FIG. 25. Figure 20 The state diagram of the gate drive circuit in the first stage is shown in FIG. 26. The state diagram of the gate drive circuit in the second stage is shown in FIG. 27.

[0030] The state diagram of the gate drive circuit in the third stage is shown in FIG. 28. Figure 22 The state diagram of the gate drive circuit in the fourth stage is shown in FIG. 29. Figure 20 The state diagram of the gate drive circuit in the fifth stage is shown in FIG. 30. Figure 21 The state diagram of the gate drive circuit in the sixth stage is shown in FIG. 31. The state diagram of the gate drive circuit in the seventh stage is shown in FIG. 32.

[0031] The state diagram of the gate drive circuit in the eighth stage is shown in FIG. 33. Figure 23 The state diagram of the gate drive circuit in the ninth stage is shown in FIG. 34. Figure 20 The state diagram of the gate drive circuit in the tenth stage is shown in FIG. 35. Figure 21 The state diagram of the gate drive circuit in the eleventh stage is shown in FIG. 36. The state diagram of the gate drive circuit in the twelfth stage is shown in FIG. 37.

[0032] The state diagram of the gate drive circuit in the thirteenth stage is shown in FIG. 38.​Figure 24 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the third stage of the process.

[0033] Figure 25 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the fourth stage of the process.

[0034] Figure 26 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the fifth stage of the process.

[0035] Figure 27 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the sixth stage of the process.

[0036] Figure 28 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the seventh stage of the process.

[0037] Figure 29 for Figure 20 The gate drive circuit shown is in Figure 21 A schematic diagram of the eighth stage of the process.

[0038] Figure 30 This is a timing diagram illustrating the generation of the Nth negative pulse gate drive signal provided in an embodiment of this application.

[0039] Figure 31 for Figure 3 or Figure 20 The diagram shows a cascaded structure between shift registers in the gate drive circuit.

[0040] Figure 32 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application.

[0041] Figure 33 This is a schematic diagram of the pixel circuit provided in an embodiment of this application.

[0042] Figure 34 for Figure 33 Timing diagram of the pixel circuit. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0045] In the gate driving circuit of application No. 202310191137.9, the Nth-level negative pulse gate driving signal Pout[N] has one negative pulse in one frame. The Nth-level positive pulse gate driving signal Nout[N] has two positive pulses in one frame, and the pulse widths of the two positive pulses must be equal and both be 2H. This restricts the width of the positive pulses of the Nth-level positive pulse gate driving signal Nout[N] to remain consistent and cannot be changed, so that if the width of the positive pulses of the Nth-level positive pulse gate driving signal Nout[N] is greater than 2H, the number of negative pulses of the Nth-level negative pulse gate driving signal Pout[N] in one frame will increase.

[0046] Therefore, this will limit Figure 1 The pixel circuit shown is in accordance with Figure 2 The timing sequence shown is followed by operation. Specifically, Figure 1 The pixel circuit shown may include at least one of the following: a write transistor T2P, a drive transistor T1P, a first light-emitting control transistor T5P, a second light-emitting control transistor T6P, a first initialization transistor T4P, a second initialization transistor T7P, a third initialization transistor T8P, a compensation transistor T3P, a light-emitting device D1, a storage capacitor Cst, and a bootstrap capacitor CbOst.

[0047] The first power line is electrically connected to the first terminal of the first light-emitting control transistor T5P and one end of the storage capacitor Cst. The second terminal of the first light-emitting control transistor T5P is electrically connected to the first terminal of the driving transistor T1P and the first terminal of the writing transistor T2P. The second terminal of the driving transistor T1P is electrically connected to the first terminal of the compensation transistor T3P and the first terminal of the second light-emitting control transistor T6P. The second terminal of the second light-emitting control transistor T6P is electrically connected to the first terminal of the second initialization transistor T7P and the anode of the light-emitting device D1. The cathode of the light-emitting device D1 is electrically connected to the second power line.

[0048] The light emitting control line is electrically connected with the gate of the first light emitting control transistor T5P and the gate of the second light emitting control transistor T6P.

[0049] The second electrode of the write transistor T2P is electrically connected with the data line, and the gate of the write transistor T2P is electrically connected with the first scan line and one end of the bootstrap capacitor CbOst. The second electrode of the second initialization transistor T7P is electrically connected with the second initialization line, and the gate of the second initialization transistor T7P is electrically connected with the second scan line.

[0050] The second electrode of the compensation transistor T3P is electrically connected with the gate of the driving transistor T1P, and the gate of the compensation transistor T3P is electrically connected with the third scan line.

[0051] The gate of the driving transistor T1P is electrically connected with the other end of the storage capacitor Cst, the other end of the bootstrap capacitor CbOst and the first electrode of the first initialization transistor T4P.

[0052] The second electrode of the first initialization transistor T4P is electrically connected with the first initialization line, and the gate of the first initialization transistor T4P is electrically connected with the fourth scan line.

[0053] The first electrode of the third initialization transistor T8P is electrically connected with the first electrode of the driving transistor T1P, the second electrode of the third initialization transistor T8P is electrically connected with the third initialization line, and the gate of the third initialization transistor T8P shares the second scan line with the gate of the second initialization transistor T7P.

[0054] It should be noted that the second initialization line can also be replaced by the first initialization line, so as to reduce the required wire of the pixel circuit, which is conducive to increasing the density of the pixel circuit in the display panel.

[0055] In the present application, the first electrode can be one of the source electrode or the drain electrode, and the second electrode can be the other one of the source electrode or the drain electrode. For example, when the first electrode is the source electrode, the second electrode is the drain electrode; or when the first electrode is the drain electrode, the second electrode is the source electrode.

[0056] The first power line is used for transmitting a power positive signal VDD, the second power line is used for transmitting a power negative signal VSS, the potential of the power positive signal VDD is higher than the potential of the power negative signal VSS. The data line is used for transmitting a data signal Data. The light-emitting control line is used for transmitting a light-emitting control signal EM. The first initialization line is used for transmitting a first initialization signal Vi1. The second initialization line is used for transmitting a second initialization signal. The third initialization line is used for transmitting a third initialization signal Vi3. The first scan line is used for transmitting a gate driving signal Pout[N]. The second scan line is used for transmitting a gate driving signal Pscan2. The third scan line is used for transmitting a gate driving signal Nout[N]. The fourth scan line is used for transmitting a gate driving signal Nout[N-1].

[0057] The gate driving signal Pout[N], the gate driving signal Nout[N-1] and the gate driving signal Nout[N] can be provided by the gate driving circuit in the application with the application number 202310191137.9. The gate driving signal Pout[N] is derived from the Nth negative pulse gate driving signal Pout[N], the gate driving signal Nout[N] is derived from the Nth positive pulse gate driving signal Nout[N], and the gate driving signal Nout[N-1] is derived from the (N-1)th positive pulse gate driving signal Nout[N-1].

[0058] As can be seen from the above, in the application with the application number 202310191137.9, the principle that the Nth negative pulse gate driving signal Pout[N] has one negative pulse in a frame is formed by filtering out the first pulse of the starting control signal STV or the (N-Y)th positive pulse gate driving signal Nout[N-Y] through the second pulse of the reset signal RST. Therefore, the width of the two positive pulses of the starting control signal STV or the (N-Y)th positive pulse gate driving signal Nout[N-Y] must be equal.

[0059] In the pixel circuit shown in Figure 1 In order to realize that the compensation transistor T3P is turned on synchronously with the first initialization transistor T4P, the pulse of the gate driving signal Nout[N-1] needs to partially overlap with the pulse of the gate driving signal Nout[N], which is also the reason why Figure 1 The first initialization transistor T4P in the pixel circuit shown in

[0060] In addition, in order to complete the third initialization signal Vi3, the third initialization transistor T8P and the compensation transistor T3P need to be turned on synchronously, which requires the pulse of the gate driving signal Pscan2 to partially overlap with the pulse of the gate driving signal Nout[N]. Therefore, the pulse width of the gate driving signal Pscan2 can only be 1H, which requires the adjustment of the pulse width of the gate driving signal Pscan2.

[0061] In order to complete the third initialization signal Vi3, the third initialization transistor T8P and the compensation transistor T3P need to be turned on synchronously, which requires the pulse of the gate driving signal Pscan2 to partially overlap with the pulse of the gate driving signal Nout[N]. Therefore, the pulse width of the gate driving signal Pscan2 can only be 1H, which requires the adjustment of the pulse width of the gate driving signal Pscan2. Figure 1 The pixel circuit shown in FIG. 1 can continue to use the gate driving signal Pscan2 with a pulse width of only 1H, which requires the adjustment of the pulse width of the gate driving signal Pscan2. Figure 2 The driving timing of the pixel circuit shown in FIG. 1 also requires improvements to the gate driving circuit in the application with the application number 202310191137.9.

[0062] In this context, in order to alleviate the technical problem that the pulse of the gate driving signal is difficult to meet the needs in terms of time and width, the embodiment provides a gate driving circuit, please refer to Figures 3 to 30 As shown in FIG. 2, the gate driving circuit includes a plurality of cascaded shift registers, and the Nth shift register includes at least one of a stage transmission signal selection module 10, a pull-up control module 20, a first filter module 30, a second filter module 80, and a first output module 46. Figure 3 Figure 20 The stage transmission signal selection module 10 is electrically connected between a first node O and a first wiring, and Y is an integer greater than or equal to 1.

[0063] The pull-up control module 20 controls the potential of a second node K according to the potential of the first node O and the potential of a first clock signal.

[0064] The first filter module 30 is electrically connected between the second node K and a third node Q, and the control end of the first filter module 30 is connected to a reset signal RST.

[0065] The second filter module 80 is electrically connected between the first filter module 30 and the third node Q, and the control end of the second filter module 80 is connected to a filter control signal RST2 having a plurality of pulses in a frame.

[0066] The first output module 46 outputs a first gate driving signal according to the potential of the third node Q and the potential of a fourth node P.

[0067] The first output module 46 outputs a first gate driving signal according to the potential of the third node Q and the potential of a fourth node P.

[0068] ​It is understood that the gate driving circuit provided in this embodiment filters out the first part of the second pulse that appears later in a frame by the first filtering module 30, and filters out the second part of the first pulse that appears earlier and the second pulse that appears later in a frame by the second filtering module 80. This can retain the first part of the first pulse with a fixed width, and then control the first output module 46 to output a gate driving signal with a pulse of that fixed width at the corresponding time. After this improvement, it can be adapted to the driving requirements of the back end.

[0069] In one embodiment, the Nth-stage shift register further includes a first inverting module 50 and a second output module 70. The first inverting module 50 is electrically connected between the second node K and the fourth node P. The second output module 70 outputs a second gate drive signal according to the potential of the second node K.

[0070] Understandably, after Figure 3 , Figure 20 right Figure 1 After the improvement shown, since the first filtering module 30 can filter out the first part of the second pulse that appears later in a frame for the second node K, and the second filtering module 80 can filter out the last part of the first pulse that appears earlier and the last part of the second pulse that appears later in a frame for the second node K, the first part of the first pulse with a fixed width can be retained. Then, the first output module 46 is controlled to output a gate drive signal with a pulse of this fixed width at the corresponding time. The pulse width of the Nth positive pulse gate drive signal Nout[N] provided by the second output module 70 will not affect the pulse width of the Nth negative pulse gate drive signal Pout[N]. Therefore, the two pulse widths of the Nth positive pulse gate drive signal Nout[N] in a frame can not only be modulated to a width greater than 2H, but also the two pulse widths can be modulated separately without needing to be equal. This provides support for the improvement of the driving timing of the pixel circuit.

[0071] In one embodiment, the frequency of the second gate drive signal is the same as the frequency of the filter control signal RST2, and the phase of the second gate drive signal is different from the phase of the filter control signal RST2.

[0072] It should be noted that in this embodiment, the shifted Nth-stage positive pulse gate drive signal Nout[N], for example, the (N-2)th-stage positive pulse gate drive signal Nout[N-2], can be used as the filter control signal RST2. This not only obtains the desired first and second gate drive signals but also avoids introducing an external control signal as the filter control signal RST2. In other embodiments, an external control signal can also be used as the filter control signal RST2. In other embodiments, the potential of the fourth node P in the (N-2)th-stage shift register can also be used as the filter control signal RST2.

[0073] In other embodiments, other positive pulse gate drive signals may be selected according to the needs of the first gate drive signal and the second gate drive signal.

[0074] In one embodiment, the frequency of the second gate drive signal is the same as the frequency of the reset signal RST, and the phase of the second gate drive signal is different from the phase of the reset signal RST.

[0075] It should be noted that in this embodiment, the shifted Nth-stage positive pulse gate drive signal Nout[N], for example, the NXth-stage positive pulse gate drive signal Nout[NX], can be used as the reset signal RST. This not only obtains the desired first and second gate drive signals but also avoids introducing an external control signal as the reset signal RST. In other embodiments, an external control signal can also be used as the reset signal RST. In other embodiments, the potential of the fourth node P in the NXth-stage shift register can also be used as the reset signal RST. Here, X is an integer greater than or equal to 2.

[0076] In one embodiment, such as Figure 3 , Figure 20 As shown, the first filtering module 30 includes a first filtering transistor T11 and a first capacitor C2. One of the sources or drains of the first filtering transistor T11 is electrically connected to the second node K, and the other of the sources or drains of the first filtering transistor T11 is electrically connected to the third node Q. The gate of the first filtering transistor T11 is connected to a reset signal RST. One end of the first capacitor C2 is electrically connected to the gate of the first filtering transistor T11, and the other end of the first capacitor C2 is electrically connected to the other of the sources or drains of the first filtering transistor T11.

[0077] It should be noted that, such as Figure 30 As shown, the first filtering module 30 is used to filter out the first part of the second pulse that appears later in a frame at the second node K.

[0078] In one embodiment, such as Figure 3、 Figure 20 As shown in FIG. 8, the second filter module 80 includes a second filter transistor T8, one of the source or the drain of the second filter transistor T8 is electrically connected with the first filter module 30, the other of the source or the drain of the second filter transistor T8 is electrically connected with the third node Q, and the gate of the second filter transistor T8 is connected with the filter control signal RST2.

[0079] It should be noted that, as shown in FIG. 8, the second filter module 80 is used to filter out the latter part of the first pulse and the latter part of the second pulse of the second node K which appears earlier in a frame. Figure 30

[0080] Therefore, the first filter module 30 and the second filter module 80 are used to filter out the second pulse and retain the fixed width of the former part of the first pulse.

[0081] In one embodiment, as shown in FIG. 9, the Nth stage shift register further includes an isolation module 75 which is connected in series between the second node K and the input end of the second output module 70, and the control end of the isolation module 75 is connected with the first clock signal. Figure 20 It should be noted that the isolation module 75 is used to reduce the coupling of the pulse amplitude of the Nth stage negative pulse gate drive signal Pout[N] to the pulse amplitude of the Nth stage positive pulse gate drive signal Nout[N], so as to stabilize the high potential of the Nth stage positive pulse gate drive signal Nout[N].

[0082] In one embodiment, as shown in FIG. 9, the isolation module 75 includes an isolation transistor T14, one of the source or the drain of the isolation transistor T14 is electrically connected with the second node K, the other of the source or the drain of the isolation transistor T14 is electrically connected with the input end of the second output module 70, the gate of the isolation transistor T14 is connected with the first clock signal, and the isolation transistor T14 is a P-channel thin film transistor.

[0083] Figure 20 It should be noted that the isolation transistor T14 can reduce the coupling of the pulse amplitude of the Nth stage negative pulse gate drive signal Pout[N] to the pulse amplitude of the Nth stage positive pulse gate drive signal Nout[N], so as to stabilize the high potential of the Nth stage positive pulse gate drive signal Nout[N].

[0084] In other embodiments, the isolation module 75 can further include a transistor which is connected in series between the gate of the isolation transistor T14 and the node N.

[0085] In other embodiments, the isolation module 75 can further include a transistor which is connected in series between the gate of the isolation transistor T14 and the node N.

[0086] ​​The input end of the stage transmission signal selection module 10 is electrically connected with a start control line or an N-Yth positive pulse scanning line, wherein N is an integer greater than or equal to 1, and Y is an integer greater than or equal to 1.

[0087] The input end of the pull-up control module 20 is electrically connected with the output end of the stage transmission signal selection module 10, and the control end of the pull-up control module 20 is electrically connected with a first clock line.

[0088] The input end of the first filter module 30 is electrically connected with the output end of the pull-up control module 20, and the control end of the first filter module 30 is electrically connected with a reset line.

[0089] The input end of the second output module 70 is electrically connected with the input end of the pull-up control module 20, and the output end of the second output module 70 is electrically connected with an Nth positive pulse scanning line, wherein the number of positive pulses output by the Nth positive pulse scanning line in a frame is greater than the number of negative pulses output by an Nth negative pulse scanning line in a frame.

[0090] In one of the embodiments, the first output module 46 comprises a pull-up module 40 and a pull-down module 60. The control end of the pull-up module 40 is electrically connected with the output end of the first filter module 30, the input end of the pull-up module 40 is electrically connected with a second clock line, and the output end of the pull-up module 40 is electrically connected with the Nth negative pulse scanning line. The input end of the first inverting module 50 is electrically connected with the output end of the pull-up control module 20.

[0091] The control end of the pull-down module 60 is electrically connected with the output end of the first inverting module 50, the input end of the pull-down module 60 is electrically connected with a high potential line, and the output end of the pull-down module 60 is electrically connected with the Nth negative pulse scanning line.

[0092] It should be noted that the first wiring can be the start control line or the N-Yth positive pulse scanning line. When N-Y is less than or equal to 0, the first wiring is the start control line. The Nth positive pulse scanning line, i.e., the second gate control line, is used to transmit the Nth positive pulse gate drive signal Nout[N], i.e., the second gate drive signal. The Nth negative pulse scanning line, i.e., the first gate control line, is used to transmit the Nth negative pulse gate drive signal Pout[N], i.e., the first gate drive signal.

[0093] In one of the embodiments, the ratio of the channel width of the first filter transistor T11 to the channel length of the first filter transistor T11 is greater than or equal to 0.5 and less than or equal to 1.5.

[0094] It should be noted that the embodiment is beneficial to guarantee the output stability of the Nth negative pulse gate drive signal Pout[N] and avoid the coupling pull-down phenomenon before the negative pulse arrives.

[0095] In one of the embodiments, the pull-up module 40 comprises a pull-up transistor T6 and a second capacitor C1, a gate of the pull-up transistor T6 is electrically connected with one of a source or a drain of the first filter transistor T11, one of a source or a drain of the pull-up transistor T6 is electrically connected with the second clock line, and the other of the source or the drain of the pull-up transistor T6 is electrically connected with the Nth negative pulse scan line; one end of the second capacitor C1 is electrically connected with the gate of the pull-up transistor T6, and the other end of the second capacitor C1 is electrically connected with the other of the source or the drain of the pull-up transistor T6; wherein a ratio of a capacity of the first capacitor C2 to a capacity of the second capacitor C1 is greater than or equal to 0.5.

[0096] It should be noted that the embodiment designs the ratio of the capacity of the first capacitor C2 to the capacity of the second capacitor C1, which is beneficial to further ensure the output stability of the Nth negative pulse gate drive signal Pout[N] and avoid the coupling pull-down phenomenon before the negative pulse arrives.

[0097] Specifically, the capacity of the first capacitor C2 can be greater than or equal to 50 fF. The capacity of the second capacitor C1 can be greater than or equal to 100 fF.

[0098] Wherein, a ratio of a channel width of the pull-up transistor T6 to a channel length of the pull-up transistor T6 is greater than 30:1, which is beneficial to further ensure the output stability of the Nth negative pulse gate drive signal Pout[N]. The pull-up transistor T6 can be a P-channel thin film transistor.

[0099] In one of the embodiments, the stage transmission signal selection module 10 comprises a transistor T13 and a transistor T12, one of a source or a drain of the transistor T13 is electrically connected with the low potential line, the other of the source or the drain of the transistor T13 is electrically connected with an input end of the pull-up control module 20, a first gate of the transistor T13 is electrically connected with the start control line or the N-Yth positive pulse scan line, the first gate of the transistor T13 is electrically connected with a second gate of the transistor T13, and the transistor T13 is an N-channel thin film transistor; one of a source or a drain of the transistor T12 is electrically connected with the high potential line, the other of the source or the drain of the transistor T12 is electrically connected with the other of the source or the drain of the transistor T13, a gate of the transistor T12 is electrically connected with the first gate of the transistor T13, and the transistor T12 is a P-channel thin film transistor.

[0100] It needs to be explained that the stage transfer signal selection module 10 in the embodiment not only has the reverse effect in the objective, that is, the potential of the input signal and the output signal is opposite at the same time, but also plays a role of making the Nth positive pulse gate drive signal Nout[N] as the stage transfer signal between the shift registers, otherwise the stage transfer between the shift registers cannot be realized, which will cause the gate drive circuit to be unable to normally provide the corresponding gate drive signal.

[0101] The ratio of the channel width of the transistor T13 to the channel length of the transistor T13 is greater than 2:1. The ratio of the channel width of the transistor T12 to the channel length of the transistor T12 ranges from 0.5:1 to 3:1.

[0102] The high potential line is used for transmitting a high potential signal VGH, and the high potential signal VGH can control the N-channel thin film transistor to be turned on or control the P-channel thin film transistor to be turned off. The low potential line is used for transmitting a low potential signal VGL, and the low potential signal VGL can control the P-channel thin film transistor to be turned on or control the N-channel thin film transistor to be turned off.

[0103] In one of the embodiments, the pull-up control module 20 includes a pull-up control transistor T2, one of the source or the drain of the pull-up control transistor T2 is electrically connected with the output end of the stage transfer signal selection module 10, the other of the source or the drain of the pull-up control transistor T2 is electrically connected with the input end of the first filter module 30, and the gate of the pull-up control transistor T2 is electrically connected with the first clock line.

[0104] It needs to be explained that the pull-up control transistor T2 can be a P-channel thin film transistor. The ratio of the channel width of the pull-up control transistor T2 to the channel length of the pull-up control transistor T2 ranges from 0.5:1 to 3:1.

[0105] In one of the embodiments, the first inverting module 50 includes a transistor T3 and a transistor T1, one of the source or the drain of the transistor T3 is electrically connected with the high potential line, the other of the source or the drain of the transistor T3 is electrically connected with one of the source or the drain of the transistor T1 and the control end of the pull-down module 60, the other of the source or the drain of the transistor T1 is electrically connected with the low potential line, and the output end of the pull-up control module 20 is electrically connected with the gate of the transistor T3, the first gate of the transistor T1, and the second gate of the transistor T1.

[0106] It needs to be explained that the transistor T3 is a P-channel thin film transistor. The transistor T1 is a double-gate N-channel thin film transistor. In this way, the dynamic performance of the transistor T3 and the transistor T1 can be improved, and the dynamic performance of the first inverting module 50 can be improved.

[0107] The ratio of the channel width of the transistor T3 to the channel length of the transistor T3 is in the range of 0.5:1 to 3:1. The ratio of the channel width of the transistor T1 to the channel length of the transistor T1 is greater than or equal to 2:1.

[0108] In one of the embodiments, the pull-down module 60 includes a pull-down transistor T7, one of the source or the drain of the pull-down transistor T7 is electrically connected with the high potential line, the other of the source or the drain of the pull-down transistor T7 is electrically connected with the Nth negative pulse scanning line, and the gate of the pull-down transistor T7 is electrically connected with the output of the first inverting module 50, i.e. the fourth node P.

[0109] It needs to be explained that the pull-down transistor T7 can be a P-channel thin film transistor. Under the joint action of the pull-down module 60 and the pull-up module 40, the required Nth negative pulse gate driving signal Pout[N] can be modulated.

[0110] The ratio of the channel width of the pull-down transistor T7 to the channel length of the pull-down transistor T7 is greater than or equal to 30:1.

[0111] In one of the embodiments, the second output module 70 includes a transistor T9 and a transistor T10, one of the source or the drain of the transistor T9 is electrically connected with the high potential line, the other of the source or the drain of the transistor T9 is electrically connected with one of the source or the drain of the transistor T10 and the Nth positive pulse scanning line, the other of the source or the drain of the transistor T10 is electrically connected with the low potential line, and the output of the pull-up control module 20 is electrically connected with the gate of the transistor T9, the first gate of the transistor T10 and the second gate of the transistor T10.

[0112] It needs to be explained that the transistor T9 is a P-channel thin film transistor. The transistor T10 is a double-gate N-channel thin film transistor. In this way, the dynamic performance of the transistor T9 and the transistor T10 can be improved, and the dynamic performance of the second output module 70 can be improved.

[0113] The ratio of the channel width of the transistor T9 to the channel length of the transistor T9 is greater than or equal to 30:1. The ratio of the channel width of the transistor T10 to the channel length of the transistor T10 is greater than or equal to 30:1.

[0114] In one of the embodiments, the Nth stage shift register further comprises a feedback module 90, the feedback module 90 comprising a transistor T4 and a transistor T5, one of the source or the drain of the transistor T4 being electrically connected with the output terminal of the pull-up control module 20, the gate of the transistor T4 being electrically connected with the second clock line, the other of the source or the drain of the transistor T4 being electrically connected with one of the source or the drain of the transistor T5, the other of the source or the drain of the transistor T5 being electrically connected with the high potential line, the gate of the transistor T5 being electrically connected with the output terminal of the first inverting module 50.

[0115] The ratio of the channel width of the transistor T4 to the channel length of the transistor T4 ranges from 0.5:1 to 3:1. The ratio of the channel width of the transistor T5 to the channel length of the transistor T5 ranges from 0.5:1 to 3:1.

[0116] It is to be noted that the feedback module 90 can maintain the second node K at the high potential according to the potential of the fourth node P and the potential maintained by the second clock line, that is, in the case that the fourth node P is at the low potential and the second clock signal CK is at the low potential, the high potential line can control the potential of the second node K to the potential of the high potential signal VGH.

[0117] It is to be noted that the Nth stage positive pulse scan line is used for transmitting the Nth stage positive pulse gate driving signal Nout[N]. The Nth stage negative pulse scan line is used for transmitting the Nth stage negative pulse gate driving signal Pout[N]. The first clock line is used for transmitting the first clock signal XCK. The second clock line is used for transmitting the second clock signal CK. The start control line is used for transmitting the start control signal STV. The Nth-Y stage positive pulse scan line is used for transmitting the Nth-Y stage positive pulse gate driving signal Nout[N-Y]. The Nth-X stage positive pulse scan line is used for transmitting the Nth-X stage positive pulse gate driving signal Nout[N-X]. The reset line is used for transmitting the reset signal RST.

[0118] Figure 3 、 Figure 20 The other parts of the gate driving circuit shown in FIG. 1 can refer to the detailed description of the gate driving circuit shown in FIG. 2, which will not be repeated here. Figure 1 The detailed description of the gate driving circuit shown in FIG. 2 will not be repeated here.

[0119] Figure 3 The working process of the shift register shown in FIG. 3 in a frame can include the following stages as shown in FIG. 4: Figure 4

[0120] The first stage S1: as shown in FIG. 5: Figure 4 、 Figure 5 ​As shown in the figure, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th positive pulse gate driving signal Nout[N-2] are all at low potentials, the first clock signal XCK is at a high potential, the first node O, the second node K, the node W, and the third node Q are all at high potentials, the fourth node P is at a low potential, the Nth positive pulse gate driving signal Nout[N] is at a low potential, and the Nth negative pulse gate driving signal Pout[N] is at a high potential.

[0121] The second stage S2 is as shown in the figure. Figure 4 , Figure 6 As shown in the figure, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th positive pulse gate driving signal Nout[N-2] are all at low potentials, the second clock signal CK is at a high potential, the first node O, the second node K, the node W, and the third node Q are all at high potentials, the fourth node P is at a low potential, the Nth positive pulse gate driving signal Nout[N] is at a low potential, and the Nth negative pulse gate driving signal Pout[N] is at a high potential.

[0122] The third stage S3 is as shown in the figure. Figure 4 , Figure 7 As shown in the figure, the start control signal STV, the second clock signal CK, and the N-2th positive pulse gate driving signal Nout[N-2] are all at low potentials, the reset signal RST, the first clock signal XCK are at high potentials, the first node O, the second node K, the node W, and the third node Q are all at high potentials, the fourth node P is at a low potential, the Nth positive pulse gate driving signal Nout[N] is at a low potential, and the Nth negative pulse gate driving signal Pout[N] is at a high potential.

[0123] The fourth stage S4 is as shown in the figure. Figure 4 , Figure 8 As shown in the figure, the start control signal STV, the first clock signal XCK, and the N-2th positive pulse gate driving signal Nout[N-2] are all at low potentials, the reset signal RST, the second clock signal CK are at high potentials, the first node O, the second node K, the node W, and the third node Q are all at high potentials, the fourth node P is at a low potential, the Nth positive pulse gate driving signal Nout[N] is at a low potential, and the Nth negative pulse gate driving signal Pout[N] is at a high potential.

[0124] The fifth stage S5 is as shown in the figure. Figure 4 , Figure 9As shown, the second clock signal CK is at a low potential, the start control signal STV, the reset signal RST, the first clock signal XCK, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at a high potential, the second node K, node W, and the third node Q are at a high potential, the first node O and the fourth node P are at a low potential, the Nth stage positive pulse gate drive signal Nout[N] is at a low potential, and the Nth stage negative pulse gate drive signal Pout[N] is at a high potential.

[0125] Phase 6 (S6): (e.g.) Figure 4 , Figure 10 As shown, the first clock signal XCK is at a low potential, the start control signal STV, the reset signal RST, the second clock signal CK, and the N-2th positive pulse gate drive signal Nout[N-2] are at a high potential, the node W, the fourth node P, and the third node Q are all at a high potential, the second node K and the first node O are at a low potential, the Nth positive pulse gate drive signal Nout[N] is at a high potential, and the Nth negative pulse gate drive signal Pout[N] is at a high potential.

[0126] Stage 7 (S7): Figure 4 , Figure 11 As shown, the reset signal RST and the second clock signal CK are at low potentials, the start control signal STV, the first clock signal XCK, and the N-2th positive pulse gate drive signal Nout[N-2] are at high potentials, the fourth node P and the third node Q are both at high potentials, the node W, the second node K, and the first node O are at low potentials, the Nth positive pulse gate drive signal Nout[N] is at high potentials, and the Nth negative pulse gate drive signal Pout[N] is at high potentials.

[0127] Stage 8 S8: As Figure 4 , Figure 12 As shown, the reset signal RST and the first clock signal XCK are at low potentials, the start control signal STV, the second clock signal CK, and the N-2th positive pulse gate drive signal Nout[N-2] are at high potentials, the fourth node P and the third node Q are both at high potentials, the node W, the second node K, and the first node O are at low potentials, the Nth positive pulse gate drive signal Nout[N] is at high potentials, and the Nth negative pulse gate drive signal Pout[N] is at high potentials.

[0128] Stage 9 S9: As Figure 4 , Figure 13As shown in FIG. 10, the second clock signal CK and the N-2th positive pulse gate driving signal Nout[N-2] are at low potential, the reset signal RST, the start control signal STV and the first clock signal XCK are at high potential, the node W, the first node O, the fourth node P and the third node Q are all at high potential, the second node K is at low potential, the Nth positive pulse gate driving signal Nout[N] is at high potential, and the Nth negative pulse gate driving signal Pout[N] is at high potential.

[0129] The tenth stage S10: as shown in FIG. 9, the start control signal STV, the first clock signal XCK and the N-2th positive pulse gate driving signal Nout[N-2] are at low potential, the reset signal RST and the second clock signal CK are at high potential, the second node K, the node W, the first node O and the third node Q are all at high potential, the fourth node P is at low potential, the Nth positive pulse gate driving signal Nout[N] is at low potential, and the Nth negative pulse gate driving signal Pout[N] is at high potential. Figure 4 Figure 14 The eleventh stage S11: as shown in FIG. 10, the reset signal RST and the N-2th positive pulse gate driving signal Nout[N-2] are at low potential, the start control signal STV, the first clock signal XCK and the second clock signal CK are at high potential, the fourth node P and the third node Q are all at high potential, the second node K, the node W and the first node O are at low potential, the Nth positive pulse gate driving signal Nout[N] is at high potential, and the Nth negative pulse gate driving signal Pout[N] is at high potential.

[0130] The twelfth stage S12: the second clock signal CK, the start control signal STV, the reset signal RST and the N-2th positive pulse gate driving signal Nout[N-2] are at low potential, the first clock signal XCK is at high potential, the fourth node P and the first node O are all at high potential, the third node Q, the second node K and the node W are at low potential, the Nth positive pulse gate driving signal Nout[N] is at high potential, and the Nth negative pulse gate driving signal Pout[N] is at low potential. Figure 4 Figure 15 The thirteenth stage S13: as shown in FIG. 11, the second clock signal CK, the start control signal STV and the N-2th positive pulse gate driving signal Nout[N-2] are at low potential, the reset signal RST is at high potential, the fourth node P and the first node O are all at high potential, the third node Q, the second node K and the node W are at low potential, the Nth positive pulse gate driving signal Nout[N] is at high potential, and the Nth negative pulse gate driving signal Pout[N] is at low potential.

[0131] The thirteenth stage S13: as shown in FIG. 11, the second clock signal CK, the start control signal STV and the N-2th positive pulse gate driving signal Nout[N-2] are at low potential, the reset signal RST is at high potential, the fourth node P and the first node O are all at high potential, the third node Q, the second node K and the node W are at low potential, the Nth positive pulse gate driving signal Nout[N] is at high potential, and the Nth negative pulse gate driving signal Pout[N] is at low potential.

[0132] The thirteenth stage S13: as shown in FIG. 11, the second clock signal CK, the start control signal STV and the N-2th positive pulse gate driving signal Nout[N-2] are at low potential, the reset signal RST is at high potential, the fourth node P and the first node O are all at high potential, the third node Q, the second node K and the node W are at low potential, the Nth positive pulse gate driving signal Nout[N] is at high potential, and the Nth negative pulse gate driving signal Pout[N] is at low potential. Figure 4 Figure 17 ​​​As shown, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potentials, the second clock signal CK is at high potentials, the second node K, node W, the third node Q, and the first node O are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0133] Phase Fourteen S14: As Figure 4 , Figure 18 As shown, the second clock signal CK, the start control signal STV, the reset signal RST, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potentials, the first clock signal XCK is at high potentials, the second node K, node W, the third node Q, and the first node O are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0134] Phase 15 S15: As Figure 4 , Figure 19 As shown, the first clock signal XCK, the start control signal STV, the reset signal RST, and the N-2th stage positive pulse gate drive signal Nout[N-2] are at low potentials, the second clock signal CK is at high potentials, the second node K, node W, the third node Q, and the first node O are all at high potentials, the fourth node P is at low potentials, the Nth stage positive pulse gate drive signal Nout[N] is at low potentials, and the Nth stage negative pulse gate drive signal Pout[N] is at high potentials.

[0135] It should be noted that, Figures 5 to 19 The "cross" in the diagram indicates that the transistor it covers is in the off state, while the transistors not covered by the "cross" are in the on state. Figures 5 to 19 The dashed arrow in the diagram indicates the direction of the current.

[0136] Figure 20 The operation of the shift register shown in the diagram within a frame may include, for example: Figure 21 The following stages are shown:

[0137] Phase 1 S1: As Figure 21 , Figure 22 As shown, the start control signal STV and the second clock signal CK are both at a low level, the first clock signal XCK is at a high level, node N is at a high level, the fourth node P is at a low level, and the Nth stage positive pulse gate drive signal Nout[N] is at a low level.

[0138] Second stage S2: as shown in Figure 21 , Figure 23 , the start control signal STV, the first clock signal XCK are at low potential, the second clock signal CK is at high potential, the node N is at high potential, the fourth node P is at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at low potential.

[0139] Third stage S3: as shown in Figure 21 , Figure 24 , the second clock signal CK is at low potential, the start control signal STV, the first clock signal XCK are at high potential, the node N is at high potential, the fourth node P is at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at low potential.

[0140] Fourth stage S4: as shown in Figure 21 , Figure 25 , the first clock signal XCK is at low potential, the start control signal STV, the second clock signal CK are at high potential, the fourth node P is at high potential, the node N is at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at high potential.

[0141] Fifth stage S5: as shown in Figure 21 , Figure 26 , the second clock signal CK is at low potential, the start control signal STV, the first clock signal XCK are at high potential, the fourth node P is at high potential, the node N is at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at high potential.

[0142] Sixth stage S6: as shown in Figure 21 , Figure 27 , the first clock signal XCK is at low potential, the start control signal STV, the second clock signal CK are at high potential, the fourth node P is at high potential, the node N is at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at high potential.

[0143] Seventh stage S7: as shown in Figure 21 , Figure 28 , the start control signal STV, the second clock signal CK are at low potential, the first clock signal XCK is at high potential, the fourth node P is at high potential, the node N is at low potential, the Nth stage positive pulse gate drive signal Nout[N] is at high potential.

[0144] Eighth stage S8: as shown in Figure 21 , Figure 29As shown, the start control signal STV, the first clock signal XCK are at low level, the second clock signal CK is at high level, the node N is at high level, the fourth node P is at low level, and the Nth positive pulse gate drive signal Nout[N] is switched from high level to low level.

[0145] It should be noted that, Figures 22 to 29 The "cross" in the "cross" indicates that the transistor covered by it is in the off state, and the transistor not covered by the "cross" is in the on state. Figures 22 to 29 The dashed arrow in the dashed arrow indicates the direction of the current.

[0146] Based on the above, Figure 30 The generation process of the Nth negative pulse gate drive signal Pout[N] is shown. For the sake of clear description, the two from right to left in the same signal are called first pulse and second pulse in turn. The second node K transmits the first pulse and the second pulse in a frame. The high level of the first part of the two pulses of the N-2th positive pulse gate drive signal Nout[N-2] controls the second filter module 80 to filter out the latter part of the first pulse and the latter part of the second pulse output by the second node K. The high level of the latter part of the first pulse of the reset signal RST controls the first filter module 30 to filter out the former part of the second pulse output by the second node K. At this time, the width of the second pulse of the node W is also narrowed; the second pulse output by the second node K is completely filtered out, and only the former part of the first pulse output by the second node K forms a negative pulse at the third node Q, and the negative pulse of the third node Q opens the pull-up module 40, forming a negative pulse of the Nth negative pulse gate drive signal Pout[N] with a fixed width.

[0147] Figure 31 For Figure 3 Or Figure 20 The structure diagram of the cascade structure between different shift registers in the gate drive circuit is shown. From top to bottom, there are the first shift register, the second shift register, the third shift register, the Nth shift register, and the N+1th shift register, etc. Each shift register works according to the first clock signal XCK and the second clock signal CK.

[0148] The control end of the first filter module 30 and the control end of the second filter module 80 in the first-stage shift register are connected to a low potential signal VGL, and the input end (IN) of the first-stage shift register connected to the start control line is connected to a start control signal STV. The first-stage shift register outputs corresponding first-stage negative pulse gate drive signals Pout[1] and first-stage positive pulse gate drive signals Nout[1]. The first-stage negative pulse gate drive signals Pout[1] and the first-stage positive pulse gate drive signals Nout[1] are used to drive dummy pixels (Dummy) or be suspended.

[0149] The control end of the first filter module 30 and the control end of the second filter module 80 in the second-stage shift register are connected to a low potential signal VGL, and the start control line connected to the second-stage shift register is connected to a cascade signal, that is, the first-stage positive pulse gate drive signals Nout[1]. The second-stage shift register outputs corresponding second-stage negative pulse gate drive signals Pout[2] and second-stage positive pulse gate drive signals Nout[2]. The second-stage negative pulse gate drive signals Pout[2] and the second-stage positive pulse gate drive signals Nout[2] are used to drive dummy pixels (Dummy) or be suspended.

[0150] The control end of the first filter module 30 and the control end of the second filter module 80 in the third-stage shift register are connected to a low potential signal VGL, and the start control line connected to the third-stage shift register is connected to a cascade signal, that is, the second-stage positive pulse gate drive signals Nout[2]. The third-stage shift register outputs corresponding third-stage negative pulse gate drive signals Pout[3] and third-stage positive pulse gate drive signals Nout[3]. The third-stage negative pulse gate drive signals Pout[3] and the third-stage positive pulse gate drive signals Nout[3] are used to drive dummy pixels (Dummy) or be suspended.

[0151] Other can be analogized in turn, until the control end of the first filter module 30 and the control end of the second filter module 80 in the Nth-stage shift register are connected to the Nth-X-stage positive pulse gate drive signals Nout[N-X] and the Nth-2-stage positive pulse gate drive signals Nout[N-2] in turn respectively, and the start control line connected to the Nth-stage shift register is connected to a cascade signal, that is, the Nth-1-stage positive pulse gate drive signals Nout[N-1]. The Nth-stage shift register outputs corresponding Nth-stage negative pulse gate drive signals Pout[N] and Nth-stage positive pulse gate drive signals Nout[N]. The Nth-stage negative pulse gate drive signals Pout[N] and the Nth-stage positive pulse gate drive signals Nout[N] are used to drive the first row of pixel circuits (Pixel).

[0152] The control end of the first filter module 30 and the control end of the second filter module 80 in the N+1th shift register are sequentially connected to the N-X+1th positive pulse gate driving signal Nout[N-X+1] and the N-1th positive pulse gate driving signal Nout[N-1] respectively, and the start control line connected with the N+1th shift register is connected with the cascade signal, i.e. the Nth positive pulse gate driving signal Nout[N]. The N+1th shift register outputs the corresponding N+1th negative pulse gate driving signal Pout[N+1] and the N+1th positive pulse gate driving signal Nout[N+1]. The N+1th negative pulse gate driving signal Pout[N+1] and the N+1th positive pulse gate driving signal Nout[N+1] are used to drive the second row of pixel circuits (Pixel).

[0153] The subsequent shift registers can be sequentially deduced. It needs to be pointed out that since the output end of some shift registers is connected with virtual pixels or is suspended, the output end of the Nth shift register is not connected with the Nth row of pixel circuits, but the number of rows of pixel circuits connected needs to be determined according to the number of shift registers connected with virtual pixels or suspended.

[0154] Figure 32 The display panel shown includes pixel circuits (Pixel) arranged in an array in the display area, a first gate driving circuit 151 providing a light emitting control signal EM, a fourth gate driving circuit 154 providing a gate driving signal Pscan2, a second gate driving circuit 152 providing an Nth negative pulse gate driving signal Pout[N] and a gate driving signal Nscan, and a third gate driving circuit 153 providing an Nth negative pulse gate driving signal Pout[N] and a gate driving signal Nscan.

[0155] The first gate driving circuit 151 can be located on the left side of the display area. The output end of each shift register in the first gate driving circuit 151 provides a light emitting control signal EM to two adjacent rows of pixel circuits through a corresponding light emitting control line, which belongs to single side driving.

[0156] The fourth gate driving circuit 154 can be located on the right side of the display area. The output end of each shift register in the fourth gate driving circuit 154 provides a gate driving signal Pscan2 to one row of pixel circuits through a corresponding gate driving line, which belongs to single side driving.

[0157] The second gate driving circuit 152 is located between the first gate driving circuit 151 and the display area. The third gate driving circuit 153 is located between the fourth gate driving circuit 154 and the display area. A scan line transmitting the Nth negative pulse gate driving signal Pout[N] is electrically connected to the output of a shift register in the second gate driving circuit 152, the output of a shift register in the third gate driving circuit 153, and the pixel circuit of one row. A gate driving line transmitting the gate driving signal Nscan is electrically connected to the output of a shift register in the second gate driving circuit 152, the output of a shift register in the third gate driving circuit 153, and the pixel circuit of one row. This is a dual-side driving configuration.

[0158] Both the second gate drive circuit 152 and the third gate drive circuit 153 can be adopted. Figure 3 , Figure 20 The gate drive circuit is shown. The gate drive signal Nscan may include the Nth positive pulse gate drive signal Nout[N] and the (N-3)th positive pulse gate drive signal Nout[N-3].

[0159] because Figure 1 The pixel circuit shown has a necessary reason for connecting the gate of the first initialization transistor T4P to the (N-1)th stage positive pulse gate drive signal Nout[N-1]. Figure 33 In the pixel circuit shown, after the gate of the write transistor T2P is connected to the Nth level negative pulse gate drive signal Pout[N] and the gate of the compensation transistor T3P is connected to the Nth level positive pulse gate drive signal Nout[N], not only can the gate of the third initialization transistor T8P continue to use the existing gate drive signal Pscan2 (without needing to improve the fourth gate drive circuit 154), but the gate of the first initialization transistor T4P can also be replaced with the N-3 level positive pulse gate drive signal Nout[N-3].

[0160] After that, Figure 33 The pixel circuit shown can operate in one frame not only Figure 34 In addition to the existing stage P12, an additional stage P11 can be added. In this stage P11, the potentials of the three terminals (Q, A, B) of the driving transistor T1P can be reset by synchronously turning on the first initialization transistor T4P and the compensation transistor T3P, so as to reduce the drift of the threshold voltage of the driving transistor T1P and improve the flicker at different refresh frequencies.

[0161] In one embodiment, this embodiment provides a display panel that includes the gate driving circuit and pixel circuit described in at least one of the above embodiments.

[0162] It can be understood that, since the display panel provided by the embodiment includes the gate drive circuit in at least one of the above embodiments, the first filter module 30 can also filter out the front part of the second pulse of the second node K appearing later in a frame, the second filter module 80 filters out the rear part of the first pulse of the second node K appearing first in a frame and the rear part of the second pulse appearing later, and the front part of the fixed width in the first pulse can be reserved, and then the first output module 46 is controlled to output the gate drive signal with the pulse of the fixed width at the corresponding time. After the improvement, it can be suitable for the driving requirements of the back end.

[0163] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0164] The above describes in detail the gate drive circuit and the display panel provided by the embodiments of the present application. The principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core idea thereof. Those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit characterized by comprising: The gate drive circuit comprises a plurality of cascaded shift registers, an Nth shift register comprising: a stage transmission signal selection module electrically connected between the first node and the first wiring; a pull-up control module for controlling a potential of a second node according to a potential of the first node and a potential of a first clock signal; a first filter module electrically connected between the second node and a third node, a control terminal of the first filter module being connected to a reset signal; a second filter module electrically connected between the first filter module and the third node, a control terminal of the second filter module being connected to a filter control signal having a plurality of pulses in a frame; and a first output module for outputting a first gate drive signal according to a potential of the third node and a potential of a fourth node, the potential of the fourth node being opposite to the potential of the second node; a second output module for outputting a second gate drive signal according to the potential of the second node; wherein the second gate drive signal has a same frequency as the reset signal and a different phase from the reset signal.

2. The gate drive circuit according to claim 1, characterized by The Nth shift register further comprises a first inverting module electrically connected between the second node and the fourth node. wherein the second gate drive signal has a same frequency as the filter control signal and a different phase from the filter control signal.

3. The gate drive circuit according to claim 1, characterized by The first filter module comprises: a first filter transistor having one of a source or a drain electrically connected to the second node, the other of the source or the drain electrically connected to the third node, and a gate connected to the reset signal; a first capacitor having one end electrically connected to the gate of the first filter transistor and the other end electrically connected to the other of the source or the drain of the first filter transistor.

4. The gate drive circuit according to claim 1, characterized by The second filter module comprises a second filter transistor having one of a source or a drain electrically connected to the first filter module, the other of the source or the drain electrically connected to the third node, and a gate connected to the filter control signal.

5. The gate drive circuit according to claim 1, characterized by The Nth shift register further comprises an isolation module connected in series between the second node and an input terminal of the second output module, a control terminal of the isolation module being connected to the first clock signal.

6. The gate drive circuit according to claim 5, characterized by The isolation module comprises an isolation transistor having one of a source or a drain electrically connected to the second node, the other of the source or the drain electrically connected to the input terminal of the second output module, and a gate connected to the first clock signal, the isolation transistor being a P-channel thin film transistor.

7. The gate drive circuit according to claim 5, wherein The isolation module is configured to reduce coupling of pulse amplitudes of the first gate drive signal to pulse amplitudes of the second gate drive signal.

8. The gate drive circuit according to any one of claims 1 to 7, characterized by The second node transmits a first pulse and a second pulse in a frame in sequence; and the first filter module is configured to filter out a front part of the second pulse.

9. The gate drive circuit according to any one of claims 1 to 7, characterized by The second node transmits a first pulse and a second pulse in a frame in sequence; and the second filter module is configured to filter out a rear part of the first pulse and a rear part of the second pulse.

10. The gate drive circuit according to any one of claims 1 to 7, characterized by The second node transmits a first pulse and a second pulse in a frame in sequence; and the first filter module and the second filter module are configured to filter out the second pulse and keep a fixed-width front part of the first pulse.

11. A display panel, characterized by, The display panel comprises: a pixel circuit comprising a write transistor for controlling input of a data signal and a compensation transistor for controlling input of the data signal to a gate of a drive transistor; and The gate drive circuit according to any one of claims 1-10, wherein an output end of the first output module is electrically connected to a gate of the write transistor, and an output end of the second output module is electrically connected to a gate of the compensation transistor.

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