A display panel and a display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes: a first driving circuit; the first driving circuit includes a multi-stage shift register, and the shift register at least includes a first input unit, a second input unit and a first output unit; a control end of the first input unit is connected to a first trigger end, an input end thereof is connected to a first signal end, and an output end thereof is connected to a first node; a control end of the second input unit is connected to a second trigger end, an input end thereof is connected to a second signal end, and an output end thereof is connected to the first node; a control end of the first output unit is connected to the first node, an input end thereof is connected to a third signal end, and an output end thereof is connected to a shift output end; the first electrical signal is a first clock signal, and / or, the second electrical signal is a second clock signal. In the present invention, at least one of the multiple clock signal lines included in the first driving circuit itself can be reused to provide a clock signal for the first signal end or the second signal end, which is beneficial to realizing a narrow border.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] In a display panel, a driving circuit disposed in a non-display area is an indispensable circuit structure for implementing functions such as display and touch control of the display panel.

[0003] The driving circuit is usually composed of cascaded multi-stage shift registers, and a driving chip provides driving signals to each stage of shift registers in the driving circuit through signal lines so that the driving circuit operates normally.

[0004] However, in the existing display panel, the number of signal lines required for the driving circuit is large, which is not conducive to the realization of a narrow bezel. Summary of the Invention

[0005] The present invention provides a display panel and a display device to achieve a narrow bezel.

[0006] According to one aspect of the present invention, there is provided a display panel, including: a first driving circuit; the first driving circuit includes multi-stage shift registers, and the shift register includes at least a first input unit, a second input unit, and a first output unit;

[0007] The control end of the first input unit is connected to a first trigger end, the input end of the first input unit is connected to a first signal end, and the output end of the first input unit is connected to a first node, and is configured to respond to the control of the first trigger end and adjust the signal of the first node according to a first electrical signal provided by the first signal end;

[0008] The control end of the second input unit is connected to a second trigger end, the input end of the second input unit is connected to a second signal end, and the output end of the second input unit is connected to the first node, and is configured to respond to the control of the second trigger end and adjust the signal of the first node according to a second electrical signal provided by the second signal end;

[0009] The control end of the first output unit is connected to the first node, the input end of the first output unit is connected to a third signal end, and the output end of the first output unit is connected to a shift output end, and is configured to respond to the control of the first node and adjust the signal of the shift output end according to a third clock signal provided by the third signal end;

[0010] The first electrical signal is a first clock signal, and / or the second electrical signal is a second clock signal.

[0011] According to another aspect of the present invention, there is provided a display device, including: the display panel as described above.

[0012] In the present invention, a first signal terminal of a first input unit of a shift register provides a first electrical signal, and a second signal terminal of a second input unit of the shift register provides a second electrical signal. At least one of the first electrical signal and the second electrical signal is a clock signal. Then, at least one of the multiple clock signal lines in the first driving circuit itself can be multiplexed to provide a clock signal to the first signal terminal or the second signal terminal. Therefore, the number of signal lines in the first driving circuit can be reduced, which is beneficial for the display panel to achieve a narrow border and a full screen. In addition, both the first clock signal and the second clock signal alternate between high and low levels. In this way, during the scanning process of the shift register, the duration of the transistor in the input unit being in the negative bias state can be reduced, and correspondingly, the degree of threshold voltage shift (Vth shift) of the transistor in the input unit can be weakened, which is beneficial for improving the working stability and reliability of the shift register. Moreover, the leakage duration of the high level of the first clock signal or the high level of the second clock signal leaking to the first node can also be halved, thereby being able to improve the problem that the shift register is prone to failure during high-temperature operation and extend the service life of the shift register.

[0013] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0015] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0016] Figure 2 is a schematic diagram of a shift register provided by an embodiment of the present invention;

[0017] Figure 3 is a schematic diagram of a shift register provided by a comparative example;

[0018] Figure 4 is a schematic diagram of another shift register provided by an embodiment of the present invention;

[0019] Figure 5 is Figure 4 a timing schematic diagram of the forward scanning of the shown shift register;

[0020] Figure 6 is Figure 4Timing diagram of reverse scanning of the shown shift register;

[0021] Figure 7 Schematic diagram of a first driving circuit provided by an embodiment of the present invention;

[0022] Figure 8 is Figure 7 Schematic diagram of the clock signal of the shown first driving circuit in the forward scanning mode;

[0023] Figure 9 is Figure 7 Schematic diagram of the clock signal of the shown first driving circuit in the reverse scanning mode;

[0024] Figure 10 Schematic diagram of another first driving circuit provided by an embodiment of the present invention;

[0025] Figure 11 is Figure 10 Schematic diagram of the clock signal of the shown first driving circuit in the forward scanning mode;

[0026] Figure 12 is Figure 10 Schematic diagram of the clock signal of the shown first driving circuit in the reverse scanning mode;

[0027] Figure 13 Timing diagram of forward scanning of the shift register (ASG 7 (1)) in the first driving circuit based on the single-sided 6phase ASG structure;

[0028] Figure 14 Timing diagram of reverse scanning of the shift register (ASG 7 (1)) in the first driving circuit based on the single-sided 6phase ASG structure;

[0029] Figure 15 Schematic diagram of another shift register provided by an embodiment of the present invention;

[0030] Figure 16 is Figure 15 Timing diagram of forward scanning of the shown shift register;

[0031] Figure 17 is Figure 15 Timing diagram of reverse scanning of the shown shift register;

[0032] Figure 18 Schematic diagram of another shift register provided by an embodiment of the present invention;

[0033] Figure 19 is Figure 18Timing diagram of forward scanning of the shown shift register;

[0034] Figure 20 is Figure 18 Timing diagram of reverse scanning of the shown shift register;

[0035] Figure 21 It is a schematic diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0036] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0038] Figure 1 It is a schematic diagram of a display panel provided by an embodiment of the present invention, Figure 2 It is a schematic diagram of a shift register provided by an embodiment of the present invention. As Figure 1 and Figure 2As shown, the display panel includes: a first driving circuit 100; the first driving circuit 100 includes a multi-stage shift register 101, and the shift register 101 at least includes a first input unit 111, a second input unit 112, and a first output unit 113; the control terminal of the first input unit 111 is connected to a first trigger terminal IN1, the input terminal of the first input unit 111 is connected to a first signal terminal SG1, and the output terminal of the first input unit 111 is connected to a first node N1, configured to respond to the control of the first trigger terminal IN1 and adjust the signal of the first node N1 according to the first electrical signal provided by the first signal terminal SG1; the control terminal of the second input unit 112 is connected to a second trigger terminal IN2, the input terminal of the second input unit 112 is connected to a second signal terminal SG2, and the output terminal of the second input unit 112 is connected to the first node N1, configured to respond to the control of the second trigger terminal IN2 and adjust the signal of the first node N1 according to the second electrical signal provided by the second signal terminal SG2; the control terminal of the first output unit 113 is connected to the first node N1, the input terminal of the first output unit 113 is connected to a third signal terminal SG3, and the output terminal of the first output unit 113 is connected to a shift output terminal GOUT, configured to respond to the control of the first node N1 and adjust the signal of the shift output terminal GOUT according to the third clock signal CK3 provided by the third signal terminal SG3; the first electrical signal is a first clock signal CK1, and / or the second electrical signal is a second clock signal.

[0039] In this embodiment, the display panel includes a first area 201 and a second area 202. The first area 201 is used for display, and the first area 201 includes a plurality of sub-pixels 203. Optionally, the sub-pixels 203 in the first area 201 are arranged in an array. The plurality of sub-pixels 203 are arranged in a row of sub-pixels 203 along a first direction F1, and the plurality of sub-pixels 203 are arranged in a column of sub-pixels 203 along a second direction F2, and the first direction F1 and the second direction F2 intersect; however, the arrangement manner of the sub-pixels in the first area may also be other arrangement manners, not limited to the array arrangement manner. The second area 202 includes a circuit structure for driving the sub-pixels 203 in the first area 201 to display. Specifically, the second area 202 at least includes a first driving circuit 100, and the first driving circuit 100 is used to drive the sub-pixels 203 in the first area 201 to display. Optionally, the first area 201 of the display panel is the display area of the display panel, and the second area 202 is the non-display area of the display panel; the sub-pixels 203 in the display area may be organic light-emitting display units, or may be micro light-emitting diode display units, or may also be other types of sub-pixels, without specific limitation. For example, liquid crystal display units, etc.; the first driving circuit 100 in the non-display area is a gate driving circuit, used to control the sub-pixels 203 in the display area to perform progressive scanning.

[0040] The first driving circuit 100 includes a multi-stage shift register 101. The shift register 101 includes a shift output terminal GOUT. One-stage shift register 101 is electrically connected to one or more rows of sub-pixels 203 through the shift output terminal GOUT. The shift register 101 provides a gate driving signal for the electrically connected sub-pixels 203 through the shift output terminal GOUT to drive the sub-pixels 203 to work. Figure 1 Optionally, one-stage shift register 101 is electrically connected to one row of sub-pixels 203 correspondingly, and the shift register 101 provides a gate driving signal for the corresponding row of sub-pixels 203. However, in other embodiments, it is also optional that one-stage shift register is electrically connected to multiple rows of sub-pixels correspondingly, and this one-stage shift register provides a gate driving signal for multiple rows of sub-pixels simultaneously.

[0041] The shift register 101 includes a first input unit 111. The control terminal of the first input unit 111 is connected to the first trigger terminal IN1, the input terminal of the first input unit 111 is connected to the first signal terminal SG1, and the output terminal of the first input unit 111 is connected to the first node N1. Specifically, the electrical signal provided by the first trigger terminal IN1 is a signal with alternating high and low levels, whereby the on-off state of the first input unit 111 can be controlled. It can be understood that among the high level and the low level of the first trigger terminal IN1, one is the conductive level that can make the first input unit 111 conduct, and the other is the cut-off level that can make the first input unit 111 cut off. If the electrical signal provided by the first trigger terminal IN1 is the conductive level, the first input unit 111 is controlled to switch to the conductive state, and the first electrical signal provided by the first signal terminal SG1 is written into the first node N1; conversely, if the electrical signal provided by the first trigger terminal IN1 is the cut-off level, the first input unit 111 is controlled to switch to the cut-off state, and the transmission path between the first signal terminal SG1 and the first node N1 is disconnected. Therefore, the first input unit 111 responds to the control of the first trigger terminal IN1 and adjusts the signal of the first node N1 according to the first electrical signal provided by the first signal terminal SG1.

[0042] The shift register 101 includes a second input unit 112. The control terminal of the second input unit 112 is connected to the second trigger terminal IN2, the input terminal of the second input unit 112 is connected to the second signal terminal SG2, and the output terminal of the second input unit 112 is connected to the first node N1. Specifically, the electrical signal provided by the second trigger terminal IN2 is a signal that alternates between high and low levels, thereby controlling the on-off state of the second input unit 112. It can be understood that among the high level and the low level of the second trigger terminal IN2, one is the conductive level that can turn on the second input unit 112, and the other is the cut-off level that can turn off the second input unit 112. If the electrical signal provided by the second trigger terminal IN2 is the conductive level, the second input unit 112 is controlled to switch to the on state, and the second electrical signal provided by the second signal terminal SG2 is written into the first node N1; conversely, if the electrical signal provided by the second trigger terminal IN2 is the cut-off level, the second input unit 112 is controlled to switch to the off state, and the transmission path between the second signal terminal SG2 and the first node N1 is disconnected. Therefore, the second input unit 112 responds to the control of the second trigger terminal IN2 and adjusts the signal of the first node N1 according to the second electrical signal provided by the second signal terminal SG2.

[0043] The shift register 101 includes a first output unit 113. The control terminal of the first output unit 113 is connected to the first node N1, the input terminal of the first output unit 113 is connected to the third signal terminal SG3, and the output terminal of the first output unit 113 is connected to the shift output terminal GOUT. Specifically, the signal of the first node N1 is controlled by the first input unit 111 and the second input unit 112 and alternates between high and low levels, thereby controlling the on-off state of the first output unit 113. The electrical signal provided by the third signal terminal SG3 is a clock signal, which is defined as the third clock signal CK3. It can be understood that among the high level and the low level of the first node N1, one is the conductive level that can turn on the first output unit 113, and the other is the cut-off level that can turn off the first output unit 113. If the signal of the first node N1 is the conductive level, the first output unit 113 is controlled to switch to the on state, and the third clock signal CK3 provided by the third signal terminal SG3 is written into the shift output terminal GOUT; conversely, if the signal of the first node N1 is the cut-off level, the first output unit 113 is controlled to switch to the off state, and the transmission path between the third signal terminal SG3 and the shift output terminal GOUT is disconnected. Therefore, the first output unit 113 responds to the control of the first node N1 and adjusts the signal of the shift output terminal GOUT according to the third clock signal CK3 provided by the third signal terminal SG3.

[0044] The optional shift register 101 further includes: a second output unit 114; a control terminal of the second output unit 114 is connected to a fourth signal terminal SG4, an input terminal of the second output unit 114 is connected to a first power supply terminal VG1, and an output terminal of the second output unit 114 is connected to a shift output terminal GOUT, configured to, in response to the control of a fourth clock signal CK4 provided by the fourth signal terminal SG4, adjust the signal of the shift output terminal GOUT according to a first power supply signal provided by the first power supply terminal VG1. Specifically, the electrical signal provided by the fourth signal terminal SG4 is a clock signal, which is defined as the fourth clock signal CK4, and can control the on / off state of the second output unit 114. It can be understood that among the high level and the low level of the fourth signal terminal SG4, one is a conductive level that can turn on the second output unit 114, and the other is a cut-off level that can turn off the second output unit 114. If the electrical signal provided by the fourth signal terminal SG4 is a conductive level, the second output unit 114 is controlled to switch to an on state, and the first power supply signal provided by the first power supply terminal VG1 is written to the shift output terminal GOUT; conversely, if the electrical signal provided by the fourth signal terminal SG4 is a cut-off level, the second output unit 114 is controlled to switch to a cut-off state, and the transmission path between the first power supply terminal VG1 and the shift output terminal GOUT is disconnected. Therefore, the second output unit 114 adjusts the signal of the shift output terminal GOUT in response to the control of the fourth clock signal CK4 provided by the fourth signal terminal SG4 and according to the first power supply signal provided by the first power supply terminal VG1.

[0045] The optional shift register 101 further includes: a reset unit 115 and a node control unit 116; the reset unit 115 is connected to a reset control terminal RST, a first power supply terminal VG1, a first node N1, and a shift output terminal GOUT, configured to, in response to the control of the reset control terminal RST, adjust the signals of the first node N1 and the shift output terminal GOUT according to a first power supply signal provided by the first power supply terminal VG1; the node control unit 116 is connected to the first node N1, the first power supply terminal VG1, and the shift output terminal GOUT, configured to, in response to the control of the first node N1, adjust the signals of the first node N1 and the shift output terminal GOUT according to the first power supply signal.

[0046] Specifically, the control terminal of the reset unit 115 is connected to the reset control terminal RST. The electrical signal provided by the reset control terminal RST is a signal that alternates between high and low levels, thereby controlling the on / off state of the reset unit 115. It can be understood that among the high level and the low level of the reset control terminal RST, one is the conductive level that can turn on the reset unit 115, and the other is the cutoff level that can turn off the reset unit 115. If the electrical signal provided by the reset control terminal RST is the conductive level, the reset unit 115 is controlled to switch to the on state, and the first power signal provided by the first power supply terminal VG1 is written into the first node N1 and the shift output terminal GOUT respectively; conversely, if the electrical signal provided by the reset control terminal RST is the cutoff level, the transmission paths between the first power supply terminal VG1 and the first node N1 and between the first power supply terminal VG1 and the shift output terminal GOUT are both disconnected. Therefore, the reset unit 115 responds to the control of the reset control terminal RST and adjusts the signals of the first node N1 and the shift output terminal GOUT according to the first power signal provided by the first power supply terminal VG1.

[0047] Specifically, at least one control terminal of the node control unit 116 is connected to the first node N1. The signal of the first node N1 alternates between high and low levels, thereby affecting the on / off state of the node control unit 116. If the node control unit 116 switches to the on state, the first power signal provided by the first power supply terminal VG1 is written into the first node N1 and the shift output terminal GOUT respectively; conversely, if the node control unit 116 switches to the off state, the transmission paths between the first power supply terminal VG1 and the first node N1 and between the first power supply terminal VG1 and the shift output terminal GOUT are both disconnected. Therefore, the node control unit 116 responds to the control of the first node N1 and adjusts the signals of the first node N1 and the shift output terminal GOUT according to the first power signal.

[0048] In this embodiment, the first driving circuit 100 can achieve bidirectional scanning (i.e., forward scanning and reverse scanning). In the forward scanning mode, the signal of the first node N1 is controlled by the first input unit 111. If the first input unit 111 is turned on, the first electrical signal provided by the first signal terminal SG1 is written into the first node N1, and the shift register 101 controls the output of the shift output terminal GOUT according to the potential signal of the first node N1. Specifically, when the first node N1 is at a conducting level, the shift register 101 transmits the third clock signal CK3 to the shift output terminal GOUT through the turned-on first output unit 113. In the reverse scanning mode, the signal of the first node N1 is controlled by the second input unit 112. If the second input unit 112 is turned on, the second electrical signal provided by the second signal terminal SG2 is written into the first node N1, and the shift register 101 controls the output of the shift output terminal GOUT according to the potential signal of the first node N1. Specifically, when the first node N1 is at a conducting level, the shift register 101 transmits the third clock signal CK3 to the shift output terminal GOUT through the turned-on first output unit 113.

[0049] Optionally, at least one of the first electrical signal and the second electrical signal is a clock signal. In this embodiment, it is optional that both the first electrical signal and the second electrical signal are clock signals. The clock signal of the first electrical signal is defined as the first clock signal CK1, and the clock signal of the second electrical signal is defined as the second clock signal CK2. In other embodiments, it is also optional that the first electrical signal is a clock signal, but the second electrical signal is not a clock signal; or, it is also optional that the first electrical signal is not a clock signal, but the second electrical signal is a clock signal; or, it is also optional that the first electrical signal is a clock signal and the second electrical signal is a clock signal. At least one of the first electrical signal and the second electrical signal being a clock signal can achieve a narrow border and improve the reliability of the shift register with forward and reverse scanning functions.

[0050] Figure 2In the shown shift register 101, the first electrical signal provided by the optional first signal terminal SG1 is the first clock signal CK1, and the second electrical signal provided by the second signal terminal SG2 is the second clock signal CK2. The first driving circuit 100 itself has multiple clock signal lines, and each clock signal line provides a kind of clock signal. These multiple clock signal lines provide multiple clock signals to the shift register 101 to drive the shift register 101 to work. Among the multiple clock signals provided by the multiple clock signal lines to the shift register 101, at least the first clock signal CK1 and the second clock signal CK2 are included. Based on this, on the premise of ensuring the normal operation of the shift register 101, the first clock signal CK1 can be sourced from the existing clock signal lines in the first driving circuit 100, and the second clock signal CK2 can be sourced from the existing clock signal lines in the first driving circuit 100. That is, the clock signal line in the first driving circuit 100 that can provide the first clock signal CK1 can be connected to the first signal terminal SG1 of the shift register 101, and the clock signal line in the first driving circuit 100 that can provide the second clock signal CK2 can be connected to the second signal terminal SG2 of the shift register 101.

[0051] Figure 3 is a schematic diagram of a shift register provided by the comparative example for comparison with Figure 2 for comparison. Figure 3 The first electrical signal provided by the first signal terminal SG1 of the shift register 101' in is a direct current signal DIR1 instead of a clock signal, and the second electrical signal provided by the second signal terminal SG2 is a direct current signal DIR2 instead of a clock signal. Based on the multi-stage shift register 101', a gate driving circuit is formed. In this gate driving circuit, additional DIR1 signal lines and DIR2 signal lines need to be added. The DIR1 signal line is used to provide the direct current signal DIR1 to the first signal terminal SG1 of the shift register 101', and the DIR2 signal line is used to provide the direct current signal DIR2 to the second signal terminal SG2 of the shift register 101'. Obviously, the gate driving circuit and its signal lines will occupy more border space.

[0052] It can be seen from this that in this embodiment, there is no need to set DIR1 signal lines and DIR2 signal lines in the first driving circuit 100. Compared with Figure 3 compared with Figure 1 the border space occupied by the shown first driving circuit 100 is reduced, which is beneficial for the display panel to achieve a narrow border and a full screen. It should be noted that the connection method of the clock signal line connecting the first signal terminal SG1 and / or the clock signal line connecting the second signal terminal SG2 is a direct connection, that is, the first signal terminal SG1 is directly connected to the clock signal line through a via or a connecting line, etc., and the second signal terminal SG2 is directly connected to the clock signal line through a via or a connecting line, etc.

[0053] Refer to Figure 3As shown, the shift register 101' includes a plurality of transistors. When the shift register 101' performs a forward scan, the DC signal DIR1 is a high-level signal and the DC signal DIR2 is a low-level signal; conversely, when the shift register 101' performs a reverse scan, the DC signal DIR1 is a low-level signal and the DC signal DIR2 is a high-level signal. Based on this, when the shift register 101' performs a scan, the transistors in the first input unit 111' will be in a negative bias state for a long time, and correspondingly, the transistors in the first input unit 111' will have a threshold voltage shift (Vth shift); alternatively, the transistors in the second input unit 112' will be in a negative bias state for a long time, and correspondingly, the transistors in the second input unit 112' will have a threshold voltage shift (Vth shift). Thus, when the scan direction of the shift register 101' is switched, the threshold voltage shift of the transistors may cause the shift register 101' to malfunction, affecting the working stability and reliability of the shift register 101'; moreover, the long-term constant high-level DC signal will continuously leak to the first node N1, and the leakage time is relatively long, which may easily cause the shift register 101' to fail due to high-temperature operation.

[0054] However Figure 2 in which, the first clock signal CK1 will have an alternating high and low level jump, then the high-level duty cycle of the first clock signal CK1 may be approximately 50%; the second clock signal CK2 will have an alternating high and low level jump, then the high-level duty cycle of the second clock signal CK2 may be approximately 50%. Compared with Figure 3 in which, when the shift register 101 performs a scan, the duration of the transistors in the first input unit 111 being in a negative bias state can be halved, and correspondingly, the degree of threshold voltage shift (Vth shift) of the transistors in the first input unit 111 is weakened; moreover, the duration of the transistors in the second input unit 112 being in a negative bias state can be halved, and correspondingly, the degree of threshold voltage shift (Vth shift) of the transistors in the second input unit 112 is weakened. Based on this, by reducing the degree of threshold voltage shift of the transistors, the problem of abnormal operation due to the switching of the scan direction of the shift register can be prevented, improving the working stability and reliability of the shift register 101; moreover, the leakage duration of the high level of the first clock signal CK1 or the second clock signal CK2 to the first node N1 can also be halved, which can improve the problem that the shift register 101 is prone to failure due to high-temperature operation and extend the service life of the shift register 101.

[0055] It can be understood that if Figure 2 as shown, in the shift register 101, the first electrical signal or the second electrical signal is a clock signal, and the other is a non-clock signal, compared with Figure 3In contrast, the first driving circuit 100 based on the shift register 101 can reduce a DC signal transmission line, achieve a narrow border, and improve the reliability of the shift register with forward and reverse scanning functions.

[0056] The optional shift register includes multiple transistors; all of the multiple transistors are N-type transistors, or all of the multiple transistors are P-type transistors. The optional shift register includes multiple transistors; the semiconductor layer of the transistors is an amorphous silicon semiconductor layer or an oxide semiconductor layer. Exemplarily, the N-type transistors in the shift register can be IGZO-TFTs. The P-type transistors in the shift register can be LTPS-TFTs. However, it is not limited thereto.

[0057] In the present invention, the first signal terminal of the first input unit of the shift register provides a first electrical signal, and the second signal terminal of the second input unit of the shift register provides a second electrical signal. At least one of the first electrical signal and the second electrical signal is a clock signal. Then, at least one of the multiple clock signal lines included in the first driving circuit itself can be multiplexed to provide a clock signal to the first signal terminal or the second signal terminal. Therefore, the number of signal lines of the first driving circuit can be reduced, which is beneficial for the display panel to achieve a narrow border and a full screen. In addition, both the first clock signal and the second clock signal alternate between high and low levels. In this way, during the scanning process of the shift register, the duration of the transistors in the input unit being in the negative bias state can be reduced, and correspondingly, the threshold voltage shift (Vth shift) degree of the transistors in the input unit can be weakened, which is beneficial for improving the working stability and reliability of the shift register; and the leakage duration of the high level of the first clock signal or the high level of the second clock signal leaking to the first node can also be halved, thereby improving the problem that the shift register is prone to failure during high-temperature operation and extending the service life of the shift register.

[0058] Figure 4 is a schematic diagram of another shift register provided by an embodiment of the present invention. As Figure 4 shown, the optional first input unit 111 includes a first transistor M1. The gate of the first transistor M1 is connected to the first trigger terminal IN1, and the first transistor M1 is connected between the first signal terminal SG1 and the first node N1; the second input unit 112 includes a second transistor M2. The gate of the second transistor M2 is connected to the second trigger terminal IN2, and the second transistor M2 is connected between the second signal terminal SG2 and the first node N1.

[0059] In this embodiment, it is optional that both the first transistor M1 and the second transistor M2 are N-type transistors. Specifically, when the electrical signal provided by the first trigger terminal IN1 is at a high level, the first transistor M1 is turned on, and the first clock signal CK1 provided by the first signal terminal SG1 is written into the first node N1; conversely, when the electrical signal provided by the first trigger terminal IN1 is at a low level, the first transistor M1 is turned off. When the electrical signal provided by the second trigger terminal IN2 is at a high level, the second transistor M2 is turned on, and the second clock signal CK2 provided by the second signal terminal SG2 is written into the first node N1; conversely, when the electrical signal provided by the second trigger terminal IN2 is at a low level, the second transistor M2 is turned off. However, this is not limited thereto. In other embodiments, on the premise of ensuring the normal operation of the shift register, it is also optional that at least one of the first transistor and the second transistor is a P-type transistor.

[0060] As Figure 4 shown, it is optional that the first output unit 113 includes a third transistor M3. The gate of the third transistor M3 is connected to the first node N1, and the third transistor M3 is connected between the third signal terminal SG3 and the shift output terminal GOUT; the second output unit 114 includes a fourth transistor M4. The gate of the fourth transistor M4 is connected to the fourth signal terminal SG4, and the fourth transistor M4 is connected between the first power supply terminal VG1 and the shift output terminal GOUT.

[0061] In this embodiment, it is optional that both the third transistor M3 and the fourth transistor M4 are N-type transistors. Specifically, when the potential of the first node N1 is at a high level, the third transistor M3 is turned on, and the third clock signal CK3 provided by the third signal terminal SG3 is written into the shift output terminal GOUT; conversely, when the potential of the first node N1 is at a low level, the third transistor M3 is turned off. When the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at a high level, the fourth transistor M4 is turned on, and the first power supply signal provided by the first power supply terminal VG1 is written into the shift output terminal GOUT; conversely, when the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at a low level, the fourth transistor M4 is turned off. Figure 4 It is optional that the first power supply terminal VG1 is a low voltage signal (VGL). However, this is not limited thereto. In other embodiments, on the premise of ensuring the normal operation of the shift register, it is also optional that at least one of the third transistor and the fourth transistor is a P-type transistor.

[0062] As Figure 4As shown, the optional reset unit 115 includes a fifth transistor M5 and a sixth transistor M6. The gates of the fifth transistor M5 and the sixth transistor M6 are both connected to the reset control terminal RST. The fifth transistor M5 is connected between the first power supply terminal VG1 and the first node N1. The sixth transistor M6 is connected between the first power supply terminal VG1 and the shift output terminal GOUT. The node control unit 116 includes a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9. The gate of the seventh transistor M7 is connected to the first node N1. The seventh transistor M7 is connected between the first power supply terminal VG1 and the second node N2. The gates of the eighth transistor M8 and the ninth transistor M9 are both connected to the second node N2. The eighth transistor M8 is connected between the first power supply terminal VG1 and the first node N1. The ninth transistor M9 is connected between the first power supply terminal VG1 and the shift output terminal GOUT.

[0063] In this embodiment, the optional fifth transistor M5, sixth transistor M6, seventh transistor M7, eighth transistor M8, and ninth transistor M9 are all N-type transistors. Based on this, for any one of the fifth transistor M5, sixth transistor M6, seventh transistor M7, eighth transistor M8, and ninth transistor M9, when the potential of the gate of the transistor is high, the transistor is turned on, and the transmission path between the source and the drain of the transistor is turned on. Conversely, for any one of the fifth transistor M5, sixth transistor M6, seventh transistor M7, eighth transistor M8, and ninth transistor M9, when the potential of the gate of the transistor is low, the transistor is turned off, and the transmission path between the source and the drain of the transistor is turned off. However, this is not limited thereto. In other embodiments, on the premise of ensuring the normal operation of the shift register, at least one of the fifth transistor, sixth transistor, seventh transistor, eighth transistor, and ninth transistor can also be a P-type transistor.

[0064] As Figure 4 shown, the optional shift register 101 further includes: a first capacitor C1 and a second capacitor C2; the first capacitor C1 is coupled between the first node N1 and the shift output terminal GOUT; the second capacitor C2 is coupled between the second node N2 and the third signal terminal SG3.

[0065] In this embodiment, the first capacitor C1 is coupled between the first node N1 and the shift output terminal GOUT. When the first node N1 is in a floating state, the potential change of the shift output terminal GOUT affects the potential change of the first node N1. Specifically, when the potential of the shift output terminal GOUT jumps from high level to low level, the potential of the first node N1 is pulled down; or when the potential of the shift output terminal GOUT jumps from low level to high level, the potential of the first node N1 is bootstrapped and lifted.

[0066] The second capacitor C2 is coupled between the second node N2 and the third signal terminal SG3. When the second node N2 is in a floating state, the potential change of the third clock signal CK3 at the third signal terminal SG3 affects the potential change of the second node N2. Specifically, when the third clock signal CK3 jumps from a high level to a low level, the potential of the second node N2 is pulled down; or when the third clock signal CK3 jumps from a low level to a high level, the potential of the second node N2 is bootstrapped and lifted.

[0067] It can be understood that the structure of the shift register in the present invention includes but is not limited to Figure 4 the 9T2C structure shown. Relevant practitioners can reasonably design the structure of the shift register according to the requirements of the product and the application scenario of the shift register. Other shift register structures are not elaborated in the present invention.

[0068] In this embodiment, Figure 4 the working process of the shift register 101 shown is taken as an example for description. Optionally, each transistor is an NMOS, and the first power signal provided by the first power terminal VG1 is a low voltage signal VGL. The display panel can perform forward scanning and reverse scanning.

[0069] Figure 5 is Figure 4 a timing schematic diagram of the forward scanning of the shift register shown, Figure 6 is Figure 4 a timing schematic diagram of the reverse scanning of the shift register shown. It should be noted that only the timing of one shift register of the first driving circuit is described here. The forward scanning timing of this shift register is as shown in Figure 5 and the reverse scanning timing is as shown in Figure 6 shown.

[0070] Combined with Figure 4 and Figure 5 shown, the forward scanning working process of the shift register 101 at least includes the following stages:

[0071] In the first stage t11, the electrical signal received by the first trigger terminal IN1 of the shift register 101 is a high level signal, which turns on the first transistor M1; the first clock signal CK1 provided by the first signal terminal SG1 jumps from a low level to a high level, then the potential of the first node N1 jumps from a low level to a high level, turning on the third transistor M3; the third clock signal CK3 provided by the third signal terminal SG3 is at a low level, so the shift output terminal GOUT outputs a low level; the electrical signal received by the second trigger terminal IN2 is at a low level, turning off the second transistor M2; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at a high level, turning on the fourth transistor M4, and the low level signal VGL provided by the first power terminal VG1 is written into the shift output terminal GOUT.

[0072] In the second stage t12, the electrical signal received by the first trigger terminal IN1 of the shift register 101 is a low-level signal, which turns off the first transistor M1. The potential of the second trigger terminal IN2 remains low, keeping the second transistor M2 off. Then, the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t11, keeping the third transistor M3 on. The fourth clock signal CK4 provided by the fourth signal terminal SG4 is at a low level, turning off the fourth transistor M4. The third clock signal CK3 provided by the third signal terminal SG3 is at a high level, so the shift output terminal GOUT jumps from the low level of the first stage t11 to a high level. The low-level to high-level transition of the shift output terminal GOUT, after being coupled by the first capacitor C1, causes the first node N1 to be lifted based on the bootstrap effect of the first capacitor C1.

[0073] In the third stage t13, the first transistor M1 remains off. The electrical signal received by the second trigger terminal IN2 of the shift register 101 is a high-level signal, turning on the second transistor M2. The second clock signal CK2 provided by the second signal terminal SG2 jumps from a high level to a low level, so the potential of the first node N1 is pulled down and reduced, causing the third transistor M3 to switch from on to off. Before the third transistor M3 turns off, the low level of the third clock signal CK3 is written to the shift output terminal GOUT. The fourth clock signal CK4 provided by the fourth signal terminal SG4 is at a high level, turning on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0074] As described above, the shift output terminal GOUT of the shift register 101 outputs a high-level signal in the second stage t12, and this high-level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register 101 keeps outputting a low-level signal in the third stage t13 and afterwards until the first trigger terminal IN1 receives a high-level signal again.

[0075] Combined Figure 4 and Figure 6 shown, the reverse scanning working process of the shift register 101 at least includes the following stages:

[0076] In the first stage t21, the electrical signal received by the second trigger terminal IN2 of the shift register 101 is a high-level signal, which turns on the second transistor M2; the second clock signal CK2 provided by the second signal terminal SG2 changes from low level to high level, then the potential of the first node N1 changes from low level to high level, turning on the third transistor M3; the third clock signal CK3 provided by the third signal terminal SG3 is at low level, so the shift output terminal GOUT outputs a low level; the electrical signal received by the first trigger terminal IN1 is at low level, turning off the first transistor M1; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at high level, turning on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0077] In the second stage t22, the electrical signal received by the second trigger terminal IN2 of the shift register 101 is a low-level signal, turning off the second transistor M2; the potential of the first trigger terminal IN1 remains at low level, turning off the first transistor M1, then the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t21, keeping the third transistor M3 turned on; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at low level, turning off the fourth transistor M4; the third clock signal CK3 provided by the third signal terminal SG3 is at high level, so the shift output terminal GOUT changes from the low level of the first stage t21 to a high-level output; the low-level to high-level change of the shift output terminal GOUT, after being coupled by the first capacitor C1, causes the first node N1 to be lifted based on the bootstrap effect of the first capacitor C1.

[0078] In the third stage t23, the second transistor M2 remains off; the electrical signal received by the first trigger terminal IN1 of the shift register 101 is a high-level signal, turning on the first transistor M1, and the first clock signal CK1 provided by the first signal terminal SG1 changes from high level to low level, then the potential of the first node N1 is pulled down and decreased, causing the third transistor M3 to switch from on to off; before the third transistor M3 turns off, the low level of the third clock signal CK3 is written to the shift output terminal GOUT; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at high level, turning on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0079] As described above, the shift output terminal GOUT of the shift register 101 outputs a high-level signal in the second stage t22, and this high-level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register 101 outputs a low-level signal in the third stage t23 and afterwards until the second trigger terminal IN2 receives a high-level signal again.

[0080] Based on this, the display panel can perform forward scanning and reverse scanning, and can switch between forward scanning and reverse scanning.

[0081] In this embodiment, the first electrical signal provided by the first signal terminal SG1 is the first clock signal CK1, and the second electrical signal provided by the second signal terminal SG2 is the second clock signal CK2, which does not affect the normal output of the shift register 101. Then, the original clock signal lines of the first driving circuit can be used to provide the first clock signal CK1 and the second clock signal CK2 for the shift register 101. Thus, the first driving circuit does not need to set additional SG1 signal lines and SG2 signal lines, which is beneficial to realizing a narrow border. On the other hand, the duty cycle of the first clock signal CK1 can be about 50%, and the duty cycle of the second clock signal CK2 can be about 50%. Therefore, the device bias time of the first transistor M1 can be halved, and the device bias time of the second transistor M2 can be halved. Correspondingly, the severity of the threshold voltage shift Vth shift of the first transistor M1 and the second transistor M2 is weakened, so that the reliability of the shift register 101 can be improved. In addition, the duration of the high level leaking into the first node N1 by the first clock signal CK1 is halved, and the duration of the high level leaking into the first node N1 by the second clock signal CK2 is halved, which can improve the problem that the shift register 101 is prone to failure during high-temperature operation.

[0082] It should be noted that the input end of the first transistor M1 is connected to the first signal terminal SG1, and the input end of the second transistor M2 is connected to the second signal terminal SG2. The first signal terminal SG1 receives the first clock signal CK1, and the second signal terminal SG2 receives the second clock signal CK2. The first clock signal CK1 is different from the second clock signal CK2. Therefore, the clock signal line connected to the first signal terminal SG1 is different from the clock signal line connected to the second signal terminal SG2. Based on this, when the first transistor M1 or the second transistor M2 is turned on, the clock signal line connected to the first signal terminal SG1 or the clock signal line connected to the second signal terminal SG2 can directly charge the first node N1, ensuring that the first node N1 can have a long charging time, and further ensuring that the third transistor M3 can have a long turn-on time. In this way, the charging effect of the shift output terminal GOUT can be enhanced. It is found through testing that the output duration of the high level of the shift output terminal GOUT (refer to t12 or t22) is greater than TA / 3 and less than TA / 2, where TA is the period of the first clock signal CK1.

[0083] The optional first driving circuit includes a multi-stage shift register circuit and Y clock signal lines, where Y ≥ 4; the shift register circuit includes Ya cascaded shift registers, and the third signal terminals of the Ya shift registers are respectively connected to Ya of the Y clock signal lines, with Y ≥ Ya ≥ 4. Among the optional Y clock signal lines, the clock signals provided by any two selected clock signal lines have the same frequency but different phases. The optional Y clock signal lines include the first clock signal line to the Yth clock signal line; the first driving circuit includes a forward scanning mode and a reverse scanning mode; in the forward scanning mode, the phase of the clock signal provided by the ith clock signal line is earlier than the phase of the clock signal provided by the (i + 1)th clock signal line, and the phase difference between the two is a H; in the reverse scanning mode, the phase of the clock signal provided by the (i + 1)th clock signal line is earlier than the phase of the clock signal provided by the ith clock signal line, and the phase difference between the two is b H; 1 ≤ i ≤ Y, both a and b are positive integers, and H is equal to the scanning duration of a row of sub-pixels in the display panel. Optionally, the first trigger terminal of the nth stage shift register is connected to the shift output terminal of the (n - m)th stage shift register; the second trigger terminal of the nth stage shift register is connected to the shift output terminal of the (n + m)th stage shift register; n is a positive integer, and m is an integer greater than or equal to 2.

[0084] In this embodiment, the first driving circuit can be a bilateral drive or a unilateral drive. For the first driving circuit, its unilateral structure can be a 4-phase ASG structure or a 6-phase ASG structure.

[0085] It can be understood that the clock signal provided by the same clock signal line during forward scanning may be different from the clock signal provided during reverse scanning. In various embodiments of the present invention, " " is the multiplication sign.

[0086] Figure 7 is a schematic diagram of a first driving circuit provided by an embodiment of the present invention, as Figure 7As shown, the unilateral structure of the first driving circuit is a 4-phase ASG structure. The optional Y clock signal lines include the first clock signal line CKL1 to the fourth clock signal line CKL4. The shift register circuit 121 includes 4 cascaded shift registers 101. The first driving circuit 100 includes a first circuit group, and the first circuit group includes at least one shift register circuit 121. The shift register circuit 121 in the first circuit group satisfies the following conditions: The first clock signal line CKL1 is respectively connected to the third signal terminal SG3 of the first-stage shift register ASG(1), the first signal terminal SG1 of the second-stage shift register ASG(2), the fourth signal terminal SG4 of the third-stage shift register ASG(3), and the second signal terminal SG2 of the fourth-stage shift register ASG(4). The second clock signal line CKL2 is respectively connected to the second signal terminal SG2 of the first-stage shift register ASG(1), the third signal terminal SG3 of the second-stage shift register ASG(2), the first signal terminal SG1 of the third-stage shift register ASG(3), and the fourth signal terminal SG4 of the fourth-stage shift register ASG(4). The third clock signal line CKL3 is respectively connected to the fourth signal terminal SG4 of the first-stage shift register ASG(1), the second signal terminal SG2 of the second-stage shift register ASG(2), the third signal terminal SG3 of the third-stage shift register ASG(3), and the first signal terminal SG1 of the fourth-stage shift register ASG(4). The fourth clock signal line CKL4 is respectively connected to the first signal terminal SG1 of the first-stage shift register ASG(1), the fourth signal terminal SG4 of the second-stage shift register ASG(2), the second signal terminal SG2 of the third-stage shift register ASG(3), and the third signal terminal SG3 of the fourth-stage shift register ASG(4). Optionally, the first driving circuit 100 includes a forward scanning mode and a reverse scanning mode. In the forward scanning mode, the phase of the clock signal provided by the i-th clock signal line is earlier than the phase of the clock signal provided by the (i + 1)-th clock signal line, and the phase difference between the two is H. In the reverse scanning mode, the phase of the clock signal provided by the (i + 1)-th clock signal line is earlier than the phase of the clock signal provided by the i-th clock signal line, and the phase difference between the two is H. 1 ≤ i ≤ 3, 2 H is equal to the effective pulse width output by the shift output terminal GOUT of the shift register 101.

[0087] In this embodiment, the 4 cascaded shift registers 101 in the first driving circuit 100 form a shift register circuit 121, and the first driving circuit 100 includes multiple shift register circuits 121. Figure 7Only the first-stage shift register circuit 121 / 1 and the second-stage shift register circuit 121 / 2 in the first driving circuit 100 are shown, and the third-stage and subsequent-stage shift register circuits in the first driving circuit 100 are not shown. A first circuit group (not shown) includes one or more shift register circuits 121.

[0088] The multi-stage shift register 101 in the first driving circuit 100 is sequentially labeled as ASG 1 , ASG 2 , ASG 3 , ASG 4 , ASG 5 , ASG 6 , …, the nth-stage shift register 101 is labeled as ASG n . The first driving circuit 100 includes a forward scanning mode and a reverse scanning mode. Specifically, the forward scanning mode can be scanning along the direction from ASG 1 to ASG 6 . Correspondingly, the reverse scanning mode is scanning along the direction from ASG 6 to ASG 1 . Here, the shift register ASG 1 to the shift register ASG 4 constitute the first-stage shift register circuit 121 / 1, and the shift register ASG 5 to the shift register ASG 8 constitute the second-stage shift register circuit 121 / 2, and so on. For any shift register circuit 121, the 4-stage shift register 101 is sequentially the first-stage shift register ASG(1) to the fourth-stage shift register ASG(4) of the shift register circuit 121 according to the cascade relationship. Therefore, the shift register ASG 1 to the shift register ASG 4 are sequentially the first-stage shift register ASG(1) to the fourth-stage shift register ASG(4) in the first-stage shift register circuit 121 / 1; the shift register ASG 5 to the shift register ASG 8 are sequentially the first-stage shift register ASG(1) to the fourth-stage shift register ASG(4) in the second-stage shift register circuit 121 / 2; and so on.

[0089] The first driving circuit 100 includes 4 or more clock signal lines, at least including the first clock signal line CKL1, the second clock signal line CKL2, the third clock signal line CKL3, and the fourth clock signal line CKL4. Each clock signal line is used to provide a clock signal, and the clock signals provided by any two clock signal lines have the same frequency but different phases.

[0090] Figure 8 is Figure 7 The schematic diagram of the clock signal of the first driving circuit in the forward scanning mode as shown. As Figure 8 shown, in the forward scanning mode, the phase of the clock signal provided by the first clock signal line CKL1 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, and the phase difference between the two is 1 H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is 1 H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is 1 H; the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is 1 H.

[0091] Figure 9 is Figure 7 The schematic diagram of the clock signal of the first driving circuit in the reverse scanning mode as shown. As Figure 9 shown, in the reverse scanning mode, the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is 1 H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, and the phase difference between the two is 1 H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is 1 H; the phase of the clock signal provided by the first clock signal line CKL1 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is 1 H.

[0092] As Figure 7 shown, optionally, the first trigger terminal IN1 of the nth stage shift register 101 is connected to the shift output terminal GOUT of the (n - 2)th stage shift register 101; the second trigger terminal IN2 of the nth stage shift register 101 is connected to the shift output terminal GOUT of the (n + 2)th stage shift register 101. For the case where n is less than or equal to 2, that is, including the shift register ASG 1 and the shift register ASG 2 , optionally, the signals received by the first trigger terminals IN1 of both can directly come from the STV signal line. For example, the STV1 signal line directly supplies the first stage shift register ASG 1The first trigger terminal IN1 of provides an electrical signal, and the STV2 signal line directly supplies the second-stage shift register ASG 2 The first trigger terminal IN1 of provides an electrical signal. However, this is not limited thereto. In other embodiments, the shift register ASG may also be selected 1 There are two levels of dummy shift registers provided thereon, respectively marked as dummy-ASG1 and dummy-ASG2. Dummy-ASG1 supplies the first-stage shift register ASG 1 The first trigger terminal IN1 of provides an electrical signal, and dummy-ASG2 supplies the second-stage shift register ASG 2 The first trigger terminal IN1 of provides an electrical signal.

[0093] Similarly, the first driving circuit 100 includes X levels of shift registers, and the last two levels of shift registers are respectively ASG X-1 and ASG X , the optional ASG X-1 and ASG X The signal received by the second trigger terminal IN2 of can directly come from the STV signal line. For example, the STV3 signal line directly supplies the (X - 1)-stage shift register ASG X-1 The second trigger terminal IN2 of provides an electrical signal, and the STV4 signal line directly supplies the X-stage shift register ASG X The second trigger terminal IN2 of provides an electrical signal. However, this is not limited thereto. In other embodiments, the shift register ASG may also be selected X There are two levels of dummy shift registers provided thereunder, respectively marked as dummy-ASG3 and dummy-ASG4. Dummy-ASG3 supplies the (X - 1)-stage shift register ASG X-1 The second trigger terminal IN2 of provides an electrical signal, and dummy-ASG4 supplies the X-stage shift register ASG X The second trigger terminal IN2 of provides an electrical signal.

[0094] When the first driving circuit 100 performs a forward scan or a reverse scan, the working timing of the first-stage shift register ASG(1) of any shift register circuit 121 is as follows: The first clock signal CK1 received by the first signal terminal SG1 comes from the fourth clock signal line CKL4, the second clock signal CK2 received by the second signal terminal SG2 comes from the second clock signal line CKL2, the third clock signal CK3 received by the third signal terminal SG3 comes from the first clock signal line CKL1, and the fourth clock signal CK4 received by the fourth signal terminal SG4 comes from the third clock signal line CKL3. Exemplarily, the first-stage shift register ASG(1) in the second-stage shift register circuit 121 / 2 is ASG 5 (1) The working timing in the forward scan mode can refer to Figure 5As shown, ASG 5 (1) The working timing in the reverse scan mode can be referred to Figure 6 as shown. Details are not elaborated here.

[0095] The working timing of the second-stage shift register ASG(2) of any shift register circuit 121 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is from the first clock signal line CKL1, the second clock signal CK2 received by the second signal terminal SG2 is from the third clock signal line CKL3, the third clock signal CK3 received by the third signal terminal SG3 is from the second clock signal line CKL2, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is from the fourth clock signal line CKL4.

[0096] The working timing of the third-stage shift register ASG(3) of any shift register circuit 121 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is from the second clock signal line CKL2, the second clock signal CK2 received by the second signal terminal SG2 is from the fourth clock signal line CKL4, the third clock signal CK3 received by the third signal terminal SG3 is from the third clock signal line CKL3, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is from the first clock signal line CKL1.

[0097] The working timing of the fourth-stage shift register ASG(4) of any shift register circuit 121 is as follows: the first clock signal CK1 received by the first signal terminal SG1 is from the third clock signal line CKL3, the second clock signal CK2 received by the second signal terminal SG2 is from the first clock signal line CKL1, the third clock signal CK3 received by the third signal terminal SG3 is from the fourth clock signal line CKL4, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is from the second clock signal line CKL2.

[0098] In this embodiment, for the single-sided 4-phase ASG structure of the first driving circuit 100, by using the existing clock signal lines of the first driving circuit 100 itself, the first clock signal CK1 is multiplexed to provide to the first signal terminal SG1, and the second clock signal CK2 is multiplexed to provide to the second signal terminal SG2. The shift register 101 can output normally, and the first driving circuit 100 can achieve forward and reverse scans. Compared with Figure 3 before, two DC signal lines are reduced; and the device bias time of either the first transistor M1 or the second transistor M2 is halved, and the severity of Vth shift is weakened. Thus, the output stability, reliability, and dependability of the shift register 101 can be improved; in addition, the high-level leakage time of the first node N1 is halved, which can improve the problem that the shift register is prone to failure when working at high temperatures.

[0099] Figure 10It is a schematic diagram of another first driving circuit provided by an embodiment of the present invention, as shown in Figure 10As shown, the unilateral structure of the first driving circuit 300 is a 6-phase ASG structure. The optional Y clock signal lines include the first clock signal line CKL1 to the sixth clock signal line CKL6, and the shift register circuit 310 includes 6 cascaded shift registers 101; the first driving circuit 300 includes a second circuit group, and the second circuit group includes at least one shift register circuit 310; the shift register circuit 310 in the second circuit group satisfies the following conditions: the first clock signal line CKL1 is respectively connected to the third signal terminal SG3 of the first-stage shift register ASG(1), the first signal terminal SG1 of the third-stage shift register ASG(3), the fourth signal terminal SG4 of the fourth-stage shift register ASG(4), and the second signal terminal SG2 of the sixth-stage shift register ASG(6); the second clock signal line CKL2 is respectively connected to the second signal terminal SG2 of the first-stage shift register ASG(1), the third signal terminal SG3 of the second-stage shift register ASG(2), the first signal terminal SG1 of the fourth-stage shift register ASG(4), and the fourth signal terminal SG4 of the fifth-stage shift register ASG(5); the third clock signal line CKL3 is respectively connected to the second signal terminal SG2 of the second-stage shift register ASG(2), the third signal terminal SG3 of the third-stage shift register ASG(3), the first signal terminal SG1 of the fifth-stage shift register ASG(5), and the fourth signal terminal SG4 of the sixth-stage shift register ASG(6); the fourth clock signal line CKL4 is respectively connected to the fourth signal terminal SG4 of the first-stage shift register ASG(1), the second signal terminal SG2 of the third-stage shift register ASG(3), the third signal terminal SG3 of the fourth-stage shift register ASG(4), and the first signal terminal SG1 of the sixth-stage shift register ASG(6); the fifth clock signal line CKL5 is respectively connected to the first signal terminal SG1 of the first-stage shift register ASG(1), the fourth signal terminal SG4 of the second-stage shift register ASG(2), the second signal terminal SG2 of the fourth-stage shift register ASG(4), and the third signal terminal SG3 of the fifth-stage shift register ASG(5); the sixth clock signal line CKL6 is respectively connected to the first signal terminal SG1 of the second-stage shift register ASG(2), the fourth signal terminal SG4 of the third-stage shift register ASG(3), the second signal terminal SG2 of the fifth-stage shift register ASG(5), and the third signal terminal SG3 of the sixth-stage shift register ASG(6). Optionally, the first driving circuit 300 includes a forward scanning mode and a reverse scanning mode; in the forward scanning mode, the phase of the clock signal provided by the i-th clock signal line is earlier than the phase of the clock signal provided by the (i + 1)-th clock signal line, and the phase difference between the two is H; in the reverse scanning mode, the phase of the clock signal provided by the (i + 1)-th clock signal line is earlier than the phase of the clock signal provided by the i-th clock signal line, and the phase difference between the two is H; 1 ≤ i ≤ 5, 3 H is equal to the effective pulse width output from the shift output terminal GOUT of the shift register 101.

[0100] In this embodiment, 6 cascaded shift registers 101 in the first driving circuit 300 form a shift register circuit 310. The first driving circuit 300 includes multiple levels of shift register circuits 310. Figure 10 Only the first-level shift register circuit 310 / 1 and the second-level shift register circuit 310 / 2 in the first driving circuit 300 are shown, and the third-level and subsequent-level shift register circuits in the first driving circuit 300 are not shown. A second circuit group (not shown) includes one or more shift register circuits 310.

[0101] The multiple shift registers 101 in the first driving circuit 300 are sequentially labeled as ASG 1 、ASG 2 、ASG 3 、ASG 4 、ASG 5 、ASG 6 、ASG 7 、ASG 8 、ASG 9 、…, the nth-level shift register 101 is labeled as ASG n . The first driving circuit 300 includes a forward scanning mode and a reverse scanning mode. Specifically, the forward scanning mode can be scanning along the direction from ASG 1 to ASG 9 . Correspondingly, the reverse scanning mode is scanning along the direction from ASG 9 to ASG 1 . Here, the shift register ASG 1 to the shift register ASG 6 form the first-level shift register circuit 310 / 1, and the shift register ASG 7 to the shift register ASG 12 form the second-level shift register circuit 310 / 2, and so on. For any shift register circuit 310, the 6-level shift registers 101 are sequentially the first-level shift register ASG(1) to the sixth-level shift register ASG(6) of the shift register circuit 310 according to the cascading relationship. Therefore, the shift register ASG 1 to the shift register ASG 6 are sequentially the first-level shift register ASG(1) to the sixth-level shift register ASG(6) in the first-level shift register circuit 310 / 1; the shift register ASG 7 to the shift register ASG 12Sequentially, it is the first - stage shift register ASG(1) to the sixth - stage shift register ASG(6) in the second - stage shift register circuit 310 / 2; and so on.

[0102] The first driving circuit 300 includes 6 or more clock signal lines, at least including a first clock signal line CKL1, a second clock signal line CKL2, a third clock signal line CKL3, a fourth clock signal line CKL4, a fifth clock signal line CKL5, and a sixth clock signal line CKL6. Each clock signal line is used to provide a clock signal, and the clock signals provided by any two clock signal lines have the same frequency but different phases.

[0103] Figure 11 Yes Figure 10 It is a schematic diagram of the clock signal of the first driving circuit in the forward scanning mode. As Figure 11 shown, in the forward scanning mode, the phase of the clock signal provided by the first clock signal line CKL1 is earlier than the phase of the clock signal provided by the second clock signal line CKL2, and the phase difference between the two is H; the phase of the clock signal provided by the second clock signal line CKL2 is earlier than the phase of the clock signal provided by the third clock signal line CKL3, and the phase difference between the two is H; the phase of the clock signal provided by the third clock signal line CKL3 is earlier than the phase of the clock signal provided by the fourth clock signal line CKL4, and the phase difference between the two is H; the phase of the clock signal provided by the fourth clock signal line CKL4 is earlier than the phase of the clock signal provided by the fifth clock signal line CKL5, and the phase difference between the two is H; the phase of the clock signal provided by the fifth clock signal line CKL5 is earlier than the phase of the clock signal provided by the sixth clock signal line CKL6, and the phase difference between the two is H; the phase of the clock signal provided by the sixth clock signal line CKL6 is earlier than the phase of the clock signal provided by the first clock signal line CKL1, and the phase difference between the two is H. Here, the phase difference between the clock signal provided by the i - th clock signal line and the clock signal provided by the (i + 1)-th clock signal line can be less than or equal to H.

[0104] Figure 12 Yes Figure 10 It is a schematic diagram of the clock signal of the first driving circuit in the reverse scanning mode. As Figure 12As shown, in the reverse scan mode, the phase of the clock signal provided by the 6th clock signal line CKL6 is earlier than the phase of the clock signal provided by the 5th clock signal line CKL5, and the phase difference between them is H; the phase of the clock signal provided by the 5th clock signal line CKL5 is earlier than the phase of the clock signal provided by the 4th clock signal line CKL4, and the phase difference between them is H; the phase of the clock signal provided by the 4th clock signal line CKL4 is earlier than the phase of the clock signal provided by the 3rd clock signal line CKL3, and the phase difference between them is H; the phase of the clock signal provided by the 3rd clock signal line CKL3 is earlier than the phase of the clock signal provided by the 2nd clock signal line CKL2, and the phase difference between them is H; the phase of the clock signal provided by the 2nd clock signal line CKL2 is earlier than the phase of the clock signal provided by the 1st clock signal line CKL1, and the phase difference between them is H; the phase of the clock signal provided by the 1st clock signal line CKL1 is earlier than the phase of the clock signal provided by the 6th clock signal line CKL6, and the phase difference between them is H.

[0105] As Figure 10 shown, the first trigger terminal IN1 of the optional nth stage shift register 101 is connected to the shift output terminal GOUT of the (n - 3)th stage shift register 101; the second trigger terminal IN2 of the nth stage shift register 101 is connected to the shift output terminal GOUT of the (n + 3)th stage shift register 101. For the case where n is less than or equal to 3, that is, including the shift registers ASG 1 to ASG 3 , optionally, the signals received by the first trigger terminals IN1 of the three can directly come from the STV signal lines. For example, the STV1 signal line directly provides an electrical signal to the first trigger terminal IN1 of the 1st stage shift register ASG 1 , the STV2 signal line directly provides an electrical signal to the first trigger terminal IN1 of the 2nd stage shift register ASG 2 , and the STV3 signal line directly provides an electrical signal to the first trigger terminal IN1 of the 3rd stage shift register ASG 3 . However, it is not limited to this. In other embodiments, it is also optional that there are three - stage dummy shift registers provided on the shift register ASG 1 , which are respectively marked as dummy - ASG1 to dummy - ASG3. Dummy - ASG1 provides an electrical signal to the first trigger terminal IN1 of the 1st stage shift register ASG 1 , dummy - ASG2 provides an electrical signal to the first trigger terminal IN1 of the 2nd stage shift register ASG 2 , and dummy - ASG3 provides an electrical signal to the first trigger terminal IN1 of the 3rd stage shift register ASG 3 .

[0106] Similarly, the first driving circuit 100 includes an X-stage shift register, and the last three shift registers are ASG X-2 , ASG X-1 and ASG X . Optionally, the signals received by the second trigger terminals IN2 of ASG X-2 , ASG X-1 and ASG X can directly come from the STV signal line. For example, the STV4 signal line directly supplies an electrical signal to the second trigger terminal IN2 of the (X - 2)-th stage shift register ASG X-2 , the STV5 signal line directly supplies an electrical signal to the second trigger terminal IN2 of the (X - 1)-th stage shift register ASG X-1 , and the STV6 signal line directly supplies an electrical signal to the second trigger terminal IN2 of the X-th stage shift register ASG X . However, it is not limited thereto. In other embodiments, there may also be three dummy shift registers provided under the shift register ASG X , which are respectively marked as dummy-ASG4 and dummy-ASG6. Dummy-ASG4 supplies an electrical signal to the second trigger terminal IN2 of the (X - 2)-th stage shift register ASG X-2 , dummy-ASG5 supplies an electrical signal to the second trigger terminal IN2 of the (X - 1)-th stage shift register ASG X-1 , and dummy-ASG6 supplies an electrical signal to the second trigger terminal IN2 of the X-th stage shift register ASG X .

[0107] When the first driving circuit 300 performs a forward scan or a reverse scan, the working timing of the first-stage shift register ASG(1) of any shift register circuit 310 is as follows: the first clock signal CK1 received by the first signal terminal SG1 comes from the fifth clock signal line CKL5, the second clock signal CK2 received by the second signal terminal SG2 comes from the second clock signal line CKL2, the third clock signal CK3 received by the third signal terminal SG3 comes from the first clock signal line CKL1, and the fourth clock signal CK4 received by the fourth signal terminal SG4 comes from the fourth clock signal line CKL4.

[0108] The working timing of the second-stage shift register ASG(2) of any shift register circuit 310 is as follows: the first clock signal CK1 received by the first signal terminal SG1 comes from the sixth clock signal line CKL6, the second clock signal CK2 received by the second signal terminal SG2 comes from the third clock signal line CKL3, the third clock signal CK3 received by the third signal terminal SG3 comes from the second clock signal line CKL2, and the fourth clock signal CK4 received by the fourth signal terminal SG4 comes from the fifth clock signal line CKL5.

[0109] The working timing of the third-stage shift register ASG(3) of any shift register circuit 310 is as follows: The first clock signal CK1 received by the first signal terminal SG1 is sourced from the first clock signal line CKL1, the second clock signal CK2 received by the second signal terminal SG2 is sourced from the fourth clock signal line CKL4, the third clock signal CK3 received by the third signal terminal SG3 is sourced from the third clock signal line CKL3, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is sourced from the sixth clock signal line CKL6.

[0110] The working timing of the fourth-stage shift register ASG(4) of any shift register circuit 310 is as follows: The first clock signal CK1 received by the first signal terminal SG1 is sourced from the second clock signal line CKL2, the second clock signal CK2 received by the second signal terminal SG2 is sourced from the fifth clock signal line CKL5, the third clock signal CK3 received by the third signal terminal SG3 is sourced from the fourth clock signal line CKL4, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is sourced from the first clock signal line CKL1.

[0111] The working timing of the fifth-stage shift register ASG(5) of any shift register circuit 310 is as follows: The first clock signal CK1 received by the first signal terminal SG1 is sourced from the third clock signal line CKL3, the second clock signal CK2 received by the second signal terminal SG2 is sourced from the sixth clock signal line CKL6, the third clock signal CK3 received by the third signal terminal SG3 is sourced from the fifth clock signal line CKL5, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is sourced from the second clock signal line CKL2.

[0112] The working timing of the sixth-stage shift register ASG(6) of any shift register circuit 310 is as follows: The first clock signal CK1 received by the first signal terminal SG1 is sourced from the fourth clock signal line CKL4, the second clock signal CK2 received by the second signal terminal SG2 is sourced from the first clock signal line CKL1, the third clock signal CK3 received by the third signal terminal SG3 is sourced from the sixth clock signal line CKL6, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is sourced from the third clock signal line CKL3.

[0113] In this embodiment, for the single-sided 6-phase ASG structure of the first driving circuit 300, by using the existing clock signal lines of the first driving circuit 300 itself, the first clock signal CK1 is multiplexed to be provided to the first signal terminal SG1, and the second clock signal CK2 is multiplexed to be provided to the second signal terminal SG2. The shift register 101 can output normally, and the first driving circuit 300 can achieve forward and reverse scans. And Figure 3Compared with that, two DC signal lines are reduced; and the device bias time of either the first transistor M1 or the second transistor M2 is halved, and the severity of Vth shift is weakened, so that the output stability, reliability and dependability of the shift register 101 can be improved; in addition, the high-level leakage time of the first node N1 is halved, which can improve the problem that the shift register is prone to failure during high-temperature operation.

[0114] For the first driving circuit 300, the working process thereof will be described below by taking the Figure 4 shown shift register 101 as an example. Optionally, each transistor therein is an NMOS, and the first power signal provided by the first power supply terminal VG1 is a low-voltage signal VGL. The display panel can perform forward scanning and reverse scanning.

[0115] Here, only the timing of one of the shift registers (such as ASG 7 (1)) of the first driving circuit 300 will be described. Exemplarily, the first-stage shift register ASG(1) in the second-stage shift register circuit 310 / 2, that is, ASG 7 (1), the first clock signal CK1 received by its first signal terminal SG1 is from the fifth clock signal line CKL5, the second clock signal CK2 received by the second signal terminal SG2 is from the second clock signal line CKL2, the third clock signal CK3 received by the third signal terminal SG3 is from the first clock signal line CKL1, and the fourth clock signal CK4 received by the fourth signal terminal SG4 is from the fourth clock signal line CKL4. Based on this, Figure 13 is a timing schematic diagram of the forward scanning of the shift register (ASG 7 (1)) in the first driving circuit based on the single-sided 6-phase ASG structure, Figure 14 is a timing schematic diagram of the reverse scanning of the shift register (ASG 7 (1)) in the first driving circuit based on the single-sided 6-phase ASG structure.

[0116] Combined with Figure 4 and Figure 13 shown, the forward scanning working process of the shift register 101 at least includes the following stages:

[0117] In the first stage t31, the electrical signal received by the first trigger terminal IN1 of the shift register 101 is a high-level signal, which turns on the first transistor M1; the first clock signal CK1 provided by the first signal terminal SG1 changes from low level to high level, then the potential of the first node N1 changes from low level to high level, turning on the third transistor M3; the third clock signal CK3 provided by the third signal terminal SG3 is at low level, so the shift output terminal GOUT outputs a low level; the electrical signal received by the second trigger terminal IN2 is at low level, turning off the second transistor M2; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at high level, turning on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0118] In the second stage t32, the electrical signal received by the first trigger terminal IN1 of the shift register 101 is a low-level signal, turning off the first transistor M1, and the potential of the second trigger terminal IN2 remaining at low level keeps the second transistor M2 turned off, then the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t31, keeping the third transistor M3 turned on; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at low level, turning off the fourth transistor M4; the third clock signal CK3 provided by the third signal terminal SG3 is at high level, then the shift output terminal GOUT changes from the low level of the first stage t31 and outputs a high level; the low-level to high-level change of the shift output terminal GOUT, after being coupled by the first capacitor C1, causes the first node N1 to be lifted based on the bootstrap effect of the first capacitor C1.

[0119] In the third stage t33, the first transistor M1 remains turned off; the electrical signal received by the second trigger terminal IN2 of the shift register 101 is a high-level signal, turning on the second transistor M2, and the second clock signal CK2 provided by the second signal terminal SG2 changes from high level to low level, then the potential of the first node N1 is pulled down and reduced, causing the third transistor M3 to switch from on to off; before the third transistor M3 turns off, the low level of the third clock signal CK3 is written to the shift output terminal GOUT; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at high level, turning on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0120] As described above, the shift output terminal GOUT of the shift register 101 outputs a high-level signal in the second stage t32, and this high-level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register 101 keeps outputting a low-level signal in the third stage t33 and afterwards until the first trigger terminal IN1 receives a high-level signal again.

[0121] CombinedFigure 4 and Figure 14 As shown in Figure 14 , the reverse scan operation process of the shift register 101 at least includes the following stages:

[0122] In the first stage t41, the electrical signal received by the second trigger terminal IN2 of the shift register 101 is a high-level signal, turning on the second transistor M2; the second clock signal CK2 provided by the second signal terminal SG2 changes from low level to high level, then the potential of the first node N1 changes from low level to high level, turning on the third transistor M3; the third clock signal CK3 provided by the third signal terminal SG3 is at low level, so the shift output terminal GOUT outputs at low level; the electrical signal received by the first trigger terminal IN1 is at low level, turning off the first transistor M1; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at high level, turning on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written into the shift output terminal GOUT.

[0123] In the second stage t42, the electrical signal received by the second trigger terminal IN2 of the shift register 101 is a low-level signal, turning off the second transistor M2; the potential of the first trigger terminal IN1 remains at low level, turning off the first transistor M1, then the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t41, keeping the third transistor M3 turned on; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at low level, turning off the fourth transistor M4; the third clock signal CK3 provided by the third signal terminal SG3 is at high level, so the shift output terminal GOUT changes from the low level of the first stage t41 to output at high level; the low-level to high-level change of the shift output terminal GOUT, after being coupled by the first capacitor C1, causes the first node N1 to be lifted based on the bootstrap effect of the first capacitor C1.

[0124] In the third stage t43, the second transistor M2 remains turned off; the electrical signal received by the first trigger terminal IN1 of the shift register 101 is a high-level signal, turning on the first transistor M1, and the first clock signal CK1 provided by the first signal terminal SG1 changes from high level to low level, then the potential of the first node N1 is pulled down and reduced, causing the third transistor M3 to switch from on to off; before the third transistor M3 is turned off, the low level of the third clock signal CK3 is written into the shift output terminal GOUT; the fourth clock signal CK4 provided by the fourth signal terminal SG4 is at high level, turning on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written into the shift output terminal GOUT.

[0125] As described above, the shift output terminal GOUT of the shift register 101 outputs a high-level signal in the second stage t42. This high-level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register 101 maintains an output low-level signal in the third stage t43 and later until the second trigger terminal IN2 receives a high-level signal again.

[0126] Based on this, the display panel can perform forward scanning and reverse scanning, and can switch between forward scanning and reverse scanning.

[0127] In this embodiment, the first electrical signal provided by the first signal terminal SG1 is the first clock signal CK1, and the second electrical signal provided by the second signal terminal SG2 is the second clock signal CK2, which does not affect the normal output of the shift register 101. Then, the original clock signal lines of the first driving circuit 300 can be used to provide the first clock signal CK1 and the second clock signal CK2 for the shift register 101. Thus, the first driving circuit 300 does not need to set additional SG1 signal lines and SG2 signal lines, which is beneficial to realizing a narrow border. On the other hand, the duty cycle of the first clock signal CK1 can be about 50%, and the duty cycle of the second clock signal CK2 can be about 50%. Therefore, the device bias time of the first transistor M1 can be halved, and the device bias time of the second transistor M2 can be halved. Correspondingly, the severity of the threshold voltage shift Vth shift of the first transistor M1 and the second transistor M2 is weakened, so that the reliability of the shift register 101 can be improved. In addition, the duration of the high-level leakage of the first clock signal CK1 into the first node N1 is halved, and the duration of the high-level leakage of the second clock signal CK2 into the first node N1 is halved, which can improve the problem that the shift register 101 is prone to failure when operating at high temperatures.

[0128] Optionally, the first electrical signal is the first clock signal; the second electrical signal is a fixed voltage signal; the first driving circuit includes a forward scanning mode and a reverse scanning mode; in the forward scanning mode, the second electrical signal is a low-level signal; in the reverse scanning mode, the second electrical signal is a high-level signal.

[0129] Figure 15 is a schematic diagram of another shift register provided by an embodiment of the present invention. Optionally, all the transistors are NMOS. Different from Figure 4 in that Figure 15 the first electrical signal of the first signal terminal SG1 is the first clock signal CK1, and the second electrical signal of the second signal terminal SG2 is the fixed voltage signal DIR2. The first driving circuit including Figure 15 the shift register shown has a working mode including a forward scanning mode and a reverse scanning mode. In the forward scanning mode, the second electrical signal DIR2 is a low-level signal; in the reverse scanning mode, the second electrical signal DIR2 is a high-level signal.

[0130] Figure 16 is Figure 15 A timing diagram showing the forward scan of the shift register shown, where the second electrical signal DIR2 is a low-level signal vgl, and the high-level signal vgh represented by the dashed line shown in the figure is only for indicating that vgl is lower than vgh. Figure 17 is Figure 15 A timing diagram showing the reverse scan of the shift register shown, where the second electrical signal DIR2 is a high-level signal vgh, and the low-level signal vgl represented by the dashed line shown in the figure is only for indicating that vgh is higher than vgl.

[0131] Combined with Figure 15 and Figure 16 as shown, the forward scan working process of the shift register at least includes the following stages:

[0132] In the first stage t51, the first trigger terminal IN1 receives a high-level signal, turning on the first transistor M1; the first clock signal CK1 jumps from a low level to a high level, then the potential of the first node N1 jumps from a low level to a high level, turning on the third transistor M3; the low level of the third clock signal CK3 is output to the shift output terminal GOUT; the second transistor M2 is turned off; the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0133] In the second stage t52, the first trigger terminal IN1 receives a low-level signal, the first transistor M1 is turned off, and the second transistor M2 remains off, then the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t51, keeping the third transistor M3 on; the fourth transistor M4 is turned off; the high level of the third clock signal CK3 is output to the shift output terminal GOUT; the shift output terminal GOUT jumps from the low level of the first stage t51 to output a high-level signal, and after being coupled by the first capacitor C1, the potential of the first node N1 is raised.

[0134] In the third stage t53, the first transistor M1 remains off; the second trigger terminal IN2 receives a high-level signal, turning on the second transistor M2, the second electrical signal DIR2 is a low-level signal vgl, then the potential of the first node N1 is pulled down and reduced, turning off the third transistor M3; the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0135] As described above, the shift output terminal GOUT of the shift register outputs a high-level signal in the second stage t52, and this high-level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register maintains an output of a low-level signal in the third stage t53 and thereafter until the first trigger terminal IN1 receives a high-level signal again.

[0136] Combined Figure 15 with Figure 17 shown, the reverse scanning operation process of the shift register at least includes the following stages:

[0137] In the first stage t61, the second trigger terminal IN2 receives a high-level signal, turning on the second transistor M2. The second electrical signal DIR2 is a high-level signal vgh, so the potential of the first node N1 jumps to a high level, turning on the third transistor M3. The low level of the third clock signal CK3 is output to the shift output terminal GOUT. The first transistor M1 is turned off. The high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0138] In the second stage t62, the second trigger terminal IN2 receives a low-level signal, turning off the second transistor M2. The first transistor M1 remains off, so the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t61, keeping the third transistor M3 on. The fourth transistor M4 is turned off. The high level of the third clock signal CK3 is output to the shift output terminal GOUT. The shift output terminal GOUT jumps from the low level of the first stage t61 to output a high-level signal. After being coupled by the first capacitor C1, the potential of the first node N1 is raised.

[0139] In the third stage t63, the second transistor M2 remains off. The first trigger terminal IN1 receives a high-level signal, turning on the first transistor M1. The first clock signal CK1 jumps from a high level to a low level, so the potential of the first node N1 is pulled down and reduced, causing the third transistor M3 to switch from on to off. Before the third transistor M3 turns off, the low level of the third clock signal CK3 is written to the shift output terminal GOUT. The high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0140] As described above, the shift output terminal GOUT of the shift register outputs a high-level signal in the second stage t62, and this high-level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register maintains an output of a low-level signal in the third stage t63 and thereafter until the second trigger terminal IN2 receives a high-level signal again.

[0141] Based on this, the display panel can perform forward scanning and reverse scanning, and can switch between forward scanning and reverse scanning.

[0142] In this embodiment, without affecting the normal operation of the shift register, the first signal terminal SG1 can be provided with the first clock signal by the clock signal line. Compared with the original DC signal line providing a DC signal to the first signal terminal, one additional DC signal line can be reduced, achieving the effect of reducing the border. Moreover, using the AC signal of the first clock signal instead of the DC signal can improve the service life, reliability, etc. of the shift register.

[0143] Optionally, the first electrical signal is a fixed voltage signal; the second electrical signal is a second clock signal; the first driving circuit includes a forward scanning mode and a reverse scanning mode; in the forward scanning mode, the first electrical signal is a high-level signal; in the reverse scanning mode, the first electrical signal is a low-level signal.

[0144] Figure 18 is a schematic diagram of another shift register provided by an embodiment of the present invention. Optionally, all the transistors are NMOS. Different from Figure 4 in that Figure 18 the first electrical signal of the first signal terminal SG1 in is a fixed voltage signal DIR1, and the second electrical signal of the second signal terminal SG2 is a second clock signal CK2. It includes Figure 18 the first driving circuit of the shift register shown, whose working mode includes a forward scanning mode and a reverse scanning mode. In the forward scanning mode, the first electrical signal DIR1 is a high-level signal; in the reverse scanning mode, the first electrical signal DIR1 is a low-level signal.

[0145] Figure 19 is Figure 18 a timing schematic diagram of the forward scanning of the shift register shown. Among them, the first electrical signal DIR1 is a high-level signal vgh, and the low-level signal vgl represented by the dotted line shown in the figure is only for indicating that vgh is higher than vgl. Figure 20 is Figure 18 a timing schematic diagram of the reverse scanning of the shift register shown. Among them, the first electrical signal DIR1 is a low-level signal vgl, and the high-level signal vgh represented by the dotted line shown in the figure is only for indicating that vgl is lower than vgh.

[0146] Combined with Figure 18 and Figure 19 shown, the forward scanning working process of the shift register at least includes the following stages:

[0147] In the first stage t71, the first trigger terminal IN1 receives a high-level signal, turning on the first transistor M1; the first electrical signal DIR1 is a high-level signal vgh, so the potential of the first node N1 jumps to a high level, turning on the third transistor M3; the low level of the third clock signal CK3 is output to the shift output terminal GOUT; the second transistor M2 is turned off; the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0148] In the second stage t72, the first trigger terminal IN1 receives a low-level signal, the first transistor M1 is turned off, and the second transistor M2 remains off, so the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t71, keeping the third transistor M3 on; the fourth transistor M4 is turned off; the high level of the third clock signal CK3 is output to the shift output terminal GOUT; the shift output terminal GOUT jumps from the low level of the first stage t71 to output a high-level signal, and after being coupled by the first capacitor C1, the potential of the first node N1 is lifted.

[0149] In the third stage t73, the first transistor M1 remains off; the second trigger terminal IN2 receives a high-level signal, turning on the second transistor M2, and the second clock signal CK2 jumps from a high level to a low level, so the potential of the first node N1 is pulled down and reduced, turning off the third transistor M3; the third clock signal CK3 is at a low level, and the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0150] As described above, the shift output terminal GOUT of the shift register outputs a high-level signal in the second stage t72, and this high-level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register maintains an output low-level signal in the third stage t73 and later until the first trigger terminal IN1 receives a high-level signal again.

[0151] Combined Figure 18 and Figure 20 As shown, the reverse scanning working process of the shift register at least includes the following stages:

[0152] In the first stage t81, the first transistor M1 is turned off; the second trigger terminal IN2 receives a high-level signal, turning on the second transistor M2. The second clock signal CK2 jumps from a low level to a high level, causing the potential of the first node N1 to jump from a low level to a high level, turning on the third transistor M3; the low level of the third clock signal CK3 is output to the shift output terminal GOUT; the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0153] In the second stage t82, the second trigger terminal IN2 receives a low-level signal, turning off the second transistor M2; the first transistor M1 remains off, so the first node N1 is in a floating state, and the potential of the first node N1 maintains the high level of the first stage t81, keeping the third transistor M3 on; the fourth transistor M4 is turned off; the high level of the third clock signal CK3 is output to the shift output terminal GOUT; the shift output terminal GOUT jumps from the low level of the first stage t81 to output a high-level signal, which, after being coupled by the first capacitor C1, raises the potential of the first node N1.

[0154] In the third stage t83, the second transistor M2 remains off; the first trigger terminal IN1 receives a high-level signal, turning on the first transistor M1. The first electrical signal DIR1 is at a low level vgl, so the potential of the first node N1 is pulled down and decreased, turning off the third transistor M3; the high level of the fourth clock signal CK4 turns on the fourth transistor M4, and the low-level signal VGL provided by the first power supply terminal VG1 is written to the shift output terminal GOUT.

[0155] As described above, the shift output terminal GOUT of the shift register outputs a high-level signal in the second stage t82, and this high-level signal is a valid pulse signal for scanning and driving the corresponding row of sub-pixels. The shift register outputs a low-level signal in the third stage t83 and afterwards until the second trigger terminal IN2 receives a high-level signal again.

[0156] Based on this, the display panel can perform forward scanning and reverse scanning, and can switch between forward scanning and reverse scanning.

[0157] In this embodiment, without affecting the normal operation of the shift register, the second signal terminal SG2 can be provided with the second clock signal by the clock signal line. Compared with the original DC signal line providing a DC signal to the second signal terminal, an additional DC signal line can be reduced, achieving the effect of reducing the border. Moreover, using the AC signal of the second clock signal instead of the DC signal can improve the service life, reliability, etc. of the shift register.

[0158] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the display panel described in any of the above embodiments. Optionally, the display panel is an organic light-emitting display panel, a micro LED display panel, a liquid crystal display panel, etc., which is not limited thereto. Figure 21 Figure 21 is a schematic diagram of a display device provided by an embodiment of the present invention. Optionally, the display device is applied to electronic devices 400 such as smart phones, tablet computers, in-vehicle display screens, etc. It can be understood that any of the above embodiments only provides some examples or partial structures of the display panel. In actual applications, the display panel further includes other structures, which will not be elaborated herein one by one. The display device provided by the embodiment of the present invention has all the functions and beneficial effects of the display panel described above, and will not be specifically elaborated.

[0159] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. There is no limitation herein.

[0160] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: A first driving circuit; the first driving circuit comprises a multi-stage shift register, the shift register comprises at least a first input unit, a second input unit and a first output unit; The control end of the first input unit is connected to the first trigger end, the input end of the first input unit is connected to the first signal end, and the output end of the first input unit is connected to the first node, so as to adjust the signal of the first node according to the first electrical signal provided by the first signal end in response to the control of the first trigger end; The control end of the second input unit is connected to the second trigger end, the input end of the second input unit is connected to the second signal end, and the output end of the second input unit is connected to the first node, so as to adjust the signal of the first node according to the second electrical signal provided by the second signal end in response to the control of the second trigger end; The control end of the first output unit is connected to the first node, the input end of the first output unit is connected to the third signal end, and the output end of the first output unit is connected to the shift output end, so as to adjust the signal of the shift output end according to the third clock signal provided by the third signal end in response to the control of the first node; The first electrical signal is a first clock signal, and / or the second electrical signal is a second clock signal; The first input unit comprises a first transistor, a gate of the first transistor is connected to the first trigger terminal, and the first transistor is connected between the first signal terminal and the first node; The second input unit comprises a second transistor, a gate of the second transistor is connected to the second trigger terminal, and the second transistor is connected between the second signal terminal and the first node; The first trigger terminal of the shift register of the nth level is connected to the shift output terminal of the shift register of the (nm)th level; The second trigger terminal of the nth stage shift register is connected to the shift output terminal of the (n+m)th stage shift register; n is a positive integer, and m is an integer greater than or equal to 2.

2. The display panel according to claim 1, characterized in that: The shift register further includes: a second output unit; The control end of the second output unit is connected to the fourth signal end, the input end of the second output unit is connected to the first power supply end, and the output end of the second output unit is connected to the shift output end, and is used to respond to the control of the fourth clock signal provided by the fourth signal end, and adjust the signal of the shift output end according to the first power supply signal provided by the first power supply end.

3. The display panel according to claim 2, characterized in that: The first output unit comprises a third transistor, a gate of the third transistor is connected to the first node, and the third transistor is connected between the third signal terminal and the shift output terminal; The second output unit includes a fourth transistor, a gate of the fourth transistor is connected to the fourth signal terminal, and the fourth transistor is connected between the first power supply terminal and the shift output terminal.

4. The display panel according to claim 1, characterized in that: The shift register further includes: a reset unit and a node control unit; The reset unit is connected to a reset control terminal, a first power supply terminal, the first node and the shift output terminal, and is used to adjust the signals of the first node and the shift output terminal according to a first power supply signal provided by the first power supply terminal in response to control of the reset control terminal; The node control unit is connected to the first node, the first power supply terminal and the shift output terminal, and is used for adjusting the signals of the first node and the shift output terminal according to the first power supply signal in response to the control of the first node.

5. The display panel according to claim 4, characterized in that: The reset unit includes a fifth transistor and a sixth transistor, the gate of the fifth transistor and the gate of the sixth transistor are both connected to the reset control terminal, the fifth transistor is connected between the first power supply terminal and the first node, and the sixth transistor is connected between the first power supply terminal and the shift output terminal; The node control unit includes a seventh transistor, an eighth transistor and a ninth transistor, the gate of the seventh transistor is connected to the first node, the seventh transistor is connected between the first power supply terminal and the second node, the gate of the eighth transistor and the gate of the ninth transistor are both connected to the second node, the eighth transistor is connected between the first power supply terminal and the first node, and the ninth transistor is connected between the first power supply terminal and the shift output terminal.

6. The display panel according to claim 5, characterized in that: The shift register further includes: a first capacitor and a second capacitor; The first capacitor is coupled between the first node and the shift output terminal; The second capacitor is coupled between the second node and the third signal terminal.

7. The display panel according to claim 2, characterized in that: The first driving circuit includes a multi-stage shift register circuit and Y clock signal lines, where Y≥4; The shift register circuit includes Ya shift registers connected in cascade, and the third signal terminals of the Ya shift registers are respectively connected to Ya clock signal lines among the Y clock signal lines, and Y≥Ya≥4.

8. The display panel according to claim 7, characterized in that: Among the Y clock signal lines, the clock signals provided by any two clock signal lines have the same frequency but different phases.

9. The display panel according to claim 7, characterized in that: The Y clock signal lines include the 1st clock signal line to the Yth clock signal line; The first driving circuit includes a forward scanning mode and a reverse scanning mode; In the forward scanning mode, the phase of the clock signal provided by the i-th clock signal line is earlier than the phase of the clock signal provided by the (i+1)-th clock signal line, and the phase difference between the two is aH; In the reverse scanning mode, the phase of the clock signal provided by the (i+1)th clock signal line is earlier than the phase of the clock signal provided by the i-th clock signal line, and the phase difference between the two is bH; 1≤i≤Y, a and b are both positive integers, and H is equal to the scanning time length of a row of sub-pixels in the display panel.

10. The display panel according to claim 7, characterized in that: The Y clock signal lines include the first clock signal line to the fourth clock signal line, and the shift register circuit includes four cascaded shift registers; The first driving circuit includes a first circuit group, and the first circuit group includes at least one shift register circuit; The shift register circuit in the first circuit group satisfies the following conditions: The first clock signal line is respectively connected to the third signal terminal of the first-stage shift register, the first signal terminal of the second-stage shift register, the fourth signal terminal of the third-stage shift register, and the second signal terminal of the fourth-stage shift register; The second clock signal line is respectively connected to the second signal terminal of the first-stage shift register, the third signal terminal of the second-stage shift register, the first signal terminal of the third-stage shift register, and the fourth signal terminal of the fourth-stage shift register; The third clock signal line is respectively connected to the fourth signal terminal of the first-stage shift register, the second signal terminal of the second-stage shift register, the third signal terminal of the third-stage shift register, and the first signal terminal of the fourth-stage shift register; The fourth clock signal line is respectively connected to the first signal terminal of the first-stage shift register, the fourth signal terminal of the second-stage shift register, the second signal terminal of the third-stage shift register, and the third signal terminal of the fourth-stage shift register.

11. The display panel according to claim 10, characterized in that: The first driving circuit includes a forward scanning mode and a reverse scanning mode; In the forward scanning mode, the phase of the clock signal provided by the i-th clock signal line is earlier than the phase of the clock signal provided by the (i+1)-th clock signal line, and the phase difference between the two is H; In the reverse scanning mode, the phase of the clock signal provided by the (i+1)th clock signal line is earlier than the phase of the clock signal provided by the i-th clock signal line, and the phase difference between the two is H; 1≤i≤3, 2H is equal to the effective pulse width output by the shift output terminal of the shift register.

12. The display panel according to claim 7, characterized in that: The Y clock signal lines include the first clock signal line to the sixth clock signal line, and the shift register circuit includes six cascaded shift registers; The first driving circuit includes a second circuit group, and the second circuit group includes at least one shift register circuit; The shift register circuit in the second circuit group satisfies the following conditions: The first clock signal line is respectively connected to the third signal terminal of the first-stage shift register, the first signal terminal of the third-stage shift register, the fourth signal terminal of the fourth-stage shift register, and the second signal terminal of the sixth-stage shift register; The second clock signal line is respectively connected to the second signal terminal of the first-stage shift register, the third signal terminal of the second-stage shift register, the first signal terminal of the fourth-stage shift register, and the fourth signal terminal of the fifth-stage shift register; The third clock signal line is respectively connected to the second signal terminal of the second-stage shift register, the third signal terminal of the third-stage shift register, the first signal terminal of the fifth-stage shift register, and the fourth signal terminal of the sixth-stage shift register; The fourth clock signal line is respectively connected to the fourth signal terminal of the first-stage shift register, the second signal terminal of the third-stage shift register, the third signal terminal of the fourth-stage shift register, and the first signal terminal of the sixth-stage shift register; The fifth clock signal line is respectively connected to the first signal terminal of the first-stage shift register, the fourth signal terminal of the second-stage shift register, the second signal terminal of the fourth-stage shift register, and the third signal terminal of the fifth-stage shift register; The sixth clock signal line is respectively connected to the first signal terminal of the second-stage shift register, the fourth signal terminal of the third-stage shift register, the second signal terminal of the fifth-stage shift register, and the third signal terminal of the sixth-stage shift register.

13. The display panel according to claim 12, characterized in that: The first driving circuit includes a forward scanning mode and a reverse scanning mode; In the forward scanning mode, the phase of the clock signal provided by the i-th clock signal line is earlier than the phase of the clock signal provided by the (i+1)-th clock signal line, and the phase difference between the two is H; In the reverse scanning mode, the phase of the clock signal provided by the (i+1)th clock signal line is earlier than the phase of the clock signal provided by the i-th clock signal line, and the phase difference between the two is H; 1≤i≤5, 3H is equal to the effective pulse width output by the shift output terminal of the shift register.

14. The display panel according to claim 1, characterized in that: The first electrical signal is the first clock signal; the second electrical signal is a fixed voltage signal; The first driving circuit includes a forward scanning mode and a reverse scanning mode; In the forward scanning mode, the second electrical signal is a low level signal; In the reverse scanning mode, the second electrical signal is a high level signal.

15. The display panel according to claim 1, characterized in that: The first electrical signal is a fixed voltage signal; the second electrical signal is the second clock signal; The first driving circuit includes a forward scanning mode and a reverse scanning mode; In the forward scanning mode, the first electrical signal is a high level signal; In the reverse scanning mode, the first electrical signal is a low level signal.

16. The display panel according to claim 1, characterized in that: The shift register comprises a plurality of transistors; The plurality of transistors are all N-type transistors, or the plurality of transistors are all P-type transistors.

17. The display panel according to claim 1, characterized in that: The shift register comprises a plurality of transistors; The semiconductor layer of the transistor is an amorphous silicon semiconductor layer or an oxide semiconductor layer.

18. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 17.

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