Digital phase frequency detector system, high-speed serial data sampling method and electronic equipment

Abstract

The invention relates to a digital phase frequency detector system, a high-speed serial data sampling method and electronic equipment, and belongs to the technical field of data transmission, and the system comprises a frequency discrimination module which is used for determining frequency information and frequency delay information of input data; the clock module is used for determining a sampling clock based on the frequency information; the configurable delay module is used for delaying the input data based on the frequency delay information to obtain delay data; the phase discrimination module is used for carrying out edge detection on the oversampling data to determine a sampling point, and taking input data corresponding to the sampling point and a sampling clock as output data; the oversampled data is obtained by oversampling the input data and the delayed data based on a sampling clock. The digital phase frequency detector system provided by the invention can dynamically adjust sampling points according to sampling information so as to reduce error codes caused by clock errors, can automatically identify and match various data frequencies, adopts a digital circuit system architecture, and has relatively high portability.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a digital frequency and phase detector system, a high-speed serial data sampling method and electronic equipment. Background Art

[0002] In order to improve transmission efficiency, high-speed serial data transmission often does not have a clock signal, and the receiving end needs to perform clock data recovery. The phase and frequency detector is a key part of it. It is used to determine the phase of the data and recover the correct clock frequency and data, thereby improving the sampling accuracy and reducing the bit error rate.

[0003] The existing technology needs to rely on analog phase-locked loop circuits for clock recovery when performing clock data recovery. It has poor portability and cannot be applied to FPGAs. It cannot automatically correct dynamic errors and clock cumulative errors, and has a high bit error rate. Summary of the invention

[0004] In view of this, it is necessary to provide a digital frequency and phase detector system, a high-speed serial data sampling method and an electronic device to solve the problems of poor portability and high bit error rate of the existing methods.

[0005] In order to solve the above problems, the present invention provides a digital frequency and phase detector system, comprising: Frequency detection module, clock module, configurable delay module and phase detection module; The first output terminal of the frequency discrimination module is connected to the clock module; The second output end of the frequency discrimination module is connected to the configurable delay module; The output end of the clock module is connected to the phase detection module; The output end of the configurable delay module is connected to the phase detection module; The output end of the phase detection module is connected to the configurable delay module.

[0006] In a possible implementation, the phase detection module is specifically used to: Performing edge detection on the oversampled data to determine edge position information corresponding to the oversampled data; When it is determined based on the edge position information that the input data does not have a phase error, determining a sampling state; When it is determined that there is no clock error in the sampling clock, a sampling point is determined based on the sampling state.

[0007] In a possible implementation, the phase detection module is further used to: When it is determined based on the edge position information that the input data has a phase error, a feedback signal is sent to the configurable delay module; the feedback signal is used to adjust the phase of the input data.

[0008] In a possible implementation, the phase detection module is further used to: When it is determined that the sampling clock has a clock error, a sampling point is determined based on the clock error.

[0009] In a possible implementation, the configurable delay module includes: a first configurable delay unit and a second configurable delay unit; An output terminal of the first configurable delay unit is connected to the second configurable delay unit.

[0010] In a possible implementation manner, the accuracy of the first configurable delay unit is smaller than the accuracy of the second configurable delay unit.

[0011] In a possible implementation manner, the second output terminal of the frequency discrimination module is connected to the first configurable delay unit; The output end of the second configurable delay unit is connected to the phase detection module; The output end of the phase detection module is connected to the second configurable delay unit.

[0012] The present invention also provides a high-speed serial data sampling method, which is applied to any one of the digital frequency and phase detector systems described above, comprising: Oversampling the input data and delayed data based on a sampling clock to obtain oversampled data; the input data is high-speed serial data; the sampling clock is determined based on the frequency information of the input data; the delayed data is obtained by delaying the input data; Performing edge detection on the oversampled data to determine edge position information corresponding to the oversampled data; When it is determined based on the edge position information that the input data does not have a phase error, determining a sampling state; When it is determined that the sampling clock does not have a clock error, determining a sampling point based on the sampling state; The sampling data corresponding to the sampling clock and the sampling point are used as output data.

[0013] On the other hand, the present invention also provides an electronic device, including a memory and a processor, wherein: The memory is used to store programs; The processor is coupled to the memory and is used to execute the program stored in the memory to implement the high-speed serial data sampling method described in any of the above implementations.

[0014] On the other hand, the present invention further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the high-speed serial data sampling method described in any of the above implementations.

[0015] The beneficial effects of the present invention are as follows: the digital frequency and phase detector system, high-speed serial data sampling method and electronic device provided by the present invention count the input high-speed serial data through the frequency detection module to obtain the frequency information and frequency delay information of the input data, the clock module divides the main clock according to the frequency information to obtain the sampling clock, the configurable delay module delays the input data according to the frequency delay information to obtain the delayed data, the phase detection module simultaneously oversamples the input data and the delayed data through the sampling clock to obtain the oversampled data, and performs edge detection on the oversampled data to correct the sampling phase, the sampling point can be dynamically adjusted according to the sampling information to reduce the bit error caused by the clock error, and after adjusting the sampling data through the phase change, the input data and the sampling clock corresponding to the sampling point are output, and a variety of data frequencies can be automatically identified and matched, a digital circuit system architecture is adopted, and the portability is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 One of the structural schematic diagrams of an embodiment of a digital frequency and phase detector system provided by the present invention; Figure 2 A schematic diagram of the edge detection principle provided by the present invention; Figure 3 A schematic diagram of the sampling state jump provided by the present invention; Figure 4 A schematic diagram of the data output principle provided by the present invention; Figure 5 A schematic diagram of a working process of an embodiment of a phase detection module provided by the present invention; Figure 6 A schematic diagram of the structure of an embodiment of a configurable delay module provided by the present invention; Figure 7 A second structural schematic diagram of an embodiment of a digital frequency and phase detector system provided by the present invention; Figure 8 A schematic diagram of the working process of an embodiment of a digital frequency and phase detector system provided by the present invention; Fig. 9 A schematic diagram of a flow chart of an embodiment of a high-speed serial data sampling method provided by the present invention; Fig.10 A schematic structural diagram of an embodiment of an electronic device provided by the present invention. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0019] In the description of the embodiments of the present invention, unless otherwise specified, "multiple" means two or more than two. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone.

[0020] The descriptions of "first", "second", etc. involved in the embodiments of the present invention are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the technical features defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0021] Figure 1 One of the structural schematic diagrams of an embodiment of the digital frequency and phase detector system provided by the present invention is as follows Figure 1 As shown, the digital phase frequency detector system 100 includes: The frequency discrimination module 110 is used to determine the frequency information and frequency delay information of the input data; A clock module 120, configured to determine a sampling clock based on the frequency information; A configurable delay module 130, configured to delay the input data based on the frequency delay information to obtain delayed data; The phase detection module 140 is used to perform edge detection on the oversampled data to determine the sampling point, and use the input data corresponding to the sampling point and the sampling clock as output data; the oversampled data is obtained by oversampling the input data and the delayed data based on the sampling clock.

[0022] like Figure 1As shown, the digital frequency and phase detector system includes a frequency detection module, a clock module, a configurable delay module and a phase detection module. The first output end of the frequency detection module is connected to the clock module; the second output end of the frequency detection module is connected to the configurable delay module; the output end of the clock module is connected to the phase detection module; the output end of the configurable delay module is connected to the phase detection module; and the output end of the phase detection module is connected to the configurable delay module.

[0023] The frequency discrimination module can count the input data through the master clock, and the input data can be high-speed serial data. Since the high-speed serial interface needs to maintain DC balance and the number of 0s and 1s is equal, the transmission frequency of the data can be determined based on the number of recorded high levels, and the frequency information and frequency delay information of the input data can be obtained.

[0024] like Figure 1 As shown, the first output end of the frequency discrimination module is connected to the clock module. The clock module is responsible for clock division. The clock input frequency is the highest operating rate of the system. The clock module can divide the main clock according to the frequency information calculated by the frequency discrimination module to obtain the sampling clock.

[0025] The output end of the clock module is connected to the phase detection module, and the clock module can input the sampling clock to the phase detection module to perform data sampling.

[0026] The second output end of the frequency discrimination module is connected to a configurable delay module, and the configurable delay module can delay the input data according to the frequency delay information to obtain delayed data.

[0027] The output end of the configurable delay module is connected to the phase detector module, which can simultaneously oversample the input data and the delayed data through the sampling clock to obtain the oversampled data. The oversampled data is edge detected to correct the sampling phase, and the sampling point can be dynamically adjusted according to the sampling information. After adjusting the sampling data through the phase change, the input data and sampling clock corresponding to the sampling point are output.

[0028] The output end of the phase detector module is connected to the configurable delay module, that is, the phase detector module can output a feedback signal to the configurable delay module to adjust the data delay or sampling position, that is, dynamically adjust the delay through the feedback signal, thereby reducing the bit error rate.

[0029] Compared with the prior art, the digital frequency and phase detector system provided by the embodiment of the present invention counts the input high-speed serial data through the frequency detection module to obtain the frequency information and frequency delay information of the input data, the clock module divides the main clock according to the frequency information to obtain the sampling clock, the configurable delay module delays the input data according to the frequency delay information to obtain the delayed data, the phase detection module simultaneously oversamples the input data and the delayed data through the sampling clock to obtain the oversampled data, and performs edge detection on the oversampled data to correct the sampling phase, the sampling point can be dynamically adjusted according to the sampling information to reduce the bit error caused by the clock error, and after adjusting the sampling data through the phase change, the input data and the sampling clock corresponding to the sampling point are output, and a variety of data frequencies can be automatically identified and matched, and a digital circuit system architecture is adopted, which has high portability.

[0030] In some embodiments of the present invention, the phase detection module is specifically used for: Performing edge detection on the oversampled data to determine edge position information corresponding to the oversampled data; When it is determined based on the edge position information that the input data does not have a phase error, a sampling state is determined.

[0031] When it is determined that there is no clock error in the sampling clock, a sampling point is determined based on the sampling state.

[0032] In some embodiments of the present invention, the phase detection module is further used for: When it is determined based on the edge position information that the input data has a phase error, a feedback signal is sent to the configurable delay module; the feedback signal is used to adjust the phase of the input data.

[0033] In some embodiments of the present invention, the phase detection module is further used for: When it is determined that the sampling clock has a clock error, a sampling point is determined based on the clock error.

[0034] For example, Figure 2 A schematic diagram of the edge detection principle provided by the present invention, such as Figure 2 The figure shows the timing diagram for edge detection, where CLK is the sampling clock, I is the input data, and II is the delayed data. The sampling clock is used to oversample I and II, and the 8-bit sampled data I[7:0] and II[7:0] are recorded.

[0035] The relative position of the transition edge is calculated by I and II and is represented by E0-E3, such as Figure 7 The test result shown is E1.

[0036] When detecting and recording edge position information E0-E3, if there is a large error between two detection results, such as the first detection result is E0 and the second detection result is E2, a feedback signal is output to adjust the data delay.

[0037] like Figure 2 The correct edge information without phase error is shown. If the delay information is wrong, then Figure 2 The number of cycles of 10 and 01 will change. Among them, 11 11 11 01 in 10 11 11 11 01 represents S0 S1 S2 S3 of this sampling state, and the sampling point of this sampling will be set at S1 or S2 to ensure the accuracy of sampling.

[0038] Figure 3 A schematic diagram of the sampling state jump provided by the present invention, Figure 4 A schematic diagram of the data output principle provided by the present invention, such as Figure 3 and Figure 4 As shown, the sampling states S0-S3 change according to the edge position information E, and the output data is determined by the sampling state S: When the state is in S0, the output data is I[0] and I[4]; When the state is in S1, the output data is I[1] and I[5]; When the state is in S2, the output data is I[2] and I[6]; When the state is in S3, the output data is I[3] and I[7]; When the sampling state S continuously jumps in one direction, it is determined that there is an error between the sampling clock and the data frequency, and a feedback signal is output and the sampling position is adjusted according to the jumping direction to redetermine the sampling point.

[0039] If the sampling clock frequency is higher than the data transmission rate, it is detected that E0 jumps to E3, and the output is adjusted, such as Figure 4 shown.

[0040] For example, Figure 5 A schematic diagram of the working process of an embodiment of the phase detection module provided by the present invention is shown in FIG. Figure 5 As shown in the figure, the workflow of the phase detection module includes: S501, data and delay input.

[0041] S502: Adjust or initialize configurable data delay.

[0042] S503 , detecting the edge position of the input data, taking the first sampled data as E0, and obtaining edge position information E0-E3.

[0043] S504: Determine, according to the edge information E, whether the phase delay is correct.

[0044] S505: Yes, the sampling state S changes according to the edge position information E0-E3, and a stable sampling point is selected for sampling; No, return to S502.

[0045] S506 , judging whether there is a clock error according to the change of the state S and the edge position information E.

[0046] S507: If yes, recalculate the sampling point according to the positive and negative values ​​of the error and provide feedback.

[0047] S508: No, convert the sampled data into parallel data and output it together with the sampling clock.

[0048] S509, data and clock output.

[0049] In the digital frequency and phase detector system provided by the embodiment of the present invention, the phase detector module samples the data and delayed data simultaneously through the sampling clock to obtain oversampled data, performs edge detection on the oversampled data to correct the sampling phase, and adjusts the sampled data through the phase change, dynamically adjusts the sampling point according to the sampling information to reduce the bit error caused by the clock error, and dynamically adjusts the data delay through the feedback signal to reduce the bit error rate.

[0050] In some embodiments of the present invention, the configurable delay module includes: a first configurable delay unit and a second configurable delay unit; An output terminal of the first configurable delay unit is connected to the second configurable delay unit.

[0051] In some embodiments of the present invention, the accuracy of the first configurable delay unit is smaller than the accuracy of the second configurable delay unit.

[0052] In some embodiments of the present invention, the second output terminal of the frequency discrimination module is connected to the first configurable delay unit; The output end of the second configurable delay unit is connected to the phase detection module; The output end of the phase detection module is connected to the second configurable delay unit.

[0053] Figure 6 A structural diagram of an embodiment of a configurable delay module provided by the present invention is shown in FIG. Figure 6 As shown, the configurable delay module is composed of two configurable delay units, including a first configurable delay unit and a second configurable delay unit.

[0054] Further, Figure 7The second structural diagram of an embodiment of the digital frequency and phase detector system provided by the present invention, the first configurable delay unit is connected to the second output end of the frequency detection module, and the input data can be delayed according to the read frequency delay information to obtain delayed data. The first configurable delay unit has a low accuracy and is used for coarse adjustment of the phase error.

[0055] The second configurable delay unit is connected to the output end of the phase detection module, that is, the second configurable delay unit can be controlled by the feedback signal of the phase detection module. The second configurable delay unit has high precision and is responsible for fine-tuning the phase error.

[0056] The digital frequency and phase detector system provided by the embodiment of the present invention adopts a multi-stage delay chain to form a configurable delay chain, and can dynamically adjust the delay through a feedback signal, thereby reducing the bit error rate.

[0057] Further, Figure 8 A schematic diagram of the working process of an embodiment of the digital frequency and phase detector system provided by the present invention is shown in FIG. Figure 8 As shown in the figure, the working process of the digital frequency and phase detector system includes: S801, serial data input.

[0058] S802, use the frequency discrimination module to lock the clock frequency, send the collected frequency information to the clock module to recover the sampling clock, and the sampling system starts working.

[0059] S803, after the data is input into the configurable delay module, the first configurable delay unit starts to work, reads the frequency delay information to perform the first delay on the input data, and then outputs the original data and the delayed data to the phase detection module. The phase difference between the delayed data and the original data can be 45 degrees.

[0060] S804, after the phase detection module samples the original data and the delayed data, it obtains oversampled parallel data, and reaches the optimal sampling point according to the edge jump, and adjusts the data delay through the feedback signal.

[0061] S805. The phase detection module determines whether the data collection is stable.

[0062] S806: If yes, output the data in parallel; if no, return to step S804.

[0063] The digital frequency and phase detector system provided by the embodiment of the present invention adopts a digital circuit system architecture, has high integration and stability, is programmable and portable, and has high portability. A multi-stage delay chain is used to form a configurable delay chain, and the delay is dynamically adjusted through the feedback signal, the data delay is dynamically adjusted, and the bit error rate is reduced. The sampling point can be dynamically adjusted according to the sampling information to reduce the bit error caused by the clock error, and can automatically identify and match a variety of data frequencies.

[0064] Fig. 9 A flow chart of an embodiment of a high-speed serial data sampling method provided by the present invention is shown in FIG. Fig. 9 As shown, the high-speed serial data sampling method includes: S901, oversampling input data and delayed data based on a sampling clock to obtain oversampled data; the input data is high-speed serial data; the sampling clock is determined based on frequency information of the input data; the delayed data is obtained by delaying the input data; S902, performing edge detection on the oversampled data to determine edge position information corresponding to the oversampled data; S903, when it is determined based on the edge position information that the input data does not have a phase error, determining a sampling state; S904: When it is determined that there is no clock error in the sampling clock, determine a sampling point based on the sampling state; S905: Use the sampling data corresponding to the sampling clock and the sampling point as output data.

[0065] The execution subject of the high-speed serial data sampling method provided by the present invention may be the digital frequency and phase detector system described in the above embodiment.

[0066] The high-speed serial data sampling method provided by the embodiment of the present invention counts the input high-speed serial data to obtain the frequency information and frequency delay information of the input data, divides the main clock according to the frequency information to obtain the sampling clock, delays the input data according to the frequency delay information to obtain the delayed data, oversamples the input data and the delayed data simultaneously through the sampling clock to obtain the oversampled data, performs edge detection on the oversampled data to correct the sampling phase, determines the edge position information corresponding to the oversampled data through edge detection, determines the sampling state when it is determined that the input data does not have a phase error according to the edge position information, determines the sampling point according to the sampling state when it is determined that the sampling clock does not have a clock error, can dynamically adjust the sampling point according to the sampling information to reduce the bit error caused by the clock error, uses the sampling clock and the sampling data corresponding to the sampling point as the output data, can dynamically adjust the data delay, reduce the bit error rate, and can automatically identify and match multiple data frequencies.

[0067] like Fig.10 As shown, the present invention also provides an electronic device 1000. The electronic device 1000 includes a processor 1001, a memory 1002 and a display 1003. Fig.10 Only some components of the electronic device 1000 are shown, but it should be understood that it is not required to implement all of the components shown, and more or fewer components may be implemented instead.

[0068] In some embodiments, the processor 1001 may be a central processing unit (CPU), a microprocessor or other data processing chip, and is used to run program codes stored in the memory 1002 or process data, such as the high-speed serial data sampling method of the present invention.

[0069] In some embodiments, processor 1001 may be a single server or a server group. The server group may be centralized or distributed. In some embodiments, processor 1001 may be local or remote. In some embodiments, processor 1001 may be implemented in a cloud platform. In some embodiments, the cloud platform may include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distributed cloud, an internal cloud, a multi-cloud, etc., or any combination thereof.

[0070] In some embodiments, the memory 1002 may be an internal storage unit of the electronic device 1000, such as a hard disk or memory of the electronic device 1000. In other embodiments, the memory 1002 may also be an external storage device of the electronic device 1000, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc., equipped on the electronic device 1000.

[0071] Furthermore, the memory 1002 may include both an internal storage unit of the electronic device 1000 and an external storage device. The memory 1002 is used to store application software installed in the electronic device 1000 and various data.

[0072] In some embodiments, the display 1003 may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an organic light-emitting diode (OLED) touch device, etc. The display 1003 is used to display information on the electronic device 1000 and to display a visual user interface. The components 1001-1003 of the electronic device 1000 communicate with each other via a system bus.

[0073] In one embodiment, when the processor 1001 executes the high-speed serial data sampling program in the memory 1002, the following steps may be implemented: Oversampling the input data and delayed data based on a sampling clock to obtain oversampled data; the input data is high-speed serial data; the sampling clock is determined based on the frequency information of the input data; the delayed data is obtained by delaying the input data; Performing edge detection on the oversampled data to determine edge position information corresponding to the oversampled data; When it is determined based on the edge position information that the input data does not have a phase error, determining a sampling state; When it is determined that the sampling clock does not have a clock error, determining a sampling point based on the sampling state; The sampling data corresponding to the sampling clock and the sampling point are used as output data.

[0074] It should be understood that: when the processor 1001 executes the high-speed serial data sampling program in the memory 1002, in addition to the above functions, other functions may also be implemented, and details may refer to the description of the corresponding method embodiments above.

[0075] Furthermore, the embodiment of the present invention does not specifically limit the type of the electronic device 1000 mentioned, and the electronic device 1000 may be a portable electronic device such as a mobile phone, a tablet computer, a personal digital assistant (PDA), a wearable device, a laptop computer, etc. Exemplary embodiments of portable electronic devices include but are not limited to portable electronic devices equipped with IOS, Android, Microsoft or other operating systems. The above-mentioned portable electronic devices may also be other portable electronic devices, such as a laptop computer with a touch-sensitive surface (e.g., a touch panel). It should also be understood that in some other embodiments of the present invention, the electronic device 1000 may not be a portable electronic device, but a desktop computer with a touch-sensitive surface (e.g., a touch panel).

[0076] Accordingly, an embodiment of the present invention further provides a computer-readable storage medium, which is used to store computer-readable programs or instructions. When the program or instructions are executed by a processor, the steps or functions in the high-speed serial data sampling method provided in the above-mentioned method embodiments can be implemented.

[0077] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware (such as a processor, a controller, etc.) through a computer program, and the computer program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0078] The digital frequency and phase detector system, high-speed serial data sampling method and electronic device provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A digital frequency and phase detector system, characterized in that: include: A frequency discrimination module, used to determine the frequency information and frequency delay information of input data; A clock module, configured to determine a sampling clock based on the frequency information; A configurable delay module, used for delaying the input data based on the frequency delay information to obtain delayed data; A phase detection module, used for performing edge detection on the oversampled data to determine a sampling point, and using the input data corresponding to the sampling point and the sampling clock as output data; The oversampled data is obtained by oversampling the input data and the delayed data based on the sampling clock.

2. The digital phase frequency detector system according to claim 1, characterized in that: The phase detection module is specifically used for: Performing edge detection on the oversampled data to determine edge position information corresponding to the oversampled data; When it is determined based on the edge position information that the input data does not have a phase error, determining a sampling state; When it is determined that there is no clock error in the sampling clock, a sampling point is determined based on the sampling state.

3. The digital phase frequency detector system according to claim 2, characterized in that: The phase detection module is also used for: When it is determined based on the edge position information that the input data has a phase error, a feedback signal is sent to the configurable delay module; the feedback signal is used to adjust the phase of the input data.

4. The digital phase frequency detector system according to claim 2, characterized in that: The phase detection module is also used for: When it is determined that the sampling clock has a clock error, a sampling point is determined based on the clock error.

5. The digital phase frequency detector system according to claim 3, characterized in that: The configurable delay module comprises: a first configurable delay unit and a second configurable delay unit; An output terminal of the first configurable delay unit is connected to the second configurable delay unit.

6. The digital phase frequency detector system according to claim 5, characterized in that: The accuracy of the first configurable delay unit is smaller than the accuracy of the second configurable delay unit.

7. The digital phase frequency detector system according to claim 5, characterized in that: The second output terminal of the frequency discrimination module is connected to the first configurable delay unit; The output end of the second configurable delay unit is connected to the phase detection module; The output end of the phase detection module is connected to the second configurable delay unit.

8. A high-speed serial data sampling method, characterized in that: The digital frequency and phase detector system as claimed in any one of claims 1 to 7 comprises: Oversampling the input data and delayed data based on a sampling clock to obtain oversampled data; the input data is high-speed serial data; the sampling clock is determined based on the frequency information of the input data; the delayed data is obtained by delaying the input data; Performing edge detection on the oversampled data to determine edge position information corresponding to the oversampled data; When it is determined based on the edge position information that the input data does not have a phase error, determining a sampling state; When it is determined that the sampling clock does not have a clock error, determining a sampling point based on the sampling state; The sampling data corresponding to the sampling clock and the sampling point are used as output data.

9. An electronic device, characterized in that: comprising a memory and a processor, wherein: The memory is used to store programs; The processor is coupled to the memory and is used to execute the program stored in the memory to implement the high-speed serial data sampling method as claimed in claim 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the high-speed serial data sampling method according to claim 8 is implemented.

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